MC74VHC4316 Quad Analog Switch/ Multiplexer/Demultiplexer with Separate Analog and Digital Power Supplies http://onsemi.com High-Performance Silicon-Gate CMOS The MC74VHC4316 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF-channel leakage current. This bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full analog power-supply range (from VCC to VEE). The VHC4316 is similar in function to the metal-gate CMOS MC14016 and MC14066, and to the High-Speed CMOS HC4066A. Each device has four independent switches. The device control and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. Logic-level translators are provided so that the On/Off Control and Enable logic-level voltages need only be VCC and GND, while the switch is passing signals ranging between VCC and VEE. When the Enable pin (active-low) is high, all four analog switches are turned off. MARKING DIAGRAMS 16 SOIC-16 D SUFFIX CASE 751B 16 1 VHC4316G AWLYWW 1 16 VHC 4316 ALYWG G TSSOP-16 DT SUFFIX CASE 948F 16 1 1 A WL, L Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) Features •Logic-Level Translator for On/Off Control and Enable Inputs •Fast Switching and Propagation Speeds •High ON/OFF Output Voltage Ratio •Diode Protection on All Inputs/Outputs •Analog Power-Supply Voltage Range (VCC - VEE) = 2.0 to 12.0 V •Digital (Control) Power-Supply Voltage Range (VCC - GND) = 2.0 V to 6.0 V, Independent of VEE •Improved Linearity of ON Resistance •Chip Complexity: 66 FETs or 16.5 Equivalent Gates •These are Pb-Free Devices ORDERING INFORMATION Package Shipping† MC74VHC4316DG SOIC-16 (Pb-Free) 48 Units / Rail MC74VHC4316DR2G SOIC-16 2500/Tape&Reel (Pb-Free) MC74VHC4316DTG TSSOP16 (Pb-Free) Device 96 Units / Rail MC74VHC4316DTR2G TSSOP16 2500/Tape&Reel (Pb-Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 March, 2008 - Rev. 2 1 Publication Order Number: MC74VHC4316/D MC74VHC4316 XA 1 16 YA 2 15 YB 3 14 XB B ON/OFF CONTROL C ON/OFF CONTROL ENABLE 4 13 5 12 YD 6 11 YC 7 10 XC GND 8 9 VEE FUNCTION TABLE VCC A ON/OFF CONTROL D ON/OFF CONTROL XD Inputs Enable On/Off Control State of Analog Switch L L H H L X On Off Off X = Don't Care. Figure 1. Pin Assignment XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC C ON/OFF CONTROL XD D ON/OFF CONTROL ENABLE 1 15 7 3 YB ANALOG OUTPUTS/INPUTS ANALOG SWITCH 11 ANALOG SWITCH 12 YC LEVEL TRANSLATOR 13 14 ANALOG SWITCH YA LEVEL TRANSLATOR 10 6 2 LEVEL TRANSLATOR 4 5 ANALOG SWITCH YD LEVEL TRANSLATOR ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD Figure 2. Logic Diagram http://onsemi.com 2 PIN 16 = VCC PIN 8 = GND PIN 9 = VEE GND ≥ VEE MC74VHC4316 MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 – 0.5 to + 14.0 V Negative DC Supply Voltage (Ref. to GND) – 7.0 to + 0.5 V Analog Input Voltage VEE – 0.5 to VCC + 0.5 V – 0.5 to VCC + 0.5 V VCC Positive DC Supply Voltage VEE VIS Vin DC Input Voltage (Ref. to GND) I (Ref. to GND) (Ref. to VEE) ± 25 mA 500 450 mW – 65 to + 150 °C DC Current Into or Out of Any Pin PD Power Dissipation in Still Air SOIC Package* TSSOP Package* Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (SOIC or TSSOP Package) °C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *Derating - SOIC Package: – 7 mW/°C from 65° to 125°C TSSOP Package: - 6.1 mW/°C from 65° to 125°C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC Positive DC Supply Voltage (Ref. to GND) 2.0 6.0 V VEE Negative DC Supply Voltage (Ref. to GND) – 6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Ref. to GND) GND VCC V - 1.2 V – 55 + 125 °C 0 0 0 0 1000 600 500 400 ns VIO* Static or Dynamic Voltage Across Switch TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Control or Enable Inputs) (Figure 10) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. http://onsemi.com 3 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance cir‐ cuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. MC74VHC4316 DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25°C v 85°C v 125°C Unit VIH Minimum High-Level Voltage, Control or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Voltage, Control or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Iin Maximum Input Leakage Current, Control or Enable Inputs Vin = VCC or GND VEE = – 6.0 V 6.0 ± 0.1 ± 1.0 ± 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND VIO = 0 V VEE = GND VEE = – 6.0 6.0 6.0 2 4 20 40 40 160 NOTE: mA Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE) Guaranteed Limit VCC V VEE V – 55 to 25°C v 85°C v 125°C Unit Vin = VIH VIS = VCC to VEE IS v 2.0 mA 2.0* 45 4.5 6.0 0.0 0.0 - 4.5 - 6.0 160 90 90 200 110 110 240 130 130 W Vin = VIH VIS = VCC or VEE (Endpoints) IS v 2.0 mA 2.0 4.5 4.5 6.0 0.0 0.0 - 4.5 - 6.0 90 70 70 115 90 90 140 105 105 Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIH VIS = 1/2 (VCC - VEE) IS v 2.0 mA 2.0 4.5 4.5 6.0 0.0 0.0 – 4.5 – 6.0 20 15 15 25 20 20 30 25 25 W Ioff Maximum Off-Channel Leakage Current, Any One Channel Vin = VIL VIO = VCC or VEE Switch Off (Figure 3) 6.0 – 6.0 0.1 0.5 1.0 mA Ion Maximum On-Channel Leakage Current, Any One Channel Vin = VIH VIS = VCC or VEE (Figure 4) 6.0 – 6.0 0.1 0.5 1.0 mA Symbol Ron DRon Parameter Maximum “ON” Resistance Test Conditions NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). *At supply voltage (VCC - VEE) approaching 2.0 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals. http://onsemi.com 4 MC74VHC4316 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND) Guaranteed Limit Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) VCC V – 55 to 25°C v 85°C v 125°C 2.0 4.5 6.0 40 6 5 50 8 7 60 9 8 Unit ns tPLZ, tPHZ Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) 2.0 4.5 6.0 130 40 30 160 50 40 200 60 50 ns tPZL, tPZH Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) 2.0 4.5 6.0 140 40 30 175 50 40 250 60 50 ns - 10 10 10 pF C Maximum Capacitance ON/OFF Control and Enable Inputs Control Input = GND Analog I/O 35 35 35 Feedthrough 1.0 1.0 1.0 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V 15 Power Dissipation Capacitance (Per Switch) (Figure 13)* pF CPD *Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) VCC V VEE V Limit* 25°C fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads – 3 dB RL = 50 W, CL = 10 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 150 160 160 MHz fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 50 – 50 – 50 dB fin = 1.0 MHz, RL = 50 W, CL = 10 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 40 – 40 – 40 Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 W, CL = 50 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 60 130 200 RL = 10 kW, CL = 10 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 30 65 100 fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 70 – 70 – 70 fin = 1.0 MHz, RL = 50 W, CL = 10 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 80 – 80 – 80 Symbol Parameter Test Conditions BW Maximum On–Channel Bandwidth or Minimum Frequency Response (Figure 5) Off–Channel Feedthrough Isolation (Figure 6) - - - THD Feedthrough Noise, Control to Switch (Figure 7) Crosstalk Between Any Two Switches (Figure 12) Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave *Limits not tested. Determined by design and verified by qualification. http://onsemi.com 5 Unit mVPP dB % 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 0.10 0.06 0.04 MC74VHC4316 PLOTTER PROGRAMMABLE POWER SUPPLY - MINI COMPUTER DC ANALYZER + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND VEE Figure 1. On Resistance Test Set-Up http://onsemi.com 6 MC74VHC4316 VCC 16 VEE VCC VCC 16 A A VCC OFF VCC N/C ON O/I VEE VIL VIH 7 8 9 SELECTED CONTROL INPUT 7 8 9 SELECTED CONTROL INPUT VEE VEE Figure 2. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up Figure 3. Maximum On Channel Leakage Current, Test Set-Up VIS VCC VCC 16 fin VCC RL 16 TO dB METER ON 0.1 mF VCC RL RL 7 8 9 SELECTED CONTROL INPUT VEE TO dB METER OFF 0.1 mF CL* RL 7 8 9 fin CL* SELECTED CONTROL INPUT VEE *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 4. Maximum On-Channel Bandwidth Test Set-Up Figure 5. Off-Channel Feedthrough Isolation, Test Set-Up VCC 16 TEST POINT ON/OFF RL 7 8 9 VEE RL VCC CL* ANALOG IN SELECTED CONTROL INPUT 50% GND tPLH CONTROL ANALOG OUT tPHL 50% *Includes all probe and jig capacitance. Figure 6. Feedthrough Noise, Control to Analog Out, Test Set-Up Figure 7. Propagation Delays, Analog In to Analog Out http://onsemi.com 7 MC74VHC4316 VCC 16 ANALOG I/O tr ANALOG O/I TEST POINT ON tf ENABLE VCC 50% CONTROL 50 pF* GND tPLZ tPZL 7 8 9 SELECTED CONTROL INPUT VCC HIGH IMPEDANCE 50% ANALOG OUT tPZH tPHZ 10% VOL 90% VOH 50% HIGH IMPEDANCE *Includes all probe and jig capacitance. Figure 8. Propagation Delay Test Set-Up Figure 9. Propagation Delay, ON/OFF Control to Analog Out VIS 1 POSITIONWHEN TESTING tPHZ AND tPZH 2 POSITIONWHEN TESTING tPLZ AND tPZL 1 VCC RL 2 VCC 0.1 mF 1 kW 16 1 RL ON CL* TEST POINT ON/OFF 2 16 fin VCC ANALOG I/O 50 pF* TEST POINT OFF CONTROL OR ENABLE 7 8 9 8 9 VEE *Includes all probe and jig capacitance. RL CL* VCC SELECTED CONTROL INPUT *Includes all probe and jig capacitance. Figure 10. Propagation Delay Test Set-Up Figure 11. Crosstalk Between Any Two Switches, Test Set-Up (Adjacent Channels Used) VCC A VIS VCC 16 N/C ON/OFF 10 mF N/C VOS 16 fin ON RL 7 8 9 VEE SELECTED CONTROL INPUT 7 8 9 VEE CONTROL SELECTED CONTROL INPUT CL* TO DISTORTION METER VCC *Includes all probe and jig capacitance. Figure 12. Power Dissipation Capacitance Test Set-Up Figure 13. Total Harmonic Distortion, Test Set-Up http://onsemi.com 8 MC74VHC4316 APPLICATIONS INFORMATION 0 FUNDAMENTAL FREQUENCY -10 -20 -30 dBm -40 -50 DEVICE -60 SOURCE -70 -80 -90 -100 1.0 3.0 2.0 FREQUENCY (kHz) Figure 14. Plot, Harmonic Distortion The Enable and Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or VEE through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In the example below, the difference between VCC and VEE is 12 V. Therefore, using the configuration in Figure 15, a maximum analog signal of twelve volts peak-to-peak can be controlled. When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 16. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOSORBs (MOSORBt is an acronym for high current surge protectors). MOSORBs are fast turn-on devices ideally suited for precise dc protection with no inherent wear out mechanism. VCC VCC = 6 V 16 +6V ANALOG I/O ON ANALOG O/I +6V SELECTED CONTROL INPUT VEE 8 16 Dx SELECTED CONTROL INPUT Dx Dx +6V ON -6 V -6 V VCC VCC Dx VEE ENABLE CONTROL INPUTS (VCC OR GND) VEE VEE ENABLE CONTROL INPUTS (VCC OR GND) -6 V Figure 15. Figure 16. Transient Suppressor Application http://onsemi.com 9 MC74VHC4316 VCC = 5 V +5 V 16 ANALOG SIGNALS 16 ANALOG SIGNALS ANALOG SIGNALS ANALOG SIGNALS R* R* R* R* R* VHC4316 7 5 6 14 15 TTL HCT BUFFER VEE = 0 TO -6 V 5 LSTTL/ NMOS ENABLE AND CONTROL 9 INPUTS 8 HC4016A 6 14 VEE = 0 TO -6 V CONTROL INPUTS 9 15 7 R* = 2 TO 10 kW a. Using Pull-Up Resistors b. Using HCT Buffer Figure 17. LSTTL/NMOS to HCMOS Interface VCC = 12 V R1 12 V POWER SUPPLY GND = 6 V R2 VEE = 0 V R1 = R2 VCC 12 VPP ANALOG INPUT SIGNAL R3 C 1 OF 4 SWITCHES ANALOG OUTPUT SIGNAL 12 V 0 R4 R1 = R2 R3 = R4 VEE Figure 18. Switching a 0-to-12 V Signal Using a Single Power Supply (GND ≠ 0 V) CHANNEL 4 1 OF 4 SWITCHES CHANNEL 3 1 OF 4 SWITCHES CHANNEL 2 1 OF 4 SWITCHES CHANNEL 1 1 OF 4 SWITCHES COMMON I/O INPUT 1 OF 4 SWITCHES + OUTPUT LF356 OR EQUIVALENT 0.01 mF 1 2 3 4 CONTROL INPUTS Figure 19. 4-Input Multiplexer Figure 20. Sample/Hold Amplifier http://onsemi.com 10 MC74VHC4316 PACKAGE DIMENSIONS SOIC-16 D SUFFIX CASE 751B-05 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 16 9 -B1 P 8 PL 0.25 (0.010) 8 B M S G R K DIM A B C D F G J K M P R F X 45 _ C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS http://onsemi.com 11 MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC74VHC4316 PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A -V- N F DETAIL E C 0.10 (0.004) -T- SEATING PLANE H D DETAIL E G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 -WJ 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS MOSORB is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC74VHC4316/D