NB4N507A 3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer Description The NB4N507A is a precision clock synthesizer which generates a very low jitter differential PECL output clock. It produces a clock output based on an integer multiple of an input reference frequency. The NB4N507A accepts a standard fundamental mode crystal, using Phase−Locked−Loop (PLL) techniques, will produce output clocks up to 200 MHz. In addition, the PLL circuitry will produce a 50% duty cycle square−wave clock output. The NB4N507A can be programmed to generate a selection of input reference frequency multiples. An exact 155.52 MHz output clock can be generated from a 19.44 MHz crystal and the x8 multiplier selection. The NB4N507A is intended for low output jitter clock generation. http://onsemi.com SOIC−16 D SUFFIX CASE 751B Features • • • • • • • • • Input Crystal Frequency of 10 − 27 MHz Enable Usage of Common Low−Cost Crystal Differential PECL Output Clock Frequencies up to 200 MHz Duty Cycle of 48%/52% Operating Range: VCC = 3.0 V to 5.5 V Ideal for SONET Applications and Oscillator Manufacturers Available in Die Form Packaged in 16−Pin Narrow SOIC Pb−Free Packages are Available* Osc PD CP NB4N507AG AWLYWW CLKOUT CLKOUT PECL VCO MARKING DIAGRAM OE Mult A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package S0 S1 Figure 1. Simplified Logic Block ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 2 1 Publication Order Number: NB4N507A/D NB4N507A VDD X1/CLK Oscillator Buffer Crystal Phase Detector X2 Charge Pump CLKOUT PECL Output VCO CLKOUT Feedback Multiplier Select OE S0 S1 GND Figure 2. NB4N507A Logic Diagram Table 1. CLOCK MULTIPLIER SELECT TABLE X1/CLK 1 16 X2 VDD 2 15 NC VDD 3 14 S0 S1 4 13 OE GND 5 12 NC GND 6 11 NC NC 7 10 NC CLKOUT 8 9 CLKOUT S1 S0 Multiplier L L 9.72X* L M 10X L H 12X M L 6.25X M M 8X M H 5X H L NA H M 3X H H 4X Table 2. OE, OUTPUT ENABLE FUNCTION Figure 3. 16−Pin SOIC (Top View) OE Function 0 Disable 1 Enable *Crystal = 16 MHz, fCLKOUT = 155.52 MHz L = GND H = VDD M = OPEN http://onsemi.com 2 NB4N507A Table 3. PIN DESCRIPTION Pin # SOIC−16 Name 1 X1/CLK Crystal Input Crystal or Clock Input 2,3 VDD Power Supply Positive Supply Voltage (3.0 V to 5.5 V) I/O Description 4 S1 Tri−Level Input Multiplier Select Pin; When Left Open, Defaults to VDD B 2 5,6 GND Power Supply Negative Supply Voltage 7,10,11,12, 15 NC No Connect 8 CLKOUT PECL Output Non−inverted differential PECL clock output. 9 CLKOUT PECL Output Inverted differential PECL clock output. 13 OE (LV)CMOS/(LV)TTL Input 14 S0 Tri−Level Input 16 X2 Crystal Input Output Enable for the CLKOUT/CLKOUT Outputs. Outputs are enabled when HIGH or when left open; OE pin has internal pullup resistor. Disables both outputs when LOW. CLKOUT goes LOW, CLKOUT goes HIGH. Multiplier Select Pin; When Left Open, Defaults to VDD B 2 Crystal Input Table 4. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Charged Device Model > 1 kV > 150 V > 1 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 1145 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 GND = 0 V Rating Unit 6 V GND − 0.5 ≤ VI ≤ VDD + 0.5 V VCC Positive Power Supply VI Input Voltage TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−16 100 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 2) SOIC−16 33 to 36 °C/W Tsol Wave Solder 265 265 °C Pb Pb−Free < 3 sec @ 248°C < 3 sec @ 260°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 3 NB4N507A Table 6. DC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C (Note 3)) Min Typ Max Unit IDD Symbol Power Supply Current (does not include output load resistor current) Characteristic VDD = 5 V VDD = 3.3 V 15 10 27 23 35 30 mA mA VOH Output HIGH Voltage (Notes 5 & 6) VDD = 5 V VDD = 3.3 V 3.95 2.57 4.05 2.67 4.15 2.77 V VOL Output LOW Voltage (Notes 5 & 6) VDD = 5 V VDD = 3.3 V 3.12 1.90 3.20 2.00 3.30 2.10 V VIH Input HIGH Voltage (Note 4) S0, S1, X1 OE VDD – 0.5 2.0 VDD V VIL Input LOW Voltage,(Note 4) S0, S1, X1 OE 0 0.5 0.8 V Cx Internal Crystal Capacitance, X1 & X2 Cin Input Capacitance, S0, S1, OE 0 pF 5.0 pF NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. PECL output parameters vary 1:1 with VDD. 4. S0 and S1 default to VDD B 2 when left open. Table 7. AC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C (Note 5)) Symbol Characteristic Min Typ Max Unit fXtal Crystal Input Frequency 10 27 MHz fCLK Input Clock Frequency (Note 8) 5 52 MHz fOUT Output Frequency Range 50 200 MHz Vout pk−pk Output Amplitude 550 DC Clock Output Duty Cycle (Note 8) 48 PLLBW PLL Bandwidth (Note 8) 10 tjitter (pd) Period Jitter (RMS, 1s, 10,000 Cycles) tjitter (pd) Period Jitter (Peak−to−Peak, 10,000 Cycles) tr/tf Output Rise and Fall Times (Note 8) 50 680 mV 52 % kHz 270 10 ps $20 ps 500 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. PECL outputs loaded with external resistors for proper operation (see Figure 4). 6. VOH and VOL can be set by the external resistors, which can be modified. 7. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL is the specified crystal load capacitance: Crystal caps (pF) = (CL−5) x 2. So, for a crystal with 16 pF load capacitance, use two 22 pF caps. 8. Guaranteed by design and characterization. http://onsemi.com 4 NB4N507A VDD NB4N507 GND z = 50 W VDD z = 50 W D 62 W VDD PECL Driver 62 W PECL Receiver D z = 50 W z = 50 W 270 W GND GND GND Figure 4. Recommended PECL Output Loading for the NB4N507A APPLICATIONS INFORMATION High Frequency Differential PECL Oscillators: The NB4N507A, along with a low frequency fundamental mode crystal, can build a high frequency differential PECL output oscillator. For example, a 10 MHz crystal connected to the NB4N507A with the 12X output selected (S1 = 0, S0 = 1) produces a 120 MHz PECL output clock. High Frequency VCXO: The bandwidth of the PLL is guaranteed to be greater than 10 kHz. This means that the PLL will track any modulation on the input with a frequency of less than 10 kHz. By using this property, a low frequency VCXO can be built. The output can then be multiplied by the NB4N507A, thereby producing a high frequency VCXO. High Frequency TCXO: Extending the previous application, an inexpensive, low frequency TCXO can be built and the output frequency can be multiplied using the NB4N507A. Since the output of the chip is phase−locked to the input, the NB4N507A has no temperature dependence, and the temperature coefficient of the combined system is the same as that of the low frequency TCXO. Decoupling and External Components The NB4N507A requires a 0.01 mF decoupling capacitor to be connected between VDD and GND on pins 2 and 5. It must be connected close to the NB4N507A. Other VDD and GND connections should be connected to those pins, or to the VDD and GND planes on the board. Another four resistors are needed for the PECL outputs as shown on the block diagram in Figure 1. Suggested values of these resistors are shown in the Block Diagram, but they can be varied to change the differential pair output swing, and the DC level. ORDERING INFORMATION Package Shipping † NB4N507AD SOIC−16 48 Units / Rail NB4N507ADG SOIC−16 (Pb−Free) 48 Units / Rail NB4N507ADR2 SOIC−16 2500 / Tape & Reel NB4N507ADR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NB4N507A Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 6 NB4N507A PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE J −A− 16 9 1 8 −B− P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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