ICST AV9107C-20 Frequency generator for fibre channel system Datasheet

Integrated
Circuit
Systems, Inc.
AV9107C-19
AV9107C-20
Frequency Generator for Fibre Channel Systems
General Description
Features
The AV9107C-19 and AV9107C-20 are high-speed clock
generators designed to support fibre channel system
requirements. The AV9107C-19 generates a single copy of
the 106.25 MHz from a 17 MHz crystal. The AV9107C-20
provides a second copy of the 106.25 MHz clock with
output skew less than ±100ps.
•
An exact frequency multiplying ratio ensures better than
±100 ppm frequency accuracy using a standard AT crystal
with external load capacitors (typically 33pF±5% for an
18pF load crystal). Achieving ±100 ppm over four years
requires the crystal to have a ±20 ppm initial accuracy, ±30
ppm tempera-ture and ±5 ppm/year aging coefficients.
•
•
•
•
•
•
•
Generates one or two 106.25 MHz clocks from a
17 MHz crystal
Less than 60ps one sigma jitter
Less than ±200ps absolute jitter
Output skew less than ±100ps on two channel
version (-20)
Rise/fall times less than 4ns driving 15pF
On-chip loop filter components
3.0V-5.5V supply range
8-pin, 150-mil SOIC package
Applications
•
Specifically designed to support the high-speed
clocking requirements of fibre channel systems
Block Diagram
AV 9107-19 20 RevC091897P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
AV9107C-19
AV9107C-20
Pin Configurations
8-Pin SOIC
8-Pin SOIC
Functionality
OE
X1, X2
(MHz)
FOUT
(MHz)
1
17.00
106.25
0
X
Tristate
Pin Descriptions
PIN
NUMBER
PIN NAME
1
2
AVSS
VSS
3
4
X1
X2
5
OE
6
7
8
TYPE
PWR
PRW
DESCRIPTION
Analog ground.
Digital Ground.
IN
IN
Crystal or clock input to device; nominally 17.0 MHz. Requires external load capacitors.
Crystal drive output from device. Requires external load capacitors.
IN
Output enable causes all outputs to tristate when at a logic low level; has a pull-up.
VDD
CLK2
AVDD
VDD+AVDD
PWR
OUT
PWR
PWR
+3.3 or +5.0 volt supply (-19).
106.25 MHz clock output (-20).
Analog power. (Must equal digital power voltage) (-19).
Digital and analog power, +3.3 or +5.0 volt supply (-20).
CLK1
OUT
106.25 MHz clock output.
2
AV9107C-19
AV9107C-20
Absolute Maximum Ratings
AVDD, VDD referenced to GND . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 5.0V
Operating VDD = +4.5V to +5.5V; TA =0°C to 70°C unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
VIL
-
-
0.8
V
Input High Voltage
VIH
2.0
-
-
V
Input Low Current
IIL
VIN=0V (Pull-up input)
-16.0
-6.0
-
µA
Input High Current
IIH
VIN=VDD
-2.0
-
2.0
µA
Output Low Voltage1
VOL
IOL=10mA
-
0.15
0.40
V
1
VOH
IOH=-30mA
2.4
3.25
-
V
IOL
VOL=0.8V
22.0
35.0
-
mA
Output High Current 1
IOH
VOH=2.0V
-
-50.0
-35.0
mA
Supply Current
IDD
Unloaded
-
22.0
45.0
mA
Pull-up Resistor 1
Rpu
-
380.0
700.0
k ohms
Rise Time1
Tr1
15pF load, 0.8 to 2.0V
-
0.8
1.4
ns
Fall Time
Tf1
15pF load, 2.0 to 0.8V
-
0.7
1.2
ns
Rise Time1
Tr2
15pF load, 20% to 80%
-
1.5
2.0
ns
Fall Time1
Tf2
15pF load, 80% to 20%
-
1.0
1.5
ns
42.0
49.0
55.0
%
-
30.0
60.0
ps
Output High Voltage
Output Low Current1
AC Characteristics
1
Duty Cycle
1
Dt
15pF load @ 1.4V
Jitter, One Sigma1
Tj1s
15pF load
Jitter, Absolute1
Tjab
15pF load
-200.0
200.0
ps
Output Skew,1 Clock 1 to 2
tsk1
15pF load @ 1.4V (-20 only)
-100.0
-20.0
100.0
ps
Input Frequency1
Fi
11.0
17.0
19.0
MHz
Fo
2.0
106.25
120.0
MHz
Tpu
-
7.58
18.0
ms
Output Frequency
1
Power-up Time1
Transition Time
1
Crystal Input Capacitance
Note 1:
1
Tft
8 to 66.6 MHz
-
6.0
13.0
ms
Cinx
X1 (Pin 3)
X2 (Pin 4)
-
5.0
-
pF
Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
AV9107C-19
AV9107C-20
Electrical Characteristics at 3.3V
Operating VDD = +3.0V to +3.7V; TA =0°C to 70°C unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
VIL
-
-
0.20VDD
V
Input High Voltage
VIH
0.7VDD
-
-
V
Input Low Current
IIL
VIN=0V (Pull-up input)
-7.0
-2.5
-
µA
Input High Current
IIH
VIN=VDD
-2.0
-
2.0
µA
Output Low Voltage1
VOL
IOL=6mA
-
0.05VDD
0.1VDD
V
Output High Voltage1
VOH
IOH=-5mA
0.85VDD
0.92VDD
-
V
1
IOL
VOL=0.2VDD
15.0
22.0
-
mA
Output High Current 1
IOH
VOH=0.7VDD
-
-17.0
-10.0
mA
Supply Current
IDD
Unloaded
-
14.0
30.0
mA
Pull-up Resistor 1
Rpu
-
550.0
900.0
k ohms
Output Low Current
AC Characteristics
Rise Time
1
Fall Time1
1
Tr1
15pF load, 0.8 to 2.0V
-
1.6
3.5
ns
Tf1
15pF load, 2.0 to 0.8V
-
0.9
1.5
ns
Tr2
15pF load, 20% to 80%
-
1.8
2.5
ns
Fall Time1
Tf2
15pF load, 80% to 20%
-
1.1
2.5
ns
Duty Cycle1
Dt
15pF load @ 1.4V
30.0
40.0
50.0
%
Rise Time
Jitter, One Sigma
1
Tj1s
15pF load
-
30.0
80.0
ps
Tjab
15pF load
-200.0
-
200.0
ps
Output Skew, Clock 1 to 2
tsk1
15pF load @ 1.4V (-20 only)
-100.0
-25.0
100.0
ps
Input Frequency1
Fi
11.0
17.0
19.0
MHz
Output Frequency1
Fo
2.0
106.25
120.0
MHz
Jitter, Absolute1
1
Power-up Time
1
-
7.58
18.0
ms
Transition Time1
Tft
8 to 66.6 MHz
-
6.0
13.0
ms
Crystal Input Capacitance1
Cinx
X1 (Pin 3)
X2 (Pin 4)
-
5.0
-
pF
Note 1:
Tpu
Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
AV9107C-19
AV9107C-20
8-Pin Plastic SOIC Package
Ordering Information
AV9107C-19CS08 or AV9107C-20CS08
Example:
XXX XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3” SOIC or .6” DIP; None=Standard Width
Package Type
S=SOIC
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
5
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
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