Revised February 2000 DM96L02 Dual Retriggerable Resettable Monostable Multivibrator General Description Features The DM96L02 is a dual TTL monostable multivibrator with trigger mode selection, reset capability, rapid recovery, internally compensated reference levels and high speed capability. Output pulse duration and accuracy depend on external timing components, and are therefore under user control for each application. It is well suited for a broad variety of applications, including pulse delay generators, square wave generators, long delay timers, pulse absence detectors, frequency detectors, clock pulse generators and fixed-frequency dividers. Each input is provided with a clamp diode to limit undershoot and minimize ringing induced by fast fall times acting on system wiring impedances. ■ Retriggerable, 0% to 100% duty cycle ■ DC level triggering, insensitive to transition times ■ Leading or trailing-edge triggering ■ Complementary outputs with active pull-ups ■ Pulse width compensation for ∆VCC and ∆TA ■ 50 ns to ∞ output pulse width range ■ Optional retrigger lock-out capability ■ Resettable, for interrupt operations Ordering Code: Order Number Package Number DM96L02N N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Logic Symbol VCC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names RX © 2000 Fairchild Semiconductor Corporation DS010203 Description I0 Trigger Input (Active Falling Edge) I1 Trigger Input (Active Rising Edge) CD Direct Clear Input (Active LOW) Q Positive Pulse Output Q Complementary Pulse Output CX External Capacitor Connection External Resistor Connection www.fairchildsemi.com DM96L02 Dual Retriggerable Resettable Monostable Multivibrator March 1989 DM96L02 Functional Block Diagram Operation Notes 4. OUTPUT PULSE WIDTH—An external resistor RX and an external capacitor CX are required, as shown in the functional block diagram. To minimize stray capacitance and noise pickup, RX and CX should be located as close as possible to the circuit. In applications which require remote trimming of the pulse width, as with a variable resistor, RX should consist of a fixed resistor in series with the variable resistor; the fixed resistor should be located as close as possible to the circuit. The output pulse width tW is defined as follows, where RX is in kΩ, CX is in pF and tW is in ns. 1. TRIGGERING—can be accomplished by a positivegoing transition on pin 4 (12) or a negative-going transition on pin 5 (11). Triggering begins as a signal crosses the input VIL:VIH threshold region; this activates an internal latch whose unbalanced cross-coupling causes it to assume a preferred state. As the latch output goes LOW it disables the gates leading to the Q output and, through an inverter, turns on the capacitor discharge transistor. The inverted signal is also fed back to the latch input to change its state and effectively end the triggering action; thus the latch and its associated feedback perform the function of a differentiator. tW = 0.33 RXCX (1 + 3/RX) for CX ≥ 103 pF The emitters of the latch transistors return to ground through an enabling transistor which must be turned off between successive triggers in order for the latch to proceed through the proper sequence when triggering is desired. Pin 5 (11) must be HIGH in order to trigger at pin 4 (12); conversely, pin 4 (12) must be LOW in order to trigger at pin 5 (11). 16 kΩ ≤ RX ≤ 220 kΩ for 0°C to +75°C 20 kΩ ≤ RX ≤ 100 kΩ for −55°C to +125°C CX may vary from 0 to any value. For pulse widths with CX less than 103 pF see Figure 1. 5. SETUP AND RELEASE TIMES—The setup times listed below are necessary to allow the latch-enabling transistor to turn off and the node voltages within the input latch to stabilize, thus insuring proper cycling of the latch when the next trigger occurs. The indicated release times (equivalent to trigger duration) allow time for the input latch to cycle and its signal to propagate. 6. RESET OPERATION—A LOW signal on CD, pin 3 (13), will terminate an output pulse, causing Q to go LOW and Q to go HIGH. As long as CD is held LOW, a delay period cannot be initiated nor will attempted triggering cause spikes at the outputs. A reset pulse duration, in the LOW state, of 25 ns is sufficient to insure resetting. If the reset input goes LOW at the same time that a trigger transition occurs, the reset will dominate and the outputs will not respond to the trigger. If the reset input goes HIGH coincident with a trigger transition, the circuit will respond to the trigger. 2. RETRIGGERING—In a normal cycle, triggering initiates a rapid discharge of the external timing capacitor, followed by a ramp voltage run-up at pin 2 (14). The delay will time out when the ramp voltage reaches the upper trigger point of a Schmitt circuit, causing the outputs to revert to the quiescent state. If another trigger occurs before the ramp voltage reaches the Schmitt threshold, the capacitor will be discharged and the ramp will start again without having disturbed the output. The delay period can therefore be extended for an arbitrary length of time by insuring that the interval between triggers is less than the delay time, as determined by the external capacitor and resistor. 3. NON-RETRIGGERABLE OPERATION—Retriggering can be inhibited logically, by connecting pin 6 (10) back to pin 4 (12) or by connecting pin 7 (9) back to pin 5 (11). Either hook-up has the effect of keeping the latchenabling transistor turned on during the delay period, which prevents the input latch from cycling as discussed above in the section on triggering. Input to Pin 5 (11) Pin 4 (12) = L www.fairchildsemi.com Pin 3 (13) = H Input to Pin 4 (12) 2 Pins 5 (11) and 3 (13) = H DM96L02 96L02 Pulse Width vs. RX and CX FIGURE 1. Typical Characteristics tw vs. VCC tw(min) vs. TA INPUT PULSE f ≅ 25 kHz Amp ≅ 3.0V Width ≅ 100 ns tr = tf ≤ 10 ns FIGURE 2. tw vs. TA 3 www.fairchildsemi.com DM96L02 Absolute Maximum Ratings(Note 1) Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V Operating Free Air Temperature Range Storage Temperature Range 0°C to +70°C −65°C to +150° Recommended Operating Conditions Symbol Parameter Conditions Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.7 V IOH HIGH Level Output Current 0.36 mA IOL LOW Level Output Current 4.8 mA TA Free Air Operating Temperature 70 °C tW (L) Minimum Input Pulse tW (H) Width, I1, I0 tW (min) Minimum Output Pulse Width at Q, Q 2 V V 0 VCC = 5.0V ns VCC = 5.0V, RX = 20 kΩ, 110 ns CX = 0, CL = 15 pF tW Output Pulse Width, Q, Q VCC = 5.0V, RX = 39 kΩ, 12.4 15.2 µs 220 kΩ CX = 1000 pF RX Timing Resistor Range www.fairchildsemi.com 4 over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −10 mA VOH HIGH Level Output Voltage VCC = Min, IOH = Max, VOL LOW Level Output Voltage VCC = Min, IOL = Max, Min Typ Max (Note 2) −1.5 2.4 Units V V VIL = Max, VIH = Min 0.3 V 1 mA VIL = Min, VIL = Max II Input Current @ Max VCC = Max, VI = 5.5V Input Voltage IIH HIGH Level Input Current VCC = Max, VI = 2.4V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.3V −0.4 mA IOS Short Circuit Output Current VCC = Max (Note 3) VO = 1.0V −13.0 mA ICC Supply Current VCC = Max (Note 4) 16 mA Max Units 80 ns 65 ns −2.0 Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs open and all inputs grounded. Switching Characteristics VCC = +5.0V, TA = +25°C Symbol tPLH Parameter Conditions Propagation Delay I0 to Q, VCC = 5.0V, RX = 20 kΩ I1 to Q CX = 0, CL = 15 pF Propagation Delay I0 to Q, VCC = 5.0V, RX = 20 kΩ I1 to Q CX = 0, CL = 15 pF tPLH Propagation Delay CD to Q, VCC = 5.0V, RX = 39 kΩ tPHL CD to Q CX = 1000 pF tPHL 5 Min ns www.fairchildsemi.com DM96L02 Electrical Characteristics DM96L02 Dual Retriggerable Resettable Monostable Multivibrator Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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