ATMEL ATA5811-PLQW Uhf ask/fsk transceiver Datasheet

Features
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High FSK Sensitivity: –106 dBm at 20 Kbit/s/–109.5 dBm at 2.4 Kbit/s (433.92 MHz)
High ASK Sensitivity: –112.5 dBm at 10 Kbit/s/–116.5 dBm at 2.4 Kbit/s (433.92 MHz)
Low Supply Current: 10.5 mA in RX and TX Mode (3V/TX with 5 dBm)
Data Rate 1 to 20 Kbit/s Manchester FSK, 1 to 10 Kbit/s Manchester ASK
ASK/FSK Receiver Uses a Low-IF Architecture with High Selectivity, Blocking and Low
Intermodulation (Typical Blocking 55 dB at ±750 kHz/61 dB at ±1.5 MHz and
70 dB at ±10 MHz, System I1dBCP = –30 dBm/System IIP3 = –20 dBm)
226 kHz IF Frequency with 30 dB Image Rejection and 170 kHz Usable IF Bandwidth
Transmitter Uses Closed Loop Fractional-N Synthesizer for FSK Modulation with a
High PLL Bandwidth and an Excellent Isolation between PLL and PA
Tolerances of XTAL Compensated by Fractional-N Synthesizer with 800 Hz RF
Resolution
Integrated RX/TX-Switch, Single-ended RF Input and Output
RSSI (Received Signal Strength Indicator)
Communication to Microcontroller with SPI Interface Working at Maximum 500 kBit/s
Configurable Self Polling and RX/TX Protocol Handling with FIFO-RAM Buffering of
Received and Transmitted Data
5 Push Button Inputs and One Wake-up Input are Active in Power-down Mode
Integrated XTAL Capacitors
PA Efficiency: up to 38% (433 MHz/10 dBm/3V)
Low Inband Sensitivity Change of Typically ±1.8 dB within ±58 kHz Center Frequency
Change in the Complete Temperature and Supply Voltage Range
Supply Voltage Switch, Supply Voltage Regulator, Reset Generation, Clock/Interrupt
Generation and Low Battery Indicator for Microcontroller
Fully Integrated PLL with Low Phase Noise VCO and PLL Loop Filter
Sophisticated Threshold Control and Quasi Peak Detector Circuit in the Data Slicer
Power Management via Different Operation Modes
433.92 MHz, 868.3 MHz and 315 MHz without External VCO and PLL Components
Inductive Supply with Voltage Regulator if Battery is Empty (AUX Mode)
Efficient XTO Start-up Circuit (> –1.5 kΩ Worst Case Start Impedance)
Changing of Modulation Type ASK/FSK and Data Rate without Component Changes
Minimal External Circuitry Requirements for Complete System Solution
Adjustable Output Power: 0 to 10 dBm Adjusted and Stabilized with External Resistor
ESD Protection at all Pins (2 kV HBM, 200 V MM)
Supply Voltage Range: 2.4V to 3.6V or 4.4V to 6.6V
Temperature Range: –40°C to +105°C
Small 7 × 7 mm QFN48 Package
UHF ASK/FSK
Transceiver
ATA5811
ATA5812
4689F–RKE–08/06
Applications
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Automotive Keyless Entry and Passive Entry Go Systems
Access Control Systems
Remote Control Systems
Alarm and Telemetry Systems
Energy Metering
Home Automation
Benefits
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No SAW Device Needed in Key Fob Designs to Meet Automotive Specifications
Low System Cost Due to Very High System Integration Level
Only One Crystal Needed in System
Less Demanding Specification for the Microcontroller Due to Handling of Power-down Mode,
Delivering of Clock, Reset, Low Battery Indication and Complete Handling of Receive/Transmit
Protocol and Polling
• Single-ended Design with High Isolation of PLL/VCO from PA and the Power Supply Allows a
Loop Antenna in the Key Fob to Surround the Whole Application
1. General Description
The ATA5811/ATA5812 is a highly integrated UHF ASK/FSK single-channel half-duplex transceiver with low power consumption supplied in a small QFN48 package. The receive part is built
as a fully integrated low-IF receiver, whereas direct PLL modulation with the fractional-N synthesizer is used for FSK transmission and switching of the power amplifier for ASK transmission.
The device supports data rates of 1 Kbit/s to 20 Kbit/s (FSK) and 1 Kbit/s to 10 Kbit/s (ASK) in
Manchester, Bi-phase and other codes in transparent mode. The ATA5811 can be used in the
433 MHz to 435 MHz and the 868 MHz to 870 MHz band, the ATA5812 in the 314 MHz to
316 MHz band. The very high system integration level results in few numbers of external components needed.
Due to its blocking and selectivity performance, together with the additional 15 dB to 20 dB loss
and the narrow bandwidth of a typical key fob loop antenna, a bulky blocking SAW is not needed
in the key fob or sensor application. Additionally, the building blocks needed for a typical RKE
and access control system on both sides, the base and the mobile stations, are fully integrated.
Its digital control logic with self polling and protocol generation enables a fast challenge
response systems without using a high-performance microcontroller. Therefore, the
ATA5811/ATA5812 contains a FIFO buffer RAM and can compose and receive the physical
messages themselves. This provides more time for the microcontroller to carry out other functions such as calculating crypto algorithms, composing the logical messages and controlling
other devices. Due to that, a standard 4-/8-bit microcontroller without special periphery and
clocked with the CLK output of about 4.5 MHz is sufficient to control the communication link.
This is especially valid for passive entry and access control systems, where within less than
100 ms several challenge response communications with arbitration of the communication partner have to be handled.
It is hence possible to design bi-directional RKE and access control systems with a fast challenge response crypto function with the same PCB board size and with the same current
consumption as uni-directional RKE systems.
2
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
Figure 1-1.
System Block Diagram
ATA5811/ATA5812
RF transceiver
Antenna
Digital control
logic
Power supply
Microcontroller
Microcontroller
interface
Matching
4 to 8
XTO
Pinning QFN48
NC
NC
RX_ACTIVE
T1
T2
T3
T4
T5
PWR_ON
RX_TX1
RX_TX2
CDEM
Figure 1-2.
1
48 47 46 45 44 43 42 41 40 39 38 37
36
2
35
3
34
4
33
5
32
6
7
ATA5811/ATA5812
31
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
RSSI
CS
DEM_OUT
SCK
SDI_TMDI
SDO_TMDO
CLK
IRQ
N_RESET
VSINT
NC
XTAL2
NC
NC
NC
AVCC
VS2
VS1
VAUX
TEST1
DVCC
VSOUT
TEST2
TXAL1
NC
NC
NC
RF_IN
NC
433_N868
NC
R_PWR
PWR_H
RF_OUT
NC
NC
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4689F–RKE–08/06
Table 1-1.
4
Pin Description
Pin
Symbol
Function
1
NC
Not connected
2
NC
Not connected
3
NC
Not connected
4
RF_IN
5
NC
6
433_N868
RF input
Not connected
Selects RF input/output frequency range
7
NC
8
R_PWR
Not connected
Resistor to adjust output power
9
PWR_H
Pin to select output power
10
RF_OUT
RF output
11
NC
Not connected
12
NC
Not connected
13
NC
Not connected
14
NC
Not connected
15
NC
16
AVCC
Not connected
17
VS2
Power supply input for voltage range 4.4V to 6.6V
18
VS1
Power supply input for voltage range 2.4V to 3.6V
Blocking of the analog voltage supply
19
VAUX
Auxiliary supply voltage input
20
TEST1
Test input, at GND during operation
21
DVCC
Blocking of the digital voltage supply
22
VSOUT
Output voltage power supply for external devices
23
TEST2
Test input, at GND during operation
24
XTAL1
Reference crystal
25
XTAL2
Reference crystal
26
NC
Not connected
27
VSINT
28
N_RESET
Microcontroller Interface supply voltage
29
IRQ
Interrupt request
30
CLK
Output to clock a connected microcontroller
31
SDO_TMDO
32
SDI_TMDI
33
SCK
34
DEM_OUT
Output pin to reset a connected microcontroller
Serial data out/transparent mode data out
Serial data in/transparent mode data in
Serial clock
Demodulator open drain output signal
35
CS
36
RSSI
Chip select for serial interface
37
CDEM
38
RX_TX2
GND pin to decouple LNA in TX mode
39
RX_TX1
Switch pin to decouple LNA in TX mode
40
PWR_ON
Input to switch on the system (active high)
41
T5
Output of the RSSI amplifier
Capacitor to adjust the lower cut-off frequency data filter
Key input 5 (can also be used to switch on the system (active low)
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
Table 1-1.
Pin Description (Continued)
Pin
Symbol
Function
42
T4
Key input 4 (can also be used to switch on the system (active low)
43
T3
Key input 3 (can also be used to switch on the system (active low)
44
T2
Key input 2 (can also be used to switch on the system (active low)
45
T1
Key input 1 (can also be used to switch on the system (active low)
46
RX_ACTIVE
47
NC
Not connected
48
NC
Not connected
Indicates RX operation mode
GND
Figure 1-3.
Ground/backplane
Block Diagram
AVCC
433_N868
RX_ACTIVE
RF transceiver
DVCC
Digital control logic
Power
supply
Frontend Enable
R_PWR
PA
RX_TX1
TX
RX_TX2
RF_IN
VSOUT
TX_DATA (FSK)
Switches
regulators
wakeup
reset
RX/TX
PWR_H
LNA
CDEM
Fractional-N
frequency
synthesizer
Signal
processing
(Mixer, IF
filter, IF
amplifier,
demodulator,
data filter
data slicer)
FREQ
VS1
VAUX
PA_Enable (ASK)
RF_OUT
VS2
9
FREF
PWR_ON
T1
Demod_Out
TX/RX - data buffer
control register
status register
polling circuit
bit check logic
T2
T3
T4
T5
Reset
RSSI
XTAL1
XTO
XTAL2
DEM_OUT
CLK
TEST
N_RESET
TES2
IRQ
CS
Microcontroller
interface
SCK
SPI
SDI_TMDI
SDO_TMDO
VSINT
GND
5
4689F–RKE–08/06
2. Typical Key Fob or Sensor Application with 1 Battery
Typical RKE Key Fob or Sensor Application, 433.92 MHz, 1 Battery
C11
NC
RX_TX2
RX_TX1
T5
PWR_ON
T4
T3
T2
RX_ACTIVE
NC
NC
T1
C6
NC
C7
CDEM
RSSI
CS
DEM_OUT
RF_IN
SCK
NC
SDI_TMDI
433_N868
R1
L2
CLK
R_PWR
IRQ
PWR_H
N_RESET
RF_OUT
VSOUT
DVCC
TEST1
VAUX
VS1
VS2
AVCC
NC
NC
C10
VSINT
NC
NC
NC
C8
Microcontroller
SDO_TMDO
ATA5811/ATA5812
NC
TEST2
AVCC
C5
VCC
VSS
NC
TXAL1
20 mm x 0.4 mm
L1
NC
Figure 2-1.
XTAL2
C9
Loop antenna
C1
C4
13.25311 MHz
C2
+ Lithium cell
C3
Figure 2-1 shows a typical 433.92 MHz RKE key fob or sensor application with one battery The
external components are 11 capacitors, 1 resistor, 2 inductors and a crystal. C1 to C4 are 68 nF
voltage supply blocking capacitors. C5 is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed
capacitor used for the internal quasi peak detector and for the highpass frequency of the data filter. C7 to C11 are RF matching capacitors in the range of 1 pF to 33 pF. L1 is a matching inductor
of about 5.6 nH to 56 nH. L2 is a feed inductor of about 120 nH. A load capacitor of 9 pF for the
crystal is integrated. R1 is typically 22 kΩ and sets the output power to about 5.5 dBm. The loop
antenna’s quality factor is somewhat reduced by this application due to the quality factor of L2
and the RX/TX switch. On the other hand, this lower quality factor is necessary to have a robust
design with a bandwidth that is broad enough for production tolerances. Due to the single-ended
and ground-referenced design, the loop antenna can be a free-form wire around the application
as it is usually employed in RKE uni-directional systems. The ATA5811/ATA5812 provides sufficient isolation and robust pulling behavior of internal circuits from the supply voltage as well as
an integrated VCO inductor to allow this. Since the efficiency of a loop antenna is proportional to
the square of the surrounded area it is beneficial to have a large loop around the application
board with a lower quality factor to relax the tolerance specification of the RF components and to
get a high antenna efficiency in spite of their lower quality factor.
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ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
3. Typical Car or Sensor Base-station Application
Typical RKE Car or Sensor Base-station Application, 433.92 MHz
L3
NC
RX_TX2
RX_TX1
T4
T3
T2
T5
PWR_ON
NC
NC
T1
CDEM
RSSI
CS
DEM_OUT
RF_IN
SCK
NC
SDI_TMDI
433_N868
L2
RFOUT
CLK
R_PWR
IRQ
PWR_H
N_RESET
RF_OUT
C10
DVCC
TEST1
VAUX
VS1
VS2
AVCC
NC
C8
VSINT
NC
NC
NC
L1
NC
50Ω
connector
Microcontroller
SDO_TMDO
ATA5811/ATA5812
NC
TEST2
R1
VSOUT
AVCC
C5
VCC
VSS
NC
TXAL1
SAW-Filter
C6
NC
C7
RX_ACTIVE
C11
NC
L4
20 mm x 0.4 mm
Figure 3-1.
XTAL2
C9
C12
C1
C2
13.25311 MHz
C4
VCC = 4.75V to 5.25V
C3
Figure 3-1 shows a typical 433.92 MHz VCC = 4.75V to 5.25V RKE car or sensor base-station
application. The external components are 12 capacitors, 1 resistor, 4 inductors, a SAW filter and
a crystal. C1 and C3 to C4 are 68 nF voltage supply blocking capacitors. C2 and C12 are 2.2 µF
supply blocking capacitors for the internal voltage regulators. C5 is a 10 nF supply blocking
capacitor. C6 is a 15 nF fixed capacitor used for the internal quasi peak detector and for the
highpass frequency of the data filter. C7 to C11 are RF matching capacitors in the range of 1 pF
to 33 pF. L2 to L4 are matching inductors of about 5.6 nH to 56 nH. A load capacitor for the crystal of 9 pF is integrated. R1 is typically 22 kΩ and sets the output power at RF_OUT to about
10 dBm. Since a quarter wave or PCB antenna, which has high efficiency and wide band operation, is typically used here, it is recommended to use a SAW filter to achieve high sensitivity in
case of powerful out-of-band blockers. L1, C10 and C9 together form a lowpass filter, which is
needed to filter out the harmonics in the transmitted signal to meet regulations. An internally regulated voltage at pin VSOUT can be used in case the microcontroller only supports 3.3V
operation, a blocking capacitor with a value of C12 = 2.2 µF has to be connected to VSOUT in
any case.
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4689F–RKE–08/06
4. Typical Key Fob Application, 2 Batteries
Typical RKE Key Fob Application, 433.92 MHz, 2 Batteries
C11
NC
RX_TX2
RX_TX1
T4
T3
T2
T5
PWR_ON
NC
NC
T1
NC
C6
RX_ACTIVE
C7
CDEM
RSSI
CS
DEM_OUT
RF_IN
SCK
NC
SDI_TMDI
433_N868
R1
L2
CLK
R_PWR
IRQ
PWR_H
N_RESET
RF_OUT
VSOUT
DVCC
TEST1
VAUX
VS1
VS2
AVCC
NC
NC
C10
VSINT
NC
NC
NC
C8
Microcontroller
SDO_TMDO
ATA5811/ATA5812
NC
TEST2
AVCC
C5
VCC
VSS
NC
TXAL1
20 mm x 0.4 mm
L1
NC
Figure 4-1.
XTAL2
C9
Loop antenna
C1
C2
C4
13.25311 MHz
+
+
Lithium cells
C3
Figure 4-1 shows a typical 433.92 MHz 2-battery RKE key fob or sensor application. The external components are 11 capacitors, 1 resistor, 2 inductors and a crystal. C1 and C4 are 68 nF
voltage supply blocking capacitors. C2 and C3 are 2.2 µF supply blocking capacitors for the internal voltage regulators. C5 is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed capacitor
used for the internal quasi peak detector and for the highpass frequency of the data filter. C7 to
C11 are RF matching capacitors in the range of 1 pF to 33 pF. L1 is a matching inductor of about
5.6 nH to 56 nH. L2 is a feed inductor of about 120 nH. A load capacitor for the crystal of 9 pF is
integrated. R1 is typically 22 kΩ and sets the output power to about 5.5 dBm.
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ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
5. RF Transceiver
According to Figure 1-3 on page 5, the RF transceiver consists of an LNA (Low-Noise Amplifier),
PA (Power Amplifier), RX/TX switch, fractional-N frequency synthesizer and the signal processing part with mixer, IF filter, IF amplifier, FSK/ASK demodulator, data filter and data slicer.
In receive mode the LNA pre-amplifies the received signal which is converted down to 226 kHz,
filtered and amplified before it is fed into an FSK/ASK demodulator, data filter and data slicer.
The RSSI (Received Signal Strength Indicator) signal and the raw digital output signal of the
demodulator are available at the pins RSSI and DEM_OUT. The demodulated data signal
Demod_Out is fed to the digital control logic where it is evaluated and buffered as described in
section “Digital Control Logic” on page 33.
In transmit mode the fractional-N frequency synthesizer generates the TX frequency which is fed
to the PA. In ASK mode the PA is modulated by the signal PA_Enable. In FSK mode the PA is
enabled and the signal TX_DATA (FSK) modulates the fractional-N frequency synthesizer. The
frequency deviation is digitally controlled and internally fixed to about ±16 kHz (see Table 6-1 on
page 25 for exact values). The transmit data can also be buffered as described in section “Digital
Control Logic” on page 33. A lock detector within the synthesizer ensures that the transmission
will only start if the synthesizer is locked.
The RX/TX switch can be used to combine the LNA input and the PA output to a single antenna
with a minimum of losses.
Transparent modes without buffering of RX and TX data are also available to allow protocols
and coding schemes other than the internal supported Manchester encoding.
5.1
Low-IF Receiver
The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking,
selectivity, supply voltage and supply current specification needed to manufacture an automotive key fob without the use of SAW blocking filter (see Figure 2-1 on page 6). The receiver can
be connected to the roof antenna in the car when using an additional blocking SAW front-end filter as shown in Figure 3-1 on page 7.
At 433.92 MHz the receiver has a typical system noise figure of 7.0 dB, a system I1dBCP of
-30 dBm and a system IIP3 of –20 dBm. There is no AGC or switching of the LNA needed, thus,
a better blocking performance is achieved. This receiver uses an IF (Intermediate Frequency) of
226 kHz, the typical image rejection is 30 dB and the typical 3 dB IF filter bandwidth is 185 kHz
(fIF = 226 kHz ±92.5 kHz, flo_IF = 133.5 kHz and fhi_IF = 318.5 kHz). The demodulator needs a
signal to Gaussian noise ratio of 8 dB for 20 Kbit/s Manchester with ±16 kHz frequency deviation
in FSK mode, thus, the resulting sensitivity at 433.92 MHz is typically –106 dBm at 20 Kbit/s
Manchester.
Due to the low phase noise and spurious of the synthesizer in receive mode(1) together with the
eighth order integrated IF filter the receiver has a better selectivity and blocking performance
than more complex double superhet receivers but without external components and without
numerous spurious receiving frequencies.
A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct
conversion receivers where every pulse or AM-modulated signal (especially the signals from
TDMA systems like GSM) demodulates to the receiving signal band at second-order
non-linearities.
Note:
1. –120 dBC/Hz at ±1 MHz and –75 dBC at ±FREF at 433.92 MHz
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4689F–RKE–08/06
5.2
Input Matching at RF_IN
The measured input impedances as well as the values of a parallel equivalent circuit of these
impedances can be seen in Table 5-1. The highest sensitivity is achieved with power matching
of these impedances to the source impedance of 50Ω.
Table 5-1.
Measured Input Impedances of the RF_IN Pin
fRF/MHz
Z(RF_IN)
Rp//Cp
315
(44-j233)Ω
1278Ω//2.1 pF
433.92
(32-j169)Ω
925Ω//2.1 pF
868.3
(21-j78)Ω
311Ω//2.2 pF
The matching of the LNA Input to 50Ω was done with the circuit according to Figure 5-1 and with
the values given in Table 5-2. The reflection coefficients were always ≤ 10 dB. Note that value
changes of C1 and L1 may be necessary to for compensate individual board layouts. The measured typical FSK and ASK Manchester code sensitivities with a Bit Error Rate (BER) of 10-3 are
shown in Table 5-3 on page 11 and Table 5-4 on page 11. These measurements were done with
inductors having a quality factor according to Table 5-2, resulting in estimated matching losses
of 1.0 dB at 315 MHz, 1.2 dB at 433.92 MHz and 0.6 dB at 868.3 MHz. These losses can be
estimated when calculating the parallel equivalent resistance of the inductor with
Rloss = 2 × π × f × L × QL and the matching loss with 10 log(1+Rp/Rloss).
With an ideal inductor, for example, the sensitivity at 433.92 MHz/FSK/20 Kbit/s/
±16 kHz/Manchester can be improved from –106 dBm to –107.2 dBm. The sensitivity depends
on the control logic which examines the incoming data stream. The examination limits must be
programmed in control registers 5 and 6. The measurements in Table 5-3 and Table 5-4 on
page 11 are based on the values of registers 5 and 6 according to Table 11-3 on page 58.
Figure 5-1.
Input Matching to 50Ω
RFIN
ATA5811/ATA5812
C1
4
RF_IN
L1
Table 5-2.
10
Input Matching to 50Ω
fRF/MHz
C1/pF
L1/nH
QL1
315
2.2
56
43
433.92
1.8
27
40
868.3
1.2
6.8
58
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
Table 5-3.
Measured Sensitivity FSK, ±16 kHz, Manchester, dBm, BER = 10-3
BR_Range_0
1.0 Kbit/s
RF Frequency
BR_Range_0
2.4 Kbit/s
BR_Range_1
5.0 Kbit/s
BR_Range_2
10 Kbit/s
BR_Range_3
20 Kbit/s
315 MHz
–110.0 dBm
–110.5 dBm
–109.0 dBm
–108.0 dBm
–107.0 dBm
433.92 MHz
–109.0 dBm
–109.5 dBm
–108.0 dBm
–107.0 dBm
–106.0 dBm
868.3 MHz
–106.0 dBm
–106.5 dBm
–105.5 dBm
–104.0 dBm
–103.5 dBm
Table 5-4.
Measured Sensitivity 100% ASK, Manchester, dBm, BER = 10-3
RF Frequency
BR_Range_0
1.0 Kbit/s
BR_Range_0
2.4 Kbit/s
BR_Range_1
5.0 Kbit/s
BR_Range_2
10 Kbit/s
315 MHz
–117.0 dBm
–117.5 dBm
–115 dBm
–113.5 dBm
433.92 MHz
–116.0 dBm
–116.5 dBm
–114.0 dBm
–112.5 dBm
868.3 MHz
–112.5 dBm
–113.0 dBm
–111.5 dBm
–109.5 dBm
5.3
Sensitivity versus Supply Voltage, Temperature and Frequency Offset
To calculate the behavior of a transmission system it is important to know the reduction of the
sensitivity due to several influences. The most important are frequency offset due to crystal
oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply voltage dependency of the noise figure and IF filter bandwidth of the receiver. Figure 5-2 shows the typical
sensitivity at 433.92 MHz/FSK/20 Kbit/s/±16 kHz/Manchester versus the frequency offset
between transmitter and receiver with Tamb = –40°C, +25°C and +105°C and supply voltage
VS1 = VS2 = 2.4V, 3.0V and 3.6V.
Figure 5-2.
Measured Sensitivity 433.92 MHz/FSK/20 Kbit/s/±16 kHz/Manchester versus Frequency Offset, Temperature and Supply Voltage
-110.0
-109.0
-108.0
Sensitivity (dBm)
-107.0
VS = 2.4V, Tamb = -40˚C
-106.0
VS = 3.0V, Tamb = -40˚C
-105.0
VS = 3.6V, Tamb = -40˚C
-104.0
VS = 2.4V, Tamb = +25˚C
-103.0
VS = 3.0V, Tamb = +25˚C
-102.0
VS = 3.6V, Tamb = +25˚C
-101.0
VS = 2.4V, Tamb = +105˚C
-100.0
VS = 3.0V, Tamb = +105˚C
-99.0
VS = 3.6V, Tamb = +105˚C
-98.0
-97.0
-96.0
-95.0
-100
-80
-60
-40
-20
0
20
40
60
80
100
Frequency Offset (kHz)
11
4689F–RKE–08/06
As can be seen in Figure 5-2 on page 11 the supply voltage has almost no influence. The temperature has an influence of about +1.5/–0.7 dB and a frequency offset of ±65 kHz also
influences by about ±1 dB. All these influences, combined with the sensitivity of a typical IC, are
then within a range of –103.7 dBm and –107.3 dBm over temperature, supply voltage and frequency offset which is –105.5 dBm ±1.8dB. The integrated IF filter has an additional production
tolerance of only ±7 kHz, hence, a frequency offset between the receiver and the transmitter of
±58 kHz can be accepted for XTAL and XTO tolerances.
Note:
For the demodulator used in the ATA5811/ATA5812, the tolerable frequency offset does not
change with the data frequency, hence, the value of ±58 kHz is valid for up to 1 Kbit/s.
This small sensitivity spread over supply voltage, frequency offset and temperature is very
unusual in such a receiver. It is achieved by an internal, very fast and automatic frequency correction in the FSK demodulator after the IF filter, which leads to a higher system margin. This
frequency correction tracks the input frequency very quickly, if however, the input frequency
makes a larger step (e.g., if the system changes between different communication partners), the
receiver has to be restarted. This can be done by switching back to Idle mode and then again to
RX mode. For that purpose, an automatic mode is also available. This automatic mote switches
to Idle mode and back into RX mode every time a bit error occurs (see section “Digital Control
Logic” on page 33).
5.4
Frequency Accuracy of the Crystals
The XTO is an amplitude regulated Pierce oscillator with integrated load capacitors. The initial
tolerances (due to the frequency tolerance of the XTAL, the integrated capacitors on XTAL1,
XTAL2 and the XTO’s initial transconductance gm) can be compensated to a value within
±0.5 ppm by measuring the CLK output frequency and programming the control registers 2 and
3 (see Table 9-7 on page 36 and Table 9-10 on page 36). The XTO then has a remaining influence of less than ±2 ppm over temperature and supply voltage due to the bandgap controlled
gm of the XTO.
The needed frequency stability of the used crystals over temperature and aging is hence
±58 kHz/433.92 MHz – 2 × ±2.5 ppm = ±128.66 ppm for 433.92 MHz and
±58 kHz/868.3 MHz – 2 × ±2.5 ppm = ±61.8 ppm for 868.3 MHz. Thus, the used crystals in
receiver and transmitter each need to be better than ±64.33 ppm for 433.92 MHz and
±30.9 ppm for 868.3 MHz. In access control systems it may be advantageous to have a more
tight tolerance at the base-station in order to relax the requirement for the key fob.
5.5
RX Supply Current versus Temperature and Supply Voltage
Table 5-5 shows the typical supply current at 433.92 MHz of the transceiver in RX mode versus
supply voltage and temperature with VS = VS1 = VS2. As you can see the supply current at 2.4V
and –40°C is less than the typical one which helps because this is also the operation point
where a lithium cell has the worst performance. The typical supply current at 315 MHz or
868.3 MHz in RX mode is about the same as for 433.92 MHz.
Table 5-5.
12
Measured 433.92 MHz Receive Supply Current in FSK Mode
VS =
2.4 V
3.0 V
3.6 V
Tamb = –40°C
8.4 mA
8.8 mA
9.2 mA
Tamb = 25°C
9.9 mA
10.3 mA
10.8 mA
Tamb = 105°C
11.4 mA
11.9 mA
12.4 mA
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
5.6
Blocking, Selectivity
As can be seen in Figure 5-3 and Figure 5-4, the receiver can receive signals 3 dB higher than
the sensitivity level in presence of very large blockers of –47 dBm/–34 dBm with small frequency
offsets of ±1/ ±10 MHz.
Figure 5-3 shows narrow band blocking and Figure 5-4 wide band blocking characteristics. The
measurements were done with a useful signal of433.92 MHz/FSK/20 Kbit/s/±16 kHz/Manchester with a level of –106 dBm + 3 dB = –103 dBm which is 3 dB above the sensitivity level. The
figures show how much a continuous wave signal can be larger than –103 dBm until the BER is
higher than 10-3. The measurements were done at the 50Ω input according to Figure 5-1 on
page 10. At 1 MHz, for example, the blocker can be 56 dB higher than –103 dBm which is
–103 dBm + 56 dB = –47 dBm. These values, together with the good intermodulation performance, avoid the need for a SAW filter in the key fob application.
Figure 5-3.
Narrow Band 3 dB Blocking Characteristic at 433.92 MHz
70,0
Blocking Level [dBC]
60,0
50,0
40,0
30,0
20,0
10,0
0,0
-10,0
-5,0
-4,0
-3,0
-2,0
-1,0
0,0
1,0
2,0
3,0
4,0
5,0
Distance of Interfering to Receiving Signal [MHz]
Figure 5-4.
Wide Band 3 dB Blocking Characteristic at 433.92 MHz
80,0
Blocking Level [dBC]
70,0
60,0
50,0
40,0
30,0
20,0
10,0
0,0
-10,0
-50,0
-40,0
-30,0
-20,0
-10,0
0,0
10,0
20,0
30,0
40,0
50,0
Distance of Interfering to Receiving Signal [MHz]
13
4689F–RKE–08/06
Figure 5-5 shows the blocking measurement close to the received frequency to illustrate the
selectivity and image rejection. This measurement was done 6 dB above the sensitivity level
with a useful signal of 433.92 MHz/FSK/20 Kbit/s/±16 kHz/ Manchester with a level of
–106 dBm + 6 dB = –100 dBm. The figure shows to which extent a continuous wave signal can
surpass –100 dBm until the BER is higher than 10-3. For example, at 1 MHz the blocker can than
be 59 dB higher than –100 dBm which is –100 dBm + 59 dB = –41 dBm.
Table 5-6 shows the blocking performance measured relative to –100 dBm for some other frequencies. Note that sometimes the blocking is measured relative to the sensitivity level (dBS)
instead of the carrier (dBC).
Blocking 6 dB Above Sensitivity Level with BER < 10-3
Table 5-6.
Frequency Offset
Blocker Level
Blocking
+0.75 MHz
–45 dBm
55 dBC/61 dBS
–0.75 MHz
–45 dBm
55 dBC/61 dBS
+1.5 MHz
–38 dBm
62 dBC/68 dBS
–1.5 MHz
–38 dBm
62 dBC/68 dBS
+10 MHz
–30 dBm
70 dBC/76 dBS
–10 MHz
–30 dBm
70 dBC/76 dBS
The ATA5811/ATA5812 can also receive FSK and ASK modulated signals if they are much
higher than the I1dBCP. It can typically receive useful signals at 10 dBm. This is often referred to
as the nonlinear dynamic range which is the maximum to minimum receiving signal which is
116 dB for 20 Kbit/s Manchester. This value is useful if two transceivers have to communicate
and are very close to each other.
Figure 5-5.
Close In 6 dB Blocking Characteristic and Image Response at 433.92 MHz
70.0
Blocking Level [dBC]
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Distance of Interfering to Receiving Signal [MHz]
14
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
This high blocking performance makes it even possible for some applications using quarter
wave whip antennas to use a simple LC band-pass filter instead of a SAW filter in the receiver.
When designing such an LC filter take into account that the 3 dB blocking at
433.92 MHz/2 = 216.96 MHz is 43 dBC and at 433.92 MHz/3 = 144.64 MHz is 48 dBC and at
2 × (433.92 MHz + 226 kHz) + –226 kHz = 868.066 MHz/868.518 MHz is 56 dBC. And especially that at 3 × (433.92 MHz + 226 kHz)+226 kHz = 1302.664 MHz the receiver has its second
LO harmonic receiving frequency with only 12 dBC blocking.
5.7
Inband Disturbers, Data Filter, Quasi Peak Detector, Data Slicer
If a disturbing signal falls into the received band or a blocker is not continuous wave the performance of a receiver strongly depends on the circuits after the IF filter. Hence the demodulator,
data filter and data slicer are important in that case.
The data filter of the ATA5811/ATA5812 implies a quasi peak detector. This results in a good
suppression of the above mentioned disturbers and exhibits a good carrier to Gaussian noise
performance. The required useful signal to disturbing signal ratio to be received with a BER of
10-3 is less than 12 dB in ASK mode and less than 3 dB (BR_Range_0 ... BR_Range_2)/6 dB
(BR_Range_3) in FSK mode. Due to the many different waveforms possible these numbers are
measured for signal as well as for disturbers with peak amplitude values. Note that these values
are worst case values and are valid for any type of modulation and modulating frequency of the
disturbing signal as well as the receiving signal. For many combinations, lower carrier to disturbing signal ratios are needed.
5.8
DEM_OUT Output
The internal raw output signal of the demodulator Demod_Out is available at pin DEM_OUT.
DEM_OUT is an open drain output and must be connected to a pull-up resistor if it is used (typically 100 kΩ) otherwise no signal is present at that pin.
5.9
RSSI Output
The output voltage of the pin RSSI is an analog voltage, proportional to the input power level.
Using the RSSI output signal, the signal strength of different transmitters can be distinguished.
The usable dynamic range of the RSSI amplifier is 70 dB, the input power range P(RFIN) is
–115 dBm to –45 dBm and the gain is 8 mV/dB. Figure 5-6 on page 16 shows the RSSI characteristic of a typical device at 433.92 MHz with VS1 = VS2 = 2.4 V to 3.6 V and Tamb = –40°C to
+105°C with a matched input according to Table 5-2 on page 10 and Figure 5-1 on page 10. At
868.3 MHz about 2.7 dB more signal level and at 315 MHz about 1 dB less signal level is
needed for the same RSSI results.
15
4689F–RKE–08/06
Figure 5-6.
Typical RSSI Characteristic versus Temperature and Supply Voltage
1100
1000
VRSSI (mV)
900
800
Max.
700
Min.
600
Typ.
500
400
-120
-110
-100
-90
-80
-70
-60
-50
-40
PRF_IN (dBm)
5.10
Frequency Synthesizer
The synthesizer is a fully integrated fractional-N design with internal loop filters for receive and
transmit mode. The XTO frequency fXTO is the reference frequency FREF for the synthesizer.
The bits FR0 to FR8 in control registers 2 and 3 (see Table 9-7 on page 36 and Table 9-10 on
page 36) are used to adjust the deviation of fXTO. In transmit mode, at 433.92 MHz, the carrier
has a phase noise of –111 dBC/Hz at 1 MHz and spurious at FREF of –66 dBC with a high PLL
loop bandwidth allowing the direct modulation of the carrier with 20 Kbit/s Manchester data. Due
to the closed loop modulation any spurious caused by this modulation are effectively filtered out
as can be seen in Figure 5-9 on page 18. In RX mode the synthesizer has a phase noise of
–120 dBC/Hz at 1 MHz and spurious of –75 dBC.
The initial tolerances of the crystal oscillator due to crystal tolerances, internal capacitor tolerances and the parasitics of the board have to be compensated at manufacturing setup with
control registers 2 and 3 as can be seen in Table 6-1 on page 25. The other control words for the
synthesizer needed for ASK, FSK and receive/transmit switching are calculated internally. The
RF (Radio Frequency) resolution is equal to the XTO frequency divided by 16384 which is
777.1 Hz at 315.0 MHz, 808.9 Hz at 433.92 MHz and 818.59 Hz at 868.3 MHz.
5.11
FSK/ASK Transmission
Due to the fast modulation capability of the synthesizer and the high resolution, the carrier can
be internally FSK modulated which simplifies the application of the transceiver. The deviation of
the transmitted signal is ±20 digital frequency steps of the synthesizer which is equal to
±15.54 kHz for 315 MHz, ±16.17 kHz for 433.92 MHz and ±16.37 kHz for 868.3 MHz.
Due to closed loop modulation with PLL filtering the modulated spectrum is very clean, meeting
ETSI and CEPT regulations when using a simple LC filter for the power amplifier harmonics as it
is shown in Figure 3-1 on page 7. In ASK mode the frequency is internally connected to the center of the FSK transmission and the power amplifier is switched on and off to perform the
modulation. Figure 5-7 on page 17 to Figure 5-9 on page 18 show the spectrum of the FSK modulation with pseudo random data with 20 Kbit/s/±16.17 kHz/Manchester and 5 dBm output
power.
16
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
Figure 5-7.
FSK-modulated TX Spectrum (20 Kbit/s/±16.17 kHz/Manchester Code)
Ref 10 dBm
Samp
Log
10
dB/
Atten 20 dB
VAvg
50
W1 S2
S3 FC
Center 433.92 MHz
Res BW 100 kHz
Figure 5-8.
Span 30 MHz
VBW 100 kHz
Sweep 7.5 ms (401 pts)
Unmodulated TX Spectrum fFSK_L
Ref 10 dBm
Atten 20 dB
Samp
Log
10
dB/
VAvg
50
W1 S2
S3 FC
Center 433.92 MHz
Res BW 10 kHz
VBW 10 kHz
Span 1 MHz
Sweep 27.5 ms (401 pts)
17
4689F–RKE–08/06
Figure 5-9.
FSK-modulated TX Spectrum (20 Kbit/s/±16.17 kHz/Manchester Code)
Ref 10 dBm
Samp
Log
10
dB/
Atten 20 dB
VAvg
50
W1 S2
S3 FC
Center 433.92 MHz
Res BW 10 kHz
5.12
VBW 10 kHz
Span 1 MHz
Sweep 27.5 ms (401 pts)
Output Power Setting and PA Matching at RF_OUT
The Power Amplifier (PA) is a single-ended open collector stage which delivers a current pulse
which is nearly independent of supply voltage, temperature and tolerances due to bandgap stabilization. Resistor R1, see Figure 5-10 on page 19, sets a reference current which controls the
current in the PA. A higher resistor value results in a lower reference current, a lower output
power and a lower current consumption of the PA. The usable range of R1 is 15 kΩ to 56 kΩ. Pin
PWR_H switches the output power range between about 0 dBm to 5 dBm (PWR_H = GND) and
5 dBm to 10 dBm (PWR_H = AVCC) by multiplying this reference current with a factor 1
(PWR_H = GND) and 2.5 (PWR_H = AVCC) which corresponds to about 5 dB more output
power.
If the PA is switched off in TX mode, the current consumption without output stage with
VS1 = VS2 = 3V, Tamb = 25°C is typically 6.5 mA for 868.3 MHz and 6.95 mA for 315 MHz and
433.92 MHz.
The maximum output power is achieved with optimum load resistances RLopt according to Table
5-7 on page 20 with compensation of the 1.0 pF output capacitance of the RF_OUT pin by
absorbing it into the matching network consisting of L1, C1, C3 as shown in Figure 5-10 on page
19. There must be also a low resistive DC path to AVCC to deliver the DC current of the power
amplifier's last stage. The matching of the PA output was done with the circuit according to Figure 5-10 on page 19 with the values in Table 5-7 on page 20. Note that value changes of these
elements may be necessary to compensate for individual board layouts.
18
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
Example:
According to Table 5-7 on page 20, with a frequency of 433.92 MHz and output power of
11 dBm the overall current consumption is typically 17.8 mA hence the PA needs
17.8 mA - 6.95 mA = 10.85 mA in this mode which corresponds to an overall power amplifier
efficiency of the PA of (10(11dBm/10) × 1 mW)/(3V × 10.85 mA) × 100% = 38.6% in this case.
Using a higher resistor in this example of R1 = 1.091 × 22 kΩ = 24 kΩ results in 9.1% less current in the PA of 10.85 mA/1.091 = 9.95 mA and 10 × log(1.091) = 0.38 dB less output power if
using a new load resistance of 300 Ω × 1.091 = 327 Ω. The resulting output power is then
11 dBm – 0.38 dB = 10.6 dBm and the overall current consumption is
6.95 mA + 9.95 mA = 16.9 mA.
The values of Table 5-7 on page 20 were measured with standard multi-layer chip inductors with
quality factors Q according to Table 5-7 on page 20. Looking to the 433.92 MHz/11 dBm case
with the quality factor of QL1 = 43 the loss in this inductor is estimated with the parallel equivalent resistance of the inductor R loss = 2 × π × f × L × Q L1 and the matching loss with
10 log (1 + RLopt/Rloss) which is equal to 0.32 dB losses in this inductor. Taking this into account
the PA efficiency is then 42% instead of 38.6%.
Be aware that the high power mode (PWR_H = AVCC) can only be used with a supply voltage
higher than 2.7V, whereas the low power mode (PWR_H = GND) can be used down to 2.4V as
can be seen in the section “Electrical Characteristics: General” on page 63.
The supply blocking capacitor C 2 (10 nF) has to be placed close to the matching network
because of the RF current flowing through it.
Figure 5-10. Power Setting and Output Matching
AVCC
C2
L1
RFOUT
C1
ATA5811/ATA5812
10
RF_OUT
C3
8
R_PWR
R1
9
VPWR_H
PWR_H
19
4689F–RKE–08/06
Table 5-7.
Measured Output Power and Current Consumption with VS1 = VS2 = 3 V, Tamb = 25°C
Frequency (MHz) TX Current (mA) Output Power (dBm)
5.13
R1 (kΩ)
VPWR_H
RLopt (Ω)
L1 (nH)
QL1
C1 (pF) C3 (pF)
315
8.5
0.4
56
GND
2500
82
28
1.5
0
315
10.5
5.7
27
GND
920
68
32
2.2
0
315
16.7
10.5
27
AVCC
350
56
35
3.9
0
433.92
8.6
0.1
56
GND
2300
56
40
0.75
0
433.92
11.2
6.2
22
GND
890
47
38
1.5
0
433.92
17.8
11
22
AVCC
300
33
43
2.7
0
868.3
9.3
–0.3
33
GND
1170
12
58
1.0
3.3
868.3
11.5
5.4
15
GND
471
15
54
1.0
0
868.3
16.3
9.5
22
AVCC
245
10
57
1.5
0
Output Power and TX Supply Current versus Supply Voltage and Temperature
Table 5-8 on page 20 shows the measurement of the output power for a typical device with
VS1 = VS2 = VS in the 433.92 MHz and 6.2 dBm case versus temperature and supply voltage
measured according to Figure 5-10 on page 19 with components according to Table 5-7. As
opposed to the receiver sensitivity the supply voltage has here the major impact on output power
variations because of the large signal behavior of a power amplifier. Thus, a two battery system
with voltage regulator or a 5V system shows much less variation than a 2.4V to 3.6V one battery
system because the supply voltage is then well within 3.0V and 3.6V.
The reason is that the amplitude at the output RF_OUT with optimum load resistance is
AVCC – 0.4V and the power is proportional to (AVCC – 0.4V) 2 if the load impedance is not
changed. This means that the theoretical output power reduction if reducing the supply voltage
from 3.0V to 2.4V is 10 log ((3V – 0.4V)2/(2.4V – 0.4V)2) = 2.2 dB. Table 5-8 shows that principle
behavior in the measurement. This is not the same case for higher voltages since here increasing the supply voltage from 3V to 3.6V should theoretical increase the power by 1.8 dB but only
0.8 dB in the measurement shows that the amplitude does not increase with the supply voltage
because the load impedance is optimized for 3V and the output amplitude stays more constant.
Table 5-8.
Measured Output Power and Supply Current at 433.92 MHz, PWR_H = GND
VS =
2.4 V
3.0 V
3.6 V
Tamb = –40°C
10.19 mA
3.8 dBm
10.19 mA
5.5 dBm
10.78 mA
6.2 dBm
Tamb = +25°C
10.62 mA
4.6 dBm
11.19 mA
6.2 dBm
11.79 mA
7.1 dBm
Tamb = +105°C
11.4 mA
3.8 dBm
12.02 mA
5.4 dBm
12.73 mA
6.3 dBm
Table 5-9 on page 21 shows the relative changes of the output power of a typical device compared to 3.0V/25°C. As can be seen a temperature change to –40° as well as to +105° reduces
the power by less than 1 dB due to the bandgap regulated output current. Measurements of all
the cases in Table 5-7 on page 20 over temperature and supply voltage have shown about the
same relative behavior as shown in Table 5-9 on page 21.
20
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
Table 5-9.
5.14
Measurements of Typical Output Power Relative to 3V/25°
VS =
2.4V
3.0V
3.6V
Tamb = –40°C
–2.4 dB
–0.7 dB
0 dB
Tamb = +25°C
–1.6 dB
0 dB
+0.9 dB
Tamb = +105°C
–2.4 dB
–0.8 dB
+0.1 dB
RX/TX Switch
The RX/TX switch decouples the LNA from the PA in TX mode, and directs the received power
to the LNA in RX mode. To do this, it has a low impedance to GND in TX mode and a high
impedance to GND in RX mode. To design a proper RX/TX decoupling a linear simulation tool
for radio frequency design together with the measured device impedances of Table 5-1 on page
10, Table 5-7 on page 20, Table 5-10 and Table 5-11 on page 22 should be used, but the exact
element values have to be found on board. Figure 5-11 on page 21 shows an approximate
equivalent circuit of the switch. The principal switching operation is described here according to
the application of Figure 2-1 on page 6. The application of Figure 3-1 on page 7 works similarly.
Table 5-10.
Impedance of the RX/TX Switch RX_TX2 Shorted to GND
Frequency
Z(RX_TX1) TX Mode
Z(RX_TX1) RX Mode
315 MHz
(4.8 + j3.2)Ω
(11.3 – j214)Ω
433.92 MHz
(4.5 + j4.3)Ω
(10.3 – j153)Ω
868.3 MHz
(5 + j9)Ω
(8.9 – j73)Ω
Figure 5-11. Equivalent Circuit of the Switch
RX_TX1
1.6 nH
2.5 pF
11Ω
TX
5Ω
21
4689F–RKE–08/06
5.15
Matching Network in TX Mode
In TX mode the 20 mm long and 0.4 mm wide transmission line which is much shorter than λ/4 is
approximately switched in parallel to the capacitor C9 to GND. The antenna connection between
C8 and C 9 has an impedance of about 50 Ω locking from the transmission line into the loop
antenna with pin RF_OUT, L2, C10, C8 and C9 connected (using a C9 without the added 7.6 pF
as discussed later). The transmission line can be approximated with a 16 nH inductor in series
with a 1.5Ω resistor, the closed switch can be approximated according to Table 5-10 on page 21
with the series connection of 1.6 nH and 5Ω in this mode. To have a parallel resonant high
impedance circuit with little RF power going into it looking from the loop antenna into the transmission line a capacitor of about 7.6 pF to GND is needed at the beginning of the transmission
line (this capacitor is later absorbed into C9 which is then higher as needed for 50Ω transformation). To keep the 50Ω impedance in RX mode at the end of this transmission line C7 has to be
also about 7.6 pF. This reduces the TX power by about 0.5 dB at 433.92 MHz compared to the
case the where the LNA path is completely disconnected.
5.16
Matching Network in RX Mode
In RX mode the RF_OUT pin has a high impedance of about 7 kΩ in parallel with 1.0 pF at
433.92 MHz as can be seen in Table 5-11 on page 22. This together with the losses of the
inductor L2 with 120 nH and QL2 = 25 gives about 3.7 kΩ loss impedance at RF_OUT. Since the
optimum load impedance in TX mode for the power amplifier at RF_OUT is 890Ω the loss associated with the inductor L2 and the RF_OUT pin can be estimated to be
10 × log(1 + 890/3700) = 0.95 dB compared to the optimum matched loop antenna without L2
and RF_OUT. The switch represents, in this mode at 433.92 MHz, about an inductor of 1.6 nH in
series with the parallel connection of 2.5 pF and 2.0 kΩ. Since the impedance level at pin
RX_TX1 in RX mode is about 50Ω this only negligiblably dampens the received signal by about
0.1 dB. When matching the LNA to the loop antenna the transmission line and the 7.6 pF part of
C9 has to be taken into account when choosing the values of C11 and L1 so that the impedance
seen from the loop antenna into the transmission line with the 7.6 pF capacitor connected is
50Ω. Since the loop antenna in RX mode is loaded by the LNA input impedance the loaded Q of
the loop antenna is lowered by about a factor of 2 in RX mode hence the antenna bandwidth is
higher than in TX mode.
Table 5-11.
Impedance RF_OUT Pin in RX Mode
Frequency
Z(RF_OUT)RX
RP//CP
315 MHz
36Ω – j 502Ω
7 kΩ/ / 1.0 pF
433.92 MHz
19Ω – j 366Ω
7 kΩ/ / 1.0 pF
868.3 MHz
2.8Ω – j 141Ω
7 kΩ/ / 1.3 pF
Note that if matching to 50Ω, like in Figure 3-1 on page 7, a high Q wire wound inductor with a
Q > 70 should be used for L2 to minimize its contribution to RX losses which will otherwise be
dominant. The RX and TX losses will be in the range of 1.0 dB there.
22
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ATA5811/ATA5812
6. XTO
The XTO is an amplitude regulated Pierce oscillator type with integrated load capacitances
(2 × 18 pF with a tolerance of ±17%) hence CLmin = 7.4 pF and CLmax = 10.6 pF. The XTO oscillation frequency fXTO is the reference frequency FREF for the fractional-N synthesizer. When
designing the system in terms of receiving and transmitting frequency offset the accuracy of the
crystal and XTO have to be considered.
The synthesizer can adjust the local oscillator frequency for more than ±150 ppm at
433.92 MHz/315 MHz and up to ±118 ppm at 868.3 MHz of initial frequency error in fXTO. This is
done at nominal supply voltage and temperature with the control registers 2 and 3 (see Table
9-7 on page 36 and Table 9-10 on page 36). The remaining local oscillator tolerance at nominal
supply voltage and temperature is then < ±0.5 ppm. A XTO frequency error of
±150 ppm/±118 ppm can hence be tolerated due to the crystal tolerance at 25°C and the tolerances of C L1 and C L2 . The XTO’s gm has very low influence of less than ±2 ppm on the
frequency at nominal supply voltage and temperature.
Over temperature and supply voltage, the XTO's additional pulling is only ±2 ppm if Cm ≤7 fF.
The XTAL versus temperature and its aging is then the main source of frequency error in the
local oscillator.
The XTO frequency depends on XTAL properties and the load capacitances CL1, 2 at pin XTAL1
and XTAL2. The pulling of fXTO from the nominal fXTAL is calculated using the following formula:
C LN – C L
Cm
6
P = -------- × ------------------------------------------------------------- × 10 ppm.
2
( C 0 + C LN ) × ( C 0 + C L )
Cm is the crystal's motional, C0 the shunt and CLN the nominal load capacitance of the XTAL
found in its data sheet. CL is the total actual load capacitance of the crystal in the circuit and consists of CL1 and CL2 in series connection.
Figure 6-1.
XTAL with Load Capacitance
Crystal equivalent circuit
C0
XTAL
Lm
CL1
CL2
Cm
Rm
CL = CL1 × CL2/ (CL1 + CL2)
With C m ≤ 14 fF, C 0 ≥ 1.5 pF, C LN = 9 pF and C L = 7.6 pF to 10.6 pF the pulling amounts to
P ≤ ±100 ppm and with Cm ≤ 7 fF, C0 ≥ 1.5 pF, CLN = 9 pF and CL = 7.4 pF to 10.6 pF the pulling
is P ≤ ±50 ppm.
Since typical crystals have less than ±50 ppm tolerance at 25° the compensation is not critical.
C0 of the XTAL has to be lower than CLmin/2 = 3.8 pF for a Pierce oscillator type in order to not
enter the steep region of pulling versus load capacitance where there is a risk of an unstable
oscillation.
23
4689F–RKE–08/06
To ensure proper start-up behavior the small signal gain and thus the negative resistance provided by this XTO at start is very large, for example oscillation starts up even in worst case with
a crystal series resistance of 1.5 kΩ at C0 ≤ 2.2 pF with this XTO. The negative resistance is
approximately given by
⎧ Z1 × Z3 + Z2 × Z3 + Z1 × Z2 × Z3 × gm ⎫
Re {Z xtocore } = Re ⎨ ------------------------------------------------------------------------------------------------------ ⎬
Z1 + Z2 + Z3 + Z1 × Z2 × gm
⎩
⎭
with Z1, Z2 as complex impedances at pin XTAL1 and XTAL2 hence
Z1 = –j/(2 × π × fXTO × CL1) + 5Ω and Z2 = –j/(2 × π × fXTO × CL2) + 5Ω.
Z3 consists of crystals C0 in parallel with an internal 110 kΩ resistor hence
Z3 = –j/(2 × π × fXTO × C0) /110 kΩ, gm is the internal transconductance between XTAL1 and
XTAL2 with typically 19 ms at 25°C.
With fXTO = 13.5 MHz, gm = 19 ms, CL = 9 pF, C0 = 2.2 pF this results in a negative resistance of
about 2 kΩ. The worst case for technological, supply voltage and temperature variations is then
for C0 ≤ 2.2 pF always higher than 1.5 kΩ.
Due to the large gain at start the XTO is able to meet a very low start-up time. The oscillation
start-up time can be estimated with the time constant τ .
2
τ = ------------------------------------------------------------------------------------------------------2
2
4 × π × f m × C m × ( Re ( Z xtocore ) + R m )
After 10 τ to 20 τ an amplitude detector detects the oscillation amplitude and sets XTO_OK to
High if the amplitude is large enough, this sets N_RESET to High and activates the CLK output if
CLK_ON in control register 3 is High (see Table 9-7 on page 36). Note that the necessary conditions of the VSOUT and DVCC voltage also have to be fulfilled (see Figure 6-2 on page 25 and
Figure 7-1 on page 27).
To save current in Idle and sleep mode, the load capacitors partially are switched off in this
modes with S1 and S2 seen in Figure 6-2 on page 25.
It is recommended to use a crystal with C m = 4.0 fF to 7.0 fF, C LN = 9 pF, R m < 120Ω and
C0 = 1.5 pF to 2.2 pF.
24
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
Figure 6-2.
XTO Block Diagram
XTAL1
XTAL2
CLK
&
fXTO
8 pF
10 pF
10 pF
CL1
CLK_ON
(control
register 3)
8 pF
VSOUT_OK
(from power supply)
Amplitude
detector
CL2
S1
DVCC_OK
(from power supply)
Divider
/3
XTO_OK
(to reset logic)
S2
Divider
/16
fDCLK
Divider
/1
/2
/4
/8
/16
fXDCLK
In IDLE mode and during Sleep mode (RX_Polling)
the switches S1 and S2 are open.
Baud1
Baud0
XLim
To find the right values used in the control registers 2 and 3 (see Table 9-7 on page 36 and
Table 9-10 on page 36) the relationship between fXTO and the fRF is shown in Table 6-1. To
determine the right content the frequency at pin CLK as well as the output frequency at RF_OUT
in ASK mode can be measured, than the FREQ value can be calculated according to Table 6-1
so that fRF is exactly the desired radio frequency
Table 6-1.
Calculation of fRF
Frequency (MHz)
Pin 6
433_N868
CREG1
Bit(4)
FS
fXTO (MHz)
fRF = fTX_ASK = fRX
fTX_FSK_L
fTX_FSK_H
433.92
AVCC
0
13.25311
+ 20,5-⎞
f XTO × ⎛⎝ 32, 5 + FREQ
--------------------------------16384 ⎠
fRF – 16.17 kHz
fRF + 16.17 kHz
868.3
GND
0
13.41191
FREQ + 20,5
f XTO × ⎛ 64, 5 + ----------------------------------⎞
⎝
16384 ⎠
fRF – 16.37 kHz
fRF + 16.37 kHz
315.0
AVCC
1
12.73193
+ 20,5-⎞
f XTO × ⎛ 24, 5 + FREQ
--------------------------------⎝
16384 ⎠
fRF – 15.54 kHz
fRF + 15.54 kHz
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4689F–RKE–08/06
The variable FREQ depends on FREQ2 and FREQ3, which are defined by the bits FR0 to FR8
in control register 2 and 3 and is calculated as follows:
FREQ = 3584 + FREQ2 + FREQ3
Only the range of FREQ = 3803 to 4053 of this register should be used because otherwise harmonics of fXTO and fCLK can cause interference with the received signals (FREQ_min = 3803,
FREQ_max = 4053). The resulting tuning range is ±118 ppm at 868.3 MHz and more than
±150 ppm at 433.92 MHz or 315 MHz.
6.1
Pin CLK
Pin CLK is an output to clock a connected microcontroller. The clock frequency fCLK is calculated
as follows:
f XTO
f CLK = ---------3
Because the enabling of pin CLK is asynchronous the first clock cycle may be incomplete. The
signal at CLK output has a nominal 50% duty cycle.
Figure 6-3.
Clock Timing
VThres_2 = 2.38V (typically)
VSOUT
VThres_2 = 2.38V (typically)
CLK
N_RESET
CLK_ON
(Control register 3)
6.2
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry is derived from one clock. According to Figure 6-2
on page 25, this clock cycle TDCLK is derived from the crystal oscillator (XTO) in combination with
a divider.
f XTO
f DCLK = ---------16
TDCLK controls the following application relevant parameters:
• Timing of the polling circuit including Bit-check
• TX bit rate
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ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
The clock cycle of the Bit-check and the TX bit rate depends on the selected bit-rate range
(BR_Range) which is defined in control register 6 (see Table 9-20 on page 39) and XLim which
is defined in control register 4 (see Table 9-13 on page 37). This clock cycle TXDCLK is defined by
the following formulas for further reference:
BR_Range ⇒
BR_Range 0: TXDCLK = 8 ×
BR_Range 1: TXDCLK = 4 ×
BR_Range 2: TXDCLK = 2 ×
BR_Range 3: TXDCLK = 1 ×
TDCLK ×
TDCLK ×
TDCLK ×
TDCLK ×
XLim
XLim
XLim
XLim
7. Power Supply
Figure 7-1.
Power Supply
VS1
SW_AVCC
IN
VS2
V_REG1
3.25V typ.
VSINT
OUT
AVCC
EN
(Control register 1)
≥1
AVCC_EN
FF1
PWR_ON
T1
S Q
to
T5
R
SW_VSOUT
DVCC_OK
OFFCMD
S
0
0
1
1
(Command via SPI)
VS1+
0.55V
typ.
VAUX
DVCC
≥1
+
IN
VSOUT_EN
R
0
1
0
1
Q
no change
0
1
1
P_On_Aux
(Status register)
V_REG2
3.25V typ.
OUT
SW_DVCC
V_Monitor
(1.5V typ.)
and
V_Monitor
(2.3V/
2.38V typ.)
DVCC_OK
(to XTO and
Reset Logic)
VSOUT_OK
(to XTO and
Reset Logic)
Low_Batt
(Status Register
and Reset Logic)
VSOUT
EN
(Control register 3)
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4689F–RKE–08/06
The supply voltage range of the ATA5811/ATA5812 is 2.4V to 3.6V or 4.4V to 6.6V.
Pin VS1 is the supply voltage input for the range 2.4V to 3.6V and is used in battery applications
using a single lithium 3V cell. Pin VS2 is the voltage input for the range 4.4V to 6.6V (2 Battery
Application and Car Applications) in this case the voltage regulator V_REG1 regulates VS1 to
typically 3.25 V. If the voltage regulator is active a blocking capacitor of 2.2 µF has to be connected to VS1.
Pin VAUX is an input for an additional auxiliary voltage supply and can be connected e.g., to an
inductive supply (see Figure 7-6 on page 33). This input can only be used together with a rectifier or as in the application of Figure 3-1 on page 7 and must otherwise be left open.
Pin VSINT is the voltage input for the Microcontoller_Interface and must be connected to the
power supply of the microcontroller. The voltage range of VVSINT is 2.4V to 5.25V (see Figure 7-5
on page 32 and Figure 7-6 on page 33).
AVCC is the internal operation voltage of the RF transceiver and is feed via the switch
SW_AVCC by VS1. AVCC must be blocked with a 68 nF capacitor (see Figure 2-1 on page 6,
Figure 3-1 on page 7 and Figure 4-1 on page 8).
DVCC is the internal operation voltage of the digital control logic and is feed via the switch
SW_DVCC by VS1 or VSOUT. DVCC must be blocked on pin DVCC with 68 nF (see Figure 2-1
on page 6, Figure 3-1 on page 7 and Figure 4-1 on page 8).
Pin VSOUT is a power supply output voltage for external devices (e.g., microcontroller) and is
fed via the switch SW_VSOUT by VS1 or via V_REG2 by the a auxiliary voltage supply VAUX.
The voltage regulator V_REG2 regulates VSOUT to typically 3.25V. If the voltage regulator is
active a blocking capacitor of 2.2 µF has to be connected to VSOUT. VSOUT can be switched
off by the VSOUT_EN bit in control register 3 and is then reactivated by conditions found in Figure 7-2 on page 29.
Pin N_RESET is set to low if the voltage VVSOUT at pin VSOUT drops below 2.3V (typically) and
can be used as a reset signal for a connected microcontroller (see Figure 7-3 on page 31 and
Figure 7-4 on page 32).
Pin PWR_ON is an input to switch on the transceiver (active high).
Pin T1 to T5 are inputs for push buttons and can also be used to switch on the transceiver
(active low).
For current consumption reasons it is recommended to set T1 to T5 to GND or PWR_ON to VCC
only temporarily. Otherwise an additional current flows.
There are two voltage monitors generating the following signals (see Figure 7-1 on page 27):
• DVCC_OK if DVCC > 1.5V typically
• VSOUT_OK if VSOUT > VThres1 (2.3V typically)
• Low_Batt if VSOUT < VThres2 (2.38V typically)
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4689F–RKE–08/06
ATA5811/ATA5812
Figure 7-2.
Flow Chart Operation Modes
Bit AVCC_EN = 0 and OFF Command and
Pin PWR_ON = 0 and
Pin T1, T2, T3, T4 and T5 = 1
IDLE Mode
VVAUX > 3.5V (typ)
Pin PWR_ON = 1 or
Pin T1, T2, T3, T4 or
Pin T5
IDLE Mode
VVAUX < 3.5V (typ)
AVCC = VS1
DVCC = VS1
VSOUT = V_REG2
VVAUX < VS1 + 0.5V
Pin PWR_ON = 1 or
Pin T1, T2, T3, T4 or
Pin T5 or
Bit AVCC_EN = 1
IDLE Mode
AVCC = VS1
DVCC = VS1
VSOUT = V_REG2
AVCC = VS1
DVCC = VS1
VSOUT = VS1
VVAUX > VS1 + 0.5V
OPM1 OPM0
0
1
TX Mode
1
0
RX Polling Mode
1
1
RX Mode
Bit AVCC_EN = 0 and
OFF Command and
Pin PWR_ON = 0 and
Pin T1, T2, T3, T4 and
T5 = 1
VSOUT_EN = 0
Statusbit Power_On = 1
or
Event on Pin T1, T2, T3, T4 or T5
AUX Mode
AVCC = OFF
DVCC = V_REG2
VSOUT = V_REG2
IDLE Mode
AVCC = VS1
DVCC = VS1
VSOUT = OFF
OPM1 = 0 and OPM0 = 1
TX Mode
AVCC = VS1
DVCC = VS1
VSOUT = VS1
or V_REG2
OPM1 = 0 and OPM0 = 1 RX Polling Mode
OPM1 = 1 and OPM0 = 0
AVCC = VS1
DVCC = VS1
VSOUT = VS1
or V_REG2
OPM1 = 1 and OPM0 = 0
OPM1 = 1 and OPM0 = 1
or Bit check ok
AUX Mode
AVCC = VS1
DVCC = VS1
VSOUT = VS1
or V_REG2
OPM1 = 1 and OPM0 = 1
VSOUT_EN = 0
Statusbit Power_On = 1
or
Event on Pin T1, T2, T3, T4 or T5
RX Polling Mode
AVCC = VS1
DVCC = VS1
VSOUT = OFF
7.1
Bit check ok
OFF Mode
After connecting the power supply (battery) to pin VS1 and/or VS2 and if the voltage on pin
VAUX VVAUX < 3.5V (typically) the transceiver is in OFF mode. In OFF mode AVCC, DVCC and
VSOUT are disabled, resulting in very low power consumption (IS_OFF is typically 10 nA). In OFF
mode the transceiver is not programmable via the 4-wire serial interface.
29
4689F–RKE–08/06
7.2
AUX Mode
The transceiver changes from OFF mode to AUX mode if the voltage at pin VAUX VVAUX > 3.5V
(typically). In AUX mode DVCC and VSOUT are connected to the auxiliary power supply input
(VAUX) via the voltage regulator V_REG2. In AUX mode the transceiver is programmable via
the 4-wire serial interface, but no RX or TX operations are possible because AVCC = OFF.
The state transition OFF mode to AUX mode is indicated by an interrupt at pin IRQ and the status bit P_On_Aux = 1.
7.3
Idle Mode
In Idle mode AVCC and DVCC are connected to the battery voltage (VS1).
From OFF mode the transceiver changes to Idle mode if pin PWR_ON is set to 1 or pin T1, T2,
T3, T4 or T5 is set to 0. This state transition is indicated by an interrupt at pin IRQ and the status
bits Power_On = 1 or ST1, ST2, ST3, ST4 or ST5 = 1.
From AUX mode the transceiver changes to Idle mode by setting AVCC_EN = 1 in control
register 1 via the 4-wire serial interface or if pin PWR_ON is set to 1 or pin T1, T2, T3, T4 or T5
is set to 0.
VSOUT is either connected to VS1 or to the auxiliary power supply (V_REG2).
If VVAUX < VS1 + 0.5V, VSOUT is connected to VS1. If V VAUX > VS1 + 0.5V, VSOUT is connected to V_REG2 and the status bit P_On_Aux is set to 1.
In Idle mode the RF transceiver is disabled and the power consumption IS_IDLE is about 230 µA
(VSOUT OFF and CLK output OFF VS1 = VS2 = 3V). The exact value of this current is strongly
dependent on the application and the exact operation mode, therefore check the section “Electrical Characteristics: General” on page 63 for the appropriate application case.
Via the 4-wire serial interface a connected microcontroller can program the required parameter
and enable the TX, RX polling or RX mode.
The transceiver can be set back to OFF mode by an OFF command via the 4-wire serial interface (the bit AVCC_EN must be set to 0, the input level of pin PWR_ON must be 0 and pin T1,
T2, T3, T4 and T5 = 1 before writing the OFF command).
Table 7-1.
7.4
Control Register 1
OPM1
OPM0
Function
0
0
Idle mode
Reset Timing and Reset Logic
If the transceiver is switched on (OFF mode to Idle mode, OFF mode to AUX mode) DVCC and
VSOUT are ramping up as illustrated in Figure 7-3 on page 31 (AVCC only ramps up if the transceiver is set to the Idle mode). The internal signal DVCC_RESET resets the digital control logic
and sets the control register to default values.
A voltage monitor generates a low level at pin N_RESET until the voltage at pin VSOUT
exceeds 2.38V (typically) and the start-up time of the XTO has elapsed (amplitude detector, see
Figure 6-2 on page 25). After the voltage at pin VSOUT exceeds 2.3V (typically) and the start-up
time of the XTO has elapsed the output clock at pin CLK is available. Because the enabling of
pin CLK is asynchronous the first clock cycle may be incomplete.
30
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
The status bit Low_Batt is set to 1 if the voltage at pin VSOUT VVSOUT drops below VThres_2 (typically 2.38V). Low_Batt is set to 0 if VVSOUT exceeds VThres_2 and the status register is read via
the 4-wire serial interface or N_RESET is set to low.
If VVSOUT drops below VThres_1 (typically 2.3V), N_RESET is set to low. If bit VSOUT_EN in control register 3 is 1, a DVCC_RESET is also generated. If V VSOUT was prior disabled by the
connected microcontroller by setting bit VSOUT_EN = 0, no DVCC_RESET is generated.
Note:
Figure 7-3.
If VSOUT < VThres_1 (typically 2.3V) the output of the pin CLK is low, the Microcontroller_Interface
is disabled and the transceiver is not programmable via the 4-wire serial interface.
Reset Timing
VThres_2 = 2.38V (typ)
VThres_1 = 2.3V (typ)
VSOUT
1.5V (typically)
DVCC
(AVCC)
DVCC_RESET
VSOUT > 2.38V and the XTO is running
N_RESET
LOW_Batt
(Status Register)
VSOUT_EN
(Control Register 3)
VSOUT > 2.3V and the XTO is running
CLK
31
4689F–RKE–08/06
Figure 7-4.
Reset Logic, SR Latch Generates the Hysteresis in the NRESET Signal
DVCC_OK
and
≥1
XTO_OK
DVCC_RESET
VSOUT_EN
and
N_RESET
and
S
Q
R
Q
VSOUT_OK
LOW_BATT
7.5
S R
Q
0
0
1
1
no change
0
1
no change
0
1
0
1
1-Battery Application
The supply voltage range is 2.4V to 3.6V and VAUX is not used.
Figure 7-5.
1-Battery Application
ATA5811/ATA5812
Microcontroller
VS1
2.4V to 3.6V
VS2
VAUX
RF-Transceiver
Digital Control
Logic
AVCC
DVCC
VSOUT
VS
Microcontroller_Interface
VSINT
CS
OUT
SCK
OUT
SDI_TMDI
OUT
SDO_TMDO
IN
IRQ
IN
CLK
IN
NRESET
IN
DEM_OUT
32
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
7.6
2-Battery Application
The supply voltage range is 4.4V to 6.6V and VAUX is connected to an inductive supply.
Figure 7-6.
2-Battery Application with Inductive Emergency Supply
ATA5811/ATA5812
Microcontroller
VS1
VS2
4.4V to 6.6V
VAUX
RF-Transceiver
Digital Control
Logic
AVCC
DVCC
VSOUT
VS
Microcontroller_Interface
VSINT
CS
OUT
SCK
OUT
SDI_TMDI
OUT
SDO_TMDO
IN
IRQ
IN
CLK
IN
NRESET
IN
DEM_OUT
8. Microcontroller Interface
The microcontroller interface is a level converter which converts all internal digital signals which
are referred to the DVCC voltage, into the voltage used by the microcontroller. Therefore, the pin
VSINT has to be connected to the supply voltage of the microcontroller.
This makes it possible to use the internal voltage regulator/switch at pin VSOUT as in Figure 2-1
on page 6 and Figure 4-1 on page 8 or to connect the microcontroller and the pin VSINT directly
to the supply voltage of the microcontroller as in Figure 3-1 on page 7.
9. Digital Control Logic
9.1
Register Structure
The configuration of the transceiver is stored in RAM cells. The RAM contains a 16 × 8-bit
TX/RX data buffer and a 6 × 8-bit control register and is write and readable via a 4-wire serial
interface (CS, SCK, SDI_TMDI, SDO_TMDO).
The 1 × 8-bit status register is not part of the RAM and is readable via the 4-wire serial interface.
33
4689F–RKE–08/06
The RAM and the status information is stored as long as the transceiver is in any active mode
(DVCC = VS1 or DVCC = V_REG2) and gets lost if the transceiver is in OFF mode
(DVCC = OFF).
After the transceiver is turned on via pin PWR_ON = High, T1 = Low, T2 = Low, T3 = Low,
T4 = Low or T5 = Low or the voltage at pin VAUX VVAUX > 3.5V (typically) the control registers
are in the default state.
Figure 9-1.
Register Structure
LSB
MSB
TX/RX Data Buffer:
16 x 8 Bit
IR1
IR0
AVCC_
EN
FR6
FR5
FR4
FR3
-
-
-
-
FR8
FR7
ASK/
NFSK
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
-
FR2
OPM 1
OPM 0
T_MODE
Control Register 1 (ADR 0)
FR1
FR0
P_MODE
Control Register 2 (ADR 1)
VSOUT_
CLK_ON
En
Control Register 3 (ADR 2)
XSleep
Control Register 4 (ADR 3)
XLim
BitChk1 BitChk0 Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0
Control Register 5 (ADR 4)
Baud0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0
Control Register 6 (ADR 5)
Baud1
ST5
34
FS
ST4
ST3
ST2
ST1
Power_
On
Low_
Batt
P_On_
Aux
Status Register (ADR 8)
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
9.2
TX/RX Data Buffer
The TX/RX data buffer is used to handle the data transfer during RX and TX operations.
9.3
Control Register
To use the transceiver in different applications it can be configured by a connected microcontroller via the 4-wire serial interface.
9.3.1
Control Register 1 (ADR 0)
Table 9-1.
Control Register 1 (Function of Bit 7 and Bit 6 in RX Mode)
IR1
IR0
0
0
Pin IRQ is set to 1 if 4 received bytes are in the TX/RX data buffer or a receiving error
occurred
0
1
Pin IRQ is set to 1 if 8 received bytes are in the TX/RX data buffer or a receiving error
occurred
1
0
Pin IRQ is set to 1 if 12 received bytes are in the TX/RX data buffer or a receiving error
occurred (default)
1
1
Pin IRQ is set to 1 if a receiving error occurred
Table 9-2.
Function (RX Mode)
Control Register 1 (Function of Bit 7 and Bit 6 in TX Mode)
IR1
IR0
0
0
Pin IRQ is set to 1 if 4 bytes still are in the TX/RX data buffer or the TX data buffer is empty
0
1
Pin IRQ is set to 1 if 8 bytes still are in the TX/RX data buffer or the TX data buffer is empty
1
0
Pin IRQ is set to 1 if 12 bytes still are in the TX/RX data buffer or the TX data buffer is empty
(default)
1
1
Pin IRQ is set to 1 if the TX data buffer is empty
Table 9-3.
Function (TX Mode)
Control Register 1 (Function of Bit 5)
AVCC_EN
Function
0
(default)
1
Enables AVCC, if the ATA5811/ATA5812 is in AUX mode
Table 9-4.
FS
Control Register 1 (Function of Bit 4)
Function
0
433/868 MHz
1
315 MHz
Table 9-5.
Control Register 1 (Function of Bit 2 and Bit 1)
OPM1
OPM0
Function
0
0
Idle mode (default)
0
1
TX mode
1
0
RX polling mode
1
1
RX mode
35
4689F–RKE–08/06
Table 9-6.
Control Register 1 (Function of Bit 0)
T_MODE
9.3.2
Function
0
TX and RX function via TX/RX data buffer (default)
1
Transparent mode, TX/RX data buffer disabled, TX modulation data stream via pin
SDI_TMDI, RX modulation data stream via pin SDO_TMDO
Control Register 2 (ADR 1)
Table 9-7.
Control Register 2 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2 and Bit 1)
FR6
FR5
FR4
FR3
FR2
FR1
FR0
0
0
0
0
0
0
0
FREQ2 = 0
0
0
0
0
0
0
1
FREQ2 = 1
.
.
.
.
.
.
.
1
0
1
1
0
0
0
.
.
.
.
.
.
.
1
Note:
Control Register 2 (Function of Bit 0 in RX Mode)
P_MODE
Function (RX Mode)
0
Pin IRQ is set to 1 if the Bit-check is successful (default)
1
No effect on pin IRQ if the Bit-check is successful
Table 9-9.
Control Register 2 (Function of Bit 0 in TX Mode)
P_MODE
Function (TX Mode)
0
Manchester modulator on (default)
1
Manchester modulator off (NRZ mode)
Control Register 3 (ADR 2)
Table 9-10.
Control Register 3 (Function of Bit 3 and Bit 2)
FR8
FR7
0
0
FREQ3 = 0
0
1
FREQ3 = 128
1
0
FREQ3 = 256 (default)
1
Note:
36
FREQ2 = 88 (default)
1
1
1
1
1
1
FREQ2 = 127
Tuning of fRF LSB’s (total 9 bits), frequency trimming, resolution of fRF is fXTO/16384 which is
approximately 800 Hz (see “XTO” on page 23, Table 6-1 on page 25)
Table 9-8.
9.3.3
Function
Function
1
FREQ3 = 384
Tuning of fRF MSB’s
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
Table 9-11.
Control Register 3 (Function of Bit 1)
VSOUT_EN
0
1
Note:
Output voltage power supply for external devices off (pin VSOUT)
Output voltage power supply for external devices on (default)
This bit is set to 1 if the Bit-check is ok (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or
T5 occurs or the bit Power_On in the status register is 1.
Setting VSOUT_EN = 0 in AUX mode is not allowed
Table 9-12.
Control Register 3 (Function of Bit 0)
CLK_ON
Function
0
1
Note:
9.3.4
Function
Clock output off (pin CLK)
Clock output on (default)
This bit is set to 1 if the Bit-check is ok (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or
T5 occurs or the bit Power_On in the status register is 1.
Control Register 4 (ADR 3)
Table 9-13.
Control Register 4 (Function of Bit 7)
ASK_NFSK
Table 9-14.
Function
0
FSK mode (default)
1
ASK mode
Control Register 4 (Function of Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2)
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
Function Sleep
(TSleep = Sleep × 1024 × TDCLK × XSleep)
0
0
0
0
0
0
0
0
0
0
1
1
.
.
.
.
.
0
1
0
1
0
.
.
.
.
.
1
1
1
1
1
Table 9-15.
XSleep
10
(TSleep = 10 × 1024 × TDCLK × XSleep)
(default)
Control Register 4 (Function of Bit 1)
Function
0
XSleep = 1; extended TSleep off (default)
1
XSleep = 8; extended TSleep on
Table 9-16.
XLim
31
Control Register 4 (Function of Bit 0)
Function
0
XLim = 1; extended TLim_min, TLim_max off (default)
1
XLim = 2; extended TLim_min, TLim_max on
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9.3.5
Control Register 5 (ADR 4)
Table 9-17.
Table 9-18.
Control Register 5 (Function of Bit 7 and Bit 6)
BitChk1
BitChk0
0
0
NBit-check = 0 (0 bits checked during Bit-check)
Function
0
1
NBit-check = 3 (3 bits checked during Bit-check (default))
1
0
NBit-check = 6 (6 bits checked during Bit-check)
1
1
NBit-check = 9 (9 bits checked during Bit-check)
Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in RX Mode)
Function (RX Mode)
Lim_min
(Lim_min < 10 are not applicable)
Lim_min5
Lim_min4
Lim_min3
Lim_min2
Lim_min1
Lim_min0
(TLim_min = Lim_min × TXDCLK)
0
0
1
0
1
0
10
0
0
1
0
1
1
11
.
.
.
.
.
.
0
1
0
0
0
0
.
.
.
.
.
.
1
1
1
1
1
1
Table 9-19.
16
(TLim_min = 16 × TXDCLK)
(default)
63
Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in TX Mode)
Lim_min5
Lim_min4
Lim_min3
Lim_min2
Lim_min1
Lim_min0
Function (TX Mode) Lim_min
(Lim_min < 10 are not applicable)
(TX_Bitrate = 1/((Lim_min + 1) × TXDCLK × 2)
0
0
1
0
1
0
10
0
0
1
0
1
1
11
.
.
.
.
.
.
0
1
0
0
0
0
38
.
.
.
.
.
.
1
1
1
1
1
1
16
(TX_Bitrate = 1/((16 + 1) × TXDCLK × 2)
(default)
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9.3.6
Control Register 6 (ADR 5)
Table 9-20.
Table 9-21.
Control Register 6 (Function of Bit 7 and Bit 6)
Baud1
Baud0
Function
0
0
Bit-rate range 0 (B0) 1.0 Kbit/s to 2.5 Kbit/s;
TXDCLK = 8 × TDCLK × XLim
0
1
Bit-rate range 1 (B1) 2.0 Kbit/s to 5.0 Kbit/s;
TXDCLK = 4 × TDCLK × XLim
1
0
Bit-rate range 2 (B2) 4.0 Kbit/s to 10.0 Kbit/s;
TXDCLK = 2 × TDCLK × XLim; (default)
1
1
Bit-rate range 3 (B3) 8.0 Kbit/s to 20.0 Kbit/s;
TXDCLK = 1 × TDCLK × XLim,
Note that the receiver is not working with >10 Kbit/s in ASK mode
Control Register 6 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0)
Lim_max5
Lim_max4
Lim_max3
Lim_max2
Lim_max1
Lim_max0
Function Lim_max
(Lim_max < 12 Are Not Applicable)
(TLim_max = (Lim_max – 1) × TXDCLK)
0
0
1
1
0
0
12
0
0
1
1
0
1
13
.
.
.
.
.
.
0
1
1
1
0
0
.
.
.
.
.
.
1
1
1
1
1
1
9.3.7
28
(TLim_max = (28 – 1) × TXDCLK)
(default)
63
Status Register
The status register indicates the current status of the transceiver and is readable via the 4-wire
serial interface. Setting Power_On or P_On_Aux or an event on ST1, ST2, ST3, ST4 or ST5 is
indicated by an IRQ.
Reading the status register resets the bits Power_On, Low_Batt, P_On_Aux and the IRQ
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9.3.8
Status Register (ADR 8)
Table 9-22.
Status Bit
Function
ST5
Status of pin T5
Pin T5 = 0 → ST5 = 1
Pin T5 = 1 → ST5 = 0
(see Figure 9-3 on page 42)
ST4
Status of pin T4
Pin T4 = 0 → ST4 = 1
Pin T4 = 1 → ST4 = 0
(see Figure 9-3 on page 42)
ST3
Status of pin T3
Pin T3 = 0 → ST3 = 1
Pin T3 = 1 → ST3 = 0
(see Figure 9-3 on page 42)
ST2
Status of pin T2
Pin T2 = 0 → ST2 = 1
Pin T2 = 1 → ST2 = 0
(see Figure 9-3 on page 42)
ST1
Status of pin T1
Pin T1 = 0 → ST1 = 1
Pin T1 = 1 → ST1 = 0
(see Figure 9-3 on page 42)
Power_On
Indicates that the transceiver was woken up by pin PWR_ON (rising edge on pin
PWR_ON). During Power_On = 1, the bits VSOUT_EN and CLK_ON in control
register 3 are set to 1.
(see Figure 9-4 on page 43)
Low_Batt
Indicates that output voltage on pin VSOUT is too low
(VVSOUT < 2.38V typically)
(see Figure 9-5 on page 44)
P_On_Aux
40
Status Register
Indicates that the auxiliary supply voltage on pin VAUX is high enough to operate.
State transition:
a) OFF mode → AUX mode (see Figure 7-2 on page 29)
b) Idle mode (VSOUT = VS1) → Idle mode (VSOUT = V_REG2)
(see Figure 9-6 on page 45)
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
9.4
Pin Tn
To switch the transceiver from OFF to Idle mode, pin Tn must set to 0 (maximum 0.2 × VVS2) for
at least T Tn_IRQ (see Figure 9-2). The transceiver recognize the negative edge, sets pin
N_RESET to low and switches on DVCC, AVCC and the power supply for external devices
VSOUT.
If VDVCC exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and
sets the status bit STn to 1 and an interrupt is issued (TTn_IRQ).
After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is
elapsed the output clock on pin CLK is available. Because the enabling of pin CLK is asynchronous the first clock cycle may be incomplete. N_RESET is set to high if VVSOUT exceeds 2.38V
(typically) and the XTO is settled.
Figure 9-2.
Timing Pin Tn, Status Bit STn
Tn
VThres_2 = 2.38V (typ)
VThres_1 = 2.3V (typ)
VSOUT
1.5V (typ)
DVCC, AVCC
N_RESET
CLK
TTn_IRQ
STn
(Status register)
IRQ
OFF
Mode
IDLE
Mode
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If the transceiver is in any active mode (Idle, AUX, TX, RX, RX_Polling), an integrated debounce
logic is active. If there is an event on pin Tn a debounce counter is set to 0 (T = 0) and started.
The status is updated, an interrupt is issued and the debounce counter is stopped after reaching
the counter value T = 8195 × TDCLK.
An event on the same key input before reaching T = 8195 × TDCLK stops the debounce counter.
An event on an other key input before reaching T = 8195 × T DCLK resets and restarts the
debounce counter.
While the debounce counter is running, the bits VSOUT_EN and CLK_ON in control register 3
are set to 1.
The interrupt is deleted after reading the status register or executes the command Delete_IRQ.
If a pin Tn is not used, it can be left open because of an internal pull-up resistor (typically 50 kΩ).
Figure 9-3.
Timing Flow Pin Tn, Status Bit STn
IDLE Mode or
AUX Mode or
TX Mode or
RX Polling Mode or
RX Mode
Event on Pin Tn ?
N
Y
T=0
Start debounce counter
Event on Pin Tn ?
N
Y
T = 8195 × T ?
N
Y
Tn = STn ?
Y
Stop debounce counter
42
N
Pin Tn = 0 ?
N
Y
Stop debounce counter
STn = 1
IRQ = 1
Stop debounce counter
STn = 0
IRQ = 1
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ATA5811/ATA5812
9.5
Pin PWR_ON
To switch the transceiver from OFF to Idle mode, pin PWR_ON must set to 1 (minimum 0.8 ×
VVS2) for at least TPWR_ON (see Figure 9-4). The transceiver recognize the positive edge, sets pin
N_RESET to low and switches on DVCC, AVCC and the power supply for external devices
VSOUT.
If VDVCC exceeds 1.5 V (typically) and the XTO is settled, the digital control logic is active and
sets the status bit Power_On to 1 and an interrupt is issued (TPWR_ON_IRQ_1).
After the voltage on pin VSOUT exceeds 2.3 V (typically) and the start-up time of the XTO is
elapsed the output clock on pin CLK is available. Because the enabling of pin CLK is asynchronous the first clock cycle may be incomplete. N_RESET is set to high if VVSOUT exceeds 2.38 V
(typically) and the XTO is settled.
If the transceiver is in any active mode (Idle, AUX, RX, RX_Polling, TX), a positive edge on pin
PWR_ON sets Power_On to 1 (after TPWR_ON_IRQ_2). The state transition Power_On 0 → 1 generates an interrupt. If Power_On is still 1 during the positive edge on pin PWR_ON no interrupt is
issued. Power_On and the interrupt is deleted after reading the status register.
During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3 are set to 1.
Note:
Figure 9-4.
It is not possible to set the transceiver to OFF mode by setting pin PWR_ON to 0. If pin PWR_ON
is not used, it must be connected to GND.
Timing Pin PWR_ON, Status Bit Power_On
TPWR_ON > TPWR_ON_IRQ_1
TPWR_ON > TPWR_ON_IRQ_2
PWR_ON
VThres_2 = 2.38V (typ)
VSOUT
VThres_1 = 2.3V
(typ)
DVCC, AVCC
1.5V (typ)
N_RESET
CLK
TPWR_ON_IRQ_1
TPWR_ON_IRQ_2
Power_ON
(Status register)
IRQ
OFF
Mode
IDLE
Mode
IDLE, AUX, RX, RX Polling, TX
Mode
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9.6
Low Battery Indicator
The status bit Low_Batt is set to 1 if the voltage on pin VSOUT V VSOUT drops under 2.38V
(typically).
Low_Batt is set to 0 if VVSOUT exceeds VThres_2 and the status register is read via the 4-wire serial
interface (see Figure 7-3 on page 31).
Figure 9-5.
Timing Status Bit Low_Batt
IDLE, AUX, TX, RX
or
RX Polling Mode
VVSOUT < 2.38V (typ)
?
No
Yes
Low_Batt = 1
Read Status Register
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9.7
Pin VAUX
To switch the transceiver from OFF to AUX mode, the voltage on pin VAUX VVAUX must exceed
3.5V (typically) (see Figure 9-6). If VVAUX exceeds 2V (typically) pin N_RESET is set to low,
DVCC and the power supply for external devices VSOUT are switched on.
If VVAUX exceeds 3.5V (typically) the status bit P_On_Aux is set to 1 and an interrupt is issued.
After the voltage on pin VSOUT exceeds 2.3 V (typically) and the start-up time of the XTO is
elapsed the output clock on pin CLK is available. Because the enabling of pin CLK is asynchronous the first clock cycle may be incomplete. N_RESET is set to high if VVSOUT exceeds 2.38V
(typically) and the XTO is settled.
If the transceiver is in any active mode (Idle, TX, RX, RX_Polling), a positive edge on pin VAUX
and VVAUX > VS1 + 0.5V sets P_On_Aux to 1. The state transition P_On_Aux 0 → 1 generates
an interrupt. If P_On_Aux is still 1 during the positive edge on pin VAUX no interrupt is issued.
P_On_Aux and the interrupt is deleted after reading the status register.
Figure 9-6.
Timing Pin VAUX, Status Bit P_On_Aux
VAUX
VSOUT
VVAUX > VS1 + 0.5V (typ)
3.5V (typ)
2.0V (typ)
VVAUX > VS1 + 0.5V (typ)
VThres_2 = 2.38V (typ)
VThres_1 = 2.3V (typ)
DVCC
N_RESET
CLK
P_ON_AUX
(Status register)
IRQ
OFF
Mode
AUX
Mode
IDLE, TX, RX, RX polling
Mode
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10. Transceiver Configuration
The configuration of the transceiver takes place via a 4-wire serial interface (CS, SCK,
SDI_TMDI, SDO_TMDO) and is organized in 8-bit units. The configuration is initiated with a 8-bit
command. While shifting the command into pin SDI_TMDI, the number of bytes in the TX/RX
data buffer are available on pin SDO_TMDO. The read and write commands are followed by one
or more 8-bit data units. Each 8-bit data transmission begins with the MSB. The serial interface
is in reset state if the level on pin CS = Low.
10.1
Command: Read TX/RX Data Buffer
During a RX operation the user can read the received bytes in the TX/RX data buffer
successively.
Figure 10-1. Read TX/RX Data Buffer
MSB
SDI_TMDI
SDO_TMDO
LSB
MSB
LSB
MSB
LSB
Command: Read TX/RX Data Buffer
X
X
Nr. Bytes in the TX/RX Data Buffer
RX Data Byte 1
RX Data Byte 2
SCK
CS
10.2
Command: Write TX/RX Data Buffer
During a TX operation the user can write the bytes in the TX/RX data buffer successively. An
echo of the command and the TX data bytes are provided for the microcontroller on pin
SDO_TMDO.
Figure 10-2. Write TX/RX Data Buffer
MSB
SDI_TMDI
SDO_TMDO
LSB
MSB
LSB
MSB
LSB
Command: Write TX/RX Data Buffer
TX Data Byte 1
TX Data Byte 2
Nr. Bytes in the TX/RX Data Buffer
Write TX/RX Data Buffer
TX Data Byte 1
SCK
CS
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10.3
Command: Read Control/Status Register
The control and status registers can be read individually or successively.
Figure 10-3. Read Control/Status Register
MSB
SDI_TMDI
SDO_TMDO
LSB
MSB
LSB
MSB
LSB
Command: Read C/S Register X
Command: Read C/S Register Y
Command: Read C/S Register Z
Nr. Bytes in the TX/RX Data Buffer
Data C/S Register X
Data C/S Register Y
SCK
CS
10.4
Command: Write Control Register
The control registers can be written individually or successively. An echo of the command and
the data bytes are provided for the microcontroller on pin SDO_TMDO.
Figure 10-4. Write Control Register
MSB
SDI_TMDI
SDO_TMDO
LSB
MSB
LSB
MSB
LSB
Command: Write Control Register X
Data Control Register X
Command: Write Control Register Y
Nr. Bytes in the TX/RX Data Buffer
Write Control Register X
Data Control Register X
SCK
CS
10.5
Command: OFF Command
If AVCC_EN in control register 1 is 0, the input level on pin PWR_ON is low and on the key
inputs Tn is high, the OFF command sets the transceiver in the OFF mode.
Figure 10-5. OFF Command
MSB
SDI_TMDI
SDO_TMDO
LSB
Command: OFF Command
Nr. Bytes in the TX/RX Data Buffer
SCK
CS
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10.6
Command: Delete IRQ
The delete IRQ command sets pin IRQ to low.
Figure 10-6. Delete IRQ
MSB
SDI_TMDI
SDO_TMDO
LSB
Command: Delete IRQ
Nr. Bytes in the TX/RX Data Buffer
SCK
CS
10.7
Command Structure
The three most significant bits of the command (Bit 5 to Bit 7) indicates the command type. Bit 0
to Bit 4 describes the target address when reading or writing a control or status register. In all
other commands Bit 0 to Bit 4 have no effect and should be set to 0 for compatibility reasons
with future products.
Table 10-1.
Command Structure
MSB
Command
10.8
LSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read TX/RX data buffer
0
0
0
x
x
x
x
x
Write TX/RX data buffer
0
0
1
x
x
x
x
x
Read control/status register
0
1
0
A4
A3
A2
A1
A0
Write control register
0
1
1
A4
A3
A2
A1
A0
OFF command
1
0
0
X
X
X
X
X
Delete IRQ
1
0
1
X
X
X
X
X
Not used
1
1
0
X
X
X
X
X
Not used
1
1
1
X
X
X
X
X
4-wire Serial Interface
The 4-wire serial interface consists of the Chip Select (CS), the Serial ClocK (SCK), the Serial
Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received
bit by bit in synchronization with the serial clock.
Note:
If the output level on pin N_RESET is low, no data communication with the microcontroller is
possible.
When CS is low and the transparent mode is inactive (T_MODE = 0), SDO_TMDO is in a
high-impedance state. When CS is low and the transparent mode is active (T_MODE = 1), the
RX data stream is available on pin SDO_TMDO.
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Figure 10-7. Serial Timing
TCS_disable
CS
TCS_setup
TSCK_setup2
TCycle
TSCK_setup1
SCK
TSCK_hold
X
X
THold
TSetup
SDI_TMDI
X
MSB
TOut_enable
SDO_TMDO
X
MSB-1
X
X
TOut_delay
TOut_disable
MSB
MSB-1
LSB
X can be either ViI or ViH
11. Operation Modes
11.1
RX Operation
The transceiver is set to RX operation with the bits OPM0 and OPM1 in control register 1
Table 11-1.
Control Register 1
OPM1
OPM0
Function
1
0
RX polling mode
1
1
RX mode
The transceiver is designed to consume less than 1 mA in RX operation while being sensitive to
signals from a corresponding transmitter. This is achieved via the polling circuit. This circuits
enables the signal path periodically for a short time. During this time the Bit-check logic verifies
the presence of a valid transmitter signal. Only if a valid signal is detected the transceiver
remains active and transfers the data to the connected microcontroller. This transfer take place
either via the TX/RX data buffer or via the pin SDO_TMDO. If there is no valid signal present the
transceiver is in sleep mode most of the time resulting in low current consumption. This condition
is called RX polling mode. A connected microcontroller can be disabled during this time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc.
In RX mode the RF transceiver is enabled permanently and the Bit-check logic verifies the presence of a valid transmitter signal. If a valid signal is detected the transceiver transfers the data to
the connected microcontroller. This transfer take place either via the TX/RX data buffer or via
the pin SDO_TMDO.
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11.1.1
RX Polling Mode
If the transceiver is in RX polling mode it stays in a continuous cycle of three different modes. In
sleep mode the RF transceiver is disabled for the time period TSleep while consuming low current
of IS = IIDLE_X. During the start-up period, TStartup_PLL and TStartup_Sig_Proc, all signal processing circuits are enabled and settled. In the following Bit-check mode, the incoming data stream is
analyzed bit by bit contra a valid transmitter signal. If no valid signal is present, the transceiver is
set back to sleep mode after the period TBit-check. This period varies check by check as it is a statistical process. An average value for TBit-check is given in the electrical characteristics. During
TStartup_PLL the current consumption is IS = IRX_X. During TStartup_Sig_Proc and TBit-check the current
consumption is I S = I Startup_Sig_Proc_X . The condition of the transceiver is indicated on pin
RX_ACTIVE (see Figure 11-1 on page 51 and Figure 11-2 on page 52). The average current
consumption in RX polling mode IP is different in 1 battery application, 2 battery application or
car application. To calculate IP the index X must be replaced by VS1, 2 in 1 battery application,
VS2 in 2 battery application or VS2, VAUX in car application (see section “Electrical Characteristics: General” on page 63)
I IDLE_X × T Sleep + I Startup_PLL_X × T Startup_PLL + I RX_X × ( T Startup_Sig_Proc + T Bitcheck )
I P = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------T Sleep + T Startup_PLL + T Startup_Sig_Proc + T Bit_check
To save current it is recommended CLK and VVSOUT be disabled during RX polling mode. IP does
not include the current of the Microcontroller_Interface IVSINT and the current of an external
device connected to pin VSOUT (e.g., microcontroller). If CLK and/or VSOUT is enabled during
RX polling mode the current consumption is calculated as follows:
I S_Poll = I P + I VSINT + I EXT
During TSleep, TStartup_PLL and TStartup_Sig_Proc the transceiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command the transmitter must start the
telegram with an adequate preburst. The required length of the preburst TPreburst depends on the
polling parameters TSleep, TStartup_PLL, TStartup_Sig_Proc and TBit-check. Thus, TBit-check depends on the
actual bit rate and the number of bits (NBit-check) to be tested
T Preburst ≥ T Sleep + T Startup_PLL + T Startup_Sig_Proc + T Bit_check
11.1.2
Sleep Mode
The length of period TSleep is defined by the 5-bit word sleep in control register 4, the extension
factor XSleep defined by the bit XSleep in control register 4 and the basic clock cycle TDCLK. It is
calculated to be:
T Sleep = Sleep × 1024 × T DCLK × X Sleep
In US and European applications, the maximum value of TSleep is about 38 ms if XSleep is set to 1
(which is done by setting the bit XSleep in control register 4 to 0). The time resolution is about
1.2 ms in that case. The sleep time can be extended to about 300 ms by setting XSleep to 8
(which is done by setting XSleep in control register 4 to 1), the time resolution is then about
9.6 ms.
11.1.3
Start-up Mode
During TStartup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing
circuit starts up (TStartup_Sig_Proc). After the start-up time all circuits are in stable condition and
ready to receive.
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Figure 11-1. Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Inactive)
Start RX Polling Mode
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.
Output level on pin RX_ACTIVE ⇒ Low; IS = IIDLE_X
TSleep = Sleep × 1024 × TDCLK × XSleep
Sleep:
XSleep:
TDCLK:
Defined by bits Sleep 0 to Sleep 4 in Control
Register 4
Defined by bit XSleep in Control register 4
Basic clock cycle
TStartup_PLL:
798.5 × TDCLK (typ)
TStartup_Sig_Proc:
882 × TDCLK
498 × TDCLK
306 × TDCLK
210 × TDCLK
Start RX Mode
Start-up mode:
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE ⇒ High; IS = IStartup_PLL_X; TStartup_PLL
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE ⇒ High; IS = IRX_X; TStartup_Sig_proc
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
Is defined by the selected baud rate range and
TDCLK .The baud-rate range is defined by bit
Baud 0 and Baud 1 in Control Register 6.
Bit-check mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,
the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to
receiving mode. Otherwise it is set to Sleep mode or to Start_up mode.
Output level on pin RX_ACTIVE ⇒ High
IS = IRX_X; TBit-check
TBit-check:
NO
Bit check
OK ?
YES
OPM0 = 1
?
Set VSOUT_EN = 1
Set CLK_ON = 1
Set OPM0 = 1
NO
YES
NO
NO
Depends on the result of the bit check.
If the bit check is ok, TBit-check depends on the
number of bits to be checked (NBit-check) and
on the utilized data rate.
If the bit check fails, the average time period for
that check despends on the selected baud-rate
range and on TXDCLK. The baud-rate range is
defined by bit Baud 0 and Baud 1 in Control
Register 6.
P_MODE = 0
?
YES
TSLEEP = 0
?
Set IRQ
YES
Receiving mode:
The incomming data stream is passed via the TX/RX Data Buffer to the connected
microcontroller. If an bit error occurs the transceiver is set back to Start-up mode.
Output level on pin RX_ACTIVE ⇒ High
IS = IRX_X
Start bit
detected ?
NO
If the transceiver detects a bit errror after a
successful bit check and before the start bit is
detected pin IRQ will be set to high (only if
P_MODE = 0) and the transceiver is set back to
start-up mode.
YES
RX data stream is
written into the TX/RX
Data Buffer
Bit error ?
NO
YES
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4689F–RKE–08/06
Figure 11-2. Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Active)
Start RX Polling Mode
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.
Output level on pin RX_ACTIVE ⇒ Low; IS = IIDLE_X
TSleep = Sleep × 1024 × TDCLK × XSleep
Sleep:
XSleep:
TDCLK:
Defined by bits Sleep 0 to Sleep 4 in Control
Register 4
Defined by bit XSleep in Control register 4
Basic clock cycle
TStartup_PLL:
798.5 × TDCLK (typ)
TStartup_Sig_Proc:
882 × TDCLK
498 × TDCLK
306 × TDCLK
210 × TDCLK
Start RX Mode
Start-up mode:
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE ⇒ High; IS = IStartup_PLL_X; TStartup_PLL
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE ⇒ High; IS = IRX_X; TStartup_Sig_proc
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
Is defined by the selected baud rate range and
TDCLK .The baud-rate range is defined by bit
Baud 0 and Baud 1 in Control Register 6.
Bit-check mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,
the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to
receiving mode. Otherwise the transceiver is set to Sleep mode
(if OPM0 = 0 and TSleep > 0) or stays in Bit-check mode.
Output level on pin RX_ACTIVE ⇒ High
IS = IRX_X; TBit-check
NO
Bit check
OK ?
YES
OPM0 = 1
?
Depends on the result of the bit check.
If the bit check is ok, TBit-check depends on the
number of bits to be checked (NBit-check) and
on the utilized data rate.
NO
YES
Set VSOUT_EN = 1
Set CLK_ON = 1
Set OPM0 = 1
NO
TBit-check:
If the bit check fails, the average time period for
that check despends on the selected baud-rate
range and on TXDCLK. The baud-rate range is
defined by bit Baud 0 and Baud 1 in Control
Register 6.
TSLEEP = 0
?
YES
Receiving mode:
The incomming data stream is passed via PIN SDO_TMDO to the connected
microcontroller. If an bit error occurs the transceiver is not set back to Start-up mode.
Output level on pin RX_ACTIVE ⇒ High
IS = IRX_X
Level on pin
CS = Low ?
NO
If in FSK mode the datastream is interrupted the
FSK-Demodulator-PLL tends to lock out and is
further not able to lock in, even there is a valid
data stream available.
In this case the transceiver must be set back to
IDLE mode.
YES
RX data stream
available on pin
SDO_TMDO
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11.1.4
Bit-check Mode
In Bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distance between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge to edge test before the transceiver
switches to receiving mode is also programmable.
11.1.5
Configuration the Bit-check
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The
maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBit-check in
control register 5. This implies 0, 6, 12 and 18 edge to edge checks respectively. If NBit-check is
set to a higher value, the transceiver is less likely to switch to receiving mode due to noise. In the
presence of a valid transmitter signal, the Bit-check takes less time if NBit-check is set to a lower
value. In RX polling mode, the Bit-check time is not dependent on NBit-check. Figure 11-3 shows
an example where 3 bits are tested successful.
Figure 11-3. Timing Diagram for Complete Successful Bit-check (Number of Checked Bits: 3)
RX_ACTIVE
Bit check ok
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
Demod_Out
TStartup_Sig_Proc
TBit-check
Start-up mode
Bit check mode
Receiving mode
According to Figure 11-4, the time window for the Bit-check is defined by two separate time limits. If the edge to edge time tee is in between the lower Bit-check limit TLim_min and the upper
Bit-check limit TLim_max, the check will be continued. If tee is smaller than limit TLim_min or exceeds
TLim_max, the Bit-check will be terminated and the transceiver switches to sleep mode.
Figure 11-4. Valid Time Window for Bit-check
1/fSig
Demod_Out
tee
TLim_min
TLim_max
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4689F–RKE–08/06
For the best noise immunity it is recommended to use a low span between TLim_min and TLim_max.
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
'11111...' or a '10101...' sequence in Manchester or Bi-phase is a good choice concerning that
advice. A good compromise between sensitivity and susceptibility to noise regarding the
expected edge to edge time tee is a time window of ±38%, to get the maximum sensitivity the
time window should be ±50% and then NBit-check ≥ 6. Using preburst patterns that contain various
edge to edge time periods, the Bit-check limits must be programmed according to the required
span.
The Bit-check limits are determined by means of the formula below:
TLim_min = Lim_min × TXDCLK
TLim_max = (Lim_max – 1) × TXDCLK
Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.
Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
TLim_min, TLim_max and TXDCLK. The time resolution defining TLim_min and TLim_max is TXDCLK. The
minimum edge to edge time tee is defined according to the section “Receiving Mode”. The lower
limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63.
Figure 11-5, Figure 11-6 on page 55, and Figure 11-7 on page 55 illustrate the Bit-check for the
Bit-check limits Lim_min = 14 and Lim_max = 24. The signal processing circuits are enabled
during TStartup_PLL and TStartup_Sig_Proc. The output of the ASK/FSK demodulator (Demod_Out) is
undefined during that period. When the Bit-check becomes active, the Bit-check counter is
clocked with the cycle TXDCLK.
Figure 11-5 shows how the Bit-check proceeds if the Bit-check counter value CV_Lim is within
the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 11-6 on
page 55 the Bit-check fails as the value CV_Lim is lower than the limit Lim_min. The Bit-check
also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 11-7 on page 55.
Figure 11-5. Timing Diagram During Bit-check
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit check ok
Bit check ok
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
Demod_Out
Bit-check counter
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 1112131415 1 2 3 4 5 6 7
TXDCLK
TStartup_Sig_Proc
Start-up mode
54
TBit-check
Bit check mode
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
Figure 11-6. Timing Diagram for Failed Bit-check (Condition CV_Lim < Lim_min)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit check failed (CV_Lim < Lim_min)
Bit check
1/2 Bit
Demod_Out
Bit-check counter
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112
TStartup_Sig_Proc
0
TBit_check
Start-up mode
TSleep
Bit check mode
Sleep mode
Figure 11-7. Timing Diagram for Failed Bit-check (Condition: CV_Lim ≥ Lim_max)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit check failed (CV_Lim < Lim_min)
Bit check
1/2 Bit
Demod_Out
Bit-check counter
0
TStartup_Sig_Proc
Start-up mode
11.1.6
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718192021222324
TBit_check
Bit check mode
0
TSleep
Sleep mode
Duration of the Bit-check
If no transmitter is present during the Bit-check, the output of the ASK/FSK demodulator delivers
random signals. The Bit-check is a statistical process and TBit-check varies for each check. Therefore, an average value for TBit-check is given in the electrical characteristics. TBit-check depends on
the selected bit rate range and on TXDCLK. A higher bit-rate range causes a lower value for
TBit-check resulting in a lower current consumption in RX polling mode.
In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that signal, fSig, and the count of the bits, NBit-check. A higher value for NBit-check thereby results in a longer
period for TBit-check requiring a higher value for the transmitter preburst TPreburst.
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4689F–RKE–08/06
11.1.7
Receiving Mode
If the Bit-check was successful for all bits specified by NBit-check, the transceiver switches to
receiving mode. To activate a connected microcontroller, the bits VSOUT_EN and CLK_ON in
control register 3 are set to 1. An interrupt is issued at pin IRQ if the control bits T_MODE = 0
and P_MODE = 0.
If the transparent mode is active (T_MODE = 1) and the level on pin CS is low (no data transfer
via the serial interface), the RX data stream is available on pin SDO_TMDO (Figure 11-8).
Figure 11-8. Receiving Mode (TMODE = 1)
Preburst
Bit check ok
Start
bit
Byte 1
Byte 2
Byte 3
Demod_Out
'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'
SDO_TMDO
Bit-check mode
Receiving mode
If the transparent mode is inactive (T_MODE = 0), the received data stream is buffered in the
TX/RX data buffer (see Figure 11-9 on page 57). The TX/RX data buffer is only usable for
Manchester and Bi-phase coded signals. It is permanently possible to transfer the data from the
data buffer via the 4-wire serial interface to a microcontroller (see Figure 10-1 on page 46).
Buffering of the data stream:
After a successful Bit-check, the transceiver switches from Bit-check mode to receiving mode. In
receiving mode the TX/RX data buffer control logic is active and examines the incoming data
stream. This is done, like in the Bit-check, by subsequent time frame checks where the distance
between two edges is continuously compared to a programmable time window as illustrated in
Figure 11-9 on page 57, only two distances between two edges in Manchester and Bi-phase
coded signals are valid (T and 2T).
The limits for T are the same as used for the Bit-check. They can be programmed in control
register 5 and 6 (Lim_min, Lim_max).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Lim_min_2T = ( Lim_min + Lim_max ) – ( Lim_max – Lim_min ) ⁄ 2
T Lim_min_2T = Lim_min_2T × T XDCLK
Upper limit of 2T:
Lim_max_2T = ( Lim_min + Lim_max ) + ( Lim_max – Lim_min ) ⁄ 2
T Lim_max_2T = ( Lim_max_2T - 1 ) × T XDCLK
If the result of Lim_min_2T or Lim_max_2T is not an integer value, it will be round up.
56
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If the TX/RX data buffer control logic detects the start bit, the data stream is written in the TX/RX
data buffer byte by byte. The start bit is part of the first data byte and must be different from the
bits of the preburst. If the preburst consists of a sequence of '00000...', the start bit must be a 1.
If the preburst consists of a sequence of '11111...', the start bit must be a 0.
If the data stream consists of more than 16 bytes, a buffer overflow occurs and the TX/RX data
buffer control logic overwrites the bytes already stored in the TX/RX data buffer. So it is very
important to ensure that the data is read in time so that no buffer overflow occurs in that case
(see Figure 10-1 on page 46). There is a counter that indicates the number of received bytes in
the TX/RX data buffer (see section “Transceiver Configuration”). If a byte is transferred to the
microcontroller, the counter is decremented, if a byte is received, the counter is incremented.
The counter value is available via the 4-wire serial interface.
An interrupt is issued, if the counter while counting forwards reaches the value defined by the
control bits IR0 and IR1 in control register 1.
Figure 11-9. Receiving Mode (TMODE = 0)
Preburst
T
Bit check ok
Start
bit
Byte 1
Byte 2
Byte 3
2T
Demod_Out
'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'
Bit-check mode
Receiving mode
TX/RX data Buffer
Byte 16, Byte 32, ...
Byte 15, Byte 31, ...
Byte 14, Byte 30, ...
Byte 13, Byte 29, ...
Byte 12, Byte 28, ...
Byte 11, Byte 27, ...
Byte 10, Byte 26, ...
Byte 9, Byte 25, ...
Byte 8, Byte 24, ...
Byte 7, Byte 23, ...
Byte 6, Byte 22, ...
Byte 5, Byte 21, ...
Byte 4, Byte 20, ...
Byte 3, Byte 19, ...
1 1 1 1 0 0 1 1 Byte 2, Byte 18, ...
1 0 1 0 0 0 0 0 Byte 1, Byte 17, ...
MSB
LSB
Readable via 4-wire serial interface
If the TX/RX data buffer control logic detects a bit error, an interrupt is issued and the transceiver
is set back to the start-up mode (see Figure 11-1 on page 51, Figure 11-2 on page 52and Figure
11-10 on page 58).
Bit error:
a) tee < TLim_min or TLim_max < tee < TLim_min_2T or tee > TLim_max_2T
b) Logical error (no edge detected in the bit center)
Note:
The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus it is not available via the 4-wire serial interface.
Writing the control register 1, 4, 5 or 6 during receiving mode resets the TX/RX data buffer control logic and the counter which indicates the number of received bytes. If the bits OPM0 and
OPM1 are still '1' after writing to a control register, the transceiver changes to the start-up mode
(start-up signal processing).
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4689F–RKE–08/06
Figure 11-10. Bit Error (TMODE = 0)
Bit check ok
Bit error
Demod_Out
Byte n-1
Byte n+1
Byte n
Receiving mode
Table 11-2.
Mode
Start-up mode Bit-check mode
Byte 1
Receiving mode
RX Modulation Scheme
ASK/_NFSK
0
RX
1
11.1.8
Preburst
T_MODE
RFIN
Bit in TX/RX Data
Buffer
Level on Pin
SD0_TMDO
0
fFSK_L → fFSK_H
1
Z
0
fFSK_H → fFSK_L
0
Z
1
fFSK_H
–
1
1
fFSK_L
–
0
0
fASK off → fASK on
1
Z
0
fASK on → fASK off
0
Z
1
fASK on
–
1
1
fASK off
–
0
Recommended Lim_min and Lim_max for Maximum Sensitivity
The sensitivity measurement in the section “Low-IF Receiver” in Table 5-3 on page 11 and Table
5-4 on page 11 have been done with the Lim_min and Lim_max values according to Table 11-3.
These values are optimized for maximum sensitivity. Note that since these Limits are optimized
for sensitivity the number of checked bit NBit-check has to be at least 6 to prevent the circuit from
waking up to a often in polling mode due to noise.
Table 11-3.
Recommended Lim_min and Lim_max Values for Different Bit Rates
fRF (fXTAL)/ 1.0 Kbit/s
2.4 Kbit/s
5 Kbit/s
10 Kbit/s
20 Kbit/s
MHz
BR_Range_0/XLim = 1 BR_Range_0/XLim = 0 BR_Range_1/XLim = 0 BR_Range_2/XLim = 0 BR_Range_3/XLim = 0
315.0
Lim_min = 13 (261 µs) Lim_min = 12 (121 µs) Lim_min = 11 (55 µs) Lim_min = 11 (28 µs)
(12.73193) Lim_max = 38 (744 µs) Lim_max = 34 (332 µs) Lim_max = 32 (156 µs) Lim_max = 32 (78 µs)
Lim_min = 11 (14 µs)
Lim_max = 31 (38 µs)
433.92
Lim_min = 13 (251 µs) Lim_min = 12 (116 µs) Lim_min = 11 (53 µs) Lim_min = 11 (27 µs)
(13.25311) Lim_max = 38 (715 µs) Lim_max = 34 (319 µs) Lim_max = 32 (150 µs) Lim_max = 32 (75 µs)
Lim_min = 11 (13 µs)
Lim_max = 32 (37 µs)
868.3
Lim_min = 13 (248 µs) Lim_min = 12 (115 µs) Lim_min = 11 (52 µs) Lim_min = 11 (26 µs)
(13.41191) Lim_max = 38 (706 µs) Lim_max = 34 (315 µs) Lim_max = 32 (148 µs) Lim_max = 32 (74 µs)
Lim_min = 11 (13 µs)
Lim_max = 32 (37 µs)
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11.2
TX Operation
The transceiver is set to TX operation by using the bits OPM0 and OPM1 in the control
register 1.
Table 11-4.
Control Register 1
OPM1
OPM0
Function
0
1
TX mode
Before activating TX mode, the TX parameters (bit rate, modulation scheme ... ) must be
selected as illustrated in Figure 11-11 on page 60. The bit rate depends on Baud0 and Baud1 in
control register 6, Lim_min0 to Lim_min5 in control register 5 and XLIM in control register 4 (see
section “Control Register” on page 35). The modulation is selected with ASK_/NFSK in control
register 4. The FSK frequency deviation is fixed to about ±16 kHz. If P_Mode is set to 1, the
Manchester modulator is disabled and pattern mode is active (NRZ, see Table 11-5 on page
62).
After the transceiver is set to TX mode the start-up mode is active and the PLL is enabled. If the
PLL is locked, the TX mode is active.
If the transceiver is in start-up or TX mode, the TX/RX data buffer can be loaded via the 4-wire
serial interface. After the first byte is in the buffer and the TX mode is active, the transceiver
starts transmitting automatically (beginning with the MSB). While transmitting it is permanently
possible to load new data in the TX/RX data buffer. To prevent a buffer overflow or interruptions
during transmitting the user must ensure that data is loaded at the same speed as it is
transmitted.
There is a counter that indicates the number of bytes to be transmitted (see section “Transceiver
Configuration” on page 46). If a byte is loaded, the counter is incremented, if a byte is transmitted, the counter is decremented. The counter value is available via the 4-wire serial interface. An
IRQ is issued, if the counter while counting backwards reaches the value defined by the control
bits IR0 and IR1 in control register 1.
Note:
Writing to the control register 1, 4, 5 or 6 during TX mode, resets the TX/RX data buffer and the
counter which indicates the number of bytes to be transmitted.
If T_Mode in control register 1 is set to 1, the transceiver is in TX transparent mode. In this mode
the TX/RX data buffer is disabled and the TX data stream must be applied on pin SDI_TMDI.
Figure 11-11 on page 60 illustrates the flow chart of the TX transparent mode.
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4689F–RKE–08/06
Figure 11-11. TX Operation (T_MODE = 0)
Write Control Register 6
Baud1, BAUD0:
Lim_max0 to Lim_max5:
Select baud rate range
Don't care
Write Control Register 5
Lim_min0 to Lim_min5:
Bit_ck0, Bit_ck1:
Select the baud rate
Don't care
Write Control Register 4
XLim:
ASK/_NFSK:
Sleep0 to Sleep4:
XSleep:
Select the baud rate
Select modulation
Don't care
Don't care
Write Control Register 3
FR7, FR8:
VSOUT_EN:
CLK_ON:
Adjust fRF
Set VSOUT_EN = 1
Don't care
Write Control Register 2
FR0 to FR6:
P_mode:
Write Control Register 1
IR1, IR0:
AVCC_EN:
FS:
OPM1, OPM0:
T_mode:
Idle Mode
Adjust fRF
Enable or disable the
Manchester modulator
Select an event which activates
an interrupt
Don't care
Select operation frequency
Set OPM1 = 0 and OPM0 = 1
Set T_mode = 0
Write TX/RX Data Buffer (max. 16 byte)
Start-up
Mode (TX)
TStartup = 331.5 × TDCLK
N
Pin IRQ = 1 ?
Y
N
TX more Data
Bytes ?
Y
Command: Delete_IRQ
N
TX Mode
Write TX/RX Data Buffer (max. 16 - number of bytes still
in the TX/RX Data Buffer)
Pin IRQ = 1 ?
Y
Write Control Register 1
OPM1, OPM0:
Set IDLE
Idle Mode
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Figure 11-12. TX Transparent Mode (T_MODE = 1)
Write Control Register 4
XLim:
ASK/_NFSK:
Sleep0 to Sleep4:
XSleep:
Don't care
Select modulation
Don't care
Don't care
Write Control Register 3
FR7, FR8:
VSOUT_EN:
CLK_ON:
Adjust fRF
Set VSOUT_EN = 1
Don't care
Idle Mode
Write Control Register 2
FR0 to FR6:
P_mode:
Write Control Register 1
IR1, IR0:
AVCC_EN:
FS:
OPM1, OPM0:
T_mode:
Adjust fRF
Don't care
Don't care
Don't care
Select operation frequency
Set OPM1 = 0 and OPM0 = 1
Set T_mode = 1
Start-up
Mode (TX)
TStartup = 331.5 × TDCLK
Apply TX Data on Pin SDI_TMDI
Write Control Register 1
OPM1, OPM0:
TX Mode
Set IDLE (OPM1 = 0, OPM0 = 1
Idle Mode
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4689F–RKE–08/06
Table 11-5.
Mode
TX Modulation Schemes
ASK/_NFSK
P_Mode
T_Mode
Bit in TX/RX
Data Buffer
Level on Pin
SDI_TMDI
RFOUT
0
0
1
X
fFSK_L → fFSK_H
0
0
0
X
fFSK_H → fFSK_L
1
0
1
X
fFSK_H
0
TX
1
11.3
1
0
0
X
fFSK_L
X
1
X
1
fFSK_H
X
1
X
0
fFSK_L
0
0
1
X
fASK off → fASK on
0
0
0
X
fASK on → fASK off
1
0
1
X
fASK on
1
0
0
X
fASK off
X
1
X
1
fASK on
X
1
X
0
fASK off
Interrupts
Via pin IRQ, the transceiver signals different operating conditions to a connected microcontroller. If a specific operating condition occurs, pin IRQ is set to high level. If an interrupt occurs it is
recommended to delete the interrupt be immediately deleted by reading the status register, thus
the next possible interrupt doesn’t get lost. If the Interrupt pin doesn’t switch to low level by reading the status register the interrupt was triggered by the RX/TX data buffer. In this case read or
write the RX/TX data buffer according to Table 11-6.
Table 11-6.
Interrupt Handling
Operating Conditions Which Sets Pin IRQ to
High Level
Operations Which Sets Pin IRQ to Low Level
Events in Status Register
State transition of status bit STn
(0 → 1; 1 → 0)
Appearance of status bit Power_On
(0 → 1)
Read status register or
Command Delete IRQ
Appearance of status bit P_On_Aux
(0 → 1)
Events During TX Operation (T_MODE = 0)
4, 8 or 12 Bytes are in the TX data buffer or the
TX data buffer is empty (depends on IR0 and
IR1 in control register 1).
Write TX data buffer or
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Command delete IRQ
Events During RX Operation (T_MODE = 0)
4, 8 or 12 received bytes are in the RX data
buffer or a receiving error is occurred (depends
on IR0 and IR1 in control register 1).
Successful Bit-check (P_MODE = 0)
Note:
62
Read RX data buffer(1) or
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Command delete IRQ
1. During reading of the RX/TX buffer, no IRQ is issued, due to the received bytes or a receiving
error.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
12. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Max.
Unit
150
°C
–55
+125
°C
Tamb
–40
+105
°C
Junction temperature
Tj
Storage temperature
Tstg
Ambient temperature
Min.
Supply voltage VS2
VMaxVS2
–0.3
+7.2
V
Supply voltage VS1
VMaxVS1
–0.3
+4
V
Supply voltage VAUX
VMaxVAUX
–0.3
+7.2
V
Supply voltage VSINT
VMaxVSINT
–0.3
+5.5
V
ESD (Human Body Model ESD S 5.1)
every pin
HBM
–2
+2
kV
ESD (Machine Model JEDEC A115A)
every pin
MM
–200
+200
V
10
dBm
Maximum input level, input matched to 50 Ω
Pin_max
13. Thermal Resistance
Parameters
Junction ambient
Symbol
Value
Unit
RthJA
25
K/W
14. Electrical Characteristics: General
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
1
1.1
1.2
Test Conditions
Pin(1)
Symbol
Min.
ATA5811
V433_N868 = 0 V
4, 10
fRF
ATA5811
V433_N868 = AVCC
4, 10
ATA5812
V433_N868 = 0 V
4, 10
Typ.
Max.
Unit
Type*
867
870
MHz
A
fRF
433
435
MHz
A
fRF
313
316
MHz
A
nA
A
RX_TX_IDLE Mode
RF operating frequency
range
Supply current
OFF mode
VVS1 = VVS2 = 3 V,
VVSINT = 0 V
(1 battery) and
VVS2 = 6 V (2 battery)
OFF mode is not
available if
IS_OFF
<10
VVS2 = VVAUX = 5 V
VVSINT = 0 V (car)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
63
4689F–RKE–08/06
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
VVSOUT disabled,
XTO running
VVS1 = VVS2 = 3V
(1 battery)
IS_IDLE
220
µA
B
VVS2 = 6V (2 battery)
IS_IDLE
310
µA
B
VVS2 = VVAUX = 5V (car)
IS_IDLE
310
µA
B
System start-up time
From OFF mode to Idle
mode including reset
and XTO start-up
(see Figure 9-4 on page
43)
XTAL: Cm = 5 fF,
C0 = 1.8 pF, Rm =15Ω
TPWR_ON_IRQ_1
0.3
ms
C
1.5
RX start-up time
From Idle mode to
receiving mode
NBit-check = 3
Bit rate = 20 Kbit/s,
BR_Range_3
(see Figure 11-1 on
page 51 , Figure 11-2
on page 52 and Figure
11-3 on page 53)
TStartup_PLL +
TStartup_Sig_Proc
+ TBit-chek
1.39
ms
A
1.6
TX start-up time
From Idle mode to TX
mode (see Figure 11-11
on page 60)
TStartup
0.4
ms
A
1.3
1.4
2
2.1
2.2
2.3
Supply current
Idle mode
Receiver/RX Mode
Supply current RX mode
Supply current
RX polling mode
Input sensitivity FSK
fRF = 433.92 MHz
fRF = 433.92 MHz and
fRF = 315 MHz
17, 18
IS_RX
10.5
mA
A
fRF = 868 MHz
17, 18
IS_RX
10.3
mA
A
TSleep = 49.45 ms
XSLEEP = 8, Sleep = 5
Bit rate = 20 Kbit/s FSK,
VVSOUT disabled
17, 18
IP
444
µA
B
Bit rate 20 Kbit/s
(4)
PREF_FSK
–104.0
–106.0
–107.5
dBm
B
Bit rate 2.4 Kbit/s
(4)
PREF_FSK
–107.5
–109.5
–111.0
dBm
B
FSK deviation
fDEV = ±16 kHz
limits according to
Table 11-3 on page 58,
BER = 10-3
Tamb = 25°C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
64
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
2.4
Input sensitivity ASK
fRF = 433.92 MHz
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
Bit rate 10 Kbit/s
(4)
PREF_ASK
–110.5
–112.5
–114.0
dBm
B
Bit rate 2.4 Kbit/s
(4)
PREF_ASK
–114.5
–116.5
–118.0
dBm
B
(4)
∆PREF1
dB
B
kHz
B
Test Conditions
ASK 100%, level of
carrier limits according
to Table 11-3 on page
58, BER = 10-3
Tamb = 25°C
fRF = 433.92 MHz
to fRF = 315.00 MHz
2.5
2.6
Sensitivity change at
fRF = 315.0 MHz
fRF = 868.3 MHz
compared to
fRF = 433.92 MHz
Maximum frequency
offset in FSK mode
fRF = 433.92 MHz to
fRF = 868.00 MHz
P = PREF_ASK + ∆PREF1 +
∆PREF2
P = PREF_FSK + ∆PREF1 +
∆PREF2
Maximum frequency
difference of fRF
between receiver and
transmitter in FSK
mode (fRF is the center
frequency of the FSK
signal with
fDEV = ±16 kHz)
–1.0
+2.7
(4)
∆fOFFSET
–58
+58
(4)
∆PREF2
+4.5
–1.5
(4)
fDEV
±14
FSK fDEV = ±16 kHz
∆fOFFSET ≤ 58 kHz
2.7
2.8
Sensitivity change versus
temperature, supply
voltage and frequency
offset
Supported FSK
frequency deviation
ASK 100%
∆fOFFSET ≤ 58 kHz
P = PREF_ASK + ∆PREF1 +
∆PREF2
P = PREF_FSK + ∆PREF1 +
∆PREF2
With up to 2 dB
loss of sensitivity.
Note that the tolerable
frequency offset is for
fDEV = ±22 kHz, 6 kHz
lower than for
fDEV = ±16 kHz hence
∆fOFFSET ≤ ±52 kHz
±16
±22
B
kHz
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
65
4689F–RKE–08/06
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
2.9
System noise figure
2.10 Intermediate frequency
Pin(1)
Symbol
fRF = 315 MHz
(4)
NF
fRF = 433.92 MHz
(4)
NF
fRF = 868.3 MHz
(4)
Test Conditions
Min.
Typ.
Max.
Unit
Type*
6.0
dB
B
7.0
dB
B
NF
9.7
dB
B
fRF = 868.3 MHz
fIF
226
kHz
A
fRF = 433.92 MHz
fIF
223
kHz
A
fRF = 315 MHz
fIF
227
kHz
A
2.11 System bandwidth
This value is for
information only!
Note that for crystal and
system frequency offset
calculations, ∆fOFFSET
must be used.
(4)
SBW
185
kHz
A
System outband
2.12 2nd-order input intercept
point with respect to fIF
∆fmeas1 = 1,800 MHz
∆fmeas2 = 2,026 MHz
fIF = ∆fmeas2 – ∆fmeas1
(4)
IIP2
+50
dBm
C
∆fmeas1 = 1.8 MHz
∆fmeas2 = 3.6 MHz
fRF = 315 MHz
(4)
IIP3
–22
dBm
C
System outband
2.13 3rd-order input intercept
point
2.14
System outband input
1 dB compression point
2.15 LNA input impedance
fRF = 433.92 MHz
(4)
IIP3
–21
dBm
C
fRF = 868.3 MHz
(4)
IIP3
–17
dBm
C
∆fmeas1 = 10 MHz
fRF = 315 MHz
(4)
I1dBCP
–31
dBm
C
fRF = 433.92 MHz
(4)
I1dBCP
–30
dBm
C
fRF = 868.3 MHz
(4)
I1dBCP
–27
dBm
C
fRF = 315 MHz
4
Zin_LNA
(44 – j233)
Ω
C
fRF = 433.92 MHz
4
Zin_LNA
(32 – j169)
Ω
C
4
Zin_LNA
(21 – j78)
Ω
C
BER < 10-3, ASK: 100%
(4)
PIN_max
–10
+10
dBm
C
FSK: fDEV = ±16 kHz
(4)
PIN_max
–10
+10
dBm
C
f < 1 GHz
(4)
dBm
C
fRF = 868.3 MHz
2.16
Maximum peak RF input
level, ASK and FSK
2.17 LO spurious at LNA_IN
2.18 Image rejection
–57
f >1 GHz
(4)
dBm
C
fRF = 315 MHz
(4)
–100
–47
dBm
C
fRF = 433.92 MHz
(4)
–97
dBm
C
fRF = 868.3 MHz
(4)
–84
dBm
C
Within the complete
image band
(4)
30
dB
A
20
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
66
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Pin(1)
Symbol
(4)
SNRFSK0-2
FSK BR_Range_3
(4)
SNRFSK3
4
6
dB
B
ASK (PRF < PRFIN_High)
(4)
SNRASK
10
12
dB
B
Dynamic range
(4), 36
DRSSI
70
dB
A
Lower level of range
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
(4), 36
PRFIN_Low
–116
–115
–112.3
dBm
dBm
dBm
Upper level of range
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
(4), 36
PRFIN_High
–46
–45
–42.3
dBm
dBm
dBm
Gain
(4), 36
Output voltage range
(4), 36
Test Conditions
Peak level of useful
signal to peak level of
interferer for BER < 10-3
with any modulation
Useful signal to interferer
scheme of interferer
2.19
ratio
FSK BR_Ranges 0, 1, 2
2.20 RSSI output
Output resistance RSSI
2.21
pin
RX mode
TX mode
36
Min.
5.5
OVRSSI
400
RRSSI
8
32
Typ.
Max.
Unit
Type*
2
3
dB
B
8.0
10
40
A
A
10.5
mV/dB
A
1100
mV
A
12.5
50
kΩ
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
67
4689F–RKE–08/06
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Pin(1)
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Type*
dBC
C
dBC
C
dBC
C
nF
D
-3
Sensitivity (BER = 10 )
is reduced by 6 dB if a
continuous wave
blocking signal at ±∆f is
∆PBlock higher than the
useful signal level
(bit rate = 20 Kbit/s,
FSK, fDEV ±16kHz,
Manchester code)
2.22 Blocking
fRF = 315 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5 MHz
∆f ±10 MHz
fRF = 433.92 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5 MHz
∆f ±10 MHz
2.23 CDEM
3
3.1
(4)
(4)
fRF = 868.3 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5 MHz
∆f ±10 MHz
(4)
C6 in
Figure 2-1 on page 6,
Figure 3-1 on page 7
and Figure 4-1 on page
8
37
56
60
63
69
71
∆PBlock
55
59
62
68
70
∆PBlock
50
53
57
67
69
∆PBlock
–5%
15
+5%
Power Amplifier/TX Mode
Supply current TX mode
power amplifier OFF
fRF = 868.3 MHz
IS_TX_PAOFF
6.50
mA
A
fRF = 433.92 MHz and
fRF = 315 MHz
IS_TX_PAOFF
6.95
mA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
68
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
(10)
PREF1
–2.5
0
+2.5
dBm
B
PA on/0 dBm
fRF = 315 MHz
17, 18
IS_TX_PAON1
8.5
mA
B
fRF = 433.92 MHz
17, 18
IS_TX_PAON1
8.6
mA
B
fRF = 868.3 MHz
17, 18
IS_TX_PAON1
9.6
mA
B
(10)
PREF2
dBm
B
Test Conditions
VVS1 = VVS2 = 3V
Tamb = 25°C
VPWR_H = 0V
fRF = 315 MHz
RR_PWR = 56 kΩ
RLopt = 2.5 kΩ
3.2
Output power 1
fRF = 433.92 MHz
RR_PWR = 56 kΩ
RLopt = 2.3 kΩ
fRF = 868.3 MHz
RR_PWR = 30 kΩ
RLopt = 1.3 kΩ
RF_OUT matched to
RLopt //
j/(2 × π × fRF × 1.0 pF)
3.3
Supply current TX mode
power amplifier ON 1
VVS1 = VVS2 = 3V
Tamb = 25°C
VPWR_H = 0V
fRF = 315 MHz
RR_PWR = 30 kΩ
RLopt = 1.0 kΩ
3.4
Output power 2
fRF = 433.92 MHz
RR_PWR = 27 kΩ
RLopt = 1.1 kΩ
3.5
5.0
6.5
fRF = 868.3 MHz
RR_PWR = 16 kΩ
RLopt = 0.5 kΩ
RF_OUT matched to
RLopt//
j/(2 × π × fRF × 1.0 pF)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
69
4689F–RKE–08/06
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
3.5
Supply current TX mode
power amplifier ON 2
Test Conditions
Pin(1)
Symbol
PA on/5 dBm
fRF = 315 MHz
17, 18
IS_TX_PAON2
Min.
Typ.
Max.
Unit
Type*
10.3
mA
B
fRF = 433.92 MHz
17, 18
IS_TX_PAON2
10.5
mA
B
fRF = 868.3 MHz
17, 18
IS_TX_PAON2
11.2
mA
B
(10)
PREF3
dBm
B
PA on/10dBm
fRF = 315 MHz
17, 18
IS_TX_PAON3
15.7
mA
B
fRF = 433.92 MHz
17, 18
IS_TX_PAON3
15.8
mA
B
fRF = 868.3 MHz
17, 18
IS_TX_PAON3
17.3
mA
B
(10)
∆PREF
–0.8
–1.5
dB
B
(10)
∆PREF
–3.5
dB
B
(10)
∆PREF
–2.5
dB
C
VVS1 = VVS2 = 3V
Tamb = 25°C
VPWR_H = AVCC
fRF = 315 MHz
RR_PWR = 30 kΩ
RLopt = 0.38 kΩ
3.6
Output power 3
fRF = 433.92 MHz
RR_PWR = 27 kΩ
RLopt = 0.36 kΩ
8.5
10
11.5
fRF = 868.3 MHz
RR_PWR = 20 kΩ
RLopt = 0.22 kΩ
RF_OUT matched to
RLopt//
j/(2 × π × fRF × 1.0 pF)
3.7
3.8
Supply current TX mode
power amplifier ON 3
Tamb = –40°C to +105°C
Pout = PREFX + ∆PREFX
Output power variation for X = 1, 2 or 3
full temperature and
VVS1 = VVS2 = 3.0V
supply voltage range
VVS1 = VVS2 = 2.4V
VVS1 = VVS2 = 2.7V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
70
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
3.9
Impedance RF_OUT in
RX mode
Noise floor power
3.10
amplifier
3.11 ASK modulation rate
4
4.1
Pin(1)
Symbol
fRF = 315 MHz
10
ZRF_OUT_RX
fRF = 433.92 MHz
10
fRF = 868.3 MHz
Test Conditions
Min.
Typ.
Max.
Unit
Type*
(36 – j502)
Ω
C
ZRF_OUT_RX
(19 – j366)
Ω
C
10
ZRF_OUT_RX
(2.8 – j141)
Ω
C
at ±10 MHz/at 5 dBm
fRF = 868.3 MHz
(10)
LTX10M
–125
dBC/Hz
C
at fRF = 433.92 MHz
(10)
LTX10M
–126
dBC/Hz
C
fRF = 315 MHz
(10)
LTX10M
–127
dBC/Hz
C
kHz
C
This correspond to
10 Kbit/s Manchester
coding and 20 Kbit/s
NRZ coding
10
fData_ASK
XTO
Pulling XTO due to XTO,
CL1 and CL2 tolerances
Pulling at nominal
temperature and supply
voltage
fXTAL = resonant
frequency of the XTAL
C0 ≥ 1.5 pF
Rm ≤ 120Ω
24, 25
∆fXTO1
Cm ≤ 7.0 fF
Cm ≤ 14 fF
4.2
At start-up, after
Transconductance XTO at
start-up the amplitude
start
is regulated to VPPXTAL
4.3
XTO start-up time
4.4
A
–50
–100
fXTAL
24, 25
gm, XTO
19
C0 ≤ 2.2 pF
Cm = 4.0 fF to 7.0 fF
Rm ≤ 120Ω
24, 25
TPWR_ON_IRQ_1
300
Maximum C0 of XTAL
Required for stable
operation with internal
load capacitors
24, 25
C0max
4.5
Internal capacitors
CL1 and CL2
24, 25
CL1, CL2
14.8
4.6
1.5 pF ≤ C0 ≤ 2.2 pF
Cm = 4.0 fF to 7.0 fF
Pulling of radio frequency
Rm ≤ 120Ω
fRF due to XTO, CL1 and
PLL adjusted with
CL2 versus temperature
FREQ at nominal
and supply changes
temperature and supply
voltage
4, 10
∆fXTO2
–2
18 pF
+50
+100
ppm
ms
B
800
µs
A
3.8
pF
D
21.2
pF
B
+2
ppm
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
71
4689F–RKE–08/06
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Pin(1)
Symbol
V(XTAL1, XTAL2)
peak-to-peak value
24, 25
VPPXTAL
V(XTAL1)
peak-to-peak value
24, 25
VPPXTAL
24, 25
ZXTAL12_START
C0 ≤ 2.2 pF
Cm = 4.0 fF to 7.0 fF
Rm ≤ 120Ω
24, 25
Rm_max
FREQ = 3,928
fRF = 868.3 MHz
fRF = 433.92 MHz
fRF = 315 MHz
24, 25
fXTAL
FREQ = 3,928
30
fCLK
fRF = 868.3 MHz
CLK division ratio = 3
CLK has nominal 50%
duty cycle
30
fRF = 433.92 MHz
CLK division ratio = 3
CLK has nominal 50%
duty cycle
Unit
Type*
700
mVpp
C
350
mVpp
C
–2,000
Ω
B
Ω
B
MHz
MHz
D
f XTO
f CLK = ---------3
MHz
D
fCLK
4.471
MHz
D
30
fCLK
4.418
MHz
D
fRF = 315 MHz
CLK division ratio = 3
CLK has nominal 50%
duty cycle
30
fCLK
4.244
MHz
D
VDC(XTAL1, XTAL2)
XTO running
(Idle mode, RX mode
and TX mode)
24, 25
VDCXTO
Test Conditions
Min.
Typ.
Max.
Cm = 5 fF, C0 = 1.8 pF
Rm =15Ω
4.7
Amplitude XTAL after
start-up
4.8
Maximum series
C0 ≤ 2.2 pF, start-up
resistance Rm of XTAL at may take longer under
these conditions
start-up
4.9
Maximum series
resistance Rm of XTAL
after start-up
Nominal XTAL load
4.10
resonant frequency
4.11 External CLK frequency
4.12 DC voltage after start-up
–1,500
15
120
13.41191
13.25311
12.73193
–150
–30
mV
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
72
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
5
5.1
5.2
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
dBC
A
dBC
A
dBC
A
dBC
A
dBC/Hz
A
Synthesizer
Spurious TX mode
Spurious RX mode
At ±fCLK, CLK enabled
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
SPTX
at ±fXTO
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
SPTX
At ±fCLK, CLK enabled
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
SPRX
at ±fXTO
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
SPRX
LTX20k
–72
–68
–70
–70
–66
–60
< –75
< –75
< –75
–75
–75
–68
5.3
In loop phase noise
TX mode
Measured at 20 kHz
distance to carrier
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
5.4
Phase noise at 1M
RX mode
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
LRX1M
–121
–120
–113
dBC/Hz
A
5.5
Phase noise at 1M
TX mode
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
LTX1M
–113
–111
–107
dBC/Hz
A
5.6
Phase noise at 10M
RX mode
Noise floor PLL
LRX10M
–135
dBC/Hz
B
5.7
Loop bandwidth PLL
TX mode
Frequency where the
absolute value loop
gain is equal to 1
fLoop_PLL
70
kHz
B
5.8
Frequency deviation
TX mode
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fDEV_TX
±15.54
±16.17
±16.37
kHz
D
5.9
Frequency resolution
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
∆fStep_PLL
777.1
808.9
818.6
Hz
D
4, 10
–85
–80
–75
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
73
4689F–RKE–08/06
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
5.10 FSK modulation rate
This correspond to
20 Kbit/s Manchester
coding and 40 Kbit/s
NRZ coding
6
6.1
6.2
7
7.1
7.2
Pin(1)
Symbol
Min.
Typ.
fData_FSK
Max.
Unit
Type*
20
kHz
B
RX/TX Switch
Impedance RX mode
Impedance TX mode
RX mode, pin 38 with
short connection to
GND, fRF = 0Hz (DC)
39
ZSwitch_RX
23000
Ω
A
fRF = 315 MHz
39
ZSwitch_RX
(11.3 – j214)
Ω
C
fRF = 433.92 MHz
39
ZSwitch_RX
(10.3 – j153)
Ω
C
fRF = 868.3 MHz
39
ZSwitch_RX
(8.9 – j73)
Ω
C
TX mode, pin 38 with
short connection to
GND, fRF = 0Hz (DC)
39
ZSwitch_TX
5
Ω
A
fRF = 315 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
39
ZSwitch_TX
(4.8 + j3.2)
(4.5 + j4.3)
(5 + j9)
Ω
C
C
C
5.25
V
A
Microcontroller Interface
Voltage range for
microcontroller interface
IVSINT < 10 µA if CLK is
disabled and all
interface pins are in
stable condition and
unloaded
CLK output rise and fall
time
fCLK < 4.5 MHz
CL = 10 pF
CL = Load capacitance
on pin CLK
2.4 V ≤ VVSINT ≤ 5.25V
20% to 80% VVSINT
27, 28,
29, 30,
31, 32,
33, 34,
35
30
2.4
trise
20
30
ns
tfall
20
30
ns
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
74
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
CLK enabled
VVSOUT enabled
( C CLK + C L ) × V VSINT × f XTO
I VSINT = --------------------------------------------------------------------------3
CLK disabled
VVSOUT enabled
7.4
Current consumption of
the microcontroller
interface
VVSOUT disabled
27
IVSINT
< 10 µA
CL = Load capacitance
on pin CLK
(All interface pins,
except pin CLK, are in
stable condition and
unloaded)
7.5
8
Internal equivalent
capacitance
Used for current
calculation
< 10 µA
30, 27
CCLK
8
pF
B
Power Supply General Definitions and AUX Mode
IVSINT
VSINT
IEXT = IVSOUT – IVSINT
VSOUT
8.1
IVSOUT IEXT
Current consumption of
an external device
connected to pin VSOUT
IEXT
IEXT = IVSOUT
IVSINT
VSINT
VSOUT
IEXT = IVSOUT
IAUX_VAUX
8.2
VAUX
AUX mode
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
75
4689F–RKE–08/06
14. Electrical Characteristics: General (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = VVAUX = 4.75V to 5.25V (car application). Typical values are given at VVS1 = VVS2 = 3V and
Tamb = 25°C, fRF = 433.92 MHz (1-battery application) unless otherwise specified. Details about current consumption, timing and digital
pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
8.3
Power supply output
voltage
AUX mode
VVAUX ≥ 4 V
IVSOUT ≤ 13.5 mA
(3.25V regulator mode,
V_REG2, see
Figure 7-1 on page 27)
8.4
Current in AUX mode on
pin VAUX
IVSOUT = 0
VVAUX = 6V
VVAUX = 4V to 7V
8.5
8.6
Supply current
AUX mode
CLK enabled
VVSOUT enabled
CLK disabled
VVSOUT enabled
Supported voltage range
VAUX
Pin(1)
Symbol
Min.
22
VVSOUT
2.7
19
IAUX_VAUX
19, 22,
27
IS_AUX
19
VVAUX
Typ.
380
Max.
Unit
Type*
3.5
V
A
500
500
µA
µA
B
IS_AUX = IAUX_VAUX + IVSINT + IEXT
IS_AUX = IAUX_VAUX + IEXT
4
6
7
V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50 Ω according to Figure 5-1 on page 10 with
component values according to Table 5-2 on page 10 and RF_OUT matched to 50 Ω according to Figure 5-10 on page 19
with component values according to Table 5-7 on page 20.
15. Electrical Characteristic: 1-Battery Application
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V typical values at VVS1 = VVS2 = 3V and
Tamb = 25°C. Application according to Figure 2-1 on page 6. fRF = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified
No.
9
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
IIDLE_VS1,2 or
IRX_VS1,2 or
IStartup_PLL_VS1,2 or
1-Battery Application
Max.
Unit
Type*
VS1
VS2
ITX_VS1,2
9.1
Supported voltage
range (every mode
except high power TX
mode)
1-battery application
PWR_H = GND
9.2
Supported voltage
range (high power TX
mode)
1-battery application
PWR_H = AVCC
17, 18
VVS1, VVS2
2.4
3.6
V
A
17, 18
VVS1, VVS2
2.7
3.6
V
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
76
1. The voltage of VAUX may rise up to 2V. The current IVAUX may not exceed 100 µA.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
15. Electrical Characteristic: 1-Battery Application (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V typical values at VVS1 = VVS2 = 3V and
Tamb = 25°C. Application according to Figure 2-1 on page 6. fRF = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified
No.
9.3
Parameters
Power supply output
voltage
Test Conditions
Pin
Symbol
Min.
1-battery application
VVS1 = VVS2 ≥ 2.6V
VAUX open (1)
IVSOUT ≤ 13.5 mA
(no voltage regulator
to stabilize VVSOUT)
22
VVSOUT
27
Typ.
Max.
Unit
Type*
2.4
VVS1
V
B
VVSINT
2.4
5.25
V
A
22
∆VThres
60
80
100
mV
B
VVS1 = VVS2 ≥ 2.425V
VAUX open (1)
IVSOUT ≤ 1.5 mA
(no voltage regulator
to stabilize VVSOUT)
9.4
Supply voltage for
microcontroller
interface
9.5
Threshold hysteresis
9.6
Reset threshold
voltage at pin VSOUT
(N_RESET)
22
VThres_1
2.18
2.3
2.42
V
A
9.7
Reset threshold
voltage at pin VSOUT
(Low_Batt)
22
VThres_2
2.26
2.38
2.5
V
A
9.8
Supply current
OFF mode
17,
18,
22, 27
IS_OFF
2
350
nA
A
312
430
µA
A
CLK disabled
VVSOUT enabled
260
370
µA
B
VVSOUT disabled
225
320
µA
B
VThres_2 – VThres_1
VVS1 = VVS2 ≤ 3.6V
VVSINT = 0V
VVS1 = VVS2 ≤ 3V
IVSOUT = 0
9.9
Current in Idle mode
on pin VS1 and VS2
CLK enabled
VVSOUT enabled
17, 18
IIDLE_VS1, 2
17,
18,
22, 27
IS_IDLE
VVS1 = VVS2 ≤ 3V
IVSOUT = 0
17, 18
IRX_VS1, 2
Supply current
RX mode
CLK enabled
VVSOUT enabled
17,
18,
22, 27
IS_RX
Current during
TStartup_PLL on pin VS1
and VS2
VVS1 = VVS2 ≤ 3V
IVSOUT = 0
17, 18
IStartup_PLL_VS1, 2
9.10
Supply current
Idle mode
9.11
Current in RX mode
on pin VS1and VS2
9.12
9.13
IS_IDLE = IIDLE_VS1, 2 + IVSINT + IEXT
10.5
14
mA
A
IS_RX = IRX_VS1, 2 + IVSINT + IEXT
8.8
11.5
mA
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. The voltage of VAUX may rise up to 2V. The current IVAUX may not exceed 100 µA.
77
4689F–RKE–08/06
15. Electrical Characteristic: 1-Battery Application (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS1 = VVS2 = 2.4V to 3.6V typical values at VVS1 = VVS2 = 3V and
Tamb = 25°C. Application according to Figure 2-1 on page 6. fRF = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified
No.
Parameters
Test Conditions
Pin
Symbol
Min.
9.14
Current in
RX polling mode on
pin VS1 and VS2
I IDLE_VS1,2 × T SLEEP + I Startup_PLL_VS1,2 × T Startup_PLL + I RX_VS1,2 × ( T Startup_Sig_Proc + T Bitcheck )
I P = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------T Sleep + T Startup_PLL + T Startup_Sig_Proc + T Bitcheck
CLK enabled
VVSOUT enabled
9.15
Supply current
RX polling mode
CLK disabled
VVSOUT enabled
17,
18,
22, 27
Typ.
9.16
Current in TX mode
on pin VS1 and VS2
9.17
Supply current
TX mode
CLK enabled
VVSOUT enabled
CLK disabled
VVSOUT enabled
Unit
Type*
IS_Poll = IP + IVSINT + IEXT
IS_Poll
IS_Poll = IP + IEXT
IS_Poll = IP
VVSOUT disabled
VVS1 = VVS2 ≤ 3V
IVSOUT = 0
Pout = 5 dBm/10 dBm
315 MHz/5 dBm
315 MHz/10 dBm
433.92 MHz/5 dBm
433.92 MHz/10 dBm
868.3 MHz/5 dBm
868.3 MHz/10 dBm
Max.
17, 18
ITX_VS1_VS2
17,
18,
22, 27
IS_TX
10.3
15.7
10.5
15.8
11.2
17.3
13.4
20.5
13.5
20.5
14.5
22.5
mA
B
IS_TX = ITX_VS1, 2 + IVSINT + IEXT
IS_TX = ITX_VS1, 2 + IEXT
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
78
1. The voltage of VAUX may rise up to 2V. The current IVAUX may not exceed 100 µA.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
16. Electrical Characteristics: 2-Battery Application
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS2 = 4.4V to 6.6V typical values at VVS2 = 6V and Tamb = 25°C.
Application according to Figure 4-1 on page 8. fRF = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified
No.
Parameters
10
2-Battery Application
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS2
IIDLE_VS2 or
IRX_VS2 or
IStartup_PLL_VS2 or
ITX_VS2
Supported voltage
range
2-battery application
17
VVS2
4.4
6.6
V
A
10.2
Power supply output
voltage
2 battery application
VVS2 ≥ 4.4V
VAUX open(1)
IVSOUT ≤ 13.5 mA
(3.3V regulator mode,
V_REG1,
see Figure 7-1 on
page 27)
22
VVSOUT
3.0
3.5
V
A
10.3
Supply voltage for
microcontroller
interface
27
VVSINT
2.4
5.25
V
A
10.4
Threshold hysteresis
22
∆VThres
60
80
100
mV
B
10.5
Reset threshold
voltage at pin VSOUT
(N_RESET)
22
VThres_1
2.18
2.3
2.42
V
A
10.6
Reset threshold
voltage at pin VSOUT
(Low_Batt)
22
VThres_2
2.26
2.38
2.5
V
A
10.7
Supply current
OFF mode
17,
22, 27
IS_OFF
10
350
nA
A
410
560
µA
A
CLK disabled
VVSOUT enabled
348
490
µA
B
VVSOUT disabled
309
430
µA
B
10.1
VThres_2 – VThres_1
VVS2 ≤ 6.6V
VVSINT = 0V
VVS2 ≤ 6V
IVSOUT = 0
10.8
Current in Idle mode
on pin VS2
10.9
Supply current Idle
mode
10.10
Current in RX mode
on pin VS2
CLK enabled
VVSOUT enabled
IVSOUT = 0
17
IIDLE_VS2
17,
22, 27
IS_IDLE
17
IRX_VS2
IS_IDLE = IIDLE_VS2 + IVSINT + IEXT
10.8
14.5
mA
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. The voltage of VAUX may rise up to 2 V. The current IVAUX may not exceed 100 µA.
79
4689F–RKE–08/06
16. Electrical Characteristics: 2-Battery Application (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS2 = 4.4V to 6.6V typical values at VVS2 = 6V and Tamb = 25°C.
Application according to Figure 4-1 on page 8. fRF = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified
No.
Parameters
Test Conditions
Pin
Symbol
10.11
Supply current
RX mode
CLK enabled
VVSOUT enabled
17,
22, 27
IS_RX
10.12
Current during
TStartup_PLL on pin VS2
IVSOUT = 0
17
IStartup_PLL_VS2
10.13
Current in
RX polling mode on
on pin VS2
Min.
10.14
Max.
Unit
Type*
IS_RX = IRX_VS2 + IVSINT + IEXT
9.1
12
mA
C
I IDLE_VS2 × T SLEEP + I Startup_PLL_VS2 × T Startup_PLL + I RX_VS2 × ( T Startup_Sig_Proc + T Bitcheck )
I P = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------T Sleep + T Startup_PLL + T Startup_Sig_Proc + T Bitcheck
CLK enabled
VVSOUT enabled
Supply current
RX polling mode
Typ.
CLK disabled
VVSOUT enabled
IS_Poll = IP + IVSINT + IEXT
17,
22, 27
IS_Poll
IS_Poll = IP + IEXT
IS_Poll = IP
VVSOUT disabled
10.15
Current in TX mode
on pin VS2
IVSOUT = 0
Pout = 5 dBm/10 dBm
315 MHz/5 dBm
315 MHz/10 dBm
433.92 MHz/5 dBm
433.92 MHz/10 dBm
868.3 MHz/5 dBm
868.3 MHz/10 dBm
17, 19
ITX_VS2
10.16
Supply current
TX mode
CLK enabled
VVSOUT enabled
CLK disabled
VVSOUT enabled
17,
22, 27
IS_TX
10.7
16.2
10.9
16.3
11.6
17.8
13.9
21.0
14.0
21.0
15.0
23.0
mA
B
IS_TX = ITX_VS2 + IVSINT + IEXT
IS_TX = ITX_VS2 + IEXT
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
80
1. The voltage of VAUX may rise up to 2 V. The current IVAUX may not exceed 100 µA.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
17. Electrical Characteristics: Car Application
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS2 = 4.75V to 5.25V. Typical values at VVS2 = 5V and Tamb = 25°C.
Application according to Figure 3-1 on page 7. fRF = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VAUX
11
IIDLE_VS2,VAUX
Car Application
VS2
or IRX_VS2,VAUX
or IStartup_PLL_VS2,VAUX
or ITX_VS2,VAUX
Supported voltage
range
Car application
11.2
Power supply output
voltage
Car application
VVS2 = VVAUX
IVSOUT ≤ 13.5 mA
(3.25V regulator
mode, V_REG2, see
Figure 7-1 on page
27)
11.3
Supply voltage for
microcontrollerinterface
11.4
Threshold hysteresis
11.5
11.6
11.1
17,
19, 27
VVS2, VAUX
4.75
5.25
V
A
22
VVSOUT
3.0
3.5
V
A
27
VVSINT
2.4
5.25
V
A
22
∆VThres
60
80
100
mV
B
Reset threshold
voltage at pin VSOUT
(N_RESET)
22
VThres_1
2.18
2.3
2.42
V
A
Reset threshold
voltage at pin VSOUT
(Low_Batt)
22
VThres_2
2.26
2.38
2.5
V
A
444
580
µA
B
380
500
µA
B
310
400
µA
B
VThres_2 – VThres_1
IVSOUT = 0
CLK enabled
VVSOUT enabled
11.7
Current in Idle mode
on pin VS2 and VAUX
CLK disabled
VVSOUT enabled
17, 19
IIDLE_VS2_VAUX
VVSOUT disabled
11.8
Supply current in Idle
mode
11.9
Current in RX mode
on pin VS2 and VAUX
11.10
Supply current in RX
mode
17,
19,
22, 27
IS_IDLE
IVSOUT = 0
17, 19
IRX_VS2_VAUX
CLK enabled VVSOUT
enabled
17,
19,
22, 27
IS_RX
IS_IDLE = IIDLE_VS2_VAUX + IVSINT + IEXT
10.8
14.5
mA
B
IS_RX = IRX_VS2_VAUX + IVSINT + IEXT
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
81
4689F–RKE–08/06
17. Electrical Characteristics: Car Application (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C, VVS2 = 4.75V to 5.25V. Typical values at VVS2 = 5V and Tamb = 25°C.
Application according to Figure 3-1 on page 7. fRF = 315.0 MHz/433.92 MHz/868.3 MHz unless otherwise specified
No.
11.11
Parameters
Test Conditions
Current during
TStartup_PLL on pin VS2
and VAUX
IVSOUT = 0
Pin
Symbol
17, 19
IStartup_PLL_VS2_
Min.
Typ.
Max.
Unit
Type*
9.1
12
mA
C
VAUX
Current in RX_Polling_Mode on pin VS2 and VAUX
11.12
I IDLE_VS2,VAUX × T SLEEP + I Startup_PLL_VS2,VAUX × T Startup_PLL + I RX_VS2,VAUX × ( T Startup_Sig_Proc + T Bitcheck )
I P = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------T Sleep + T Startup_PLL + T Startup_Sig_Proc + T Bitcheck
CLK enabled
VVSOUT enabled
11.13
Supply current in RX
polling mode
CLK disabled
VVSOUT enabled
17,
19,
22, 27
IS_Poll = IP + IVSINT + IEXT
IS_Poll
IS_Poll = IP + IEXT
IS_Poll = IP
VVSOUT disabled
11.14
Current in TX mode
on pin VS2 and VAUX
11.15
Supply current in
TX mode
IVSOUT = 0
Pout = 5dBm/10dBm
315 MHz/5dBm
315 MHz/10dBm
433.92 MHz/5dBm
433.92 MHz/10dBm
868.3 MHz/10dBm
CLK enabled
VVSOUT enabled
CLK disabled
VVSOUT enabled
17, 19
ITX_VS2_VAUX
17,
19,
22, 27
IS_TX
10.7
16.2
10.9
16.3
11.6
17.8
13.9
21.0
14.0
21.0
15.0
23.0
mA
B
IS_TX = ITX_VS2_VAUX + IVSINT + IEXT
IS_TX = ITX_VS2_VAUX + IEXT
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
82
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
18. Digital Timing Characteristics
All parameters refer to GND and are valid for Tamb = –40°C to +105°C. VVS1 = VS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = 4.75V to 5.25V (car application), typical values at VVS1 = VVS2 = 3V and Tamb = 25°C unless
otherwise specified.
No.
Parameters
12
Basic Clock Cycle of the Digital Circuitry
12.1
Test Conditions
Basic clock cycle
Pin
Symbol
Min.
TDCLK
Typ.
Max.
Unit
Type*
16/fXTO
16/fXTO
µs
A
8
4
2
1
× TDCLK
8
4
2
1
× TDCLK
µs
A
16
8
4
2
× TDCLK
16
8
4
2
× TDCLK
Sleep ×
XSleep ×
1024 ×
TDCLK
Sleep ×
XSleep ×
1024 ×
TDCLK
ms
A
798.5 ×
TDCLK
µs
A
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
12.2
Extended basic clock
cycle
XLIM = 1
TXDCLK
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
13
RX Mode/RX Polling Mode
Sleep and XSleep are
defined in control
register 4
13.1
Sleep time
13.2
Start-up PLL RX mode from Idle mode
13.3
13.4
Start-up signal
processing
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
Time for Bit-check
Average time during
polling. No RF signal
applied.
fSignal = 1/(2 × tee)
Signal data rate
Manchester
(Lim_min and Lim_max
up to ±50% of tee,
see
Figure 11-4 on page
53)
Bit-check time for a
valid input signal fSig
NBit-check = 0
NBit-check = 3
NBit-check = 6
NBit-check = 9
TSleep
798.5 ×
TDCLK
TStartup_PLL
TStartup_Sig_Proc
882
498
306
210
× TDCLK
882
498
306
210
× TDCLK
1/fSignal
TBit_check
3/fSig
6/fSig
9/fSig
A
ms
C
3.5/fSig
6.5/fSig
9.5/fSig
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
83
4689F–RKE–08/06
18. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C. VVS1 = VS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = 4.75V to 5.25V (car application), typical values at VVS1 = VVS2 = 3V and Tamb = 25°C unless
otherwise specified.
No.
13.5
Parameters
Test Conditions
Bit-rate range
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Pin
Symbol
BR_Range
Min.
Typ.
1.0
2.0
4.0
8.0
Max.
Unit
Type*
Kbit/s
A
µs
A
500
250
125
62.5
µs
B
331.5
× TDCLK
µs
A
2.5
5.0
10.0
20.0
XLIM = 0
13.6
Minimum time period
between edges at pin
SDO_TMDO in RX
transparent mode
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
31
TDATA_min
10 ×
TXDCLK
TDATA
200
100
50
25
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
13.7
14
14.1
15
15.1
Edge-to-edge time
period of the data signal
for full sensitivity in RX
mode
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
TX Mode
Start-up time
From Idle mode
331.5
× TDCLK
TStartup
Configuration of the Transceiver with 4-wire Serial Interface
CS set-up time to rising
edge of SCK
33, 35
TCS_setup
1.5
× TDCLK
µs
A
15.2
SCK cycle time
33
TCycle
2
µs
A
15.3
SDI_TMDI set-up time
to rising edge of SCK
32, 33
TSetup
250
ns
C
15.4
SDI_TMDI hold time
from rising edge of SCK
32, 33
THold
250
ns
C
15.5
SDO_TMDO enable
time from rising edge of
CS
31, 35
TOut_enable
250
ns
C
15.6
SDO_TMDO output
delay from falling edge
of SCK
31, 35
TOut_delay
250
ns
C
15.7
SDO_TMDO disable
time from falling edge of
CS
31, 33
TOut_disable
250
ns
C
15.8
CS disable time period
35
TCS_disable
1.5
× TDCLK
µs
A
15.9
Time period SCK low to
CS high
33, 35
TSCK_setup1
250
ns
C
CL = 10 pF
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
84
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
18. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C. VVS1 = VS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = 4.75V to 5.25V (car application), typical values at VVS1 = VVS2 = 3V and Tamb = 25°C unless
otherwise specified.
No.
Pin
Symbol
Min.
15.10
Time period SCK low to
CS low
33, 35
TSCK_setup2
15.11
Time period CS low to
SCK high
33, 35
TSCK_hold
16
Parameters
Test Conditions
Typ.
Max.
Unit
Type*
250
ns
C
250
ns
C
ms
B
Start Time Push Button Tn and PWR_ON
Timing of wake-up via PWR_ON or Tn
From OFF mode to Idle
mode, applications
according to Figure 2-1
on page 6, Figure 3-1
on page 7 and Figure
4-1 on page 8
XTAL:
Cm = 4..7 fF (typ. 5 fF)
C0 < 2.2 pF (typ. 1.8 pF)
Rm ≤ 120Ω (typ. 15Ω)
16.1
PWR_ON high to
1-battery application
positive edge on pin
C1 = C2 = 68 nF
IRQ (see Figure 9-4 on
C3 = C4 = 68 nF
page 43)
C5 = 10 nF
0.3
0.8
29, 40 TPWR_ON_IRQ_1
2-battery application
C1 = C4 = 68 nF
C2 = C3 = 2.2 µF
C5 = 10 nF
0.45
1.3
Car application
C1 = C3 = C4 = 68 nF
C2 = C12 = 2.2 µF
C5 = 10nF
0.45
1.3
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
85
4689F–RKE–08/06
18. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +105°C. VVS1 = VS2 = 2.4V to 3.6V (1-battery application), VVS2 = 4.4V to
6.6V (2-battery application) and VVS2 = 4.75V to 5.25V (car application), typical values at VVS1 = VVS2 = 3V and Tamb = 25°C unless
otherwise specified.
No.
Parameters
16.2
PWR_ON high to
positive edge on pin
Every mode except
IRQ (see Figure 9-4 on OFF mode
page 43)
Test Conditions
Pin
Symbol
Min.
Typ.
29, 40 TPWR_ON_IRQ_2
Max.
Unit
Type*
2×
TDCLK
µs
A
ms
B
µs
A
From OFF mode to Idle
mode, applications
according to Figure 2-1
on page 6, Figure 3-1
on page 7 and Figure
4-1 on page 8
XTAL:
Cm = 4..7 fF (typ 5 fF)
C0 < 2.2 pF (typ 1.8 pF)
Rm ≤ 120Ω (typ 15Ω)
16.3
16.4
Tn low to positive edge 1-battery application
on pin IRQ (see Figure C1 = C2 = 68 nF
C3 = C4 = 68 nF
9-2 on page 41)
C5 = 10 nF
Push button debounce
time
29, 41,
42, 43,
44, 45
0.3
0.8
TTn_IRQ
2-battery application
C1 = C4 = 68 nF
C2 = C3 = 2.2 µF
C5 = 10 nF
0.45
1.3
Car application
C1 = C3 = C4 = 68 nF
C2 = C12 = 2.2 µF
C5 = 10 nF
0.45
1.3
Every mode except
OFF mode
29, 41,
42, 43,
44, 45
TDebounce
8195
× TDCLK
8195
× TDCLK
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
86
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
19. Digital Port Characteristics
All parameter refer to GND and valid for Tamb = –40°C to +105°C, VVS1 = VS2 = 2.4V to 3.6V (1 Battery Application) and VVS2 = 4.4V to
6.6V (2 Battery Application) and VVS2 = 4.75V to 5.25V (Car Application) typical values at VVS1 = VVS2 = 3V and Tamb = 25°C unless
otherwise specified
No.
Parameters
17
Digital Ports
17.1
17.2
17.3
Test Conditions
Pin
Symbol
CS input
= 2.4V to 5.25V
V
-Low level input voltage VSINT
35
VIl
-High level input voltage VVSINT = 2.4V to 5.25V
35
VIh
SCK input
= 2.4V to 5.25V
V
-Low level input voltage VSINT
33
VIl
-High level input voltage VVSINT = 2.4V to 5.25V
33
VIh
SDI_TMDI input
= 2.4V to 5.25V
V
-Low level input voltage VSINT
32
VIl
-High level input voltage VVSINT = 2.4V to 5.25V
32
VIh
Min.
0.8
× VVSINT
0.8
× VVSINT
0.8
× VVSINT
Typ.
Max.
Unit
Type*
0.2
× VVSINT
V
A
VVSINT
V
A
0.2
× VVSINT
V
A
VVSINT
V
A
0.2
× VVSINT
V
A
VVSINT
V
A
17.4
TEST1 input
TEST1 input must
always be directly
connected to GND
20
D
17.5
TEST2 input
TEST2 input must
always be direct
connected to GND
23
D
17.6
Internal pull-down with
PWR_ON input
series connection of
-Low level input voltage 40 kΩ ±20% resistor
and diode
40
VIl
Internal pull-down with
series connection of
40 kΩ ±20% resistor
and diode
40
VIh
Tn input
Internal pull-up resistor
-Low level input voltage of 50 kΩ ±20%
41, 42,
43, 44,
45
VIl
-High level input
voltage(1)
41, 42,
43, 44,
45
VIh
6
VIl
-High level input
voltage(1)
17.7
433_N868 input
-Low level input voltage
17.8
Internal pull-up resistor
of 50 kΩ ±20%
-Input current low
6
IIl
-High level input voltage
6
VIh
-Input current high
6
IIh
0.4
V
A
V
A
V
A
V
A
0.25
V
A
0.8
× VVS2
0.2
× VVS2
× VVS2
–0.5V
1.7
–5
µA
A
AVCC
V
A
1
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. If a logic high level is applied to this pin a minimum serial impedance of 100 Ω must be ensured for proper operation over full
temperature range.
87
4689F–RKE–08/06
19. Digital Port Characteristics (Continued)
All parameter refer to GND and valid for Tamb = –40°C to +105°C, VVS1 = VS2 = 2.4V to 3.6V (1 Battery Application) and VVS2 = 4.4V to
6.6V (2 Battery Application) and VVS2 = 4.75V to 5.25V (Car Application) typical values at VVS1 = VVS2 = 3V and Tamb = 25°C unless
otherwise specified
No.
17.9
17.10
Parameters
Pin
Symbol
PWR_H input
-Low level input voltage
9
-Input current low
-High level input voltage
17.13
17.15
Max.
Unit
Type*
VIl
0.25
V
A
9
IIl
–5
µA
A
9
VIh
AVCC
V
A
1
µA
A
0.4
V
B
V
B
V
B
V
B
V
B
V
B
V
B
1.7
IIh
SDO_TMDO output
VVSINT = 2.4V to 5.25V
-Saturation voltage low ISDO_TMDO = 250 µA
31
Vol
VVSINT = 2.4V to 5.25V
ISDO_TMDO = –250 µA
31
Voh
IRQ output
VVSINT = 2.4V to 5.25V
-Saturation voltage low IIRQ = 250 µA
29
Vol
VVSINT = 2.4V to 5.25V
IIRQ = –250 µA
29
Voh
VVSINT = 2.4V to 5.25V
ICLK = 100 µA
CLK output
internal series resistor
-Saturation voltage low
of 1 kΩ for spurious
reduction in PLL
30
Vol
VVSINT = 2.4V to 5.25V
ICLK = –100 µA
Saturation voltage high internal series resistor
of 1 kΩ for spurious
reduction in PLL
30
Voh
N_RESET output
VVSINT = 2.4V to 5.25V
-Saturation voltage low IN_RESET = 250 µA
28
Vol
VVSINT = 2.4V to 5.25V
IN_RESET = –250 µA
28
Voh
VVSINT –
0.4
VVSINT –
0.15
V
B
RX_ACTIVE output
VVSINT = 2.4V to 5.25V
-Saturation voltage high IRX_ACTIVE = –1.5 mA
46
Voh
VAVCC
–0.5V
VAVCC
–0.15V
V
B
-Saturation voltage low
VVSINT = 2.4V to 5.25V
IRX_ACTIVE = 25 µA
46
Vol
0.25
0.4
V
B
DEM_OUT output
Saturation voltage low
Open drain output
IDEM_OUT = 250 µA
34
Vol
0.15
0.4
V
B
-Saturation voltage high
17.14
Typ.
9
Saturation voltage high
17.12
Min.
-Input current high
Saturation voltage high
17.11
Test Conditions
0.15
VVSINT –
0.4
VVSINT –
0.15
0.15
VVSINT –
0.4
VVSINT –
0.15
0.15
VVSINT –
0.4
0.4
0.4
VVSINT –
0.15
0.15
0.4
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
88
1. If a logic high level is applied to this pin a minimum serial impedance of 100 Ω must be ensured for proper operation over full
temperature range.
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
20. Ordering Information
Extended Type Number
Package
Remarks
ATA5811-PLQW
QFN48
7 mm × 7 mm, Pb-free
ATA5812-PLQW
QFN48
7 mm × 7 mm, Pb-free
21. Package Information
Package: QFN 48 - 7 x 7
Exposed pad 5.1 x 5.1
Dimensions in mm
Not indicated tolerances ± 0.05
7
1 max.
5.5
+0
0.05-0.05
5.1
37
48
48
36
1
1
technical drawings
according to DIN
specifications
25
12
24
0.4±0.1
0.23
12
13
0.5 nom.
Drawing-No.: 6.543-5089.02-4
Issue: 1; 14.01.03
89
4689F–RKE–08/06
22. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4689F-RKE-08/06
• Quality of drawings improved
4689E-RKE-06/06
4689D-RKE-09/05
90
•
•
•
•
Put datasheet in a new template
kBaud replaced through Kbit/s
Baud replaced through bit
Table 11-6 “Interrupt Handling” on page 62 changed
• Pb-free Logo on page 1 added
• Table 1-1 “Pin Description” on pages 4 to 5 changed
• Ordering Information on page 89 changed
ATA5811/ATA5812
4689F–RKE–08/06
ATA5811/ATA5812
23. Table of Contents
Features ..................................................................................................... 1
Applications .............................................................................................. 2
Benefits...................................................................................................... 2
1
General Description ................................................................................. 2
2
Typical Key Fob or Sensor Application with 1 Battery ......................... 6
3
Typical Car or Sensor Base-station Application ................................... 7
4
Typical Key Fob Application, 2 Batteries .............................................. 8
5
RF Transceiver ......................................................................................... 9
6
XTO .......................................................................................................... 23
7
Power Supply ......................................................................................... 27
8
Microcontroller Interface ....................................................................... 33
9
Digital Control Logic .............................................................................. 33
10 Transceiver Configuration .................................................................... 46
11 Operation Modes .................................................................................... 49
12 Absolute Maximum Ratings .................................................................. 63
13 Thermal Resistance ............................................................................... 63
14 Electrical Characteristics: General ...................................................... 63
15 Electrical Characteristic: 1-Battery Application .................................. 76
16 Electrical Characteristics: 2-Battery Application ................................ 79
17 Electrical Characteristics: Car Application ......................................... 81
18 Digital Timing Characteristics .............................................................. 83
19 Digital Port Characteristics ................................................................... 87
20 Ordering Information ............................................................................. 89
21 Package Information ............................................................................. 89
22 Revision History ..................................................................................... 90
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