Linear LTC1663 10-bit rail-to-rail micropower dac with Datasheet

LTC1663
10-Bit Rail-to-Rail
Micropower DAC with
2-Wire Interface
DESCRIPTION
FEATURES
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Micropower 10-Bit DAC in SOT-23
Low Operating Current: 60μA
Ultralow Power Shutdown Mode: 10μA
2-Wire Serial Interface Compatible
with SMBus
Selectable Internal Reference or Ratiometric to
VCC
Maximum DNL Error: 0.75LSB
8 User Selectable Addresses (MSOP Package)
Single 2.7V to 5.5V Operation
Buffered True Rail-to-Rail Voltage Output
Power-On Reset
0.6V VIL and 1.4V VIH for SDA and SCL
Small 5-Lead SOT-23 and 8-Lead MSOP Packages
APPLICATIONS
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The LTC®1663 is a 10-bit voltage output DAC with true
buffered rail-to-rail output voltage capability. It operates
from a single supply with a range of 2.7V to 5.5V. The
reference for the DAC is selectable between the supply
voltage or an internal bandgap reference. Selecting the
internal bandgap reference will set the full-scale output
voltage range to 2.5V. Selecting the supply as the reference
sets the output voltage range to the supply voltage.
The part features a simple 2-wire serial interface compatible with SMBus that allows communication between many
devices. The internal data registers are double buffered to
allow for simultaneous update of several devices at once.
The DAC can be put in low current power-down mode for
use in power conscious systems.
Power-on reset ensures the DAC output is at 0V when
power is initially applied, and all internal registers are
cleared.
Digital Calibration
Offset/Gain Adjustment
Industrial Process Control
Automatic Test Equipment
Arbitrary Function Generators
Battery-Powered Data Conversion Products
For I2C designs, please refer to the LTC1669.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
BLOCK DIAGRAM
4 (5)
Differential Nonlinearity (DNL)
VCC
1.25V
BANDGAP
REFERENCE
1.0
VREF = VCC = 5V
TA = 25°C
0.8
0.6
REFERENCE
SELECT
10-BIT
DAC LATCH
+
VOUT 3 (8)
COMMAND
LATCH
–1.0
0
R
(6) AD0
(2) AD1
(3) AD2
–0.4
–0.8
R
INPUT
LATCH
0
–0.2
–0.6
–
MSOP
PACKAGE
ONLY
ERROR (LSB)
0.4
0.2
28
156 384 512 640 768 896 1024
CODE
1663 TA01
2-WIRE INTERFACE
SDA
SCL
GND
1 (1)
5 (4)
2 (7)
1663 BD
NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE
1663fd
1
LTC1663
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC to GND .............................................. – 0.3V to 7.5V
SDA, SCL ................................................. –0.3V to 7.5V
AD0, AD1, AD2 (MSOP Only) ........–0.3V to (VCC + 0.3V)
VOUT .............................................–0.3V to (VCC + 0.3V)
Storage Temperature Range.................. –65°C to 150°C
Operating Temperature Range
LTC1663C ............................................... 0°C to 70°C
LTC1663I............................................. –40°C to 85°C
LTC1663E (Note 8).............................. –40°C to 85°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
PACKAGE/ORDER INFORMATION
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
SDA
AD1
AD2
SCL
1
2
3
4
ORDER PART
NUMBER
8
7
6
5
LTC1663CMS8
LTC1663IMS8
LTC1663-8CMS8
LTC1663-8IMS8
VOUT
GND
AD0
VCC
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 150°C/W
SDA 1
GND 2
VOUT 3
MS8 PART MARKING
LTEQ
LTJJ
LTC1663CS5
LTC1663-1CS5
LTC1663-2CS5
LTC1663ES5
5 SCL
4 VCC
S5 PACKAGE
5-LEAD PLASTIC SOT-23
TJMAX = 125°C, θJA = 250°C/W
S5 PART MARKING*
LTA6
LTA7
LTEP
LTSA
LTSB
LTEP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
l
10
10
Bits
Monotonicity
(Note 2)
l
DNL
Differential Nonlinearity
Guaranteed Monotonic (Note 2)
l
± 0.2
±0.75
LSB
INL
Integral Nonlinearity
(Note 2)
LTC1663E (Note 2)
l
l
±0.5
±0.5
± 2.5
±3
LSB
LSB
VOS
Offset Error
Measured at Code 20
Measured at Code 20 (LTC1663E)
l
l
±10
±10
±30
±35
mV
mV
VOSTC
Offset Error Temperature Coefficient
FSE
Full-Scale Error
Reference Set to VCC
Reference Set to Internal Bandgap
Reference Set to VCC (LTC1663E)
Reference Set to Internal Bandgap (LTC1663E)
VOUT
DAC Output Span
Reference Set to VCC
Reference Set to Internal Bandgap
0 to VCC
0 to 2.5
VFSTC
Full-Scale Voltage Temperature
Coefficient
Reference Set to VCC
Reference Set to Internal Bandgap
±30
±50
μV/°C
μV/°C
PSRR
Power Supply Rejection Ratio
Reference Set to Internal Bandgap,
Code = 1023
±0.4
LSB/V
Bits
±15
l
l
l
l
±3
±3
μV/°C
±15
±15
±20
±20
LSB
LSB
LSB
LSB
V
V
1663fd
2
LTC1663
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VCC
Positive Supply Voltage
l
ICC
Supply Current
VCC = 3V (Note 3)
VCC = 5V (Note 3)
l
l
ISD
Supply Current in Shutdown Mode
(Note 3)
LTC1663E (Note 3)
Short-Circuit Current (Sourcing)
TYP
MAX
2.7
UNITS
5.5
V
60
75
100
125
μA
μA
l
l
10
12
16
24
μA
μA
VOUT Shorted to GND, Input Code = 1023
l
25
100
mA
Short-Circuit Current (Sinking)
VOUT Shorted to VCC, Input Code = 0
l
30
120
mA
Output Impedance to GND
Input Code = 0, VCC = 5V
Input Code = 0, VCC = 3V
In Shutdown Mode
65
150
500
Ω
Ω
kΩ
Output Impedance to VCC
Input Code = 1023, VCC = 5V
Input Code = 1023, VCC = 3V
80
120
Ω
Ω
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
0.75
0.25
V/μs
V/μs
Voltage Output Settling Time
To ± 0.5LSB (Notes 4, 5)
Op Amp DC Performance
AC Performance
30
Digital Feedthrough
Digital-to-Analog Glitch Impulse
1LSB Change Around Major Carry
μs
0.75
nV•s
70
nV•s
Digital Inputs SCL, SDA
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
1.4
V
0.6
V
VLTH
Logic Threshold Voltage
ILEAK
Digital Input Leakage
VCC = 5.5V and 0V, VIN = GND to VCC
VCC = 5.5V and 0V, VIN = GND to VCC (LTC1663E)
l
l
1
±1.0
±1.2
μA
μA
V
CIN
Digital Input Capacitance
(Note 7)
l
10
pF
IPULLUP = 350μA
l
0.4
V
VIN = 0V
l
1.5
μA
Digital Output SDA
VOL
Digital Output Low Voltage
Address Inputs AD0, AD1, AD2 (MSOP Only)
IUP
Address Pin Pull-Up Current
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
0.5
VCC – 0.3
V
0.8
V
TIMING CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
100
kHz
SMBus Timing Characteristics (Notes 6, 7)
fSMB
SMBus Operating Frequency
●
10
tBUF
Bus Free Time Between Stop and Start Condition
●
4.7
μs
tHD, STA
Hold Time After (Repeated) Start Condition
●
4.0
μs
tSU, STA
Repeated Start Condition Setup Time
●
4.7
μs
tSU, STO
Stop Condition Setup Time
●
4.0
μs
tHD, DAT
Data Hold Time
●
300
ns
1663fd
3
LTC1663
TIMING CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
MIN
tSU, DAT
Data Setup Time
●
250
tLOW
Clock Low Period
●
4.7
tHIGH
Clock High Period
●
4.0
tf
Clock, Data Fall Time
tr
Clock, Data Rise Time
TYP
MAX
UNITS
ns
μs
50
μs
●
300
ns
●
1000
ns
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS, i.e.,
codes k = 102 and k = 922.
Note 6: All values are referenced to VIH and VIL levels.
Note 7: Guaranteed by design and not subject to test.
Note 8: The LTC1663E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1003 (full scale). See Applications Information.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
1.0
1.0
VREF = VCC = 5V
TA = 25°C
0.8
5.0
VREF = VCC = 5V
TA = 25°C
0.8
0.6
OUTPUT VOLTAGE (V)
ERROR (LSB)
0
–0.2
0.2
0
–0.2
3.5
3.0
2.5
2.0
–0.4
–0.4
–0.6
–0.6
1.0
–0.8
–0.8
0.5
–1.0
0
28
156 384 512 640 768 896 1024
CODE
DAC CODE = 1023
4.0
0.4
0.2
TA = 25°C
4.5
0.6
0.4
ERROR (LSB)
Source and Sink Current
Capability with VCC = 5V
Differential Nonlinearity (DNL)
–1.0
0
28
1.5
0
156 384 512 640 768 896 1024
CODE
1663 G01
DAC CODE = 0
1 2 3 4 5 6 7 8 9 10
OUTPUT CURRENT SOURCE/SINK (mA)
0
1663 G02
Large-Signal Step Response
1663 G03
Midscale Glitch
Load Regulation vs Output Current
1.0
5
SDA
(VOLTS) 0
5
3
VOUT
(VOLTS) 2
0.6
VCC = 5V
RL = 4.7k
CL = 100pF
TA = 25°C
VOUT
10mV/DIV
VCC = 5V
RL = 4.7k
CL = 100pF
TA = 25°C
1
CODE = 32
0
5μs/DIV
1663 G04
2μs/DIV
VCC = VREF = 5V
VOUT = 2.5V
CODE = 512
TA = 25°C
0.4
CODE = 512 TO 511
CODE = 990
ΔVOUT (LSB)
4
0.8
5V
SDA
0V
1663 G05
0.2
0
–0.2
SOURCE
–0.4
SINK
–0.6
–0.8
–1.0
–4
–3
–2
–1 0
1
IOUT (mA)
2
3
4
1663fd
1663 G06
4
LTC1663
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error Voltage vs
Temperature
Load Regulation vs Output Current
OFFSET ERROR VOLTAGE (mV)
0.6
VCC = VREF = 3V
VOUT = 1.5V
CODE = 512
TA = 25°C
ΔVOUT (LSB)
0.4
0.2
0
–0.2
–0.4
SOURCE
SINK
5
2.510
4
2.508
3
2.506
OUTPUT VOLTAGE (V)
1.0
0.8
Full-Scale Output Voltage vs
Temperature
2
1
0
–1
–2
2.504
2.502
2.500
2.498
2.496
–3
2.494
–0.8
–4
2.492
–1.0
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
IOUT (mA)
–5
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
–0.6
1663 G07
80
100
REFERENCE SET TO
INTERNAL BANDGAP
2.490
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
1663 G08
80
100
1663 G09
PIN FUNCTIONS
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged
by the SDA pin. High impedance pin while data is shifted
in. Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to VCC.
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin.
Data is shifted into the SDA pin at the rising edges of the
clock. This high impedance pin requires a pull-up resistor
or current source to VCC.
VCC (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ VCC
≤ 5.5V. Also used as the reference voltage input when the
part is programmed to use VCC as the reference.
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1663’s slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
VOUT (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
rail-to-rail DAC output.
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (ΔVOUT – LSB)/LSB
Where ΔVOUT is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs
when they change state. The area of the glitch is specified
in (nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-scale
voltage from ideal. FSE includes the effects of offset and
gain errors (see Applications Information).
1663fd
5
6
NOTE: X = DON’T CARE
2
1
SCL
3
0
0
4
0
0
5
1
AD2
ADDRESS
6
1
AD1
tr
tHIGH
tf
tSU, DAT
tHD, DAT
REPEATED START
CONDITION
tSU, STA
tHD, STA
STOP
CONDITION
tBUF
tSU, STO
START
CONDITION
1663 TD
7
1
AD0
8
0
WR
9
ACK
1
X
X
2
X
X
3
X
X
4
X
X
5
X
X
COMMAND
6
0
BG
7
0
SD
8
0
SY
9
ACK
1
1
D7
2
1
D6
3
1
D5
4
1
5
1
D3
LS DATA
D4
6
1
D2
7
1
D1
8
1
D0
9
ACK
1
X
X
2
X
X
3
X
X
4
X
X
5
X
X
MS DATA
6
X
X
7
1
D9
8
1
D8
9
ACK
STOP
1663 TA02
ZERO-SCALE
VOLTAGE
FULL-SCALE
VOLTAGE
TIMING DIAGRAM
VOUT
1
0
START
1
SDA
0
tLOW
Typical LTC1663 Input Waveform—Programming DAC Output for Full Scale (AD2 to AD0 Set High)
START
CONDITION
tHD, STA
SCL
SDA
LTC1663
1663fd
LTC1663
DEFINITIONS
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go
below zero, the linearity is measured between full scale
and the lowest code that guarantees the output will be
greater than zero. The INL error at a given input code is
calculated as follows:
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
Where VOUT is the output voltage of the DAC measured
at the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = VREF/1024
APPLICATIONS INFORMATION
Write Word Protocol Used by the LTC1663
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address
Wr
A
Command Byte
A
LSData Byte
A
MSData Byte
A
P
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition
Serial Digital Interface
The LTC1663 communicates with a host (master) using
the standard 2-wire interface. The Timing Diagram shows
the timing relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus Accelerator, are required on
these lines.
The LTC1663 is a receive-only (slave) device. The master
can communicate with the LTC1663 using the Quick Command, Send Byte or Write Word protocols as explained
later.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA
from high to low while SCL is high.
1663 TA03
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another SMBus device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge related
clock pulse is generated by the master. The master releases
the SDA line (HIGH) during the Acknowledge clock pulse.
The slave-receiver must pull down the SDA line during the
Acknowledge clock pulse so that it remains a stable LOW
during the HIGH period of this clock pulse.
Write Word Protocol
The master initiates communication with the LTC1663 with
a START condition and a 7-bit address followed by the Write
1663fd
7
LTC1663
APPLICATIONS INFORMATION
Bit (Wr) = 0. The LTC1663 acknowledges and the master
delivers the command byte. The LTC1663 acknowledges
and latches the command byte into the command byte
input register. The master then delivers the least significant
data byte. Again the LTC1663 acknowledges and the data
is latched into the least significant data byte input register.
The master then delivers the most significant data byte.
The LTC1663 acknowledges once more and latches the
data into the most significant data byte input register.
Lastly, the master terminates the communication with a
STOP condition. On the reception of the STOP condition,
the LTC1663 transfers the input register information to
output registers and the DAC output is updated.
Slave Address (MSOP Package Only)
The LTC1663 can respond to one of eight 7-bit addresses.
The first 4 bits (MSBs) have been factory programmed to
0100. The first 4 bits of the LTC1663-8 have been factory
programmed to 0011. The three address bits, AD2, AD1
and AD0 are programmed by the user and determine the
LSBs of the slave address, as shown in the table below:
LTC1663
LTC1663-8
AD2
AD1
AD0
0100 xxx
0011 xxx
L
L
L
0100 000
0011 000
L
L
H
0100 001
0011 001
L
H
L
0100 010
0011 010
L
H
H
0100 011
0011 011
H
L
L
0100 100
0011 100
H
L
H
0100 101
0011 101
H
H
L
0100 110
0011 110
H
H
H
0100 111
0011 111
Slave Address (SOT-23 Package)
The slave address for the SOT-23 package has been
factory programmed to be “0100 000” (LTC1663),
“0100 001” (LTC1663-1) and “0100 010” (LTC1663-2) If
another address is required, please consult the factory.
Command Byte
7
6
5
4
3
2
1
0
X
X
X
X
X
BG
SD
SY
SY
1
0
Allows update on Acknowledge of SYNC Address only
Update on Stop condition only (Power-On Default)
SD
1
0
Puts the device in power-down mode
Puts the device in standard operating mode
(Power-On Default)
BG
1
0
Selects the internal bandgap reference
Selects the supply as the reference (Power-On Default)
X
X
Don’t Care
The stop condition normally initiates the update of the
DAC’s output latches. Simultaneous update of more than
one DAC or other devices on the bus can be achieved by
reissuing new start bit, address, command and data bytes
before issuing a final stop condition (which will update
all the devices). An alternate way to achieve simultaneous
LTC1663 updates is to override the stop condition update
by setting the “SY” bit of the command byte. Setting this
bit sets the device to update the DAC output latches only
at the reception of a SYNC address quick command. The
actual update occurs on the rising edge of SCL during the
Acknowledge. In this way, all devices can update on the
reception of the SYNC address quick command instead
of the STOP condition.
A Shutdown (SD) bit = HIGH will put the device in a low
power state but retain all data latch information. Shutdown
will occur at the reception of a STOP condition. This way
shutdown could be synchronized to other devices. The
output impedance of the DAC will go to a high impedance
state (≈ 500kΩ to GND).
The Bandgap (BG) bit when set to “0” selects the DAC
supply voltage as its voltage reference. The full-scale
output of the DAC with this setting is equal to the supply
voltage. When the BG bit is set to “1,” the internal bandgap
reference (≈1.25V) is selected as the DAC’s reference. The
full-scale output voltage for this setting is 2.5V.
1663fd
8
LTC1663
APPLICATIONS INFORMATION
Data Bytes
Least Significant Data Byte
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
The SY/CLR bit set high only has meaning when the “SY”
bit of the command byte was previously set HIGH. On
the otherhand, the SY/CLR bit set LOW will always clear
the part, independent of the state of the “SY” bit in the
command byte.
Most Significant Data Byte
6
5
4
3
2
1
0
Input Threshold
X
X
X = Don’t care
X
X
X
X
D9
D8
Anticipating the trend toward lower supply voltages,
the SMBus is specified with a VIH of 1.4V and a VIL of
0.6V. While some SMBus parts may violate this stringent
SMBus specification by allowing a higher VIH value for a
correspondingly higher input supply voltage, the LTC1663
meets and maintains the constant SMBus input threshold
specification across the entire supply voltage range of
2.7V to 5.5V. The logic input threshold is designed to be
1V with 50mV of hysteresis.
7
Send Byte Protocol
The Send Byte protocol used on the LTC1663 is actually a
subset of the Write Word protocol described previously.
The Send Byte protocol can only be used to send the
command byte information to the LTC1663.
1
7
1
1
8
1
1
S
Slave Address
Wr
A
Command Byte
A
P
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition
1663 TA04
The Send Byte protocol is also used whenever the Write
Word protocol is interrupted for any reason. Reception of
a START or STOP condition after the Acknowledge of the
command byte, but before the Acknowledge of the last
data byte, will cause both data bytes to be ignored and
the command byte to be accepted.
Reception of a START or STOP condition before the Acknowledge of the command byte will cause the interrupted
command byte to be ignored.
SYNC Address/Quick Command
In addition to the slave address, the LTC1663 has an address
that can be shared by other devices so that they may be
updated synchronously. The address is called to the SYNC
address and uses the quick command protocol.
The SYNC Address is 1111 110
1
Start
7
1
1
1
1111 110
SY/CLR
Ack
Stop
SYNC Address
SY/CLR
1
0
1663 TA05
Update output latches on rising edge of SCL during
Acknowledge of SYNC Address
Clear all internal latches on rising edge of SCL during
Acknowledge of SYNC Address
Voltage Output
The output amplifier contained in the LTC1663 can source
or sink up to 5mA. The output stage swings to within a
few millivolts of either supply rail when unloaded and
has an equivalent output resistance of 85Ω when driving
a load to the rails. The output amplifier is stable driving
capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance greater
than 1000pF. For example, a 0.1μF load can be driven
by the LTC1663 if a 110Ω series resistance is used. The
phase margin of the resulting circuit is 45° and increases
monotonically from this point if larger values of resistance,
capacitance or both are substituted for the values given.
Rail-to-Rail Output Considerations
As in any rail-to-rail device, the output is limited to voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when VCC is
used as the reference. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if the internal reference is used.
1663fd
9
LTC1663
APPLICATIONS INFORMATION
POSITIVE
FSE
VREF = VCC
OUTPUT
VOLTAGE
INPUT CODE
(c)
VREF = VCC
OUTPUT
VOLTAGE
0
512
INPUT CODE
(a)
1023
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1663 F01
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Internal Reference
In applications where a predictable output is required
that is independent of supply voltage, the LTC1663 has a
user-selectable internal reference. Selecting the internal
reference will set the full-scale output voltage to 2.5V. This
can be useful in applications where the supply voltage is
poorly regulated.
used. The LT1460 is ideal for use as a power supply for
the LTC1663 and can provide 3V, 3.3V and 5V full-scale
output voltage ranges. The LT1460 provides accuracy, noise
immunity and extended supply range to the LTC1663 when
the LTC1663 is operated ratiometric to VCC. Since both
parts are available in SOT-23 packages, the PC board space
for this application is extremely small. See Figure 2.
3.9V TO 20V
0.1μF
1
IN
LT1460S3-3
2
OUT
+
GND
In applications where the advantages of using the internal
reference are required but the full-scale range needs to
be greater than 2.5V, an external series reference can be
0.01μF
3
4 (5)
VCC
5 (4)
Using the LT®1460 Micropower Series Reference as a
Power Supply for the LTC1663
3V
TO
μP
1 (1)
SCL
LTC1663
OUT
3 (8)
0V ≤ VOUT ≤ 3V
SDA
GND
LTC1663 PIN NUMBERS IN PARENTHESES
REFER TO MSOP PACKAGE
2 (7)
1663 F02
Figure 2. LT1460 As Power Supply for the LTC1663
1663fd
10
LTC1663
PACKAGE DESCRIPTION
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
1.50 – 1.75
(NOTE 4)
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
1.90 BSC
S5 TSOT-23 0302
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.254
(.010)
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
8
7 6 5
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.52
(.0205)
REF
0° – 6° TYP
GAUGE PLANE
1
0.53 ± 0.152
(.021 ± .006)
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
2 3
1.10
(.043)
MAX
4
0.86
(.034)
REF
0.18
(.007)
SEATING
NOTE:
PLANE
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.127 ± 0.076
(.005 ± .003)
MSOP (MS8) 0204
1663fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1663
TYPICAL APPLICATION
Program Up to 8 Control Outputs Per BUS (8 LTC1663 and 8 LTC1663-8 DACs) and Place Them Where They Are Needed
VCC = 2.7V TO 5.5V
μP
SDA SCL
5
4
+
5
4
VCC
SCL
1
SDA
8
LTC1663-8CMS8
6
VOUT
AD0
2
AD1
3
AD2
GND
+
0.1μF
SMBus 2
GND
2
+
5
4
VCC
SCL
1
SDA
8
LTC1663CMS8
6
VOUT
AD0
2
AD1
3
AD2
GND
0.1μF
CONTROL
OUTPUT 0
0V ≤ VOUT0 < VCC
7
0.1μF
CONTROL
OUTPUT 8
0V ≤ VOUT8 < VCC
7
+
5
4
VCC
SCL
1
SDA
8
LTC1663-8CMS8
6
VOUT
AD0
2
AD1
3
AD2
GND
+
5
4
VCC
SCL
1
SDA
8
LTC1663CMS8
6
VOUT
AD0
2
AD1
3
AD2
GND
0.1μF
CONTROL
OUTPUT 1
0V ≤ VOUT1 < VCC
7
0.1μF
CONTROL
OUTPUT 9
0V ≤ VOUT9 < VCC
7
+
5
4
VCC
SCL
1
SDA
8
LTC1663-8CMS8
6
VOUT
AD0
2
AD1
3
AD2
GND
TO OTHER SMBus
DEVICES
1
VCC
SMBus 1
LTC1694
+
5
4
VCC
SCL
1
SDA
8
LTC1663CMS8
6
VOUT
AD0
2
AD1
3
AD2
GND
0.1μF
CONTROL
OUTPUT 7
0V ≤ VOUT7 < VCC
TO OTHER SMBus
DEVICES
7
0.1μF
CONTROL
OUTPUT 15
0V ≤ VOUT15 < VCC
7
1663 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1694
SMBus I2C Accelerator
Dual SMBus Accelerator with Active AC and DC Pull-Up Current
Sources
LTC1694-1
SMBus I2C Accelerator
Dual SMBus Accelerator with Active AC Pull-Up Current Only
Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP
Package. VCC = 2.7V to 5.5V
Low Power Multiplying VOUT DAC. Output Swings from GND to REF.
REF Input Can Be Tied to VCC. 3-Wire Interface.
DACs
LTC1659
LTC1660/LTC1664
Octal/Quad 10-Bit VOUT DACs in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface
LTC1661
Dual 10-Bit VOUT in 8-Lead MSOP Package
VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
LTC1669
10-Bit VOUT DAC in SOT-23, I2C Interface
Pin-Compatible with LTC1663
LTC1285/LTC1288
8-Pin SO, 3V Micropower ADCs
1- or 2-Channel, Autoshutdown
LTC1286/LTC1298
8-Pin SO, 5V Micropower ADCs
1- or 2-Channel, Autoshutdown
LTC1594/LTC1598
4/8-Channel, 5V Micropower 12-Bit ADCs
Low Power, Small Size, Low Cost
ADCs
1663fd
12 Linear Technology Corporation
LT 1007 REV D • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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