Supertex inc.
AT9917
Automotive LED Driver IC
with High Current Accuracy
Features
General Description
► Switch mode controller for boost, SEPIC & buck
converters
► Closed loop control of output current
► High PWM dimming ratio
► Internal 40V linear regulator
► Internal 3% voltage reference
► Constant frequency operation with programmable
slope compensation
► Linear and PWM dimming
► Programmable jitter to reduce EMI
► +/-1.0A MOSFET gate driver
► Output short circuit protection
► Output over voltage protection
► Programmable hiccup timer
► Temperature fold-back with external NTC resistor
► Soft start
► Meets AEC-Q100 requirements
The AT9917 is an advanced fixed frequency PWM IC
designed to control single-switch, boost, SEPIC, and buck
LED drivers in a constant current mode. The controller uses a
peak current-mode control scheme (with programmable slope
compensation) and includes an internal transconductance
amplifier to control the output current with high accuracy.
The IC includes a +/-1A gate driver that makes the AT9917
suitable for high power applications. An internal 40V linear
regulator powers the IC eliminating the need for a separate
power supply for the IC. The IC provides a FAULT output,
which can be used to disconnect the LEDs in case of a fault
condition (such as an alternator load dump in automobiles)
using an external disconnect FET. AT9917 also provides a
TTL compatible, low-frequency PWM dimming input that
can accept an external control signal with a duty ratio of 0100% and a frequency of up to several kilohertz. Temperature
foldback of the output current is possible, using an external
NTC resistor.
Applications
The AT9917-based LED driver is suited for automotive LED
driver applications. The AT9917 based LED lamp drivers can
achieve efficiencies in excess of 90% when buck or boost
topologies are used.
► Automotive LED driver applications
Typical Boost Application Circuit
D1
L1
Q1
RCS
CAVDD
CSC
CPVDD
VIN
PVDD
RSC
AVDD GT
CS
PGND
FDBK
AT9917
COMP
PWMD
CSS
JT
CJTR
NTC
DIV
R4
CC
IREF
REF
T2
T1
RR1
R1
RNTC
RT
RT
SS
OVP
FLT
GND
EN
Co
ROVP2
CIN1
CIN
ROVP1
D2 (Optional)
R3
CREF
Q2
RS
RR2
R2
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
AT9917
Ordering Information
24-Lead TSSOP
Device
7.80x4.40mm body
1.20mm height (max)
0.65mm pitch
AT9917
AT9917TS-G
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
Absolute Maximum Ratings
Parameter
Value
VIN to GND
-0.5V to +45V
PVDD, AVDD to GND
-0.3V to +6.0V
GATE to GND
-0.3V to (PVDD +0.3V)
All other pins to GND
-0.3V to (AVDD +0.3V)
Continuous power dissipation
VIN
AVDD
PVDD
GATE
PGND
GND
JTR
RT
CS
OVP
T2
T1
1000mW
(TA = +25°C)
Junction temperature
-40°C to +150°C
Storage temperature range
-65°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
1
24
REF
EN
NC
NC
FDBK
IREF
COMP
SS
PWMD
FLT
DIV
RNTC
24-Lead TSSOP (TS)
(top view)
Product Marking
Top Marking
YYWW AAA
9917T S
LLLLLLLL
Bottom Marking
CCCCCCCCC
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID
= “Green” Packaging
*May be part of ejector pin
Package may or may not include the following marks: Si or
24-Lead TSSOP (TS)
Electrical Characteristics
(Specifications are at TA = 25OC. VIN = 12V, PVDD = AVDD, EN = PWMD = AVDD, GATE = OPEN, CREF =
0.1μF, CAVDD = CPVDD = 1.0μF, RT = 200kΩ, IT1 = IT2 = 100μA unless otherwise noted.)
Sym
Parameter
Min
Typ
Max
Units
Conditions
Input
VINDC
Input DC supply voltage range
-
5.3
-
40
V
DC input voltage
IINDIS
Shut-down mode supply current
*
-
-
100
µA
EN = 0.8V, PWMD = GND
IINEN
Input current when enabled
*
-
-
2.0
mA
EN = 2.0V, GATE OPEN,
PWMD = GND
Internally regulated voltage
*
4.65
5.0
5.35
V
VIN = 6.0 - 40V, GATE OPEN,
PWMD = GND, IDD = 0 - 20mA
AVDD undervoltage lockout threshold
*
4.25
-
4.85
V
AVDD rising
AVDD undervoltage lockout
hysteresis
-
-
250
-
mV
AVDD falling
Internal Regulator
AVDD
UVLO
∆UVLO
Notes:
* Specifications apply over the full operating ambient temperature range of -40ºC < TA < +125ºC. Guaranteed by design and characterization.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
2
AT9917
Electrical Characteristics
(Specifications are at TA = 25OC. VIN = 12V, PVDD = AVDD, EN = PWMD = AVDD, GATE = OPEN, CREF =
0.1μF, CAVDD = CPVDD = 1.0μF, RT = 200kΩ, IT1 = IT2 = 100μA unless otherwise noted.)
Sym
Description
Min
Typ
Max
Units
Conditions
EN Input
VEN(LO)
EN input low voltage
*
-
-
0.8
V
---
VEN(HI)
EN input high voltage
*
2.0
-
-
V
---
Pull down resistor at EN
-
-
100
-
kΩ
---
REF pin voltage
*
1.210
1.250
1.290
V
VREF,DIS
REF pin voltage when disabled
-
-
0
-
mV
IREF = 0, EN = GND
VREFLOAD
Load regulation of reference voltage
-
0
-
2.0
mV
IREF = 0 - 1.0mA
TRISE
GATE output rise time
-
-
20
35
ns
CGATE = 4.0nF,
VIN = AVDD = PVDD = 5.0V
TFALL
GATE output fall time
-
-
20
35
ns
CGATE = 4.0nF,
VIN = AVDD = PVDD = 5.0V
DMAX
Maximum duty cycle
*
87
-
93
%
---
REN
Reference
VREF
IREF = 0
GATE
PWM Dimming
VPWMD(lo)
PWMD input low voltage
*
-
-
0.8
V
---
VPWMD(hi)
PWMD input high voltage
*
2.0
-
-
V
---
PWMD pull-down resistance
-
-
200
-
kΩ
---
RPWMD
Over Voltage Protection
VOVP,rising
Over voltage rising trip point
*
1.15
1.25
1.35
V
OVP rising
VOVP,HYST
Over voltage hysteresis
-
-
0.125
-
V
OVP falling
Current Sense
TBLANK
Leading edge blanking
*
100
-
250
ns
---
TDELAY1
Delay to output of comparator
-
-
-
150
ns
COMP = AVDD = PVDD = 5.0V,
VCS = 0 - 400mV step
VOFFSET
Comparator offset voltage
#
-10
-
10
mV
--150pF capacitance at COMP
pin
Internal Transconductance Opamp
GB
Gainbandwidth product
#
1.0
-
-
MHz
AV
Open loop DC gain
-
65
-
-
dB
Output OPEN
VCM
Input common-mode range
#
-0.3
-
3.0
V
---
VO
Output voltage range
#
0.7
-
AVDD
-
---
GM
Transconductance
-
-
950
-
µA/V
---
VOFFSET
Input offset voltage
*
-9.0
-
9.0
mV
---
Notes:
* Specifications apply over the full operating ambient temperature range of -40ºC < TA < +125ºC. Guaranteed by design and characterization.
# Specifications guaranteed by design and not tested in production
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
3
AT9917
Electrical Characteristics
(Specifications are at TA = 25OC. VIN = 12V, PVDD = AVDD, EN = PWMD = AVDD, GATE = OPEN, CREF =
0.1μF, CAVDD = CPVDD = 1.0μF, RT = 200kΩ, IT1 = IT2 = 100μA unless otherwise noted.)
Sym
Parameter
Min
Typ
Max
Units
ICOMP
COMP sink current
ICOMP
IBIAS
#
0.2
-
-
mA
VFB = 0.1V, VCOMP = 0
COMP source current
#
-0.2
-
-
mA
VFB = -0.1V, VCOMP = AVDD
Input bias current
#
-
0.5
1.0
nA
---
*
90
105
120
kHz
RT = 1.0MΩ
Oscillator
fOSC1
Oscillator frequency
Conditions
fOSC2
Oscillator frequency
*
427
505
583
kHz
RT = 200kΩ
fOSC
Output frequency range
#
100
-
800
kHz
---
-
-
50
-
Hz
CJTR = 100nF
-
-
500
-
Hz
CJTR = 10nF
-
±4.5
-
-
kHz
---
Charging current
-
-
10
-
µA
---
Voltage swing for hiccup timer
-
-
0.6
-
V
-----
Jitter
FJTR
Jitter frequency
∆F
Change in the switching frequency
Hiccup Timer
Ihiccup
∆V
Temperature Foldback Circuit
INTC
NTC current range
#
-
-
1.0
mA
NNTC
IFDBK / INTC current gain
-
-
0.13
-
-
INTC = 0.5mA
NT1
INTC / IT1 current gain
-
-
3.0
-
-
INTC = 0.5mA
NT2
INTC / IT2 current gain
-
-
6.0
-
-
INTC = 0.5mA
T1 and T2 reference voltage
-
-
3.5
-
V
---
Amplifier gain at IREF pin
-
1.8
2.0
2.2
-
VIREF = 400mV
Propagation time for short circuit
detection
-
-
-
250
ns
VIREF = 400mV,
FDBK steps from 0 - 1.0V;
FLT goes from high to low
TRISE,FAULT
Fault output rise time
-
-
-
300
ns
330pF capacitor at FLT pin
TFALL,FAULT
Fault output fall time
-
-
-
200
ns
330pF capacitor at FLT pin
Minimum voltage at the output of
the amplifier
#
250
-
-
mV
VIREF = 0
PWMD Blanking time
*
200
-
900
ns
---
ISS
Charging current
-
10
-
25
µA
---
ISS
Discharging current
-
1.0
-
-
mA
VSS = 5.0V
VSS
Reset voltage
-
-
-
100
mV
---
*
-
-
200
Ω
---
VT1, VT2
Output Short Circuit
GFAULT
TOFF
VMIN
TPWMD
Soft Start
Slope Compensation
RSLOPE
On-resistance of FET at CS pin
Notes:
* Specifications apply over the full operating ambient temperature range of -40ºC < TA < +125ºC. Guaranteed by design and characterization.
# Specifications guaranteed by design and not tested in production
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
4
AT9917
Functional Block Diagram
Linear
Regulator
VIN
4.25V/4.50V
0.8V/2V
REF
GATE
+
_
AVDD
EN
Vbg
POR
POR
PVDD
FC
GATE
+
_
HCP
PGND
RT
Clock
S
Q
FLT
FC
R
HCP
+
Blanking
OVPD
_
GATE
14R
COMP
+
CS
1.25V/1.125V
_
JTR
OVP
R
GND
DIS
SCD
OTP
SS
POR
S
POR
HCP
+
0.7V
+
GM
_
PWMD
OVPD
R
-
Q
DIS
Q
FC
TBLANK
FDBK
2
Current Mirror
IREF
250mV
4
(I - 3ITI)
30 NTC
Jitter
-
IT1
INTC
NTC
Supertex inc.
DIV
T1
_
SCD
OTP JTR
+
IDRP =
+
HCP
DIS
IT2
T2
JTR
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5
AT9917
Power Topology
rent externally. It should be bypassed with a low impedance
The AT9917 is a closed-loop, switch-mode LED driver de- (≥0.1µF) capacitor (0.01 -0.1μF).
signed to control a buck, boost or SEPIC converter in a constant frequency mode. The IC includes an internal linear reg- Timing Resistor (RT)
ulator, which operates from input voltages from 6.0 to 40V. The switching frequency of the converter is set by connectThe IC includes features typically required in LED drivers like ing a resistor between RT and GND. The resistor value can
open LED protection, output short circuit protection, linear be determined as:
and PWM dimming, and accurate control of the LED current.
1.0
RT =
It also includes a thermal derating circuit which can be used
fS • 9.5pF
to reduce the LED current at high temperatures to prevent
a thermal runaway. A high current gate drive output enables
Current Sense (CS)
the controller to be used in high power converters.
The current sense input is used to sense the source current
of the switching FET. The CS input of the AT9917 includes a
Power Supply to the IC (VIN, AVDD, PVDD)
The AT9917 can be powered directly from its VIN pin that built in 100ns (minimum) blanking time to prevent spurious
takes a voltage up to 40V. When a voltage is applied at the turn off due to the initial current spike when the FET turns
VIN pin, the AT9917 tries to maintain a constant 5.0V(typ) at on.
the AVDD pin. The regulator also has a built in under-voltage lockout which shuts off the IC if the voltage at the AVDD The IC includes an internal resistor divider network, which
pin falls below the UVLO threshold. This linear regulator also steps down the voltage at the COMP pins by a factor of 15.
This voltage is used as the reference for the current sense
provides the power supply to the built-in gate driver.
comparators. Since the maximum voltage of the COMP pin
The AVDD pin must by bypassed by a low ESR capacitor is AVDD, this voltage determines the maximum reference cur(≥0.1µF) to provide a low impedance path for the high fre- rent for the current sense comparator and thus the maximum
quency current of the output gate driver. The PVDD pin is inductor current.
used to provide power to the gate driver. It should be bypassed with a low ESR capacitor (≥0.1µF), and should be The current sense resistor RCS should be chosen so that the
input inductor current is limited to below the saturation curshorted to the AVDD pin.
rent level of the input inductor. For discontinuous conduction
The input current drawn from the external power supply (or mode of operation, no slope compensation is necessary. In
VIN pin) is a sum of the 2.0mA (max) current drawn by the all this case, the current sense resistor is chosen as:
the internal circuitry and the current drawn by the gate driver
(which, in turn, depends on the switching frequency and the
gate charge of the external FET).
IIN = 2mA + QG • fS
RCS =
AVDD - 0.8V
15 • ISAT
where ISAT is the maximum desired peak inductor current.
In the above equation, fS is the switching frequency of the For continuous conduction mode converters operating in the
converter and QG is the gate charge of the external FET constant frequency mode, slope compensation becomes
(which can be obtained from the FET datasheet).
necessary to ensure stability of the peak current mode controller, if the operating duty cycle is greater than 0.5. This
The EN pin is a TTL compatible input used to disable the IC. factor must also be accounted for when determining R (see
CS
Pulling the EN pin to GND will shut down the IC and reduce Slope Compensation section).
the quiescent current drawn by the IC to be less than 100μA.
If the enable function is not required, the EN pin can be conSlope Compensation
nected to AVDD.
Choosing a slope compensation, which is one half of the
Reference Voltage (REF)
down slope of the inductor current, ensures that the converter will be stable for all duty cycles.
The AT9917 provides a 1.25V reference voltage at the REF
pin. This voltage is used to derive the various internal volt- Slope compensation in the AT9917 can be programmed by
ages required by the IC, and is also used to set the LED cur- two external components (see Fig. 1). A resistor from AVDD
Supertex inc.
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6
AT9917
sets a current (which is almost constant since the AVDD
voltage is much larger than the voltage at the CS pin). This
current flows into the capacitor and produces a ramp voltage across the capacitor. The voltage at the CS pin is then
the sum of the voltage across the capacitor and the voltage
across the current sense resistor, with the voltage across the
capacitor providing the required slope compensation. When
the GATE turns off, an internal pull down FET discharges the
capacitor. The 200Ω(max) resistance of the internal FET will
prevent the voltage at the CS pin from going all the way to
zero. The minimum value of the voltage will instead be:
VCS,MIN =
AVDD
RSC
• 200Ω
FLT Output
The FLT pin is used to drive a disconnect FET while driving
boost and SEPIC converters. In the case of boost converters, when there is a short circuit fault at the output, there is a
direct path from the input source to ground which can cause
high currents to flow. The disconnect switch is used to interrupt this path and prevent damage to the converter.
The disconnect switch also helps to disconnect the output
filter capacitors for the boost and SEPIC converters from
the LED load during PWM dimming and enables a very high
PWM dimming ratio.
Control of the LED Current (IREF, FDBK and
COMP)
The slope compensation capacitor is chosen so that it can
The LED current in the AT9917 is controlled in a closed-loop
be completely discharged by the internal 200Ω(max) FET at
manner. The current reference which sets the LED current at
the CS pin during the time the FET is off. Assuming the worst
the IREF pin is set by using a resistor divider from the REF
case switch duty cycle of 93%,
pin (or can be set externally with a low voltage source). This
0.07
reference voltage is compared to the voltage at the FDBK pin,
CSC =
which senses the LED current in the current sense resistor.
3 • 200Ω • fS
The AT9917 includes a 1.0MHz transconductance amplifier
with a tri-state output, which is used to close the feedback
Assuming a down slope of DS (A/μs) for the inductor current,
loops and provide accurate current control. The compensathe current sense resistor and the slope compensation resistion network is connected at the COMP pin.
tor can be computed as:
RCS =
RCS =
AVDD - 0.8V
15
•
{
1
DS • 106 • 0.93
2 • fS
}
The output of the op-amp is buffered and connected to the
current sense comparator using a 14R:1R resistor divider.
+ ISAT
2 • AVDD
DS • 106 • CSC • RCS
+
GATE
AVDD
Linear Dimming
RSC
CS
CSC
RCS
Figure 1: Slope Compensation
Gate Driver Output (GATE, PGND)
The GATE output of the AT9917 is used to drive the gate of
the switching FET. The PGND pin should be connected to
the GND connection of the current sense resistor and the
two grounds of the IC (PGND and GND) should be connected together at the input GND connection to minimize noise.
Supertex inc.
The output of the op-amp is also controlled by the signal applied to the PWMD pin. When PWMD is high, the output of
the op-amp is connected to the COMP pin. When PWMD is
low, the output is left open. This enables the integrating capacitor to hold the charge when the PWMD signal has turned
off the gate drive. When the IC is enabled, the voltage on the
integrating capacitor will almost instantaneously force the
converter into a steady state.
Linear dimming can be accomplished in the AT9917 by varying the voltages at the IREF pin. Note that since the AT9917
is a peak current mode controller, it has a minimum on-time
for the GATE output. This minimum on-time will prevent the
converter from completely turning off even when the IREF
pin is pulled to GND. Thus, linear dimming cannot accomplish true zero LED current. To get zero LED current, PWM
dimming has to be used.
Due to the offset voltage of the short circuit comparator, as
well as the non-linearity of the X2 gain stage, pulling the
IREF pin very close to GND might cause the internal short
circuit comparator to trigger and shut down the IC. To overcome this, the output of the gain stage is limited to 250mV
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
7
AT9917
(minimum), allowing the IREF pin to be pulled all the way to Fault Conditions
0V without triggering the short circuit comparator. Therefore, The AT9917 is a robust controller which can protect the LEDs
the minimum voltage for a short circuit detection is 250mV.
and the LED driver in case of fault conditions. The AT9917
includes both open LED protection and output short circuit
PWM Dimming (PWMD)
protection. In both cases, the AT9917 shuts down and atPWM dimming in the AT9917 can be accomplished using a tempts a restart. The hiccup time is programmed by the caTTL-compatible square wave source at the PWMD pin.
pacitor at the JTR pin.
When the PWM signal is high, the GATE and FLT pins are
enabled and the output of the transconductance op-amp
is connected to the external compensation network. Thus,
the internal amplifier controls the output current. When the
PWMD signal goes low, the output of the transconductance
amplifier is disconnected from the compensation network.
Thus, the integrating capacitor maintains the voltage across
it. The GATE is disabled, so the converter stops switching
and the FLT pin goes low, turning off the disconnect switch.
Note that disconnecting the LED load during PWM dimming
causes the energy stored in the inductor to be dumped into
the output capacitor. The filter capacitor that is chosen should
be large enough so that it can absorb the inductor energy
without significant change of the voltage across it. If the capacitor voltage change is significant, it would cause a turn-on
spike in the inductor current when PWMD goes high.
When a fault condition is detected, both GATE and FLT outputs are disabled, the COMP pins and JTR pins are pulled to
GND. Once the voltage at the JTR pin falls below 0.1V and
the fault condition(s) have disappeared, the capacitor at the
JTR pin is released and is charged slowly by a 10μA current
source. Once the capacitor is charged to 0.7V, the COMP
pins are released and GATE and FLT pins are allowed to turn
on. If the hiccup time is long enough, it will ensure that the
compensation networks are all completely discharged and
that the converters start at minimum duty cycle.
Short Circuit Protection
When a short circuit condition is detected (output current becomes higher than twice the steady state current), the GATE
and FLT outputs are pulled low. As soon as the disconnect
FET is turned off, the output current goes to zero and the
short circuit condition disappears. At this time, the hiccup
timer is started. Once the timing is complete, the converter
Jitter and Hiccup Timer (JTR)
attempts to restart. If the fault condition still persists, the conThe JTR pin is a multipurpose pin in the AT9917. It is used verter shuts down and goes through the cycle again. If the
to set the jitter frequency (frequency at which the switching fault condition is cleared (due to a momentary output short)
frequency swings between its limits). It is also used to set the the converter will start regulating the output current normally.
hiccup time for fault conditions.
This allows the LED driver to recover from accidental shorts
without having to reset the IC.
The value of the capacitor required for the jitter frequency is
given by:
During short circuit conditions, there are two conditions that
CJTR =
determine the hiccup time.
5.0µF
FJTR(Hz)
The first is the time required to discharge the compensation
capacitors. Assuming a pole-zero R-C network at the COMP
Note that the jitter frequency must be chosen to be signifi- pin (series combination of R and C in parallel with C ),
Z
Z
C
cantly lower than the cross over frequency of the closed loop
control. If not, the controller will not be able to reject the jitter
tCOMP = 3 • RZ • CZ
frequency and the LED current will have a current ripple at
In case the compensation networks are only type 1 (single
the jitter frequency.
capacitor), then:
The same capacitor is used to determine the hiccup time.
tCOMP = 3 • 300Ω • CC
The hiccup time is computed as:
CJTR • 0.6V
The second is the time required for the inductors to comtHICCUP =
10µA
pletely discharge following a short circuit. This time can be
computed as:
If the hiccup time is lower than desired, the capacitor at the
pin can be increased at the cost of a lower jitter frequency.
Supertex inc.
tIND =
π
√L • CO
4
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8
AT9917
where L and Co are the input inductor and output capacitor When the output voltage reaches the OVP rising threshold,
of the power stage.
the AT9917 detects an over voltage condition and turns off
the converter. The converter is turned back on only when the
The hiccup time is then chosen as:
output voltage falls below the falling OVP threshold (which
is 10% lower than the rising threshold). This time is mostly
tHICCUP > max (tCOMP, tIND)
dictated by the R-C time constant of the output capacitor CO
and the resistor network used to sense over voltage (ROVP1
Note that the power rating of the LED sense inductor has to
be chosen properly if it has to survive a persistent fault condi- + ROVP2). In case of a persistent open circuit condition, this
cycle maintains the output voltage within a 10% band.
tion. The power rating can be determined using:
PRS ≥
I2SAT • RS • (tfall,fault + tOFF)
tHICCUP
Where ISAT is the saturation current of the disconnect FET. In
case of the AT9917, (tfall,fault + tOFF) is 450ns (max).
False Triggering of the Short Circuit Comparator During PWM Dimming
During PWM dimming, the parasitic capacitance of the LED
string might cause a spike in the output current when the
disconnect FET is turned on. If this spike is detected by the
short circuit comparator, it will cause the IC to falsely detect
an over current condition and shut down.
In the AT9917, to prevent these false triggerings, there is a
built in 500ns blanking network for the short circuit comparator. This blanking network is activated when the PWMD input
goes high. Thus, the short circuit comparator will not see the
spike in the LED current during the PWM dimming turn-on
transition. Once the blanking timer has completed its task,
the short circuit comparator will start monitoring the output
current. Thus, the total delay time for detecting a short circuit
will depend on the condition of the PWMD input.
In most designs, the lower threshold voltage of the over
voltage protection (VOVP -10%) at which point the AT9917 attempts to restart will be more than the LED string voltage.
Thus, when the LED load is reconnected to the output of the
converter, the voltage differential between the actual output
voltage and the LED string voltage will cause a spike in the
output current. This causes a short circuit to be detected and
the AT9917 will trigger short circuit protection. This behavior
continues until the output voltage becomes lower than the
LED string voltage, at which point no fault will be detected
and normal operation of the circuit will commence.
Thermal Derating
The reference voltage used to set the LED current is programmed using two resistors - R r1 and R r2 connected as
shown in Figure 2.
Rr2
IO • RS = VREF •
Rr1 + Rr2
where IO is the output LED current and RS is the current
sense resistor.
Thermal derating is programmed using 4 pins - NTC, DIV,
T1 and T2. When no temperature foldback is required, NTC
If the output short circuit exists before the PWM dimming
and T1 should be connected to AVDD, and DIV should
signal goes high, the total detection time will be:
be connected to GND. T2 still requires a resistor to GND
(10~100kΩ). No pins should be left floating (Figure 2).
tDETECT1 = tPWMD + tfall, fault + tOFF ≈ 950ns(max)
If the short circuit occurs when the PWM dimming signal is
already high, the time to detect will be:
IO
FDBK
RS
tDETECT1 = tfall, fault + tOFF ≈ 450ns(max)
Rr2
Over Voltage Protection
The AT9917 provides hysteretic over voltage protection. allowing the IC to recover in case the LED load is momentarily
disconnected.
AVDD
When the load is disconnected in a boost converter, the
output voltage rises as the output capacitor starts charging. Figure 2: No Thermal Derating
Supertex inc.
REF
Rr1
IREF
NTC
DIV
T1
T2
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
9
AT9917
When thermal derating needs to be implemented, four resis- Temperature T1 is programmed by selecting R2 such that:
tors are used to set the various points to obtain the thermal
derating curve shown in Figure 3.
R2 = 3 • RNTC(T1)
where RNTC(T1) is resistance of the NTC resistor at the temperature T1.
ISHORT
R1 can be computed using the maximum current (≤1.0mA)
that will flow through the NTC resistor at temperature T2.
ILED
I1
R1 =
I2
T1
T2
Figure 3: Thermal Derating Curve
When an external NTC resistor is connected (Figure 4), both
temperatures T1 and T2, as well as the current I2 can be accurately programmed to maximize the light output of the LED
lamp.
IO
R4
RS
R1
IREF
RNTC
NTC
DIV
R2
R1
R3
INTC,MAX
•
T1
T2
{
R2
RNTC(T2)
}
- R2
Further reduction of the NTC resistance RNTC will create a
proportional offset of the current feedback reference at
FDBK, and hence will cause decrease of the LED current. To
program the desired current I2 at the temperature T2, resistor
R4 at FDBK can be calculated as:
(I1 - I2 ) • RS • (R1 + R2 )
R4 =
VT1 •
{
R2
4
- 3.0
30 RNTC(T2)
FDBK
REF
Rr2
VT1
}
The turn off of the converter at the maximum temperature is
programmed using R3.
R3 =
{
6 • (R1 + R2)
R2
RNTC(T2)
- 3.0
}
The over-temperature recovery threshold is independent of
the current in T2. AT9917 recovers from thermal shutdown at
the break temperature T1, where:
INTC < 3 • IT1.
Figure 4: With Thermal Derating
The ratio of the resistor divider R2/(R1 + R2) programs the
voltage at the NTC pin. The voltage VT1 at T1 is approximately 3.5V. The current sourced by NTC and T1 is mirrored out
of FDBK in accordance with the following equation:
IFDBK =
4
30 (INTC - 3IT1)
when:
INTC > 3 • IT1.
INTC, IT1, and IT2 are the currents sourced from pins NTC, T1,
and T2 respectively.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
10
AT9917
Pin Description
Pin #
Name
Description
1
VIN
2
AVDD
This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to
GND (at least 0.1μF).
3
PVDD
This is the power supply pin for the gate driver. It should be connected externally to AVDD and bypassed with a low ESR capacitor to PGND (at least 0.1μF).
4
GATE
This pin is the output gate driver for an external logic level N-channel power MOSFET.
5
PGND
Ground return for the gate drive circuitry.
6
GND
Ground return for all the low power analog internal circuitry. This pin must be connected to the return
path from the input.
7
JTR
This pin controls the jitter of the clock programmed by a capacitor connected at this pin. This capacitor
also determines the hiccup time.
8
RT
This pin sets the frequency of the power circuit. A resistor between RT and GND will program the
circuit in constant frequency mode.
9
CS
This pin is used to sense the source current of the external power FET. It includes a built-in 100ns
(min) blanking time. Slope compensation is implemented by connecting an RC network to this pin as
shown in the Typical Application.
10
OVP
This pin provides the over voltage protection for the converter. When the voltage at this pin exceeds
1.25V, the gate output of the AT9917 is turned off and FLT goes low. Switching is enabled when the
voltage at this pin goes below 1.125V.
11
T2
This current programs the temperature at which the driver is shut off due to over temperature conditions for the LED.
12
T1
This current input programs the break temperature threshold which determines the start of the current
derating when using the external NTC resistor.
13
RNTC
14
DIV
Programs the voltage input for the transconductance at NTC pin.
15
FLT
This pin is pulled to ground when there is an output short circuit condition or output over voltage condition. This pin can be used to drive an external MOSFET in the case of boost converters to disconnect
the load from the source. It is also controlled by the PWM dimming input to provide excellent PWM
dimming response.
16
PWMD
When this pin is pulled to GND (or left open), switching of the AT9917 is disabled. When an external
TTL high level is applied to it, switching will resume.
17
SS
18
COMP
Stable closed loop control can be accomplished by connecting a compensation network between
COMP and GND. This pin is discharged upon detection of a fault condition and on startup.
19
IREF
The voltage at this pin sets the output current level. The current reference can be set using a resistor
divider from the REF pin.
20
FDBK
This pin provides output current feedback to the AT9917 by using a current sense resistor. A resistor
in series with the FDBK pin can be used to reduce the current at elevated temperatures.
21
NC
22
NC
23
EN
Pulling EN to GND causes the AT9917 to go into a low current standby mode. A voltage greater than
2.0V will cause the IC to start up.
24
REF
This pin provides accurate reference voltage. It must be bypassed with a 0.01μF -0.1μF capacitor to
GND.
This pin is the input of a 40V high voltage regulator.
Connect an external NTC resistor to this pin for temperature fold-back of the output current.
Connecting a capacitor from this pin to GND programs the soft start time of the LED driver.
No connection.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
11
AT9917
24-Lead TSSOP Package Outline (TS)
7.80x4.40mm body, 1.20mm height (max), 0.65mm pitch
D
24
θ1
E1
E
L2
Note 1
(Index Area
D/2 x E1/2)
L
L1
1
Top View
θ
Gauge
Plane
Seating
Plane
View B
A
A A2
View
B
Seating
Plane
e
A1
b
Side View
View A-A
A
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
Dimension
(mm)
A
A1
A2
b
D
E
E1
MIN
0.85*
0.05
0.80
0.19
7.70
6.20*
4.30
NOM
-
-
1.00
-
7.80
6.40
4.40
MAX
1.20
0.15
1.15†
0.30
7.90
6.60*
4.50
e
0.65
BSC
L
L1
0.45
0.60
0.75
1.00
REF
L2
0.25
BSC
θ
0O
8O
θ1
12O
REF
JEDEC Registration MS-153, Variation AD, Issue F, May 2001.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-24TSSOPTS, Version B041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2010 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-AT9917
A071610
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
12