Low Power, Selectable Gain Differential ADC Driver, G = 1, 2, 3 ADA4950-1/ADA4950-2 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS 13 –VS 14 –VS 16 –VS 15 –VS ADA4950-1 11 –OUT –INA 3 10 +OUT –INB 4 9 07957-001 VOCM +VS 8 +VS 7 12 PD +INA 2 +VS 5 +INB 1 +VS 6 High performance at low power High speed −3 dB bandwidth of 750 MHz, G = 1 0.1 dB flatness to 210 MHz, VOUT, dm = 2 V p-p, RL, dm = 200 Ω Slew rate: 2900 V/µs, 25% to 75% Fast 0.1% settling time of 9 ns Low power: 9.5 mA per amplifier Low harmonic distortion 108 dB SFDR @ 10 MHz 98 dB SFDR @ 20 MHz Low output voltage noise: 9.2 nV/√Hz, G = 1, RTO ±0.2 mV typical input offset voltage Selectable differential gains of 1, 2, and 3 Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage Input common-mode range shifted down by 1 VBE Wide supply range: +3 V to ±5 V Available in 16-lead and 24-lead LFCSP packages Figure 1. ADA4950-1 20 PD1 19 –OUT1 21 –VS1 22 –VS1 24 +INA1 23 +INB1 ADA4950-2 –INA1 1 18 +OUT1 –INB1 2 17 VOCM1 16 –VS2 15 –VS2 +INB2 5 14 PD2 +INA2 6 13 –OUT2 VOCM2 11 +OUT2 12 –50 +VS2 10 GENERAL DESCRIPTION +VS2 9 –40 –INA2 7 ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Line drivers –INB2 8 APPLICATIONS 07957-002 +VS1 4 +VS1 3 Figure 2. ADA4950-2 The ADA4950-1/ADA4950-2 are gain-selectable versions of the ADA4932-1/ADA4932-2 with on-chip feedback and gain resistors. They are ideal choices for driving high performance ADCs as singleended-to-differential or differential-to-differential amplifiers. The output common-mode voltage is user adjustable by means of an internal common-mode feedback loop, allowing the ADA4950-1/ ADA4950-2 output to match the input of the ADC. The internal feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. HARMONIC DISTORTION (dBc) VOUT, dm = 2V p-p –60 –70 –80 HD2, HD3, HD2, HD3, ±5V ±5V ±2.5V ±2.5V –90 –100 –110 –120 –130 Figure 3. Harmonic Distortion vs. Frequency at Various Supplies The ADA4950-1/ADA4950-2 are fabricated using the Analog Devices, Inc., proprietary silicon-germanium (SiGe) complementary bipolar process, enabling them to achieve low levels of distortion and noise at low power consumption. The low offset and excellent dynamic performance of the ADA4950-x make it well suited for a wide variety of data acquisition and signal processing applications. The devices are available in a Pb-free, 3 mm × 3 mm, 16-lead LFCSP (ADA4950-1, single) or a Pb-free, 4 mm × 4 mm, 24-lead LFCSP (ADA4950-2, dual). The pinout has been optimized to facilitate PCB layout and minimize distortion. The ADA4950-1/ ADA4950-2 are specified to operate over the −40°C to +105°C temperature range; both operate on supplies from +3 V to ±5 V. Rev. B 1 10 FREQUENCY (MHz) 100 07957-025 Differential gain configurations of 1, 2, and 3 are easily realized with internal feedback networks that are connected externally to set the closed-loop gain of the amplifier. –140 0.1 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4950-1/ADA4950-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 18 Applications ....................................................................................... 1 Applications Information .............................................................. 19 General Description ......................................................................... 1 Analyzing an Application Circuit ............................................ 19 Functional Block Diagrams ............................................................. 1 Selecting the Closed-Loop Gain............................................... 19 Revision History ............................................................................... 2 Estimating the Output Noise Voltage ...................................... 19 Specifications..................................................................................... 3 ±5 V Operation ............................................................................. 3 Calculating the Input Impedance for an Application Circuit .......................................................................................... 20 5 V Operation ............................................................................... 5 Input Common-Mode Voltage Range ..................................... 22 Absolute Maximum Ratings ............................................................ 7 Input and Output Capacitive AC Coupling ............................ 22 Thermal Resistance ...................................................................... 7 Input Signal Swing Considerations .......................................... 22 Maximum Power Dissipation ..................................................... 7 Setting the Output Common-Mode Voltage .......................... 22 ESD Caution .................................................................................. 7 Layout, Grounding, and Bypassing .............................................. 23 Pin Configurations and Function Descriptions ........................... 8 High Performance ADC Driving ................................................. 24 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 25 Test Circuits ..................................................................................... 16 Ordering Guide .......................................................................... 25 Terminology .................................................................................... 17 REVISION HISTORY 10/15—Rev. A to Rev. B Changed CP-16-2 to CP-16-21 ......................................... Universal Changes to Figure 1 .......................................................................... 1 Changes to Figure 5 .......................................................................... 8 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 3/13—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 5/09—Revision 0: Initial Version Rev. B | Page 2 of 26 Data Sheet ADA4950-1/ADA4950-2 SPECIFICATIONS ±5 V OPERATION TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, G = 1, RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 52 for signal definitions. Differential Inputs to VOUT, dm Performance Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small-Signal Bandwidth −3 dB Large-Signal Bandwidth Bandwidth for 0.1 dB Flatness ADA4950-1 ADA4950-2 Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic IMD3 Voltage Noise (Referred to Output) Crosstalk (ADA4950-2) INPUT CHARACTERISTICS Offset Voltage (Referred to Input) Input Capacitance Input Common-Mode Voltage Range CMRR Open-Loop Gain OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error Gain Error Test Conditions/Comments Min VOUT, dm = 0.1 V p-p VOUT, dm = 2.0 V p-p VOUT, dm = 2.0 V p-p, RL = 200 Ω VOUT, dm = 2 V p-p, 25% to 75% VOUT, dm = 2 V step VIN = 0 V to 5 V ramp, G = 2 See Figure 51 for distortion test circuit VOUT, dm = 2 V p-p 1 MHz 10 MHz 20 MHz 50 MHz VOUT, dm = 2 V p-p 1 MHz 10 MHz 20 MHz 50 MHz f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p f = 1 MHz Gain = 1 Gain = 2 Gain = 3 f = 10 MHz; Channel 2 active, Channel 1 output V+DIN = V−DIN = VOCM = 0 V TMIN to TMAX variation Single-ended at package pin Directly at internal amplifier inputs, not external input terminals DC, ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −2.5 64 Maximum ∆VOUT, single-ended output, RL = 1 kΩ 200 kHz, RL, dm = 10 Ω, SFDR = 69 dB ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 2 V p-p, 1 MHz; see Figure 50 for output balance test circuit Gain = 1 Gain = 2 Gain = 3 Rev. B | Page 3 of 26 –VS + 1.4 to +VS – 1.4 Typ Max Unit 750 350 MHz MHz 210 230 2900 9 20 MHz MHz V/µs ns ns −108 −107 −98 −80 dBc dBc dBc dBc −126 −105 −99 −84 −94 dBc dBc dBc dBc dBc 9.2 12.5 16.6 −87 nV/√Hz nV/√Hz nV/√Hz dB ±0.2 –3.7 0.5 −VS + 0.2 to +VS − 1.8 −64 66 +2.5 mV µV/°C pF V −49 dB dB −VS + 1.2 to +VS − 1.2 114 −62 0.5 1.0 0.8 V mA peak dB 1.2 1.9 1.7 % % % ADA4950-1/ADA4950-2 Data Sheet VOCM to VOUT, cm Performance Table 2. Parameter VOCM DYNAMIC PERFORMANCE −3 dB Small-Signal Bandwidth −3 dB Large-Signal Bandwidth Slew Rate Input Voltage Noise (Referred to Input) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Test Conditions/Comments Min Typ Max Unit VOUT, cm = 100 mV p-p VOUT, cm = 2 V p-p VIN = 1.5 V to 3.5 V, 25% to 75% f = 1 MHz 250 105 430 9.8 MHz MHz V/µs nV/√Hz V V+DIN = V−DIN = 0 V ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.98 –VS + 1.2 to +VS – 1.2 26 +0.8 −60 1.0 32 +6 −49 1.01 kΩ mV dB V/V Min Typ Max Unit 11 10.1 V mA µA/°C mA dB 22 −6 General Performance Table 3. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled Test Conditions/Comments 3.0 8.8 TMIN to TMAX variation Powered down ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p Powered down Enabled 9.5 31 0.7 −96 1.0 −84 ≤(+VS – 2.5) ≥(+VS – 1.8) 600 28 PD = 5 V PD = 0 V −1.0 −250 OPERATING TEMPERATURE RANGE −40 Rev. B | Page 4 of 26 +0.2 −180 V V ns ns +1.0 −140 µA µA +105 °C Data Sheet ADA4950-1/ADA4950-2 5 V OPERATION TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = 2.5 V, G = 1, RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 52 for signal definitions. Differential Inputs to VOUT, dm Performance Table 4. Parameter DYNAMIC PERFORMANCE −3 dB Small-Signal Bandwidth −3 dB Large-Signal Bandwidth Bandwidth for 0.1 dB Flatness ADA4950-1 ADA4950-2 Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic IMD3 Voltage Noise (Referred to Input) Crosstalk (ADA4950-2) INPUT CHARACTERISTICS Offset Voltage (Referred to Input) Input Capacitance Input Common-Mode Voltage Range CMRR Open-Loop Gain OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error Gain Error Test Conditions/Comments Min VOUT, dm = 0.1 V p-p VOUT, dm = 2.0 V p-p VOUT, dm = 2.0 V p-p, RL = 200 Ω VOUT, dm = 2 V p-p, 25% to 75% VOUT, dm = 2 V step VIN = 0 V to 2.5 V ramp, G = 2 See Figure 51 for distortion test circuit VOUT, dm = 2 V p-p 1 MHz 10 MHz 20 MHz 50 MHz VOUT, dm = 2 V p-p 1 MHz 10 MHz 20 MHz 50 MHz f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p f = 1 MHz Gain = 1 Gain = 2 Gain = 3 f = 10 MHz; Channel 2 active, Channel 1 output V+DIN = V−DIN = VOCM = 2.5 V TMIN to TMAX variation Single-ended at package pin Directly at internal amplifier inputs, not external input terminals DC, ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −4 64 Maximum ∆VOUT, single-ended output, RL = 1 kΩ 200 kHz, RL, dm = 10 Ω, SFDR = 67 dB ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V p-p, 1 MHz; see Figure 50 for output balance test circuit Gain = 1 Gain = 2 Gain = 3 Rev. B | Page 5 of 26 –VS + 1.2 to +VS – 1.2 Typ Max Unit 770 320 MHz MHz 220 160 2200 10 19 MHz MHz V/µs ns ns −108 −107 −98 −82 dBc dBc dBc dBc −124 −114 −99 −83 −94 dBc dBc dBc dBc dBc 9.2 12.5 16.6 −87 nV/√Hz nV/√Hz nV/√Hz dB ±0.4 −3.7 0.5 –VS + 0.2 to +VS – 1.8 −64 66 +4 mV µV/°C pF V −49 dB dB –VS + 1.1 to +VS – 1.1 70 −62 0.5 1.0 0.8 V mA peak dB 1.2 1.9 1.7 % % % ADA4950-1/ADA4950-2 Data Sheet VOCM to VOUT, cm Performance Table 5. Parameter VOCM DYNAMIC PERFORMANCE −3 dB Small-Signal Bandwidth −3 dB Large-Signal Bandwidth Slew Rate Input Voltage Noise (Referred to Input) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Test Conditions/Comments Min Typ Max Unit VOUT, cm = 100 mV p-p VOUT, cm = 2 V p-p VIN = 1.5 V to 3.5 V, 25% to 75% f = 1 MHz 240 90 380 9.8 MHz MHz V/µs nV/√Hz V V+DIN = V−DIN = 2.5 V ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.98 –VS + 1.2 to +VS – 1.2 26 +1.0 −60 1.0 32 +6.5 −49 1.01 kΩ mV dB V/V Test Conditions/Comments Min Typ Max Unit 11 9.6 V mA µA/°C mA dB 22 −6.5 General Performance Table 6. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled 3.0 8.4 TMIN to TMAX variation Powered down ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p Powered down Enabled 8.9 31 0.6 −96 0.9 −84 ≤(+VS – 2.5) ≥(+VS – 1.8) 600 29 PD = 5 V PD = 0 V −1.0 −100 OPERATING TEMPERATURE RANGE −40 Rev. B | Page 6 of 26 +0.2 −65 V V ns ns +1.0 −40 µA µA +105 °C Data Sheet ADA4950-1/ADA4950-2 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Power Dissipation Input Current, +INx, −INx, PD Storage Temperature Range Operating Temperature Range ADA4950-1 ADA4950-2 Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 11 V See Figure 4 ±5 mA −65°C to +125°C −40°C to +105°C −40°C to +105°C 300°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. The power dissipated due to the load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power planes reduces θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the single 16-lead LFCSP (91°C/W) and the dual 24-lead LFCSP (65°C/W) on a JEDEC standard 4-layer board with the exposed pad soldered to a PCB pad that is connected to a solid plane. 3.5 MAXIMUM POWER DISSIPATION (W) THERMAL RESISTANCE θJA is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p printed circuit board, as described in EIA/JESD51-7. Table 8. Thermal Resistance Package Type ADA4950-1, 16-Lead LFCSP (Exposed Pad) ADA4950-2, 24-Lead LFCSP (Exposed Pad) θJA 91 65 θJC 28 16 Unit °C/W °C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the ADA4950-x package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4950-x. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. 3.0 2.5 2.0 ADA4950-2 1.5 ADA4950-1 1.0 0.5 0 –40 07957-004 Table 7. –20 0 20 40 60 AMBIENT TEMPERATURE (°C) 80 100 Figure 4. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board ESD CAUTION Rev. B | Page 7 of 26 ADA4950-1/ADA4950-2 Data Sheet 20 PD1 19 –OUT1 22 –VS1 21 –VS1 24 +INA1 23 +INB1 18 +OUT1 –INA1 1 12 PD –INB1 2 17 VOCM1 +INA 2 ADA4950-1 11 –OUT +VS1 3 ADA4950-2 –INA 3 TOP VIEW (Not to Scale) 10 +OUT +VS1 4 TOP VIEW (Not to Scale) +VS2 10 13 –OUT2 +VS2 9 14 PD2 +INA2 6 VOCM2 11 07957-005 NOTES 1. SOLDER THE EXPOSED PADDLE ON THE BACK OF THE PACKAGE TO A GROUND PLANE OR TO A POWER PLANE. +INB2 5 –INA2 7 +VS 8 +VS 7 +VS 6 +VS 5 VOCM –INB2 8 9 –INB 4 16 –VS2 15 –VS2 +OUT2 12 +INB 1 NOTES 1. SOLDER THE EXPOSED PADDLE ON THE BACK OF THE PACKAGE TO A GROUND PLANE OR TO A POWER PLANE. Figure 5. ADA4950-1 Pin Configuration 07957-006 13 –VS 14 –VS 16 –VS 15 –VS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. ADA4950-2 Pin Configuration Table 9. ADA4950-1 Pin Function Descriptions Pin No. 1 2 3 4 5 to 8 9 10 11 12 13 to 16 17 (EPAD) Mnemonic +INB +INA −INA −INB +VS VOCM +OUT −OUT PD −VS Exposed Paddle (EPAD) Description Positive Input B, 250 Ω Input. Use alone for G = 2 or tie to +INA for G = 3. Positive Input A, 500 Ω Input. Use alone for G = 1 or tie to +INB for G = 3. Negative Input A, 500 Ω Input. Use alone for G = 1 or tie to −INB for G = 3. Negative Input B, 250 Ω Input. Use alone for G = 2 or tie to −INA for G = 3. Positive Supply Voltage. Output Common-Mode Voltage. Positive Output. Negative Output. Power-Down Pin. Negative Supply Voltage. Solder the exposed paddle on the back of the package to a ground plane or to a power plane. Table 10. ADA4950-2 Pin Function Descriptions Pin No. 1 2 3, 4 5 6 7 8 9, 10 11 12 13 14 15, 16 17 18 19 20 21, 22 23 24 25 (EPAD) Mnemonic −INA1 −INB1 +VS1 +INB2 +INA2 −INA2 −INB2 +VS2 VOCM2 +OUT2 −OUT2 PD2 −VS2 VOCM1 +OUT1 −OUT1 PD1 −VS1 +INB1 +INA1 Exposed Paddle (EPAD) Description Negative Input A, Amplifier 1, 500 Ω Input. Use alone for G = 1 or tie to –INB1 for G = 3. Negative Input B, Amplifier 1, 250 Ω Input. Use alone for G = 2 or tie to –INA1 for G = 3. Positive Supply Voltage, Amplifier 1. Positive Input B, Amplifier 2, 250 Ω Input. Use alone for G = 2 or tie to +INA2 for G = 3. Positive Input A, Amplifier 2, 500 Ω Input. Use alone for G = 1 or tie to +INB2 for G = 3. Negative Input A, Amplifier 2, 500 Ω Input. Use alone for G = 1 or tie to –INB2 for G = 3. Negative Input B, Amplifier 2, 250 Ω Input. Use alone for G = 2 or tie to –INA2 for G = 3. Positive Supply Voltage, Amplifier 2. Output Common-Mode Voltage, Amplifier 2. Positive Output, Amplifier 2. Negative Output, Amplifier 2. Power-Down Pin, Amplifier 2. Negative Supply Voltage, Amplifier 2. Output Common-Mode Voltage, Amplifier 1. Positive Output, Amplifier 1. Negative Output, Amplifier 1. Power-Down Pin, Amplifier 1. Negative Supply Voltage, Amplifier 1. Positive Input B, Amplifier 1, 250 Ω Input. Use alone for G = 2 or tie to +INA1 for G = 3. Positive Input A, Amplifier 1, 500 Ω Input. Use alone for G = 1 or tie to +INB1 for G = 3. Solder the exposed paddle on the back of the package to a ground plane or to a power plane. Rev. B | Page 8 of 26 Data Sheet ADA4950-1/ADA4950-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, G = 1, RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. Refer to Figure 49 for test setup. Refer to Figure 52 for signal definitions. 2 0 G = 1, RT = 53.6Ω G = 2, RT = 57.6Ω G = 3, RT = 61.9Ω –1 –2 –3 –4 –5 –6 –7 1 10 100 FREQUENCY (MHz) –4 –5 –6 –7 1 10 100 FREQUENCY (MHz) 1000 2 VOUT, dm = 2V p-p 1 0 CLOSED-LOOP GAIN (dB) 0 VS = ±5V VS = ±2.5V –1 –2 –3 –4 –5 –1 VS = ±5V VS = ±2.5V –2 –3 –4 –5 –6 07957-008 –6 –7 1 10 100 FREQUENCY (MHz) 07957-011 CLOSED-LOOP GAIN (dB) –3 Figure 10. Large-Signal Frequency Response for Various Gains VOUT, dm = 100mV p-p 1 –7 –8 1000 Figure 8. Small-Signal Frequency Response for Various Supplies 1 10 100 FREQUENCY (MHz) 1000 Figure 11. Large-Signal Frequency Response for Various Supplies 2 2 VOUT, dm = 100mV p-p 1 VOUT, dm = 2V p-p 1 0 –1 CLOSED-LOOP GAIN (dB) 0 CLOSED-LOOP GAIN (dB) –2 –8 2 TA = –40°C TA = +25°C TA = +105°C –2 –3 –4 –5 TA = –40°C TA = +25°C TA = +105°C –1 –2 –3 –4 –5 –6 07957-009 –6 –7 –8 G = 1, RT = 53.6Ω G = 2, RT = 57.6Ω G = 3, RT = 61.9Ω –1 1000 Figure 7. Small-Signal Frequency Response for Various Gains –8 0 1 10 100 FREQUENCY (MHz) 07957-012 –8 VOUT, dm = 2V p-p 1 07957-010 NORMALIZED CLOSED-LOOP GAIN (dB) VOUT, dm = 100mV p-p 1 07957-007 NORMALIZED CLOSED-LOOP GAIN (dB) 2 –7 –8 1000 Figure 9. Small-Signal Frequency Response for Various Temperatures 1 10 100 FREQUENCY (MHz) 1000 Figure 12. Large-Signal Frequency Response for Various Temperatures Rev. B | Page 9 of 26 ADA4950-1/ADA4950-2 Data Sheet 2 2 VOUT, dm = 100mV p-p 1 CLOSED-LOOP GAIN (dB) RL = 1kΩ RL = 200Ω –2 –3 –4 –5 –6 –3 –4 –5 10 100 FREQUENCY (MHz) 07957-016 07957-013 1 –7 –8 1000 Figure 13. Small-Signal Frequency Response at Various Loads 1 10 100 FREQUENCY (MHz) 1000 Figure 16. Large-Signal Frequency Response at Various Loads 2 2 VOUT, dm = 100mV p-p 1 VOUT, dm = 2V p-p 1 0 –1 CLOSED-LOOP GAIN (dB) 0 CLOSED-LOOP GAIN (dB) RL = 1kΩ RL = 200Ω –2 –6 –7 VOCM = –2.5VDC VOCM = 0V VOCM = +2.5VDC –2 –3 –4 –5 –1 VOCM = –2.5VDC VOCM = 0V VOCM = +2.5VDC –2 –3 –4 –5 –6 07957-014 –6 –7 –8 –1 1 10 100 FREQUENCY (MHz) 07957-017 CLOSED-LOOP GAIN (dB) 0 –1 –8 VOUT, dm = 2V p-p 1 0 –7 –8 1000 Figure 14. Small-Signal Frequency Response for Various VOCM Levels 1 10 100 FREQUENCY (MHz) 1000 Figure 17. Large-Signal Frequency Response for Various VOCM Levels 4 4 VOUT, dm = 100mV p-p 0 CL = 0pF CL = 0.9pF CL = 1.8pF CL = 2.7pF –2 –4 –6 0 CL = 0pF CL = 0.9pF CL = 1.8pF CL = 2.7pF –2 –4 1 10 100 FREQUENCY (MHz) –8 1000 Figure 15. Small-Signal Frequency Response at Various Capacitive Loads 07957-018 –6 07957-015 –8 VOUT, dm = 2V p-p 2 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 2 1 10 100 FREQUENCY (MHz) 1000 Figure 18. Large-Signal Frequency Response at Various Capacitive Loads Rev. B | Page 10 of 26 Data Sheet ADA4950-1/ADA4950-2 0.5 0.5 VOUT, dm = 2V p-p 0.4 0.4 0.3 0.3 CLOSED-LOOP GAIN (dB) 0.2 0.1 0 –0.1 –0.3 –0.4 RL = 1kΩ R L = 200Ω AMP 1, RL = 1kΩ AMP 1, RL = 200Ω AMP 2, RL = 1kΩ AMP 2, RL = 200Ω 10 100 FREQUENCY (MHz) 0 –0.1 ADA4950-1, ADA4950-1, ADA4950-2, ADA4950-2, ADA4950-2, ADA4950-2, –0.2 –0.3 –0.5 1 0.1 07957-019 ADA4950-1, ADA4950-1, ADA4950-2, ADA4950-2, ADA4950-2, ADA4950-2, –0.2 0.2 –0.4 RL = 1kΩ R L = 200Ω AMP 1, RL = 1kΩ AMP 1, RL = 200Ω AMP 2, RL = 1kΩ AMP 2, RL = 200Ω 07957-022 CLOSED-LOOP GAIN (dB) VOUT, dm = 100mV p-p –0.5 1000 1 Figure 19. 0.1 dB Flatness, Small-Signal Frequency Response for Various Loads 10 100 FREQUENCY (MHz) 1000 Figure 22. 0.1 dB Flatness, Large-Signal Frequency Response for Various Loads 2 2 VOCM (AC) = 2V p-p 1 0 0 –1 –1 VOCM GAIN (dB) VOCM = –2.5VDC VOCM = 0V VOCM = +2.5VDC –3 –4 –3 –4 –5 –5 –6 –6 –7 –8 1 10 100 FREQUENCY (MHz) VOCM = –2.5VDC VOCM = 0V VOCM = +2.5VDC –2 –7 –8 1000 Figure 20. VOCM Small-Signal Frequency Response at Various DC Levels 1 –40 VOUT, dm = 2V p-p VOUT, dm = 2V p-p HD2, RL, dm = 1kΩ HARMONIC DISTORTION (dBc) –80 –50 HD3, RL, dm = 1kΩ HD2, RL, dm = 200Ω HD3, RL, dm = 200Ω –90 –100 –110 –120 –130 –140 0.1 –60 –70 –80 –90 HD2, HD3, HD2, HD3, HD2, HD3, G G G G G G =1 =1 =2 =2 =3 =3 –100 –110 –120 –130 1 10 FREQUENCY (MHz) 100 07957-021 HARMONIC DISTORTION (dBc) –50 –70 1000 Figure 23. VOCM Large-Signal Frequency Response at Various DC Levels –40 –60 10 100 FREQUENCY (MHz) Figure 21. Harmonic Distortion vs. Frequency at Various Loads –140 0.1 1 10 FREQUENCY (MHz) 100 Figure 24. Harmonic Distortion vs. Frequency at Various Gains Rev. B | Page 11 of 26 07957-024 –2 07957-023 VOCM (AC) = 100mV p-p 07957-020 VOCM GAIN (dB) 1 ADA4950-1/ADA4950-2 Data Sheet –40 –40 –50 –50 –60 –60 HD2, HD3, HD2, HD3, –70 –80 HARMONIC DISTORTION (dBc) ±5V ±5V ±2.5V ±2.5V –90 –100 –110 –120 –130 –80 –100 –110 –120 –140 0 1 2 3 5 4 7 8 9 6 VOUT, dm (V p-p) 10 11 12 13 14 07957-028 100 10 FREQUENCY (MHz) 07957-025 1 Figure 28. Harmonic Distortion vs. VOUT, dm, f = 10 MHz –40 –30 VOUT, dm = 2V p-p VOUT, dm = 2V p-p –50 –50 HD2 AT HD3 AT HD2 AT HD3 AT –60 –70 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) ±5V ±5V ±2.5V ±2.5V –90 Figure 25. Harmonic Distortion vs. Frequency at Various Supplies 10MHz 10MHz 30MHz 30MHz –80 –90 –100 –110 HD2 AT HD3 AT HD2 AT HD3 AT –60 –70 10MHz 10MHz 30MHz 30MHz –80 –90 –100 –110 –120 –3 –2 –1 0 1 2 3 4 VOCM (V) –120 07957-026 –130 –4 HD2, HD3, HD2, HD3, –70 –130 –140 0.1 –40 VOCM = 0V Figure 26. Harmonic Distortion vs. VOCM at Various Frequencies, ±5 V Supplies 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VOCM (V) 07957-029 HARMONIC DISTORTION (dBc) VOUT, dm = 2V p-p Figure 29. Harmonic Distortion vs. VOCM at Various Frequencies, 5 V Supply –40 –50 VOUT, dm = 2V p-p –80 HD2, VOUT, dm = 2V p-p HD3, VOUT, dm = 2V p-p HD2, VOUT, dm = 4V p-p HD3, VOUT, dm = 4V p-p –90 –100 –110 –120 –130 –140 0.1 1 10 FREQUENCY (MHz) 100 Figure 27. Harmonic Distortion vs. Frequency at Various VOUT, dm –60 –70 –80 –90 RL, dm = 200Ω –100 RL, dm = 1kΩ –110 –120 –130 –140 0.1 1 10 FREQUENCY (MHz) 100 07957-030 –70 SPURIOUS-FREE DYNAMIC RANGE (dBc) –60 07957-027 HARMONIC DISTORTION (dBc) –50 Figure 30. Spurious-Free Dynamic Range vs. Frequency at Various Loads Rev. B | Page 12 of 26 Data Sheet ADA4950-1/ADA4950-2 10 –10 –20 90 60 45 40 0 20 –40 –50 –60 –70 –45 0 –90 PHASE –20 –135 –40 –180 –60 –225 PHASE (Degrees) GAIN –30 GAIN (dB) NORMALIZED SPECTRUM (dB) 80 VOUT, dm = 2V p-p 0 –80 –90 –100 29.7 29.8 29.9 30.0 30.1 30.2 FREQUENCY (MHz) 30.3 30.4 30.5 –80 1k 10k 100k 1M 10M 100M 1G –270 10G 07957-240 –120 29.6 07957-031 –110 FREQUENCY (Hz) Figure 34. Open-Loop Gain and Phase vs. Frequency Figure 31. 30 MHz Intermodulation Distortion 0 –45 RL, dm = 200Ω VIN, dm = 100mV p-p RL, dm = 200Ω VIN = 2V p-p –47 –20 –49 –40 –53 PSRR (dB) CMRR (dB) –51 –55 –57 PSRR+ –60 PSRR– –80 –59 –61 –65 1 10 100 FREQUENCY (MHz) 07957-035 07957-032 –100 –63 –120 1 1000 0 0 RL, dm = 200Ω VIN, dm = 2V p-p –20 –20 –40 –30 –40 –60 AMPLIFIER 2 TO AMPLIFIER 1 –80 –50 –100 –60 –120 –70 100M FREQUENCY (Hz) 1G AMPLIFIER 1 TO AMPLIFIER 2 07957-036 CROSSTALK (dB) –10 07957-033 OUTPUT BALANCE (dB) VOUT, dm = 2V p-p 10M 1000 Figure 35. PSRR vs. Frequency Figure 32. CMRR vs. Frequency 1M 10 100 FREQUENCY (MHz) –140 1 10 100 FREQUENCY (MHz) Figure 36. Crosstalk vs. Frequency, ADA4950-2 Figure 33. Output Balance vs. Frequency Rev. B | Page 13 of 26 1000 ADA4950-1/ADA4950-2 –10 INPUT SINGLE-ENDED, 50Ω LOAD TERMINATION OUTPUT DIFFERENTIAL, 100Ω SOURCE TERMINATION S11: SINGLE-ENDED-TO-SINGLE-ENDED S22: DIFFERENTIAL-TO-DIFFERENTIAL –20 RL, dm = 200Ω VIN, dm = 100mV p-p 1k 100 –30 S11 –40 S22 07957-037 –50 –60 1 10 100 FREQUENCY (MHz) +OUT –OUT VOUT, dm 1 0.1 0.1 1000 10 FREQUENCY (MHz) 1 100 1k Figure 40. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1 Figure 37. Return Loss (S11, S22) vs. Frequency 1000 15 10 100 5 VOLTAGE (V) G=2 G=3 G=1 0 VOUT, dm –5 10 –10 1 1 10 100 1k 10k 100k 1M –15 10M 0 0.1 0.2 0.4 0.3 0.5 0.6 07957-041 2 × VIN 07957-038 OUTPUT VOLTAGE NOISE DENSITY (nV/√Hz) 10 07957-040 CLOSED-LOOP OUTPUT IMPEDANCE MAGNITUDE (Ω) S-PARAMETERS (dB) 0 Data Sheet 0.7 0.8 0.9 1.0 TIME (µs) FREQUENCY (Hz) Figure 41. Overdrive Recovery, G = 2 Figure 38. Voltage Noise Spectral Density for Various Gains, Referred to Output 0.06 1.5 G=3 0.02 0 –0.02 –0.04 –0.06 0 5 10 15 TIME (ns) 20 25 1.0 G=1 G=2 0.5 G=3 0 –0.5 –1.0 07957-042 G=2 NORMALIZED OUTPUT VOLTAGE (V) 0.04 07957-039 NORMALIZED OUTPUT VOLTAGE (V) G=1 –1.5 30 0 Figure 39. Small-Signal Pulse Response for Various Gains 5 10 15 TIME (ns) 20 25 Figure 42. Large-Signal Pulse Response for Various Gains Rev. B | Page 14 of 26 30 Data Sheet ADA4950-1/ADA4950-2 2.0 0.10 1.5 OUTPUT VOLTAGE (V) 0 CL = 0pF CL = 0.9pF CL = 1.8pF CL = 2.7pF 5 10 CL = 0pF CL = 0.9pF CL = 1.8pF CL = 2.7pF –0.5 –1.5 15 TIME (ns) 20 25 –2.0 0 30 Figure 43. Small-Signal Pulse Response for Various Capacitive Loads 5 15 TIME (ns) 20 25 30 1.5 0.02 0 –0.02 07957-044 –0.04 5 10 15 TIME (ns) 20 25 0.5 0 –0.5 –1.0 –1.5 5 0 30 Figure 44. VOCM Small-Signal Pulse Response 10 15 TIME (ns) 20 30 25 Figure 47. VOCM Large-Signal Pulse Response 1.5 6 0.5 1.2 VOCM = +1V DC 0.4 1.0 5 1.0 4 0.8 3 0.6 2 0.4 ERROR 0.1 0 0 INPUT –0.1 –0.5 ERROR (%) 0.2 0.5 –0.2 OUTPUT PD PIN VOLTAGE (V) 0.3 1 –0.3 –1.0 0.2 PD PIN INPUT (SHOWN INVERTED FOR CLARITY) –1.5 –0.5 –5 0 5 10 15 20 TIME (ns) 25 30 35 40 07957-045 0 –0.4 0 –1 Figure 45. Settling Time –0.2 0 1 2 3 4 TIME (ms) 5 6 Figure 48. PD Response Time Rev. B | Page 15 of 26 7 8 07957-048 0 1.0 07957-047 OUTPUT COMMON-MODE VOLTAGE (V) 0.04 –0.06 VOLTAGE (V) 10 Figure 46. Large-Signal Pulse Response for Various Capacitive Loads 0.06 OUTPUT COMMON-MODE VOLTAGE (V) 0 07957-046 –0.10 0 0.5 –1.0 07957-043 –0.05 1.0 NONINVERTING OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.05 ADA4950-1/ADA4950-2 Data Sheet TEST CIRCUITS +5V NC DC-COUPLED SOURCE 500Ω 250Ω 500Ω 50Ω 53.6Ω VIN VOCM ADA4950-x 1kΩ 500Ω 0.1µF NC 250Ω 500Ω 07957-049 25.5Ω –5V Figure 49. Equivalent Basic Test Circuit, G = 1 DIFFERENTIAL NETWORK ANALYZER SOURCE DIFFERENTIAL NETWORK ANALYZER RECEIVER +5V 49.9Ω 500Ω 250Ω NC 56.2Ω 49.9Ω 50Ω 500Ω VOCM ADA4950-x 500Ω 50Ω 56.2Ω NC 500Ω 49.9Ω 07957-051 49.9Ω 250Ω –5V Figure 50. Test Circuit for Output Balance, CMRR +5V NC DC-COUPLED SOURCE LOW-PASS FILTER VIN 500Ω 0.1µF 500Ω 53.6Ω VOCM ADA4950-x 25.5Ω 261Ω 0.1µF 500Ω 50Ω 200Ω 442Ω 2:1 DUAL FILTER CT 442Ω 0.1µF NC 250Ω 500Ω –5V Figure 51. Test Circuit for Distortion Measurements Rev. B | Page 16 of 26 07957-252 50Ω 250Ω Data Sheet ADA4950-1/ADA4950-2 TERMINOLOGY +INA VOCM –INA –INB RGB RF 250Ω 500Ω RGA +IN 500Ω 500Ω RGB –OUT ADA4950-x RGA Common-Mode Voltage Common-mode voltage refers to the average of two node voltages with respect to the local ground reference. The output common-mode voltage is defined as –IN 250Ω RL, dm VOUT, dm +OUT RF 500Ω VOUT, cm = (V+OUT + V−OUT)/2 07957-152 +INB Figure 52. Signal and Circuit Definitions Differential Voltage Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or equivalently, output differential node voltage) is defined as VOUT, dm = (V+OUT − V−OUT) Output Balance Output balance is a measure of how close the output differential signals are to being equal in amplitude and opposite in phase. Any imbalances in amplitude or phase produce an undesired common-mode signal at the amplifier output. Output balance error is defined as the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. where V+OUT and V−OUT refer to the voltages at the +OUT and −OUT output terminals with respect to a common ground reference. The input differential voltage is defined in different ways, depending upon the selected gain. For G = 1 VIN, dm = (+INA − (−INA)) where +INA and −INA refer to the voltages at the +INA and −INA input terminals with respect to a common ground reference (input terminals +INB and −INB are floating). For G = 2 VIN, dm = (+INB − (−INB)) where +INB and −INB refer to the voltages at the +INB and −INB input terminals with respect to a common ground reference (input terminals +INA and −INA are floating). For G = 3, input terminals +INA and +INB are connected together, and input terminals −INA and −INB are connected together. VIN, dm = (+INAB − (−INAB)) where +INAB and −INAB refer to the voltages at the connection of input terminals +INA and +INB and at the connection of input terminals −INA and −INB with respect to a common ground reference. Rev. B | Page 17 of 26 Output Balance Error = ∆VOUT , cm ∆VOUT , dm ADA4950-1/ADA4950-2 Data Sheet THEORY OF OPERATION The ADA4950-x differs from conventional op amps in that it has two outputs whose voltages move in opposite directions and an additional input, VOCM. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The ADA4950-x behaves much like a standard voltage feedback op amp and facilitates single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. Like an op amp, the ADA4950-x has high input impedance at its internal input terminals (to the right of the internal gain resistors) and low output impedance. Because it uses voltage feedback, the ADA4950-x manifests a nominally constant gain bandwidth product. Two feedback loops are used to control the differential and common-mode output voltages. The differential feedback loop, set with on-chip feedback and gain resistors, controls only the differential output voltage. The common-mode feedback loop is internal to the actual amplifier and controls only the commonmode output voltage. This architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. The output common-mode voltage is forced, by the internal common-mode feedback loop, to be equal to the voltage applied to the VOCM input. The internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. This results in differential outputs that are very close to the ideal of being identical in amplitude and that are exactly 180° apart in phase. Rev. B | Page 18 of 26 Data Sheet ADA4950-1/ADA4950-2 APPLICATIONS INFORMATION ANALYZING AN APPLICATION CIRCUIT The ADA4950-x uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +INx and −INx (see Figure 52). For most purposes, this voltage can be assumed to be 0. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM can also be assumed to be 0. Starting from these principles, any application circuit can be analyzed. SELECTING THE CLOSED-LOOP GAIN Using the approach described in the Analyzing an Application Circuit section, the differential gain of the circuit in Figure 52 can be determined by V IN , dm = RF RG where the input resistors (RG) and the feedback resistors (RF) on each side are equal. For G = 1, the +INA and −INA inputs are used, and the +INB and −INB inputs are left floating. The differential gain in this case is calculated as follows: G= G= 500 Ω RF = =3 RG 500 Ω || 250 Ω ESTIMATING THE OUTPUT NOISE VOLTAGE The differential output noise of the ADA4950-x can be estimated using the noise model in Figure 53. The values of RG depend on the selected gain. The input-referred noise voltage density, vnIN, is modeled as a differential input, and the noise currents, inIN− and inIN+, appear between each input and ground. The output voltage due to vnIN is obtained by multiplying vnIN by the noise gain, GN (defined in the GN equation that follows Table 13). The noise currents are uncorrelated with the same mean-square value, and each produces an output voltage that is equal to the noise current multiplied by the associated feedback resistance. The noise voltage density at the VOCM pin is vnCM. When the feedback networks have the same feedback factor, as is true in most cases, the output noise due to vnCM is common mode. Each of the four resistors contributes (4kTRxx)1/2. The noise from the feedback resistors appears directly at the output, and the noise from the gain resistors appears at the output multiplied by RF/RG. Table 11 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. R F 500 Ω = =1 RG 500 Ω vnRG1 vnRF1 RF1 inIN+ For G = 2, the +INB and −INB inputs are used, and the +INA and −INA inputs are left floating. The differential gain in this case is calculated as follows: G= RG1 + inIN– R F 500 Ω = =2 RG 250 Ω vnIN ADA4950-x vnOD VOCM vnRG2 RG2 RF2 vnCM vnRF2 07957-053 VOUT , dm For G = 3, the +INA and +INB inputs are connected together, and the −INA and −INB inputs are connected together. The differential gain in this case is calculated as follows: Figure 53. Noise Model Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks Input Noise Contribution Differential Input Inverting Input Noninverting Input VOCM Input Gain Resistor, RG1 Gain Resistor, RG2 Feedback Resistor, RF1 Feedback Resistor, RF2 Input Noise Term vnIN inIN− inIN+ vnCM vnRG1 vnRG2 vnRF1 vnRF2 Input Noise Voltage Density vnIN inIN− × (RF2) inIN+ × (RF1) vnCM (4kTRG1)1/2 (4kTRG2)1/2 (4kTRF1)1/2 (4kTRF2)1/2 Rev. B | Page 19 of 26 Output Multiplication Factor GN 1 1 0 RF1/RG1 RF2/RG2 1 1 Differential Output Noise Voltage Density Term vnO1 = GN(vnIN) vnO2 = (inIN−)(RF2) vnO3 = (inIN+)(RF1) vnO4 = 0 V vnO5 = (RF1/RG1)(4kTRG1)1/2 vnO6 = (RF2/RG2)(4kTRG2)1/2 vnO7 = (4kTRF1)1/2 vnO8 = (4kTRF2)1/2 ADA4950-1/ADA4950-2 Data Sheet Table 12. Differential Input, DC-Coupled Nominal Linear Gain 1 2 3 RF (Ω) 500 500 500 RG (Ω) 500 250 250||500 RIN, dm (Ω) 1000 500 333 Differential Output Noise Density (nV/√Hz) 9.25 12.9 16.6 Table 13. Single-Ended, Ground-Referenced Input, DC-Coupled, RS = 50 Ω Nominal Linear Gain 1 2 3 RG1 (Ω) 500 250 250||500 RT (Ω) (Std 1%) 53.6 57.6 61.9 RIN, se (Ω) 667 375 267 RG2 (Ω)1 526 277 194 Differential Output Noise Density (nV/√Hz) 9.07 12.2 15.0 RG2 = RG1 + (RS||RT). RF Similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the inputreferred terms at +INx and −INx by the appropriate output factor, where: +VS RG R IN , se Note that the output noise from VOCM goes to 0 in this case. The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms. RG = RF 1− ( ) 2 R R × + F G RF 8 2 ∑ v nOi +VS RIN, se i =1 RG Table 12 and Table 13 list the three available gain settings, associated resistor values, input impedance, and output noise density for both balanced and unbalanced input configurations. VOCM ADA4950-x –VS RF The effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, as shown in Figure 54, the input impedance (RIN, dm) is RL VOUT, dm RG CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT The value of RG depends on the selected gain. –IN For an unbalanced, single-ended input signal (see Figure 55), the input impedance is R 1 =1+ F β RG RIN, dm = (RG + RG) = 2 × RG VOUT, dm Figure 54. ADA4950-x Configured for Balanced (Differential) Inputs When the feedback factors are matched, RF1/RG1 = RF2/RG2, β1 = β2 = β, and the noise gain becomes v nOD = ADA4950-x –VS RF RG1 RG2 and β2 = are the feedback factors. β1 = RF1 + RG1 RF2 + RG2 GN = VOCM VIN, dm 2 is the circuit noise gain. GN = (β1 + β 2 ) +IN 07957-054 RG 07957-055 1 RF (Ω) 500 500 500 Figure 55. ADA4950-x with Unbalanced (Single-Ended) Input The input impedance of the circuit is effectively higher than it is for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor, RG. The common-mode voltage at the amplifier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider that is formed by RF and RG in the lower loop. This voltage is present at both input terminals due to negative voltage feedback and is in phase with the input signal, thus reducing the effective voltage across RG in the upper loop and partially bootstrapping RG. Rev. B | Page 20 of 26 Data Sheet ADA4950-1/ADA4950-2 Terminating a Single-Ended Input Figure 57 shows that the effective RG in the upper feedback loop is now greater than the RG in the lower loop due to the addition of the termination resistors. To compensate for the imbalance of the gain resistors, add a correction resistor (RTS) in series with RG in the lower loop. RTS is the Thevenin equivalent of the source resistance, RS, and the termination resistance, RT, and is equal to RS||RT. 3. This section describes how to properly terminate a single-ended input to the ADA4950-x with a gain of 1, RF = 500 Ω, and RG = 500 Ω. An example using an input source with a terminated output voltage of 1 V p-p and source resistance of 50 Ω illustrates the steps that must be followed. Note that because the terminated output voltage of the source is 1 V p-p, the open-circuit output voltage of the source is 2 V p-p. The source shown in Figure 56 indicates this open-circuit voltage. RS The input impedance is calculated using the following formula: VS 2V p-p RG 500 = 667 Ω = RIN , se = 500 RF 1 − 1 − ) 500 500 ( 2 × + ) ( 2 + × R R F G +VS RG 50Ω 500Ω VOCM RF 500Ω +VS ADA4950-x RL VOUT, dm RG VTH 1.03V p-p 500Ω RTH RG 25.5Ω 500Ω VOCM 07957-156 –VS RF 500Ω RTS 25.5Ω 500Ω Figure 59. Thevenin Equivalent and Matched Gain Resistors Figure 59 presents a tractable circuit with matched feedback loops that can be easily evaluated. RF 500Ω +VS RG 500Ω RT 53.6Ω VOCM ADA4950-x RL VOUT, dm RG 500Ω –VS RF 500Ω Figure 57. Adding Termination Resistor, RT 07957-157 VS 2V p-p RS 50Ω 500Ω RF To match the 50 Ω source resistance, calculate the termination resistor, RT, using RT||667 Ω = 50 Ω. The closest standard 1% value for RT is 53.6 Ω. RIN, se 50Ω RL VOUT, dm –VS Figure 56. Calculating Single-Ended Input Impedance, RIN 2. ADA4950-x RG 07957-059 RS VTH 1.03V p-p 25.9Ω Note that VTH is greater than 1 V p-p, which was obtained with RT = 50 Ω. The modified circuit with the Thevenin equivalent (closest 1% value used for RTH) of the terminated source and RTS in the lower feedback loop is shown in Figure 59. RF VS 2V p-p RT 53.6Ω Figure 58. Calculating the Thevenin Equivalent 500Ω RIN, se 667Ω RTH 50Ω 07957-052 1. RTS = RTH = RS||RT = 25.9 Ω It is useful to point out two effects that occur with a terminated input. The first is that the value of RG is increased in both loops, lowering the overall closed-loop gain. The second is that VTH is a little larger than 1 V p-p, as it would be if RT = 50 Ω. These two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops (~1 kΩ), the effects essentially cancel each other out. For small RF and RG, or high gains, however, the diminished closed-loop gain is not canceled completely by the increased VTH. This can be seen by evaluating Figure 59. The desired differential output in this example is 1 V p-p because the terminated input signal is 1 V p-p and the closedloop gain = 1. The actual differential output voltage, however, is equal to (1.03 V p-p)(500/525.5) = 0.98 V p-p. Rev. B | Page 21 of 26 ADA4950-1/ADA4950-2 Data Sheet +VS INPUT COMMON-MODE VOLTAGE RANGE The ADA4950-x input common-mode voltage range is shifted down by approximately one VBE, in contrast to other ADC drivers with centered input ranges such as the ADA4939-x. The downward-shifted input common-mode range is especially suited to dc-coupled, single-ended-to-differential, and singlesupply applications. ×1 250Ω 500Ω ×4 ×1 For ±5 V operation, the input common-mode voltage range at the summing nodes of the amplifier is specified as −4.8 V to +3.2 V. With a 5 V supply, the input common-mode voltage range at the summing nodes of the amplifier is specified as +0.2 V to +3.2 V. To avoid nonlinearities, the voltage swing at the +INx and −INx terminals must be confined to these ranges. ×4 ×1 ×1 ×1 500Ω VOCM ADA4950-x 500Ω ×4 ×1 250Ω 500Ω ×4 Although the ADA4950-x is well suited to dc-coupled applications, it is nonetheless possible to use it in ac-coupled circuits. Input ac coupling capacitors can be inserted between the source and RG. This ac coupling blocks the flow of the dc commonmode feedback current and causes the ADA4950-x dc input common-mode voltage to equal the dc output common-mode voltage. The ac coupling capacitors must be placed in both loops to keep the feedback factors matched. Output ac coupling capacitors can be placed in series between each output and its respective load. INPUT SIGNAL SWING CONSIDERATIONS The input terminals of fully differential amplifiers with external gain and feedback resistors connect directly to the amplifier summing nodes; the common-mode voltage swing at these terminals is generally smaller than the input and output swings. In most linear applications, the summing node voltages do not approach levels that result in the forward-biasing of the internal ESD protection diodes on the amplifier inputs. Signals at the inputs of the ADA4950-x are applied to the input side of the gain resistors, and, if caution is not exercised, these signals can be large enough to forward-bias the ESD protection diodes. The four inputs that make up the differential signal paths each have four ESD diodes in series to the negative supply and one diode to the positive supply; the VOCM input has one ESD diode to each supply. Figure 60 illustrates the ESD protection circuitry. –VS 07957-253 INPUT AND OUTPUT CAPACITIVE AC COUPLING Figure 60. Input ESD Protection Circuitry SETTING THE OUTPUT COMMON-MODE VOLTAGE The VOCM pin of the ADA4950-x is internally biased with a voltage divider comprising two 50 kΩ resistors across the supplies, with a tap at a voltage approximately equal to the midsupply point, [(+VS) + (−VS)]/2. Because of this internal divider, the VOCM pin sources and sinks current, depending on the externally applied voltage and its associated source resistance. Relying on the internal bias results in an output common-mode voltage that is within approximately 100 mV of the expected value. In cases where more accurate control of the output commonmode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 Ω. If an external voltage divider consisting of equal resistor values is used to set VOCM to midsupply with greater accuracy than produced internally, higher values can be used because the external resistors are placed in parallel with the internal resistors. The input VOCM offset listed in the Specifications section assumes that the VOCM input is driven by a low impedance voltage source. It is also possible to connect the VOCM input to a common-mode level (CML) output of an ADC; however, care must be taken to ensure that the output has sufficient drive capability. The input impedance of the VOCM pin is approximately 10 kΩ to a voltage of nominally midsupply. If multiple ADA4950-x devices share one ADC reference output, a buffer may be necessary to drive the parallel inputs. Rev. B | Page 22 of 26 Data Sheet ADA4950-1/ADA4950-2 LAYOUT, GROUNDING, AND BYPASSING As a high speed device, the ADA4950-x is sensitive to the PCB environment in which it operates. Realizing its superior performance requires attention to the details of high speed PCB design. Signal routing should be short and direct to avoid parasitic effects. Wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. When routing differential signals over a long distance, keep PCB traces close together, and twist any differential wiring to minimize loop area. Doing this reduces radiated energy and makes the circuit less susceptible to interference. The first requirement is a solid ground plane that covers as much of the board area around the ADA4950-x as possible. The thermal resistance, θJA, is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in EIA/JESD51-7. 1.30 0.80 Bypass the power supply pins as close to the device as possible and directly to a nearby ground plane. Use high frequency ceramic chip capacitors. It is recommended that two parallel bypass capacitors (1000 pF and 0.1 μF) be used for each supply. Place the 1000 pF capacitor closer to the device. Farther away, provide low frequency bulk bypassing using 10 μF tantalum capacitors from each supply to ground. 07957-056 1.30 0.80 Figure 61. Recommended PCB Thermal Attach Pad (Dimensions in Millimeters) 1.30 TOP METAL GROUND PLANE 0.30 PLATED VIA HOLE 07957-057 POWER PLANE BOTTOM METAL Figure 62. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters) Rev. B | Page 23 of 26 ADA4950-1/ADA4950-2 Data Sheet HIGH PERFORMANCE ADC DRIVING Because the inputs are dc-coupled, dc common-mode current flows in the feedback loops, and a nominal dc level of 0.76 V is present at the amplifier input terminals. A fraction of the output signal is also present at the input terminals as a common-mode signal; its level is equal to the ac output swing at the noninverting output, divided down by the feedback factor of the lower loop. In this example, this ripple is 0.5 V p-p × [276.7/(276.7 + 500)] = 0.18 V p-p. This ac signal is riding on the 0.76 V dc level, producing a voltage swing between 0.67 V and 0.85 V at the input terminals. This is well within the specified limits of 0.2 V to 1.5 V. The ADA4950-x is ideally suited for broadband dc-coupled applications. The circuit in Figure 63 shows a front-end connection for an ADA4950-1 driving an AD9245 ADC, with dc coupling on the ADA4950-1 input and output. (The AD9245 achieves its optimum performance when driven differentially.) The ADA4950-1 eliminates the need for a transformer to drive the ADC and performs a single-ended-todifferential conversion and buffering of the driving signal. The ADA4950-1 is configured with a single 3.3 V supply and a gain of 2 for a single-ended input to differential output. The 57.6 Ω termination resistor, in parallel with the single-ended input impedance of 375 Ω, provides a 50 Ω termination for the source. The additional 26.7 Ω Thevenin resistance added to the inverting input balances the parallel impedance of the 50 Ω source and the termination resistor driving the noninverting input. The required Thevenin bias voltage of 0.27 VDC applied to the lower loop is obtained by scaling the VREF output of the AD9245 and buffering it with the AD8031. With an output common-mode voltage of 1.65 V, each ADA4950-1 output swings between 1.4 V and 1.9 V, opposite in phase, providing a gain of 2 and a 1 V p-p differential signal to the ADC input. The differential RC section between the ADA4950-1 output and the ADC provides single-pole low-pass filtering and extra buffering for the current spikes that are output from the ADC input when its SHA capacitors are discharged. The AD9245 is configured for a 1 V p-p full-scale input by connecting its SENSE pin to VREF, as shown in Figure 63. In this example, the 50 Ω signal generator has a 1 V p-p unipolar open-circuit output voltage, and 0.5 V p-p output voltage when terminated in 50 Ω. The VOCM input is bypassed for noise reduction and set externally with 1% resistors to maximize output dynamic range on the tight 3.3 V supply. +3.3V VOUT, dm = 1V p-p VOUT, cm = +1.65V 1.0V 50Ω 0.5V 1.0V p-p UNIPOLAR SIGNAL SOURCE 0.1µF 0.1µF 500Ω 0.1µF 57.6Ω 10kΩ NC 500Ω VOCM 10kΩ NC ADA4950-1 20pF AD9245 33Ω 500Ω AVDD VIN– 33Ω VIN+ VREF SENSE 250Ω AGND 500Ω 0.1µF 26.7Ω 10µF + 866Ω 0.1µF 0.1µF 10µF + 0.1µF 1.0kΩ AD8031 07957-254 0V 250Ω Figure 63. ADA4950-1 Driving an AD9245 ADC with Unipolar DC-Coupled Input and Output, Gain = 2 Rev. B | Page 24 of 26 Data Sheet ADA4950-1/ADA4950-2 OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 PIN 1 INDICATOR 0.30 0.23 0.18 13 0.50 BSC PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.45 1.30 SQ 1.15 4 9 0.80 0.75 0.70 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 111808-A TOP VIEW 5 8 0.50 0.40 0.30 COMPLIANT TO JEDEC STANDARDS MO-220-WEED. Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-21) Dimensions shown in millimeters 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 0.50 BSC 24 19 18 PIN 1 INDICATOR 1 2.40 2.30 SQ 2.20 EXPOSED PAD 6 13 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 12 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.30 0.25 0.20 7 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 01-18-2012-A TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. Figure 65. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-14) Dimensions shown in millimeters ORDERING GUIDE Model1 ADA4950-1YCPZ-R2 ADA4950-1YCPZ-RL ADA4950-1YCPZ-R7 ADA4950-1YCP-EBZ ADA4950-2YCPZ-R2 ADA4950-2YCPZ-RL ADA4950-2YCPZ-R7 ADA4950-2YCP-EBZ 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ Evaluation Board 24-Lead LFCSP_WQ 24-Lead LFCSP_WQ 24-Lead LFCSP_WQ Evaluation Board Z = RoHS Compliant Part. Rev. B | Page 25 of 26 Package Option CP-16-21 CP-16-21 CP-16-21 Ordering Quantity 250 5,000 1,500 CP-24-14 CP-24-14 CP-24-14 250 5,000 1,500 Branding H1L H1L H1L ADA4950-1/ADA4950-2 Data Sheet NOTES ©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07957-0-10/15(B) Rev. B | Page 26 of 26