CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL Static RAM Functional Description[1] Features • Temperature Ranges — Industrial: –40°C to 85°C The CY62157DV30 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). — Automotive: –40°C to 125°C (Preliminary) • Very high speed: 45 ns, 55 ns and 70 ns • Wide voltage range: 2.20V – 3.60V • Pin-compatible with CY62157CV25, CY62157CV30, and CY62157CV33 • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz — Typical active current: 12 mA @ f = fmax • Ultra-low standby power Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). • Easy memory expansion with CE1, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Packages offered: 48-ball BGA, 48-pin TSOPI, and 44-pin TSOPII Logic Block Diagram Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes. 512K × 16 RAM Array SENSE AMPS ROW DECODER DATA-IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 BHE WE OE CE2 CE1 BLE Power-down Circuit Notes: 1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05392 Rev. *E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 24, 2004 CY62157DV30 MoBL® Product Portfolio Power Dissipation Operating ICC, (mA) VCC Range (V) f = 1MHz f = fmax Standby ISB2, (µA) Min. Typ.[2] Max. Speed (ns) Typ.[2] Max. Typ.[2] Max. Typ.[2] Max. Industrial 2.2 3.0 3.6 45, 55, 70 1.5 3 12 20 2 20 CY62157DV30LL Industrial 2.2 3.0 3.6 45, 55, 70 1.5 3 12 15 2 8 2.2 3.0 3.6 55 1.5 3 12 20 2 50 Product CY62157DV30L CY62157DV30L Range Automotive[3] Pin Configuration[4, 5, 6, 7] op FBGA e 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H 48TSOPI 44 TSOP II Top View A15 A14 A13 A12 A11 A10 A9 A8 NC DNU WE CE2 DNU BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Top View 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss I/O15/A19 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13 Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 3. Automotive data is PRELIMINARY. Shaded areas of the datasheet contain PRELIMINARY information. 4. NC pins are not internally connected on the die. 5. DNU pins have to be left floating. 6. The BYTE pin in the 48-TSOPI package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOPI package can also be used as a 1M × 8 SRAM by tying the BYTE signal LOW. For 1M × 8 Functionality, please refer to the CY62158DV30 datasheet. In the 1M × 8 configuration, Pin 45 is A19. 7. The 44-TSOPII package device has only one chip enable pin (CE). Document #: 38-05392 Rev. *E Page 2 of 12 CY62157DV30 MoBL® Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................ –55°C to + 125°C Supply Voltage to Ground Potential ......................................... –0.3V to + VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State[8, 9] ............................ –0.3V to VCC(max) + 0.3V DC Input Voltage[8, 9] ........................–0.3V to VCC(max) + 0.3V Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Device Range CY62157DV30L Industrial Ambient Temperature (TA) VCC[10] –40°C to +85°C CY62157DV30LL CY62157DV30L Automotive –40°C to +125°C (Preliminary) 2.20V to 3.60V Electrical Characteristics Over the Operating Range CY62157DV30 Parameter Description Test Conditions VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VCC = 2.2V to 2.7V VIL Input LOW Voltage VCC= 2.7V to 3.6V IIX Input Leakage Current GND < VI < VCC IOH = –0.1 mA Min. VCC = 2.20V 2.0 IOH = –1.0 mA VCC = 2.70V 2.4 IOL = 0.1 mA VCC = 2.20V IOL = 2.1mA VCC = 2.70V Typ.[2] V V 0.4 V 0.4 V VCC + 0.3V V VCC= 2.7V to 3.6V 2.2 VCC + 0.3V V VCC = 2.2V to 2.7V –0.3 0.6 V –0.3 0.8 V Industrial –1 +1 µA Automotive -4 +4 µA Industrial –1 +1 µA Automotive VCC = VCCmax L IOUT = 0 mA LL CMOS levels -4 Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current f = fMAX = 1/tRC f = 1 MHz L 12 1.5 LL ISB2 Unit 1.8 IOZ ISB1 Max. Automatic CE Power-Down Current — CMOS Inputs CE1 > VCC−0.2V, CE2< 0.2V Industrial VIN>VCC–0.2V, VIN<0.2V) f = fMAX (Address and Data Automotive Only), f = 0 (OE, WE, BHE and BLE), VCC=3.60V Automatic CE Power-Down Current — CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V Industrial Automotive +4 µA 20 mA 15 mA 3 mA 3 mA µA L 2 20 LL 2 8 L 50 L 2 20 LL 2 8 L µA 50 Notes: 8. VIL(min.) = –2.0V for pulse durations less than 20 ns. 9. VIH(max)= VCC+0.75V for pulse duration less than 20 ns. 10. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. Document #: 38-05392 Rev. *E Page 3 of 12 CY62157DV30 MoBL® Capacitance[11, 12] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 10 pF 10 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance[11] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board BGA TSOP II TSOP I Unit 72 75.13 74.88 °C/W 8.86 8.95 8.6 °C/W AC Test Loads and Waveforms[13] VCC OUTPUT R1 30 pF / 50 pF VCC GND R2 10% ALL INPUT PULSES 90% 90% 10% Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters 2.50V 3.0V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[11] Chip Deselect to Data Retention Time tR[14] Operation Recovery Time Conditions Min. Typ.[2] Max. 1.5 VCC= 1.5V CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V V Industrial (L) 10 Industrial (LL) 4 Automotive (L) Unit µA 25 0 ns tRC ns Notes: 11. Tested initially and after any design or process changes that may affect these parameters. 12. The input capacitance on the CE2 pin of the FBGA and 48TSOPI packages and on the BHE pin of the 44TSOPII package is 15 pF. 13. Test condition for the 45 ns part is a load capacitance of 30 pF. 14. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 us or stable at VCC(min.) > 100 us. Document #: 38-05392 Rev. *E Page 4 of 12 CY62157DV30 MoBL® Data Retention Waveform[15] DATA RETENTION MODE VDR > 1.5 V VCC, min. tCDR VCC VCC, min. tR CE1 or BHE.BLE or CE2 Switching Characteristics Over the Operating Range [16] 45 ns [13] Parameter Min. Description Max. 55 ns Min. 70 ns Max. Min. Max. Unit 70 ns Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 45 55 45 10 tDOE OE LOW to Data Valid tLZOE OE LOW to LOW Z[17] tHZOE OE HIGH to High Z[17, 18] tLZCE CE1 LOW and CE2 HIGH to Low Z[17] 10 45 15 35 5 20 10 ns ns 25 10 ns ns CE1 HIGH and CE2 LOW to High tPU CE1 LOW and CE2 HIGH to Power-Up tPD CE1 HIGH and CE2 LOW to Power-Down 45 55 70 ns tDBE BLE / BHE LOW to Data Valid 45 55 70 ns 25 ns tLZBE BLE / BHE LOW to Low tHZBE BLE / BHE HIGH to HIGH Z[17, 18] 0 20 ns tHZCE Z[17] 20 ns 70 25 5 10 ns 10 55 25 5 Z[17, 18] 70 55 0 10 10 15 25 0 ns 10 20 ns ns Write Cycle[19] tWC Write Cycle Time 45 55 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 40 40 60 ns tAW Address Set-up to Write End 40 40 60 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 35 40 45 ns tBW BLE / BHE LOW to Write End 40 40 60 ns tSD Data Set-up to Write End 25 25 30 ns tHD Data Hold from Write End 0 0 0 ns tHZWE WE LOW to High-Z[17, 18] tLZWE WE HIGH to Low-Z[17] 15 10 20 10 25 10 ns ns Notes: 15. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 16. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedence state. 19. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05392 Rev. *E Page 5 of 12 CY62157DV30 MoBL® Switching Waveforms Read Cycle 1 (Address Transition Controlled)[20, 21] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle 2 (OE Controlled) [21, 22] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tLZBE tDBE tHZBE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tHZOE HIGH IMPEDANCE DATA VALID tLZCE SUPPLY CURRENT tPU 50% 50% ICC ISB Notes: 20. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 21. WE is HIGH for read cycle. 22. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05392 Rev. *E Page 6 of 12 CY62157DV30 MoBL® Switching Waveforms (continued) Write Cycle 1 (WE Controlled) [19, 23, 24, 25] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA See note 24 tHZOE Write Cycle 2 (CE1 or CE2 Controlled) [19, 23, 24, 25] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA See note 24 tHZOE Notes: 23. Data I/O is high impedance if OE = VIH. 24. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 25. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05392 Rev. *E Page 7 of 12 CY62157DV30 MoBL® Switching Waveforms (continued) [24, 25] Write Cycle 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tHA tAW tSA tPWE WE tHD tSD DATA I/O See note 24 VALID DATA tLZWE tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[24, 25] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O See note 24 Document #: 38-05392 Rev. *E tHD VALID DATA Page 8 of 12 CY62157DV30 MoBL® Truth Table CE1 CE2 WE OE BHE BLE Inputs/Outputs Mode Power H X X X X X High Z Deselect/Power-Down Standby (ISB) X L X X X X High Z Deselect/Power-Down Standby (ISB) X X X X H H High Z Deselect/Power-Down Standby (ISB) L H H L L L Data Out (I/O0 – I/O15) Read (Upper byte and Lower Byte) Active (ICC) L H H L H L Data Out (I/O0 – I/O7); Read (Lower Byte only) High Z (I/O8 – I/O15) Active (ICC) L H H L L H High Z (I/O0 – I/O7); Read (Upper Byte only) Data Out (I/O8 – I/O15) Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H L X L L Data In (I/O0 – I/O15) Write(Upper byte and Lower Byte) Active (ICC) L H L X H L Data In (I/O0 – I/O7); High Z (I/O8 – I/O15) Write (Lower Byte only) Active (ICC) L H L X L H High Z (I/O0 – I/O7); Data In (I/O8 – I/O15) Write (Upper Byte only) Active (ICC) Ordering Information Speed (ns) 45 45 45 55 55 55 55 55 55 55 55 70 70 70 Ordering Code CY62157DV30L-45BVI CY62157DV30LL-45BVI CY62157DV30L-45ZXI CY62157DV30LL-45ZXI CY62157DV30L-45ZSXI CY62157DV30LL-45ZSXI CY62157DV30L-55BVI CY62157DV30LL-55BVI CY62157DV30L-55BVXI CY62157DV30LL-55BVXI CY62157DV30L-55BVE CY62157DV30L-55ZXI CY62157DV30LL-55ZXI CY62157DV30L-55ZXE CY62157DV30L-55ZSXI CY62157DV30LL-55ZSXI CY62157DV30L-55ZSXE CY62157DV30L-55ZSI CY62157DV30LL-55ZSI CY62157DV30L-70BVI CY62157DV30LL-70BVI CY62157DV30L-70BVXI CY62157DV30LL-70BVXI CY62157DV30L-70ZXI CY62157DV30LL-70ZXI Document #: 38-05392 Rev. *E Package Name Package Type BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) Operating Range Industrial Z-48 48-pin TSOP I (Pb-free) Industrial ZS-44 44-pin TSOP II (Pb-free) Industrial BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) Industrial BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) (Pb-free) Industrial BV48A Z-48 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) 48-pin TSOP I (Pb-free) Automotive Industrial Z-48 ZS-44 48-pin TSOP I (Pb-free) 44-pin TSOP II (Pb-free) Automotive Industrial ZS-44 ZS-44 44-pin TSOP II (Pb-free) 44-pin TSOP II Automotive Industrial BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) Industrial BV48A 48-ball Fine Pitch BGA (6 mm × 8 mm × 1 mm) (Pb-free) Industrial 48-pin TSOP I (Pb-free) Industrial Z-48 Page 9 of 12 CY62157DV30 MoBL® Ordering Information (continued) Speed (ns) 70 70 Ordering Code CY62157DV30L-70ZSXI CY62157DV30LL-70ZSXI CY62157DV30L-70ZSI CY62157DV30LL-70ZSI Package Name Package Type ZS-44 44-pin TSOP II (Pb-free) ZS-44 44-pin TSOP II Operating Range Industrial Industrial Package Diagrams 48-ball (6.0 mm × 8.0 mm × 1.0 mm) Fine Pitch BGA BV48A 51-85150-*B Document #: 38-05392 Rev. *E Page 10 of 12 CY62157DV30 MoBL® Package Diagrams (continued) DIMENSIONS IN INCHES[MM] MIN. 48-Lead TSOP I (12 mm x 18.4 mm x 1.0 mm) Z48A MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] N 1 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.002[0.05] 0.006[0.15] 0.724 [18.40] 0.047[1.20] MAX. SEATING PLANE 0.004[0.10] 0.787[20.00] 0.004[0.10] 0.008[0.21] 0.010[0.25] GAUGE PLANE 0°-5° 0.020[0.50] 0.028[0.70] 51-85183-*A 44-Pin TSOP II ZS44 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05392 Rev. *E Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62157DV30 MoBL® Document History Page Document Title:CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL Static RAM Document Number: 38-05392 REV. ECN NO. Issue Date ** 126316 05/22/03 *A 131013 11/19/03 Orig. of Change HRT Description of Change New Data Sheet CBD/LDZ Change from Advance to Preliminary *B 133115 01/24/04 CBD Minor Change: Change MPN and upload. *C 211601 See ECN AJU Change from Preliminary to Final Changed Marketing part number from CY62157DV to CY62157DV30 in the title and in the Ordering Information table Added footnotes 4, 5 and 11 Modified footnote 8 to include ramp time and wait time Removed MAX value for VDR on Data Retention Characteristics table Changed ordering code for Pb-free parts Modified voltage limits in Maximum Ratings section *D 236628 See ECN *E 257349 See ECN Document #: 38-05392 Rev. *E SYT/AJU Added 45-ns and 70-ns Speed Bins Added Automotive product information PCI Added test condition for 45 ns part (footnote #13 on page 4) Page 12 of 12