ct du ro LP EO HM5316123B Series Preliminary 131,072-word × 16-bit Multiport CMOS Video RAM E0160H10 (Ver. 1.0) (Previous ADE-203-266 (Z)) Jun. 14, 2001 The HM5316123B is a 2-Mbit multiport video RAM equipped with a 128-kword × 16-bit dynamic RAM and a 256-word × 16-bit SAM (full-sized SAM). Its RAM and SAM operate independently and asynchronously. The HM5316123B has compatibility with the HM5316123. Features • Multiport organization Asynchronous and simultaneous operation of RAM and SAM capability RAM: 128-kword × 16-bit SAM: 256-word × 16-bit • Access time RAM: 70 ns/80 ns/100 ns (max) SAM: 20 ns/23 ns/25 ns (max) • Cycle time RAM: 130 ns/150 ns/180 ns (min) SAM: 25 ns/28 ns/30 ns (min) • Low power Active RAM: 660 mW/605 mW/550 mW SAM: 468 mW/413 mW/385 mW Standby 38.5mW (max) • Masked-write-transfer cycle capability • Stopping column feature capability • Persistent mask capability • Byte write control capability: 2WE control • Fast page mode capability Cycle time: 45ns/50ns/55ns Power RAM: 688 mW/660 mW/633 mW • Mask write mode capability • Bidirectional data transfer cycle between RAM and SAM capability • Split transfer cycle capability • Block write mode capability • Flash write mode capability • 3 variations of refresh (8 ms/512 cycles) –RAS-only refresh –CAS-before-RAS refresh –Hidden refresh • TTL compatible Ordering Information Type No. Access time Package ——————————————————————— HM5316123BF-7 70ns 64-pin plastic —————————————— shrink SOP HM5316123BF-8 80ns (FP-64DS) —————————————— HM5316123BF-10 100ns ——————————————————————— Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice. Elpida Memory, Inc. is a joint venture DRAM company of NEC corporation and Hitachi, Ltd. ct du ro LP EO HM5316123B Series Pin Arrangement Pin Description HM5316123BF Series VCC DT/DE VSS SI/O0 I/O0 SI/O1 I/O1 VCC SI/O2 I/O2 SI/O3 I/O3 VSS SI/O4 I/O4 SI/O5 I/O5 VCC SI/O6 I/O6 SI/O7 I/O7 VSS WEL WEU RAS A8 A7 A6 A5 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SC SE VSS SI/O15 I/O15 SI/O14 I/O14 VCC SI/O13 I/O13 SI/O12 I/O12 VSS SI/O11 I/O11 SI/O10 I/O10 VCC SI/O9 I/O9 SI/O8 I/O8 VSS DSF1 DSF2 CAS QSF A0 A1 A2 A3 VSS Symbol Function ——————————————————————– A0 – A8 Address inputs ——————————————————————– I/O0 – I/O15 RAM port data inputs/outputs ——————————————————————– SI/O0 – SI/O15 SAM port data inputs/outputs ——————————————————————– RAS Row address strobe ——————————————————————– CAS Column address strobe ——————————————————————– WEU Upper byte write enable ——————————————————————– WEL Lower byte write enable ——————————————————————– DT/OE Date transfer/output enable ——————————————————————– SC Serial clock ——————————————————————– SE SAM port enable ——————————————————————– DSF1, DSF2 Special function input flag ——————————————————————– QSF Special function output flag ——————————————————————– VCC Power Supply ——————————————————————– VSS Ground ——————————————————————– (Top View) 2 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Block Diagram A0 – A8 A0 – A8 Row Address Buffer Refresh Counter 0 Data Register Serial Output Buffer Color Resister Serial Input Buffer SI/O0 – SI/O15 Input Buffer Output Buffer Timing Generator Preliminary Data Sheet E0160H10 WEU/WEL DSF1/DSF2 SC SE I/O0 – I/O15 RAS CAS DT/OE Mask Register Input Data Control Address Mask Register Transfer Gate 511 Transfer Gate Data Register Sense Amplifier & I/O Bus Column Decoder Block Write Flash Write Control Control 0 255 Memory Array QSF SAM Column Decoder Serial Address Counter Row Decoder SAM I/O Bus A0 – A7 Column Address Buffer 3 ct du ro LP EO HM5316123B Series Pin Functions RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of RAS. The input level of these signals determine the operation cycle of the HM5316123B. Table 1. Operation Cycles of the HM5316123B RAS CAS Address I/On Input Mnemonic ———————————————— ——————— —————— —————————— Code CAS DT/OE WE DSF1 DSF2 DSF1 DSF2 RAS CAS RAS CAS/WE ———————————————————————————————————————————————– CBRS 0 — 0 1 0 — 0 Stop — — — ———————————————————————————————————————————————– CBRR 0 — 1 0 0 — 0 — — — — ———————————————————————————————————————————————– CBRN 0 — 1 1 0 — 0 — — — — ———————————————————————————————————————————————– MWT 1 0 0 0 0 — 0 Row TAP WN — ———————————————————————————————————————————————– MSWT 1 0 0 1 0 — 0 Row TAP WM — ———————————————————————————————————————————————– RT 1 0 1 0 0 — 0 Row TAP — — ———————————————————————————————————————————————– SRT 1 0 1 1 0 — 0 Row TAP — — ———————————————————————————————————————————————– RWM 1 1 0 0 0 0 0 Row Column WM Input data ———————————————————————————————————————————————– Register Mnemonic Write Pers ———————– No.of Code Mask W.M. WM Color Bndry Function ———————————————————————————————————————————————– CBRS — — — — Set CBR refresh with stop resister set ———————————————————————————————————————————————– CBRR — Reset Reset — Reset CBR refresh with register reset ———————————————————————————————————————————————– CBRN — — — — — CBR refresh (no reset) ———————————————————————————————————————————————– MWT Yes No Load/use — — Mask write transfer (new/old mask) Yes Use ———————————————————————————————————————————————– MSWT Yes No Load/use — Use Masked split write transfer (new/old mask) Yes Use ———————————————————————————————————————————————– RT — — — — — Read transfer ———————————————————————————————————————————————– SRT — — — — Use Split read transfer ———————————————————————————————————————————————– RWM YES No Load/use — — Road/write (new/old mask) Yes Use ———————————————————————————————————————————————– 4 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Table 1. Operation Cycles of the HM5316123B (cont) Mnemonic RAS CAS Address I/On Input ———————————————— —————— —————— —————————– Code CAS DT/OE WE DSF1 DSF2 DSF1 DSF2 RAS CAS RAS CAS/WE ———————————————————————————————————————————————– BWM 1 1 0 0 0 1 0 Row Column WM Column Mask ———————————————————————————————————————————————– RW (No) 1 1 1 0 0 0 0 Row Column — Input data ———————————————————————————————————————————————– BW (No) 1 1 1 0 0 1 0 Row Column — Column Mask ———————————————————————————————————————————————– FWM 1 1 0 1 0 — 0 Row — WM — ———————————————————————————————————————————————– LMR and 1 1 1 1 0 0 0 (Row) — — Mask Old Mask Set Data ———————————————————————————————————————————————– LCR 1 1 1 1 0 1 0 (Row) — — Color ———————————————————————————————————————————————– Option 0 0 0 0 0 — 0 Mode — Data — ———————————————————————————————————————————————– Register Mnemonic Write Pers ——————— No.of Code Mask W.M. WM Color Bndry Function ———————————————————————————————————————————————– BWM Yes No Load/use Block write (new/old mask) Yes Use Use — ———————————————————————————————————————————————– RW (No) No No — — — Read/write (no mask) ———————————————————————————————————————————————– BW (No) No No — Use — Block write (no mask) ———————————————————————————————————————————————– FWM Yes No Load/use Use — Masked flash write (new/old mask) Yes Use ———————————————————————————————————————————————– LMR and — Set Load — — Load mask register and old mask set Old Mask Set ———————————————————————————————————————————————– LCR — — — Load — Load color resister set ———————————————————————————————————————————————– Option — — — — — — ———————————————————————————————————————————————– Notes: 1. With CBRS, all SAM operations use stop register. 2. After LMR, RWM, BWM, FWM, MWT, and MSWT, use old mask which can be reset by CBRR. 3. DSF2 is fixed low in all operation. (for the addition of operation mode in future) Preliminary Data Sheet E0160H10 5 ct du ro LP EO HM5316123B Series CAS (input pin): Column address and DSF1 signals are fetched into chip at the falling edge of CAS, which determines the operation mode of the HM5316123B. CAS controls output impedance of I/O in RAM. A0 – A8 (input pins): Row address (AX0 – AX8) is determined by A0 – A8 level at the falling edge of RAS. Column address (AY0 – AY7) is determined by A0 – A7 level at the falling edge of CAS. In transfer cycles, row address is the address on the word line which transfers data with SAM data register, and column address is the SAM start address after transfer. WEU and WEL (Input pins): WEU and WEL pins have two functions at the falling edge of RAS and after. When either WEU or WEL is low at the falling edge of RAS, the HM5316123B turns to mask write mode. According to the I/O level at the time, write on each I/O can be masked. (WEU and WEL levels at the falling edge of RAS is don’t care in read cycle.) When both WEU and WEL are high at the falling edge of RAS, a no mask write cycle is executed. After that, WEU and WEL switch read/write cycles. Both WEU and WEL must be held high in a read cycle. In a transfer cycle, the direction of transfer is determined by WEU and WEL levels at the falling edge of RAS. When either WEU or WEL is low, data is transferred from SAM to RAM (data is written into RAM), and when both WEU and WEL are high, data is transferred from RAM to SAM (data is read from RAM). I/O0 – I/O15 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained. After that, they function as inut/output pins as those of a standard DRAM. In block write cycle, they function as column mask data at the falling edges of CAS, and WEU or WEL. 6 DT/OE (input pin): DT/OE pin functions as DT (data transfer) pin at the falling edge of RAS and as OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently. SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into the SAM data register. SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a mask for serial write because the internal pointer is incremented at the rising edge of SC. SI/O0 – SI/O15 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was a masked write transfer cycle, SI/O inputs data. DSF1 (input pin): DSF1 is a special function data input flag pin. It is set to high at the falling edge of RAS when new functions such as color register and mask register read/write, split transfer, and flash write, are used. DSF2 (input pin): DSF2 is also a special function data input flag pin. This pin is fixed to low level in all operations of the HM5316123B. QSF (output pin): QSF outputs data of address A7 in SAM. QSF is switched from low to high by accessing address 127 in SAM and from high to low by accessing address 255 in SAM. Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Operation of HM5316123B RAM Port Operation RAM Read Cycle (DT/OE high, CAS high and DSF1 low at the falling edge of RAS, DSF1 low at the falling edge of CAS) Row address is entered at the RAS falling edge and column address at the CAS falling edge to the device as in standard DRAM. Then, when WEU or WEL is high and DT/OE is low while CAS is low, the selected address data outputs through I/O pin. At the falling edge of RAS, DT/OE and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address access time (t AA ) and RAS to column address delay time (t RAD ) specifications are added to enable fast page mode. RAM Write Cycle (Eraly Write, Delayed Write, Read-Modify-Write) (DT/OE high, CAS high and DSF1 low at the falling edge of RAS, DSF1 low at the falling edge of CAS) • No Mask Write Cycle (WEU and WEL high at the falling edge of RAS) When CAS is set low and either WEU or WEL is set low after RAS low, a write cycle is executed. If either WEU or WEL is set low before the CAS falling edge, this cycle becomes an early write cycle and all I/O become in high impedance. All 16 data are latched on the falling edge of CAS. If only one of WEU and WEL is low when CAS falls, the write will affect only those corresponding 8 bits. If the other of WEU and WEL falls at the same time in the cycle, the write will then occur for those 8 bits, with the latched data. If both WEU and WEL are set low after the CAS falling edge, this cycle becomes a delayed write cycle and all 16 data are latched on the falling edge of WEU or WEL. Byte write occures if only one of WEU or WEL falls during the cycle. I/O does not become high impedance in this cycle, so data should be entered with OE in high. If both WEU and WEL are set low after tCWD (min) and tAWD (min) after the CAS falling edge, this cycle becomes a read-modify-write cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O contention, data should be input after reading data and driving OE high. • Mask Write Mode (WEU or WEL low at the falling edge of RAS) If WEU or WEL is set low at the falling edge of RAS, two modes of mask write cycle are capable. 1. In new mask mode, mask data is loaded from I/O pin and used. Whether or not an I/O is written depends on I/O level at the falling edge of RAS. The data is written in high level I/Os, and the data is masked and retained in low level I/Os. This mask data is effective during the RAS cycle. So, in page mode cycles the mask data is retained during the page access. 2. If a load mask register cycle (LMR) has been performed, the mask data is not loaded from I/O pins and the mask data stored in mask registers persistently are used. This operation is known as persistent write mask, set by LMR cycle and reset by CBRR cycle. Fast Page Mode Cycle (DT/OE high, CAS high and DSF1 low at the falling edge of RAS) High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while RAS is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and block write cycles can be mixed. Note that address access time (tAA), RAS to column address delay time (tRAD), and access time from CAS precharge (tACP) are added. In one RAS cycle, 256-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 µs). Preliminary Data Sheet E0160H10 7 ct du ro LP EO HM5316123B Series Color Register Set/Read Cycle (CAS high, DT/OE high, WEU and WEL high and DSF1 high at the falling edge of RAS) In color register set cycle, color data is set to the internal color register used in flash write cycle or block write cycle. 16 bits of internal color register are provided at each I/O. This register is composed of static circuits, so once it is set, it retains the data until reset. Since color register set cycle is just as same as the usual write cycle, so read, early write and delayed write cycle can be executed. In this cycle, the HM5316123B refreshes the row address fetched at the falling edge of RAS. Mask Register Set/Read Cycle (CAS high, DT/OE high, WEU and WEL high, and DSF1 high at the falling edge of RAS) In mask register set cycle, mask data is set to the internal mask register used in mask write cycle, block write cycle, flash write cycle, masked write transfer, and masked split write transfer. 16 bits of internal mask register are provided at each I/O. This mask register is composed of static circuits, Color Register Set Cycle so once it is set, it retains the data until reset. Since mask register set cycle is just as same as the usual read and write cycle, so read, early and delayed write cycles can be executed. Flash Write Cycle (CAS high, DT/OE high, WEU or WEL low, and DSF1 high at the falling edge of RAS) In a flash write cycle, a row of data (256 word x 16 bit) is cleared to 0 or 1 at each I/O according to the data of color register mentioned before. It is also necessary to mask I/O in this cycle. When CAS and DT/OE is set high, WEU or WEL is low, and DSF1 is high at the falling edge of RAS, this cycle starts. Then, the row address to clear is given to row address. Mask data is as same as that of a RAM write cycle. Cycle time is the same as those of RAM read/write cycles, so all bits can be cleared in 1/256 of the usual cycle time. (See figure 1.) Flash Write Cycle Flash Write Cycle RAS CAS Address Row Xi Xj WEU,WEL DT/OE DSF1 I/O Color Data Set color register *1 *1 Execute flash write into each I/O on row address Xi using color register. Note: 1. I/O Mask Data (In new mask mode) Low: Mask High: Non Mask In persistent mask mode, I/O don't care Figure 1 Use of Flash Write 8 Preliminary Data Sheet E0160H10 Execute flash write into each I/O on row address Xj using color register. ct du ro LP EO HM5316123B Series Block Write Cycle (CAS high, DT/OE high and DSF1 low at the falling edge of RAS, DSF1 high and WEU or WEL low at the falling edge of CAS) In a block write cycle, 4 columns of data (4 column x 16 bit) are cleared to 0 or 1 at each I/O according to the data of color register. Column addresses A0 and A1 are disregarded. The mask data on I/Os and the mask data on column addresses can be determined independently. I/O level at the falling edge of CAS determines the address to be cleared. (See Figure 2.) The block write cycle is as the same as the usual write cycle, so early and delayed write, read-modify-write, and page mode write cycle can be executed. • No mask Mode Block Write Cycle (WEU and WEL high at the falling edge of RAS) The data on 16 I/Os are all cleared when WEU and WEL are high at the falling edge of RAS. • Mask Block Write Cycle (WEU or WEL low at the falling edge of RAS) When either WEU or WEL is low at the falling edge of RAS, the HM5316123B starts mask block write cycle to clear the data on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. In new mask mode, the mask data is available in the RAS cycle. In persistent mask mode, I/O don't care about mask mode. • Column Mask (WEU or WEL low at the falling edge of CAS) Column mask data is determined by 4I/Os (I/O0, I/O1, I/O2, I/O3) level at CAS low and WEU or WEL low edge. When upper byte column mask is performed by WEL high and WEU low, column mask data are determined by 4I/Os (I/O0, I/O1, I/O2, I/O3) and other I/Os (I/O4 to I/O15) don't care. Preliminary Data Sheet E0160H10 9 ct du ro LP EO HM5316123B Series Color Register Set Cycle Block Write Cycle Block Write Cycle RAS CAS Address Row Row Column A2–A7 *1 WEU, WEL Row Column A2–A7 *1 DT/OE DSF1 Color Data I/O Column Mask *1 *1 *1 WEU, WEL Either Low Both High Mode New mask mode Persistent mask mode No mask I/O data/RAS Mask H or L (mask register used) H or L I/O Mask Data (In new mask mode) Low: Mask High: Non Mask In persistent mask mode, I/O don't care Column Mask Data I/O0 I/O1 I/O2 I/O3 Column0 (A0 = 0, A1 = 0) Mask Data Column1 (A0 = 1, A1 = 0) Mask Data Column2 (A0 = 0, A1 = 1) Mask Data Column3 (A0 = 1, A1 = 1) Mask Data Low: Mask High: Non Mask Figure 2 Use of Block Write 10 Preliminary Data Sheet E0160H10 Column Mask ct du ro LP EO HM5316123B Series Transfer Operation The HM5316123B provides the read transfer cycle, split read transfer cycle, masked write transfer cycle and masked split write transfer cycle as data transfer cycles. Theses transfer cycles are set by driving CAS high and DT/OE low at the falling edge of RAS. They have following functions: (1) Transfer data between row address and SAM data register Read transfer cycle and split read transfer cycle: RAM to SAM Masked write transfer cycle and masked split write transfer cycle: SAM to RAM (2) Determine SI/O state (except for split read transfer cycle and masked split write transfer cycle) Read transfer cycle: SI/O output Masked write transfer cycle: SI/O input (3) Determine first SAM address to access after transferring at column address (SAM start address). SAM start address must be determined by read transfer cycle or masked write transfer cycle (split transfer cycle isn’t available)before SAM access, after power on, and determined for each transfer cycle. (4) Use the stopping columns (boundaries) in the serial shift register. If the stopping columns have been set, split transfer cycles use the stopping columns, but any boundaries cannot be set as the start address. (5) Load/use mask data in masked write transfer cycle and masked split write transfer cycle. Read Transfer Cycle (CAS high, DT/OE low, WEU and WEL high and DSF1 low at the falling edge of RAS) This cycle becomes read transfer cycle by driving DT/OE low, WEU and WEL high and DSF1 low at the falling edge of RAS. The row address data (256 x 16 bits) determined by this cycle is transferred to SAM data register synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs from SAM start address determined by column address. In read transfer cycle, DT/OE must be risen to transfer data from RAM to SAM. This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min) specified between the last SAM access before transfer and DT/OE rising edge and tSDH (min) specified between the first SAM access and DT/OE rising edge must be satisfied. (See figure 3.) When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high impedance before tSZS (min) of the first SAM access to avoid data contention. RAS CAS Address DT/OE DSF1 Xi Yj L t SDD t SDH SC Yj SI/O SAM Data before Transfer Yj + 1 SAM Data after Transfer Figure 3 Real Time Read Transfer Preliminary Data Sheet E0160H10 11 ct du ro LP EO HM5316123B Series Masked Write Transfer cycle (CAS high, DT/OE low, WEU or WEL low, and DSF1 low at the falling edge of RAS) Masked write transfer cycle can transfer only selected I/O data in a row of data input by serial write cycle to RAM. Whether one I/O data is transferred or not depends on the corresponding I/O level (mask data) at the falling edge of RAS. This mask transfer operation is the same as a mask write operation in RAM cycles, so the persistent mode can be supported. The row address of data transferred into RAM is determined by the address at the falling edge of RAS. The column address is specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access becomes enabled after tSRD (min) after RAS becomes high. SAM access is inhibited during RAS low. In this period, SC must bot be risen. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addreses of RAM by write transfer cycle. However, the adddress to write data must be the same as that of the read transfer cycle or the split read transfer cycle (row address AX8) Split Read Transfer Cycle (CAS high, DT/OE low, WEU and WEL high and DSF1 high at the falling edge of RAS) To execute a continuous serial read by real time read transfer, the HM5316123B must satisfy SC and DT/OE timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it possible to execute a continuous serial read without the above timing limitation. The HM5316123B supports two types of split register operation. One is the normal split register operation to split the data register into two halves. The other is the boundary split register operation using stopping columns described later. Figure 4 shows the block diagram for the normal split register operation. SAM data register (DR) consists of 2 split buffers, whose organizations are 128-word x 16-bit each. Let us suppose that data is read from upper data reagister DR1 (The row address AX8 is 0 and SAM address A7 is 1.). When split read transfer is executed setting row address AX8 to 0 and SAM start addresses A0 to A6, 128-word x 16-bit data are transferred from RAM to the lower data register DR0 (SAM 12 address A7 is 0) automatically. After data are read from data register DR1, data start to be read from SAM start addresses of data register DR0. If the next split read transfer isn’t executed while data are read from data register DR0, data start to be read from SAM start address 0 of DR1 after data are read from data register DR0. If split read transfer is executed setting row address AX8 to 1 and SAM start addresses A0 to A6 while data are read from data register DR1, 128-word x 16-bit data are transferred to data register DR2. After data are read from data register DR1, data start to be read from SAM start addresses of data register DR2. If the next split read transfer isn’t executed while data is read from data register DR2, data start to be read from SAM start address 0 of data register DR1 after data are read from data register DR2. In split read data transfer, the SAM start address A7 is automatically set in the data register, which isn’t used. The data on SAM address A7, which will be accessed next, outputs to QSF, QSF is switched from low to high by accessing SAM last address 127 and from high to low by accessing address 255. Split read transfer cycle is set when CAS is high, DT/OE is low, WEU and WEL is high and DSF1 is high at the falling edge of RAS. The cycle can be executed asyncronously with SC. However, HM5316123B must be satisfied tSTS (min) timing specified between SC rising (Boundary address) and RAS falling. In split transfer cycle, the HM5316123B must satisfy tRST (min), tCST (min) and tAST (min) timings specified between RAS or CAS falling and column address. (See figure 5.) In split read transfer, SI/O isn’t switched to output state. Therefore, read transfer must be executed to switch SI/O to output state when the previous transfer cycle is masked write transfer cycle or masked split write transfer cycle. SAM start address must be set in every split read transfer cycle. Preliminary Data Sheet E0160H10 DR3 Memory Array AX8 = 1 DR2 DR0 AX8 = 0 SAM I/O Bus SAM Column Decoder Memory Array SAM I/O Bus DR1 ct du ro LP EO HM5316123B Series SAM I/O Buffer SI/O Figure 4 Block Diagram for Split Transfer RAS tSTS (min) tRST (min) CAS t CST (min) Address Xi Yj t AST (min) DT/OE DSF1 SC Bi Ym Bj – 1 Bj Yj Note: Ym is the SAM start address in before SRT. Bi and Bj initiate the boundary address. Figure 5 Limitation in Split Transfer Preliminary Data Sheet E0160H10 13 ct du ro LP EO HM5316123B Series Masked Split Write Transfer Cycle (CAS high, DT/OE low, WEU or WEL low and DSF1 high at the falling edge of RAS) A continuous serial write cannot be executed because accessing SAM is inhibited during RAS low in write transfer. Masked split write transfer cycle makes it possible. In this cycle, tSTS (min), tRST (min), tCST (min) and tAST (min) timings must be satisfied like split read transfer cycle. And it is impossible to switch SI/O to input state in this cycle. If SI/O is in output state, masked write transfer cycle should be executed to switch SI/O into input state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of RAM by masked split write transfer cycle. However, masked write transfer cycle must be executed before split write transfer cycle. And in this masked split write transfer cycle, the MSB of row address (AX8) to write data must be the same as that of the read transfer cycle or the split read transfer cycle. Column size 64 bit (Y1) Start Stopping Column in Split Transfer Cycle The HM5316123B has the boundary split register operation using stopping columns. If a CBRS cycle has been performed, split transfer cycle performs the boundary operation. Figure 6 shows an example of boundary split register. (Boundary code is B6.) First of all a read data transfer cycle is executed, and SAM start addresses A0 to A7 are set. The RAM data are transferred to the SAM, and SAM serial read starts from the start address (Y1) on the lower SAM. After that, a split read transfer cycle is executed, and the next start address (Y2) is set. The RAM data are transferred to the upper SAM. When the serial read arrive at the first boundary after the split read transfer cycle, the next read jumps to the start address (Y2) on the upper SAM (jump 1) and continues. Then the second split read transfer cycle is executed, and another start address (Y3) is set. The RAM data are transferred to the lower SAM. When the serial read arrive at the other boundary again, the next read jumps to the start address (Y3) on the lower SAM. In stopping column, split transfer is needed for jump operation between lower SAM and upper SAM. Boundaries (B6) (Y3) (Y2) Jump 2 Jump 1 Lower SAM 128 bits Upper SAM 128 bits Figure 6 Example of Boundary Split Register 14 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Stopping Column Boundary Table —————————————————————————————— Stop Address —————————————————————————————— Boundary code Column size A2 A3 A4 A5 A6 —————————————————————————————— B2 4 0 * * * * —————————————————————————————— B3 8 1 0 * * * —————————————————————————————— B4 16 1 1 0 * * —————————————————————————————— B5 32 1 1 1 0 * —————————————————————————————— B6 64 1 1 1 1 0 —————————————————————————————— B7 128 1 1 1 1 1 —————————————————————————————— Notes: 1. A0, A1, and A7: don't care 2. *: don’t care Stopping Column Set Cycle (CBRS) No Reset CBR Cycle (CBRN) This cycle becomes stopping column set cycle by driving CAS low, WEU or WEL low, DSF1 high at This cycle becomes no reset CBR cycle (CBRN) by driving CAS low, WE high and DSF1 high at the falling edge of RAS. The CBRN can only execute the refresh operation. the falling edge of RAS. Stopping column data (boundaries) are latched from address inputs on the falling edge of RAS. To determine the boundary, A2 to A6 can be used and don’t care A0, A1, and A7. In the HM5316123B, 6 types of boundary (B2 to B7) can be set including the default case. (See stopping column boundary table.) If A2 to A5 are set to high and A6 is set to low, the boundaries (B6) are selected. Figure 6 shows the example. The stop address that is set by the CBRS is used from next split transfer cycle. Once a CBRS is executed, the stopping column operation mode continues until CBRR. Register Reset Cycle (CBRR) This cycle becomes register reset cycle (CBRR) by driving CAS low, WEU and WEL high, and DSF1 low at the falling edge of RAS. A CBRR can reset the persistent mask operation and stopping column operation, so the HM5316123B becomes the new mask operation and boundary code B7. When a CBRR is executed for stopping column operation reset and split transfer operation, it need to satisfy tSTS (min) and tRST (min) between RAS falling and SC rising for correct SAM read/write operation. Byte Control (WEU, WEL) In a write cycle, when WEL set low and WEU set high, I/O0 to I/O7 become write mode and I/O8 to I/O15 become no write mode, and when WEL set high and WEU set low, I/O0 to I/O7 become no write mode and I/O8 to I/O15 become write mode. The write cycle that byte control is capable are RAM write cycle, block write cycle, load write mask register cycle and load color register cycle. The byte control write cycle is capable to execute early write, delay write, read-modify-write and page mode. But write mask in new mask mode, flash write, transfer and refresh cycle can not execute byte control. Preliminary Data Sheet E0160H10 15 ct du ro LP EO HM5316123B Series SAM Port Operation Refresh Serial Read Cycle RAM Refresh SAM port is in read mode when the previous data transfer cycle is a read transfer cycle. Access is synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address 255), the internal pointer indicates address 0 at the next access. RAM, which is composed of dynamic circuits, requires refresh cycle to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS-only refresh cycle, (2) CAS-before-RAS (CBRN, CBRS, and CBRR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate RAS, such as read/write cycles or transfer cycles, can also refresh the row address. Therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. Serial Write Cycle If previous data transfer cycle is masked write transfer cycle, SAM port goes into write mode. In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle. If SE is high, SI/O data isn ’t fetched into data register. The internal pointer is incremented by the SC rising, so SE high can be used as mask data for SAM. After indicating the last address (address 255), the internal pointer indicates address 0 at the next access. (1) RAS-Only Refresh Cycle: RAS-only refresh cycle is executed by activating only the RAS cycle with CAS fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this cycle from a data transfer cycle, DT/OE must be high at the falling edge of RAS. (2) CBR Refresh Cycle: CBR refresh cycle (CBRN, CBRS and CBRR) are set by activating CAS before RAS. In this cycle, the refresh address need not to be input through external circuits because it is input through an internal refresh counter. In this cycle, output is in high impedance and power dissipation is lowered because CAS circuits don’t operate. (3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating RAS when DT/OE and CAS keep low in normal RAM read cycles. SAM Refresh SAM parts (data register, shift resister and selector), organized as fully static circuitry, require no refresh. 16 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Absolute Maximum Ratings Parameter Symbol Value Unit —————————————————————————————————————————— Voltage on any pin relative to VSS VT –1.0 to +7.0 Supply voltage relative to VSS VCC –0.5 to +7.0 Short circuit output current Iout 50 V —————————————————————————————————————————— V —————————————————————————————————————————— mA —————————————————————————————————————————— Power dissipation PT 1.0 Topr 0 to +70 W —————————————————————————————————————————— Operating temperature °C —————————————————————————————————————————— Storage temperature Tstg –55 to +125 °C —————————————————————————————————————————— Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Notes —————————————————————————————————————————— Supply voltage VCC 4.5 VIH 2.4 VIL –0.5*2 5.0 5.5 V 1 —————————————————————————————————————————— Input high voltage — 6.5 V 1 —————————————————————————————————————————— Input low voltage — 0.8 V 1 —————————————————————————————————————————— Notes: 1. All voltage referred to VSS 2. –3.0 V for pulse width < 10 ns. Preliminary Data Sheet E0160H10 17 ct du ro LP EO HM5316123B Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM5316123B —————————————– -7 -8 -10 ———— ———— ———— Parameter Symbol Min Max Min Max Min Max Unit Test conditions —————————————————————————————————————————— 120 ————————— ICC7 — SE = VIL, SC cycling tSCC = min — 110 — 175 — 100 160 mA SC = VIL, SE = VIH — ———————————————————— cycling 195 — RAS, CAS Operating current ICC1 mA tRC = min —————————————————————————————————————––––––––– — — ————————— ICC7BW — 200 SE = VIL, SC cycling tSCC = min 180 — 100 160 mA SC = VIL, SE = VIH 125 ———————————————————— cycling — 115 RAS, CAS Block write current ICC1BW — mA tRC = min —————————————————————————————————————––––––––– Standby current ICC2 — ICC8 — 7 — 7 — 7 mA RAS, CAS ———————————————————— = VIH 85 — 75 — 70 mA SC = VIL, SE = VIH ————————— SE = VIL, SC cycling tSCC = min —————————————————————————————————————––––––––– RAS-only refresh ICC3 — 115 — 105 — 90 mA RAS cycling SC = VIL, SE = VIH current ———————————————————— CAS =VIH ————————— ICC9 — 185 — 165 — 150 mA tRC = min SE = VIL, SC cycling tSCC = min —————————————————————————————————————––––––––– Fast page mode current *3 ICC4 — ICC10 — 125 — 120 — 115 mA CAS cycling SC = VIL, SE = VIH ———————————————————— RAS = VIL 200 — 185 — 175 mA tPC = min ————————— SE = VIL, SC cycling tSCC = min —————————————————————————————————————––––––––– Fast page mode block write current *3 ICC4BW — 145 ICC10BW — 220 — 135 — 130 mA CAS cycling SC = VIL, SE = VIH ———————————————————— RAS = VIL — 205 — 195 mA tPC = min ————————— SE = VIL, SC cycling tSCC = min —————————————————————————————————————––––––––– CAS-before RAS ICC5 — 85 — 75 — 65 mA RAS cycling SC = VIL, SE = VIH refresh current ———————————————————— tRC = min ————————— ICC11 — 155 — 140 — 125 mA SE = VIL, SC cycling tSCC = min —————————————————————————————————————––––––––– Data transfer current 130 ICC12 — SE = VIL, SC cycling tSCC = min — 120 — 185 — 110 165 mA SC = VIL, SE = VIH ————————— 205 — RAS, CAS ICC6 — ———————————————————— cycling mA tRC = min —————————————————————————————————————––––––––– Input leakage current ILI –10 10 Output leakage current ILO –10 10 Output high voltage VOH 2.4 Output low voltage VOL — –10 10 –10 10 µA —————————————————————————————————————––––––––– –10 10 –10 10 µA —————————————————————————————————————––––––––– — 2.4 — 2.4 — V IOH = –1 mA —————————————————————————————————————––––––––– 0.4 — 0.4 — 0.4 V IOL = 2.1 mA —————————————————————————————————————————— 18 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once while RAS is low and CAS is high. 3. Address can be changed once in 1 page cycle (tPC). Capacitance (Ta = 25°C, VCC = 5 V ± 10 %, f = 1 MHz, Bias: Clock, I/O = VCC, address = VSS) Parameter Symbol Typ Max Unit Note —————————————————————————————————————————— Input capacitance (Address) CI1 — CI2 — CI/O — 5 pF 1 —————————————————————————————————————————— Input capacitance (Clocks) 5 pF 1 —————————————————————————————————————————— Output capacitance (I/O, SI/O, QSF) 7 pF 1 —————————————————————————————————————————— Notes: 1. This parameter is sampled and not 100% tested. Preliminary Data Sheet E0160H10 19 ct du ro LP EO HM5316123B Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) *1, *16 Test Conditions – Input rise and fall times: 5ns – Input pulse levels: VSS to 3.0 V – Input timing reference levels: 0.8 V, 2.4 V – Output timing reference levels: 0.8 V, 2.0 V – Output load: RAM 1TTL+CL(50PF) SAM, QSF 1TTL+CL(30PF) (Including scope and jig) Common Parameter HM5316123B —————————————— Parameter Symbol -7 -8 -10 ———— ———— ———— Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— Random read or write cycle time tRC 130 — tRP 50 tRAS 70 tCAS 20 tASR 0 tRAH 10 tASC 0 tCAH 12 tRCD 20 RAS hold time referenced to CAS tRSH 20 CAS hold time referenced to RAS tCSH 70 CAS to RAS precharge time 10 150 — 180 — ns ————————————————————————————————————————— RAS precharge time — 60 — 70 — ns ————————————————————————————————————————— RAS pulse width 10000 80 10000 100 10000 ns ————————————————————————————————————————— CAS pulse width — 20 — 25 — ns ————————————————————————————————————————— Row address setup time — 0 — 0 — ns ————————————————————————————————————————— Row address hold time — 10 — 10 — ns ————————————————————————————————————————— Column address setup time — 0 — 0 — ns ————————————————————————————————————————— Column address hold time — 15 — 15 — ns ————————————————————————————————————————— RAS to CAS delay time 50 20 60 20 75 ns 2 ————————————————————————————————————————— — 20 — 25 — ns ————————————————————————————————————————— — 80 — 100 — ns ————————————————————————————————————————— tCRP — 10 — 10 — ns ————————————————————————————————————————— 20 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Common Parameter (cont) HM5316123B —————————————— Parameter Symbol -7 -8 -10 ———— ———— ———— Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— Transition time (rise to fall) tT 3 tREF — tDTS 0 tDTH 10 tFSR 0 tRFH 10 tFSC 0 tCFH 12 tDZC 0 tDZO 0 tOFF1 — 50 3 50 3 50 ns 3 ————————————————————————————————————————— Refresh period 8 — 8 — 8 ms ————————————————————————————————————————— DT to RAS setup time — 0 — 0 — ns ————————————————————————————————————————— DT to RAS hold time — 10 — 10 — ns ————————————————————————————————————————— DSF1 to RAS setup time — 0 — 0 — ns ————————————————————————————————————————— DSF1 to RAS hold time — 10 — 10 — ns ————————————————————————————————————————— DSF1 to CAS setup time — 0 — 0 — ns ————————————————————————————————————————— DSF1 to CAS hold time — 15 — 15 — ns ————————————————————————————————————————— Data-in to CAS delay time — 0 — 0 — ns 4 ————————————————————————————————————————— Data-in to OE delay time — 0 — 0 — ns 4 ————————————————————————————————————————— Output buffer turn-off delay referenced to CAS 15 — 20 — 20 ns 5 ————————————————————————————————————————— Output buffer turn-off delay referenced to OE tOFF2 — 15 — 20 — 20 ns 5 ————————————————————————————————————————— Preliminary Data Sheet E0160H10 21 ct du ro LP EO HM5316123B Series Read Cycle (RAM), Page Mode Read Cycle HM5316123B —————————————— Parameter Symbol -7 -8 -10 ———— ———— ———— Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— Access time from RAS tRAC — tCAC — tOAC — tAA — tRCS 0 tRCH 0 tRRH 0 70 — 80 — 100 ns 6, 7 ————————————————————————————————————————— Access time from CAS 20 — 20 — 25 ns 7, 8 ————————————————————————————————————————— Access time from OE 20 — 20 — 25 ns 7 ————————————————————————————————————————— Address access time 35 — 40 — 45 ns 7, 9 ————————————————————————————————————————— Read command setup time — 0 — 0 — ns ————————————————————————————————————————— Read command hold time — 0 — 0 — ns 10 ————————————————————————————————————————— Read command hold time referenced to RAS — 5 — 10 — ns 10 ————————————————————————————————————————— RAS to column address delay time tRAD 15 Column address to RAS lead time tRAL 35 Column address to CAS lead time tCAL 35 Page mode cycle time tPC 45 tCP 7 tACP — tRASP 70 100000 80 100000 100 100000 ns 35 15 40 15 55 ns 2 ————————————————————————————————————————— — 40 — 45 — ns ————————————————————————————————————————— — 40 — 45 — ns ————————————————————————————————————————— — 50 — 55 — ns ————————————————————————————————————————— CAS precharge time — 10 — 10 — ns ————————————————————————————————————————— Access time from CAS precharge 40 — 45 — 50 ns ————————————————————————————————————————— Page mode RAS pulse width ————————————————————————————————————————— 22 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle HM5316123B —————————————— Parameter Symbol -7 -8 -10 ———— ———— ———— Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— Write command setup time tWCS 0 — 0 — 0 — ns tWCH 12 tWP 12 tRWL 20 tCWL 20 tDS 0 tDH 12 tWS 0 tWH 10 tMS 0 tMH 10 tOEH 15 tPC 45 tCP 7 tCDD 15 tRASP 70 100000 80 100000 100 100000 ns 11 ————————————————————————————————————————— Write command hold time — 15 — 15 — ns ————————————————————————————————————————— Write command pulse width — 15 — 15 — ns ————————————————————————————————————————— Write command to RAS lead time — 20 — 20 — ns ————————————————————————————————————————— Write command to CAS lead time — 20 — 20 — ns ————————————————————————————————————————— Data-in setup time — 0 — 0 — ns 12 ————————————————————————————————————————— Data-in hold time — 15 — 15 — ns 12 ————————————————————————————————————————— WE to RAS setup time — 0 — 0 — ns ————————————————————————————————————————— WE to RAS hold time — 10 — 10 — ns ————————————————————————————————————————— Mask data to RAS setup time — 0 — 0 — ns ————————————————————————————————————————— Mask data to RAS hold time — 10 — 10 — ns ————————————————————————————————————————— OE hold time referenced to WE — 20 — 20 — ns ————————————————————————————————————————— Page mode cycle time — 50 — 55 — ns ————————————————————————————————————————— CAS precharge time — 10 — 10 — ns ————————————————————————————————————————— CAS to data-in delay time — 20 — 20 — ns 13 ————————————————————————————————————————— Page mode RAS pulse width ————————————————————————————————————————— Preliminary Data Sheet E0160H10 23 ct du ro LP EO HM5316123B Series Read-Modify-Write Cycle HM5316123B —————————————— Parameter -7 -8 -10 ———— ———— ———— Symbol Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— Read-modify-write cycle time tRWC 180 — 200 — 230 — ns ————————————————————————————————————————— RAS pulse width (read-modify-write cycle) tRWS 120 10000 130 10000 150 10000 ns CAS to WE delay time tCWD 40 tAWD 60 tODD 15 tRAC — tCAC — tOAC — tAA — tRAD 15 tRCS 0 tRWL 20 tCWL 20 tWP 12 tDS 0 tDH 12 tOEH 15 ————————————————————————————————————————— — 45 — 50 — ns 14 ————————————————————————————————————————— Column address to WE delay time — 65 — 70 — ns 14 ————————————————————————————————————————— OE to data-in delay time — 20 — 20 — ns 12 ————————————————————————————————————————— Access time from RAS 70 — 80 — 100 ns 6, 7 ————————————————————————————————————————— Access time from CAS 20 — 20 — 25 ns 7, 8 ————————————————————————————————————————— Access time from OE 20 — 20 — 25 ns 7 ————————————————————————————————————————— Address access time 35 — 40 — 45 ns 7, 9 ————————————————————————————————————————— RAS to column address delay time 35 15 40 15 55 ns ————————————————————————————————————————— Read command setup time — 0 — 0 — ns ————————————————————————————————————————— Write command to RAS lead time — 20 — 20 — ns ————————————————————————————————————————— Write command to CAS lead time — 20 — 20 — ns ————————————————————————————————————————— Write command pulse width — 15 — 15 — ns ————————————————————————————————————————— Data-in setup time — 0 — 0 — ns 12 ————————————————————————————————————————— Data-in hold time — 15 — 15 — ns 12 ————————————————————————————————————————— OE hold time referenced to WE — 20 — 20 — ns ————————————————————————————————————————— 24 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Refresh Cycle HM5316123B —————————————— -7 -8 -10 ———— ———— Parameter Symbol Min Max Min Max ———— Min Max Unit Notes ————————————————————————————————————————— CAS setup time (CAS-before-RAS refresh) tCSR 10 CAS hold time (CAS-before-RAS refresh) 10 — 10 — 10 — ns ————————————————————————————————————————— tCHR — 10 — 10 — ns ————————————————————————————————————————— RAS precharge to CAS hold time tRPC 10 — 10 — 10 — ns ————————————————————————————————————————— Flash Write Cycle, Block Write Cycle, and Register Read Cycle HM5316123B —————————————— Parameter Symbol -7 8 -10 ———— ———— ———— Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— CAS to data-in delay time tCDD 15 tODD 15 — 20 — 20 — ns 13 ————————————————————————————————————————— OE to data-in delay time — 20 — 20 — ns 13 ————————————————————————————————————————— CBR Refresh with Register Reset HM5316123B —————————————— Parameter -7 -8 -10 ———— ———— ———— Symbol Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— Split transfer setup time tSTS 20 Split transfer hold time referenced to RAS tRST 70 — 20 — 25 — ns ————————————————————————————————————————— — 80 — 100 — ns ————————————————————————————————————————— Preliminary Data Sheet E0160H10 25 ct du ro LP EO HM5316123B Series Read Transfer Cycle HM5316123B —————————————— Parameter -7 -8 -10 ———— ———— ———— Symbol Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— DT hold time referenced to RAS tRDH 60 tCDH 20 DT hold time referenced to column address tADH 25 DT precharge time tDTP 20 tDRD 60 tSRS 15 tSRH 70 tSCH 25 tSAH 40 tSDD 5 tSDH 10 tDQD — tDQH 5 tSZS 0 tSCC 25 tSC 5 tSCP 10 tSCA — tSOH 5 tSIS 0 tSIH 15 tRAD 15 tRAL 35 tRQD — tCQD — 10000 65 10000 80 10000 ns ————————————————————————————————————————— DT hold time referenced to CAS — 20 — 25 — ns ————————————————————————————————————————— — 30 — 30 — ns ————————————————————————————————————————— — 20 — 30 — ns ————————————————————————————————————————— DT to RAS delay time — 70 — 80 — ns ————————————————————————————————————————— SC to RAS setup time — 20 — 30 — ns ————————————————————————————————————————— 1st SC to RAS hold time — 80 — 100 — ns ————————————————————————————————————————— 1st SC to CAS hold time — 25 — 25 — ns ————————————————————————————————————————— 1st SC to column address hold time — 45 — 50 — ns ————————————————————————————————————————— Last SC to DT delay time — 5 — 5 — ns ————————————————————————————————————————— 1st SC to DT hold time — 13 — 15 — ns ————————————————————————————————————————— DT to QSF delay time 30 — 35 — 35 ns 15 ————————————————————————————————————————— QSF hold time referenced to DT — 5 — 5 — ns ————————————————————————————————————————— Serial data-in to 1st SC delay time — 0 — 0 — ns ————————————————————————————————————————— Serial clock cycle time — 28 — 30 — ns ————————————————————————————————————————— SC pulse width — 10 — 10 — ns ————————————————————————————————————————— SC precharge time — 10 — 10 — ns ————————————————————————————————————————— SC access time 20 — 23 — 25 ns 15 ————————————————————————————————————————— Serial data-out hold time — 5 — 5 — ns ————————————————————————————————————————— Serial data-in setup time — 0 — 0 — ns ————————————————————————————————————————— Serial data-in hold time — 15 — 15 — ns ————————————————————————————————————————— RAS to column address delay time 35 15 40 15 55 ns ————————————————————————————————————————— Column address to RAS lead time — 40 — 45 — ns ————————————————————————————————————————— RAS to QSF delay time 70 — 75 — 85 ns 15 ————————————————————————————————————————— CAS to QSF delay time 35 — 35 — 35 ns 15 ————————————————————————————————————————— 26 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Read Transfer Cycle (cont) HM5316123B —————————————— Parameter Symbol -7 -8 -10 ———— ———— ———— Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— QSF hold time referenced toRAS tRQH 20 — 20 — 25 — ns ————————————————————————————————————————— QSF hold time referenced to CAS tCQH 5 — 5 — 5 — ns ————————————————————————————————————————— Masked Write Transfer Cycle HM5316123B —————————————— Parameter Symbol -7 -8 -10 ———— ———— ———— Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— SC setup time referenced to RAS tSRS 15 tSRD 20 tSRZ 10 — 20 — 30 — ns ————————————————————————————————————————— RAS to SC delay time — 25 — 25 — ns ————————————————————————————————————————— Serial output buffer turn-off time referenced to RAS 30 10 35 10 50 ns ————————————————————————————————————————— RAS to serial data-in delay time tSID 30 tRQD — tCQD — QSF hold time referenced to RAS tRQH 20 QSF hold time referenced to CAS tCQH 5 Serial clock cycle time tSCC 25 tSC 5 tSCP 10 tSCA — tSOH 5 tSIS 0 tSIH 15 — 35 — 50 — ns ————————————————————————————————————————— RAS to QSF delay time 70 — 75 — 85 ns 15 ————————————————————————————————————————— CAS to QSF delay time 35 — 35 — 35 ns 15 ————————————————————————————————————————— — 20 — 25 — ns ————————————————————————————————————————— — 5 — 5 — ns ————————————————————————————————————————— — 28 — 30 — ns ————————————————————————————————————————— SC pulse width — 10 — 10 — ns ————————————————————————————————————————— SC precharge time — 10 — 10 — ns ————————————————————————————————————————— SC access time 20 — 23 — 25 ns 15 ————————————————————————————————————————— Serial data-out hold time — 5 — 5 — ns ————————————————————————————————————————— Serial data-in setup time — 0 — 0 — ns ————————————————————————————————————————— Serial data-in hold time — 15 — 15 — ns ————————————————————————————————————————— Preliminary Data Sheet E0160H10 27 ct du ro LP EO HM5316123B Series Split Read Transfer Cycle, Masked Split Write Transfer Cycle HM5316123B —————————————— Parameter -7 -8 -10 ———— ———— ———— Symbol Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— Split transfer setup time tSTS 20 Split transfer hold time referenced to RAS tRST 70 Split transfer hold time referenced to CAS tCST 20 Split transfer hold time referenced to column address 35 — 20 — 25 — ns ————————————————————————————————————————— — 80 — 100 — ns ————————————————————————————————————————— — 20 — 25 — ns ————————————————————————————————————————— tAST — 40 — 45 — ns ————————————————————————————————————————— SC to QSF delay time tSQD — tSQH 5 tSCC 25 tSC 5 tSCP 10 tSCA — tSOH 5 tSIS 0 tSIH 15 tRAD 15 tRAL 35 30 — 30 — 30 ns 15 ————————————————————————————————————————— QSF hold time referenced to SC — 5 — 5 — ns ————————————————————————————————————————— Serial clock cycle time — 28 — 30 — ns ————————————————————————————————————————— SC pulse width — 10 — 10 — ns ————————————————————————————————————————— SC precharge time — 10 — 10 — ns ————————————————————————————————————————— SC access time 20 — 23 — 25 ns 15 ————————————————————————————————————————— Serial data-out hold time — 5 — 5 — ns ————————————————————————————————————————— Serial data-in setup time — 0 — 0 — ns ————————————————————————————————————————— Serial data-in hold time — 15 — 15 — ns ————————————————————————————————————————— RAS to column address delay time 35 15 40 15 55 ns ————————————————————————————————————————— Column address to RAS lead time — 40 — 45 — ns ————————————————————————————————————————— 28 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Serial Read Cycle, Serial Write Cycle HM5316123B —————————————— Parameter -7 -8 -10 ———— ———— ———— Symbol Min Max Min Max Min Max Unit Notes ————————————————————————————————————————— Serial clock cycle time tSCC 25 tSC 5 tSCP 10 tSCA — tSEA — tSOH 5 tSHZ — — 28 — 30 — ns ————————————————————————————————————————— SC pulse width — 10 — 10 — ns ————————————————————————————————————————— SC precharge width — 10 — 10 — ns ————————————————————————————————————————— Access time from SC 20 — 23 — 25 ns 15 ————————————————————————————————————————— Access time from SE 17 — 20 — 25 ns 15 ————————————————————————————————————————— Serial data-out hold time — 5 — 5 — ns ————————————————————————————————————————— Serial output buffer turn-off time referenced to SE 15 — 20 — 20 ns 5,17 ————————————————————————————————————————— SE to serial output in low-Z tSLZ 0 tSIS 0 tSIH 15 tSWS 0 tSWH 15 tSWIS 0 tSWIH 15 — 0 — 0 — ns 5,17 ————————————————————————————————————————— Serial data-in setup time — 0 — 0 — ns ————————————————————————————————————————— Serial data-in hold time — 15 — 15 — ns ————————————————————————————————————————— Serial write enable setup time — 0 — 0 — ns ————————————————————————————————————————— Serial wrtie enable hold time — 15 — 15 — ns ————————————————————————————————————————— Serial write disable setup time — 0 — 0 — ns ————————————————————————————————————————— Serial write disable hold time — 15 — 15 — ns ————————————————————————————————————————— Preliminary Data Sheet E0160H10 29 ct du ro LP EO HM5316123B Series Notes: 1. AC measurements assume tT = 5 ns. 2. When tRCD > tRCD (max) and tRAD > tRAD (max), access time is specified by tCAC or tAA. 3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT is measured between VIH and VIL. 4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied. 5. tOFF1 (max), tOFF2 (max), tSHZ (max) and tSLZ (min) are defined as the time at which the output acheives the open circuit condition (VOH – 100 mV, VOL + 100 mV). This parameter is sampled and not 100% tested. 6. Assume that tRCD < tRCD (max) and tRAD < tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 7. Measured with a load circuit equivalent to 1 TTL loads and 50 pF. 8. When tRCD > tRCD (max) and tRAD < tRAD (max), access time is specified by tCAC. 9. When tRCD < tRCD (max) and tRAD > tRAD (max), access time is specified by tAA. 10. If either tRCH or tRRH is satisfied, operation is guaranteed. 11. When tWCS > tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 12. These parameters are specified by the later falling edge of CAS or WEU and WEL. 13. Either tCDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or OE prior to applying data to the device when output buffer is on. 14. When tAWD > tAWD (min) and tCWD > tCWD (min) in read-modify-write cycle, the data of the selected address outputs to an I/O pin and input data is written into the selected address. tODD (min) must be satisfied because output buffer must be turned off by OE prior to applying data to the device. 15. Measured with a load circuit equivalent to 1 TTL loads and 30 pF. 16. After power-up, pause for 100 µs or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. Hitachi recommends that least 8 initialization cycle is the CBRR for internal register reset. This CBRR need not tSTS and tRST. 17. When tSHZ and tSLZ are measured in the same VCC and Ta condition and tr and tf of SE are less than 5 ns, tSHZ < tSLZ +5 ns. This parameter is sampled and not 100% tested. 18. When both WEU and WEL go low at the same time, all 16-bits data are written into the device, WEU and WEL cannot be staggered within the same write cycles. 19. After power-up, QSF output may be High-Z, so 1 sc cycle is needed to be Low-Z it. 20. DSF2 pin is open pin, but Hitachi recommends it is fixed low in all operation for the addition mode in future. 30 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Timing Waveforms*21 Read Cycle t RC t RAS t RP RAS t CRP t CSH t RSH t CAS t RCD CAS Address t RAL t RAD t ASR t RAH t ASC Row Column t RCS WEL t CAL t CAH t RRH t RCH t CAC t AA t CDD t OFF1 t RAC I/O 0 to I/O 7 (Output) Valid Dout t OAC t DZC I/O 0 to I/O 7 (Input) t OFF2 t DZO t RCS t RRH WEU t RCH t CAC t CDD t AA t OFF1 t RAC I/O 8 to I/O 15 (Output) Valid Dout t OAC t DZC I/O 8 to I/O 15 (Input) t OFF2 t DZO t DTS t DTH t FSR t RFH DT/OE t FSC t CFH DSF1 Note: 21. VIH or V IL Invalid Dout Preliminary Data Sheet E0160H10 31 ct du ro LP EO HM5316123B Series Fast page Mode Read Cycle t RC t RASP RAS t PC t CSH t CAS t RCD CAS t RAD t ASR Address t RAH t ASC Row t CP t CAL t CAH WEU, WEL I/O (Input) t DTS t DZO t DTH t FSR t RFH Column t RCS t RCH t AA t ACP t CAC Valid Dout t DZC t CAL t CAH t ASC Column t RCH t CDD t OAC t OFF2 t RCS 32 t CFH t FSC t FSC t DZC t OAC t CFH t OFF1 Valid Dout t CDD t OFF2 t OAC DT/OE DSF1 t RRH t RCH t AA t ACP t CAC t OFF1 Valid Dout t DZC t CRP t RAL t CAL t CAH t RAC t OFF1 t AA t CAC I/O (Output) t RSH t CAS t CP t CAS t ASC Column t RCS t RP t FSC Preliminary Data Sheet E0160H10 t CFH t CDD ct du ro LP EO HM5316123B Series Write Cycle The write cycle state table as shown below is applied to early write, delayed write, page mode write, and read-modify write. Write Cycle State Table RAS CAS RAS RAS CAS ————————————————————————— DSF1 DSF1 WEU, WEL I/O I/O ————————————————————————— MNEU Cycle W1 W2 W3 W4 W5 —————————————————————————————————————————— RWM Write mask (new/old) Write DQs to I/Os 0 0 0 Write mask*1 Valid data —————————————————————————————————————————— BWM Write mask (new/old) Block write 0 1 0 Write mask*2 Column mask*2 —————————————————————————————————————————— RW Normal write (no mask) 0 0 1 H or L*1 Valid data —————————————————————————————————————————— BW Block write (no mask) 0 1 1 H or L*2 Column mask*2 —————————————————————————————————————————— LMR*4 Load write mask resister 1 0 1 H or L Write mask data*3 —————————————————————————————————————————— LCR*4 Load color resister 1 1 1 H or L Color data —————————————————————————————————————————— Notes: 1. WEU, WEL Either Low Both High 2. 3. 4. Mode New mask mode Persistent mask mode No mask I/O data/RAS Mask H or L (mask register used) H or L I/O Mask Data (In new mask mode) Low: Mask High: Non Mask In persistent mask mode, I/O don't care Reference Figure 2 Use of Block Write. I/O Write Mask Data Low: Mask High: Non Mask Column Address: H or L Preliminary Data Sheet E0160H10 33 ct du ro LP EO HM5316123B Series Early Write Cycle t RC t RAS t RP RAS t CRP t CSH t RSH t RCD CAS (CASU/CASL) Address t CAS t ASR t RAH Row t WS t WH t WCS t WCH High-Z t MH t MS I/O 0 to I/O 7 (Input) t DH t DS W4 t WS W5 t WH t WCS t WCH W3 WEU I/O 8 to I/O 15 (Output) t CAH Column W3 WEL I/O 0 to I/O7 (Output) t ASC High-Z t MH t MS I/O 8 to I/O 15 (Input) W4 t DTS t DH t DS W5 t DTH DT/OE t FSR DSF1 t RFH W1 t FSC t CFH W2 W1 to W5: See write cycle state table for the logic states. 34 Preliminary Data Sheet E0160H10 ct du ro LP EO HM5316123B Series Delayed Write Cycle t RC t RAS t RP RAS CAS (CASU, CASL) t CAS t ASR Address t RAH Row t WS t DS t DZC t DH t RWL t WH I/O 8 to I/O 15 (Input) t MH t DS t DZC t DTS t DTH t FSR t RFH t DH W5 W4 W1 CWL t WP W3 t MS t CWL W5 W4 WEU DSF1 t RWL t WP t MH t WS DT/OE t CAH Column t WH t MS I/O 0 to I/O 7 (Input) I/O 8 to I/O 15 (Output) t ASC W3 WEL I/O 0 to I/O 7 (Output) t CRP t CSH t RSH t RCD t OFF2 t ODD t FSC t OEH t CFH W2 W1 to W5: See write cycle state table for the logic states Preliminary Data Sheet E0160H10 35 ct du ro LP EO HM5316123B Series Fast page Mode Write Cycle (Early Write) t RC t RP t RASP RAS t CSH t PC t RCD CAS (CASU, CASL) t ASR Address t CP t CAS t RAH t ASC t CAH t ASC Row Column t WS t WH t WCS t WCH WEU, WEL t RSH t CAS t CP t CAS t CAH t ASC t CRP t CAH Column Column t WCS t WCH t WCS t WCH W3 High-Z I/O (Output) t MS I/O (Input) t DS t MH t DH W4 W5 t DTS t DH t DS W5 W5 t DTH DT/OE t RFH t FSC t FSR W1 DSF1 t DS t DH t CFH t FSC W2 t CFH t FSC t CFH W2 W2 W1 to W5: See write cycle state table for the logic states Fast page Mode Write Cycle (Delayed Write) t RC t RASP t RP RAS t CSH t RCD t PC CAS (CASU, CASL) t ASR t RAH t ASC Address WEU, WEL I/O (Output) t CAH Column Row t WS t CP t CAS t ASC t CAS t ASC t CAH Column t CAH t RWL t CWL t WP t WP t WP W3 High-Z t MS I/O (Input) t MH t DS t DH t DS t DH t DS t DH W5 W5 W5 W4 t OEH t DTS DT/OE t FSR DSF1 t RFH t FSC W1 t CFH W2 t FSC t CFH W2 W1 to W5: See write cycle state table for the logic states 36 t CRP Column t CWL t WH t RSH t CP t CAS Preliminary Data Sheet E0160H10 t FSC t CFH W2 t CWL ct du ro LP EO HM5316123B Series Read Modify Write Cycle t RWC t RP t RWS RAS t CRP t RCD CAS (CASU, CASL) t RAD t ASR Address Row t WS t CAH t AWD t CWD t RCS t RWL t CWL t WP t CAC t AA W3 t RAC Valid Dout t MS I/O 0 to I/O 7 (Input) t MH t OAC t DZC W4 t WS t RCS t CWD W5 t RWL t CWL t WP t ODD Valid Dout I/O 8 to I/O 15 (Input) t DH t CAC t AA t RAC W3 t MS t DS t OFF2 t WH WEU I/O 8 to I/O 15 (Output) t ASC Column t WH WEL I/O 0 to I/O 7 (Output) t RAH t MH t OAC t DZC W4 t DS t DH W5 t DTS t DTH t DZO t ODD t OEH DT/OE t FSR DSF1 t RFH W1 t FSC t CFH W2 W1 to W5: See write cycle state table for the logic states Preliminary Data Sheet E0160H10 37 ct du ro LP EO HM5316123B Series RAS-Only Refresh Cycle t RC t RP t RAS RAS t RPC t CRP CAS t ASR t RAH Row Address t OFF1 I/O (Output) t CDD I/O (Input) t OFF2 t ODD t DTS t DTH t FSR t RFH DT/OE DSF1 WE: H or L CAS-Before-RAS refresh Cycle t RC t RP RAS t RPC t CP t CSR t CHR CAS t RPC Inhibit Falling Transition Address t WS t WH WEU, WEL t OFF1 High-Z I/O (Output) DT/OE t FSR t RFH DSF1 SC : H or L 38 t RP t RAS Preliminary Data Sheet E0160H10 t CSR ct du ro LP EO HM5316123B Series Hidden Refresh Cycle t RC t RAS t RC t RAS t RP t RP RAS t RCD CAS t CHR Row Column t RCS t RRH t WS t WH t CAC WEU, WEL t AA t RAC I/O (Output) t OFF1 Valid Dout t DZC I/O (Input) t DTS DT/OE t CRP t RAD t RAL t RAH t ASC t CAH t ASR Address t RSH t FSR t OAC t OFF2 t DZO t DTH t RFH t FSC t CFH t FSR t RFH DSF1 Preliminary Data Sheet E0160H10 39 ct du ro LP EO HM5316123B Series CAS-Before-RAS Set Cycle (CBRS) t RC t RAS t RP t RP RAS t RPC t CSR t CHR t CRP Inhibit falling transition CAS t ASR Address (A2-A6) t RAH Stop Address t WS t WH WEU, WEL High-Z I/O (Output) I/O (Input) DT/OE t FSR t RFH DSF1 A0, A1, A7 : Don't care SC: Dont care CAS-Before-RAS Reset Cycle (CBRR) t RC t RP t RAS t RP RAS t RPC t CSR t CHR t CRP Inhibit falling transition CAS Address t WS t WH WEU, WEL High-Z I/O (Output) I/O (Input) DT/OE t FSR t RFH DSF1 t STS SC Bi*1 t RST Bj-2 Note: 1. Bi, Bj initiate the boundary addresses. 40 Preliminary Data Sheet E0160H10 Bj-1 Bj*1 ct du ro LP EO HM5316123B Series Flash Write Cycle t RC t RAS t RP RAS t CRP CAS t RCD t ASR t RAH Row Address t WS t WH WEU, WEL t OFF1 I/O (Output) I/O (Input) DT/OE t OFF2 t CDD High-Z t MS t ODD t DTS t MH Mask Data t DTH t FSR t RFH DSF1 Preliminary Data Sheet E0160H10 41 ct du ro LP EO HM5316123B Series Register Read Cycle (Mask data, Color data) t RC t RAS t RP RAS t CSH t RCD CAS t ASR t RAH Row t WS t WH Address t CAS t RRH t RCS WEU, WEL t CAC t RAC I/O (Output) I/O (Input) DT/OE t FSR t OAC t DZO t DTH t RFH t FSC DSF1 t CFH *1 Note: 1. State of DSF1 at falling edge of CAS State 0 Accessed Mask data data (LMR) 42 1 Color data (LCR) Preliminary Data Sheet E0160H10 t RCH t CDO t OFF1 t DZC t DTS t CRP t RSH Valid Out t OFF2 t ODD ct du ro LP EO HM5316123B Series Read Transfer Cycle-1 t RC t RP t RAS RAS t CRP t CSH t RCD t RSH t CAS CAS t RAD t RAH t ASR Address Row t WS t RAL t ASC t CAH SAM Start Address t WH WEU, WEL High-Z I/O (Output) t CDH t DTS t DRD t ADH t DTP t RDH DT/OE t FSR t RFH DSF1 t SCC t SCC SC SI/O (Output) t SCA t SOH Valid Sout Valid Sout t SC t SCA t SOH t SCA t SOH t SCA t SOH t SCC t SCC t SDH t SDD Valid Sout Valid Sout Previous Row t SCP t SOH Valid Sout New Row High-Z SI/O (Input) t DQD t DQH QSF SAM Address MSB Preliminary Data Sheet E0160H10 43 ct du ro LP EO HM5316123B Series Read Transfer Cycle-2 t RC t RAS t RP RAS t CSH t CRP t RSH t CAS t RCD CAS t ASR Address t RAD t RAH t CAH SAM Start Address Row t WS t RAL t ASC t WH WEU, WEL High-Z I/O (Output) t DTS t DTH t DRD t DTP DT/OE t FSR t RFH DSF1 t SRS t SDH t SAH t SC t SCP t SOH t SRH t SIS t SIH t SZS Valid Sin t RQD t RQH t DQD t CQD t CQH t DQH QSF 44 t SCA t SCA t SCH SI/O (Input) t SCP Inhibit Rising Transition SC SI/O (Output) t SCC t SC SAM Address MSB Preliminary Data Sheet E0160H10 Valid Sout ct du ro LP EO HM5316123B Series Masked Write Transfer Cycle t RC t RP t RAS RAS t CSH t RCD CAS t ASR Address t RAH t CAS t ASC t CRP t RSH t CAH SAM Start Address Row t WS t WH WEU, WEL High-Z I/O (Output) DT/OE t DTS t DTH t FSR t RFH DSF1 t SRD t SRS t SC SC SI/O (Output) SI/O (Input) QSF I/O (Input) t SCA Valid t SOH t SCP t SRZ t SCC t SC t SCP Inhibit Rising Transition t SID Valid t SIS t SIH High-Z t RQD t CQH t RQH SAM Address MSB t MS t MH t CQD Valid Sin t SIS t SIH Valid Sin I/O Mask Data *1 Note: 1. I/O mask data (In new mask mode) Low: Mask High: Non mask I/O: Don't care in persistent mask mode. Preliminary Data Sheet E0160H10 45 ct du ro LP EO HM5316123B Series Split Read Transfer Cycle t RC t RP t RAS RAS t CSH t RSH t RCD t CRP t CRP t CAS CAS t RAD t ASR Address t RAL t RAH SAM Start *3 Address Yi Row t WS t CAH t ASC t WH WEU, WEL t OFF1 High-Z I/O (Output) t DTS t DTH t FSR t RFH DT/OE DSF1 t CST t AST t RST t SCC t SC t STS SC Bi *2 Ym*1 Ym + 1 SI/O (Input) Bj – 2 Valid Sout Valid Sout Valid Sout Valid Sout Valid Sout t SQD t SQD t SQH SAM Address MSB Notes: 1. Ym is the SAM start address in before SRT. 2. Bi, Bj initiate the boundary address. 3. A7 : H or L SAM start address can't set on the boundary address. 46 Bj *2 High-Z t SQH QSF Bj – 1 t SOH t SOH Valid Sout Ym + 2 t SCA t SCA SI/O (Output) t SCP Preliminary Data Sheet E0160H10 Yi ct du ro LP EO HM5316123B Series Masked Split Write Transfer Cycle t RC t RAS t RP RAS , t CSH t RSH t CAS t RCD CAS t ASR t RAH t ASC t CAH Row SAM Start Address Yi Address *4 t WS tWH WEU, WEL t OFF1 High-Z I/O (Output) t DTS t DTH DT/OE t FSR t RFH DSF1 t RST Bi*2 Ym*1 t CST t SCC t SC t SCP t STS SC t AST Ym+1 Ym+2 Bj-2 Bj-1 Bj*2 Yi SI/O (Output) t SIS SI/O (Input) Valid Sin t SIH Valid Sin t SIS t SIH Valid Sin Valid Sin Valid Sin Valid Sin t SQD t SQH t SQD t SQH SAM Address MSB QSF t CDD t MS I/O (Input) Valid Sin t SIS t SIH t MH I/O Mask Data*3 Notes: 1. Ym is the SAM start address in before SRWT. 2. Bi, Bj initiate the boundary address. 3. I/O Mask data (In new mask mode) Low: Mask High: Non mask I/O: Don't care in persistent mask mode. 4. A7: H or L SAM start address can't set on the boundary address. Preliminary Data Sheet E0160H10 47 ct du ro LP EO HM5316123B Series Serial Read Cycle SE tSCC tSCC tSC SC tSCP tSC tSCA tSOH tSEA tSCA tSLZ tSHZ Valid Sout tSCC tSCP tSC tSCA tSOH SI/O (Output) tSCP tSC Valid Sout Valid Sout Sereal Write Cycle tSWH tSWIS tSWIH tSWS SE tSCC tSC tSCC tSCC tSCP tSC tSC tSCP tSCP tSC SC tSIS SI/O (Input) 48 tSIH Valid Sin tSIS tSIH Valid Sin Preliminary Data Sheet E0160H10 tSIS tSIH Valid Sin Valid Sout ct du ro LP EO HM5316123B Series Package Dimensions HM5316123BF Series (FP-64DS) Unit: mm 26.2 27.0 Max 33 11.60 64 1 13.8 ± 0.2 0 – 10° +0.30 0.16 M 0.80 0.10 0.05 Min 0.20 Max 0.30 +0.08 –0.02 +0.08 1.10 Max 0.17 –0.07 3.0 Max 32 Preliminary Data Sheet E0160H10 0.50 –0.25 49 HM5316123B Series ct du ro LP EO Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. 50 Preliminary Data Sheet E0160H10