Hynix HY57V641620HGT-H 4 banks x 1m x 16bit synchronous dram Datasheet

HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM
D E S C R IP T IO N
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
Auto refresh and self refresh
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
•
Programmable Burst Length and Burst Type
•
Single 3.3± 0 . 3 V
•
•
power supply
Note)
of pin pitch
- 1, 2, 4, 8 or Full page for Sequential Burst
•
All inputs and outputs referenced to positive edge of
- 1, 2, 4 or 8 for Interleave Burst
system clock
•
Data mask function by UDQM or LDQM
•
Internal four banks operation
•
Programmable CAS Latency ; 2, 3 Clocks
O R D E R IN G IN F O R M A T IO N
Part No.
C lock Frequency
Power
Organization
HY57V641620HGT-5/55/6/7
200/183/166/143MHz
HY57V641620HGT-K
133MHz
HY57V641620HGT-H
133MHz
HY57V641620HGT-8
125MHz
HY57V641620HGT-P
100MHz
HY57V641620HGT-S
100MHz
4Banks x 1Mbits
HY57V641620HGLT-5/55/6/7
200/183/166/143MHz
x16
HY57V641620HGLT-K
133MHz
HY57V641620HGLT-H
133MHz
HY57V641620HGLT-8
125MHz
HY57V641620HGLT-P
100MHz
HY57V641620HGLT-S
100MHz
Interface
Package
LVTTL
400mil 54pin TSOP II
Normal
Low power
N o t e : V D D ( M in ) o f H Y 5 7 V 6 4 1 6 2 0 H G ( L ) T - 5 /5 5 / 6 i s 3 . 1 3 5 V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.5/Jun.01
HY57V641620HG
P IN C O N F IG U R A T IO N
VDD
1
54
V SS
DQ0
2
53
DQ15
VDDQ
3
52
V SSQ
DQ1
4
51
DQ14
DQ2
5
50
DQ13
VSSQ
6
49
V DDQ
DQ3
7
48
DQ12
DQ4
8
47
DQ11
VDDQ
9
46
V SSQ
DQ5
10
45
DQ10
DQ6
11
44
DQ9
VSSQ
12
43
V DDQ
DQ7
13
54pin TSOP II
42
DQ8
VDD
14
400mil x 875mil
41
V SS
LDQM
15
0.8mm pin pitch
40
NC
/WE
16
39
UDQM
/CAS
17
38
CLK
/RAS
18
37
CKE
/CS
19
36
NC
BA0
20
35
A11
BA1
21
34
A9
A10/AP
22
33
A8
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VDD
27
28
V SS
P IN D E S C R IP T IO N
PIN
P I N N A M E
CLK
Clock
CKE
Clock Enable
CS
Chip Select
BA0,BA1
Bank Address
A0 ~ A11
Address
Row Address Strobe,
R A S , C A S, W E
Column Address Strobe,
Write Enable
D E S C R IPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity
S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
R A S , C A S and W E define the operation
Refer function truth table for details
LDQM, UDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
V D D /V S S
Power Supply/Ground
Power supply for internal circuits and input buffers
V D D Q /V S S Q
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
Rev. 0.5/Jun.01
2
HY57V641620HG
F U N C T IO N A L B L O C K D IA G R A M
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic
Internal Row
& timer
counter
1Mx16 Bank 3
CLK
Row
Row active
1Mx16 Bank 2
Decoders
C S
Cell
Array
Column
Active
Pre
U D Q M
Decoders
D Q 0
I/O Buffer & Logic
Memory
Sense AMP & I/O Gate
Column
X decoders
W E
refresh
1Mx16 Bank 0
X decoders
C A S
State Machine
R A S
1Mx16 Bank 1
X decoders
X decoders
Pre
C K E
D Q 1
DQ14
DQ15
L D Q M
Y decoders
Column Add
Bank Select
A 0
Address
A 1
Registers
Counter
Address buffers
Burst
Counter
A11
B A 0
B A 1
Rev. 0.5/Jun.01
CAS Latency
Mode Registers
Data Out Control
Pipe Line Control
3
HY57V641620HG
A B S O L U T E M A X IM U M R A T IN G S
P a r a m e ter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TS T G
-55 ~ 125
°C
Voltage on Any Pin relative to V S S
V IN, V O U T
-1.0 ~ 4.6
V
Voltage on V D D relative to V S S
VDD, VD D Q
-1.0 ~ 4.6
V
Short Circuit Output Current
IO S
50
mA
Power Dissipation
PD
1
W
Soldering Temperature ⋅ T i m e
TSOLDER
260 ⋅ 10
°C ⋅ S e c
N o te : O p e r a t i o n a t a b o v e a b s o l u t e m a x i m u m r a t i n g c a n a d v e r s e l y a f f e c t d e v i c e r e l i a b i l i t y
D C O P E R A T IN G C O N D IT IO N
P a r a m e ter
( T A = 0 t o 7 0 °C )
Symbol
M in
Typ.
Max
U n it
N o te
Power Supply Voltage
VD D , VDDQ
3.0
3.3
3.6
V
1,2
Input High Voltage
V IH
2.0
3.0
V DDQ + 2.0
V
1,3
Input Low Voltage
V IL
V S S Q - 2.0
0
0.8
V
1,4
N o te :
1.All voltages are referenced to VSS = 0 V
2.VDD(min) of HY57V641620HG(L)T-5/55/6 is 3.135V
3.V IH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration
4.V IL (min) is acceptable -2.0V AC pulse width with ≤ 3ns of duration
A C O P E R A T IN G C O N D IT IO N
( T A = 0 t o 7 0 ° C , V D D = 3 . 3 ± 0 . 3 VN o t e 2 , V S S = 0 V )
P a r a m e ter
S y m b o l
Value
U n it
AC Input High / Low Level Voltage
V I H / V IL
2.4/0.4
V
Vtrip
1.4
V
tR / tF
1
ns
Voutref
1.4
V
CL
50
pF
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level
Output Load Capacitance for Access Time Measurement
Note
1
N o te :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
2.VDD(min) of HY57V641620HG(L)T-5/55/6 is 3.135V
Rev. 0.5/Jun.01
4
HY57V641620HG
C A P A C IT A N C E
( T A = 2 5° C , f = 1 M H z )
Parameter
P in
Input capacitance
S y m b o l
M in
Max
Unit
CLK
C I1
2
4
pF
A0 ~ A11, BA0, BA1, CKE, C S, RAS,
CI 2
2.5
5
pF
C I/O
2
6.5
pF
CAS, W E, UDQM, LDQM
Data input / output capacitance
DQ0 ~ DQ15
O U T P U T L O A D C IR C U IT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
50 pF
DC Output Load Circuit
D C C H A R A C T E R IS T IC S I ( T A = 0
P a r a m e ter
Symbol
AC Output Load Circuit
t o 7 0 ° C , V DD =3.3 ± 0 . 3 V Note3)
M in.
Max
Unit
Note
Input Leakage Current
IL I
-1
1
uA
1
Output Leakage Current
IL O
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IO H = - 4 m A
Output Low Voltage
VOL
-
0.4
V
IO L = + 4 m A
N o te :
1 . V I N = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t t e s t e d u n d e r V IN = 0 V
2.DO U T is disabled, V O U T =0 to 3.6
Rev. 0.5/Jun.01
5
HY57V641620HG
D C C H A R A C T E R IS T IC S II ( T A = 0
t o 7 0 °C , V D D = 3 . 3 ± 0 . 3 V
Note5
, VSS =0V)
Speed
Parameter
S y m b o l
Test Condition
Burst length=1, One bank active
Operating Current
ID D 1
Precharge Standby
ID D 2 P
C K E ≤ V IL(max), tC K = min
ID D 2 P S
C K E ≤ V IL(max), tC K =
tRC ≥ tRC ( m i n ) , I O L = 0 m A
-5
-55
-6
-7
-K
-H
-8
-P
-S
100
95
90
85
85
85
80
80
80
Unit
N o te
mA
1
2
mA
2
mA
15
mA
12
mA
6
mA
5
mA
30
mA
20
mA
Current
in Power Down Mode
∞
C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K
= min
Precharge Standby
ID D 2 N
Input signals are changed one time
during 2clks. All other pins ≥ V DD -
Current
0.2V or ≤ 0.2V
in Non Power Down Mode
ID D 2 N S
C K E ≥ V IH ( m i n ) , t C K =
∞
Input signals are stable.
Active Standby Current
in Power Down Mode
ID D 3 P
C K E ≤ V IL(max), tC K = min
ID D 3 P S
C K E ≤ V IL(max), tC K =
∞
C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K
= min
ID D 3 N
Input signals are changed one time
Active Standby Current
during 2clks. All other pins ≥ V DD -
in Non Power Down Mode
0.2V or ≤ 0.2V
ID D 3 N S
Burst Mode Operating
Current
ID D 4
C K E ≥ V IH ( m i n ) , t C K =
∞
Input signals are stable.
tC K ≥ tC K ( m i n ) , I O L = 0 m A
All banks active
CL=3
170
160
150
150
CL=2
NA
NA
NA
NA
Auto Refresh Current
ID D 5
t R R C ≥ tR R C ( m i n ) , A l l b a n k s a c t i v e
Self Refresh Current
ID D 6
C K E ≤ 0.2V
150
150
120
120
120
120
mA
1
mA
160
mA
2
1
mA
3
400
uA
4
N o te :
1.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh R A S cycle time) is shown at AC CHARACTERISTICS II
3.HY57V641620HGT-6/7/K/H/P/S
4.HY57V641620HGLT-6/7/K/H/P/S
Rev. 0.5/Jun.01
6
HY57V641620HG
A C C H A R A C T E R IS T IC S I ( A C
operating conditions unless otherwise noted)
-5
Parameter
C A S Latency =
cycle time
3
tCK3
Max
55
Min
M a x
55
1000
C A S Latency =
2
-6
-7
-K
-H
-8
-P
-S
Unit
M in
System clock
-55
Symbol
M in
Max
6
Max
7
100
1000
M a x
7.5
1000
0
Max
7.5
1000
Max
8
1000
10
M in
Max
10
1000
10
Min
10
1000
10
Note
Max
ns
1000
tCHW
2.5
-
2.75
-
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Clock low pulse width
tCLW
2.5
-
2.75
-
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
tAC3
-
5.4
-
5.4
-
5.4
-
5.4
-
5.4
5.4
-
6
6
-
6
ns
tAC2
-
6
-
6
-
6
-
6
-
5.4
6
-
6
-
6
-
8
ns
from clock
7.5
M in
Clock high pulse width
3
10
M in
10
C A S Latency =
10
M in
tCK2
Access time
10
Min
12
ns
2
C A S Latency =
2
Data-out hold time
tOH
2.5
-
2.5
-
2.7
-
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
ns
Data-Input setup time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Data-Input hold time
tDH
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Address hold time
tAH
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
CKE hold time
tCKH
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Command hold time
tCH
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1
-
1.5
-
1.5
-
1.5
-
1
-
1
-
2
-
ns
3
6
CLK to data
output in high
Z-time
C A S Latency =
3
tOHZ3
5.4
C A S Latency =
2
5.4
tOHZ2
5.4
5.4
5.4
5.4
ns
6
3
6
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.5/Jun.01
7
HY57V641620HG
A C C H A R A C T E R IS T IC S I
Parameter
-5
S y m b o
l
-55
-6
-7
-K
-H
-8
-P
-S
Unit
M in
Max
M in
Max
M in
Max
M in
Max
M in
Max
M in
Max
M in
Max
Min
Max
M in
Max
Operation
tRC
55
-
55
-
60
-
62
-
65
-
65
-
68
-
70
-
70
-
ns
Auto Refresh
tR R C
60
-
60
-
60
-
62
-
65
-
65
-
68
-
70
-
70
-
ns
R A S to C A S Delay
tR C D
15
-
16.5
-
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
R A S Active Time
tR A S
38.5
100K
38.5
100K
42
100
K
42
120K
45
120K
45
120K
48
100
K
50
120K
50
120K
ns
RAS Precharge Time
tR P
15
-
16.5
-
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
tR R D
10
-
11
-
12
-
14
-
15
-
15
-
16
-
20
-
20
-
ns
tC C D
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
tW T L
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-In to Precharge
Command
tD P L
2
-
2
-
2
-
1
-
1
-
1
-
2
-
1
-
1
-
CLK
Data-In to Active Command
tD A L
5
-
5
-
5
-
4
-
4
-
4
-
5
-
3
-
3
-
CLK
DQM to Data-Out Hi-Z
tD Q Z
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tD Q M
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command
tM R D
2
-
2
-
2
-
1
-
1
-
1
-
2
-
1
-
1
-
CLK
3
-
3
-
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
R A S Cycle
Time
R A S to R A S Bank Active
Delay
C A S to C A S Delay
Write Command to Data-In
Delay
Precharge to
Data Output
Hi-Z
CAS Latency
= 3
tP R O Z
CAS Latency
tP R O Z
= 2
2
3
Power Down Exit Time
tP D E
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tS R E
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Refresh Time
tR E F
-
64
-
64
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
Note
1
N o te :
1. A new command can be given tRRC after self refresh exit
Rev. 0.5/Jun.01
8
HY57V641620HG
D E V IC E O P E R A T IN G O P T IO N T A B L E
H Y 5 7 V 6 4 1 6 2 0 H G (L)T-5
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tO H
200MHz(5ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.5ns
183MHz(5.5ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.5ns
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.7ns
H Y 5 7 V 6 4 1 6 2 0 H G (L)T-55
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tO H
183MHz(5.5ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.5ns
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.7ns
143MHz(7ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.7ns
H Y 5 7 V 6 4 1 6 2 0 H G (L)T-6
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tO H
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.7ns
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
133MHz(7.5ns)
2CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tO H
H Y 5 7 V 6 4 1 6 2 0 H G (L)T-7
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
133MHz(7.5ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tO H
133MHz(7.5ns)
2CLKs
2CLKs
6CLKs
8CLKs
2CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
H Y 5 7 V 6 4 1 6 2 0 H G (L)T-K
H Y 5 7 V 6 4 1 6 2 0 H G (L)T-H
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tO H
133MHz(7.5ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
Rev. 0.5/Jun.01
9
HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM
H Y 5 7 V 6 4 1 6 2 0 H G (L)T-8
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tO H
125MHz(8ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
3CLKs
6ns
3ns
83MHz(12ns)
3CLKs
3CLKs
6CLKs
9CLKs
2CLKs
6ns
3ns
H Y 5 7 V 6 4 1 6 2 0 H G (L)T-P
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tO H
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
H Y 5 7 V 6 4 1 6 2 0 H G (L)T-S
C A S Latency
tRCD
tRAS
tRC
tRP
tAC
tO H
100MHz(10ns)
3CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.5/Jun.01
HY57V641620HG
COMMAND TRUTH TABLE
C o m m a n d
A10/
A D D R
CKEn-1
C K E n
C S
R A S
C A S
W E
D Q M
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
AP
RA
Read
Note
V
L
CA
Read with Autoprecharge
V
H
Write
L
H
X
L
H
L
L
X
CA
Write with Autoprecharge
H
X
L
L
H
L
X
Burst Stop
H
X
DQM
H
Auto Refresh
H
H
L
L
L
Entry
H
L
L
L
H
H
H
X
Exit
L
H
L
L
V
X
V
X
H
X
X
L
H
X
X
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge
X
X
X
Self Refresh1
H
L
H
X
Precharge selected Bank
Entry
V
H
Precharge All Banks
X
X
power down
Exit
Clock
BA
Entry
L
H
H
L
Suspend
Exit
L
X
H
X
X
X
X
N o te :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2 . X = D o n′ t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s ,
Opcode = Operand Code, NOP = No Operation
Rev. 0.5/Jun.01
11
HY57V641620HG
P A C K A G E IN F O R M A T IO N
4 0 0 m i l 5 4 p i n T h i n S m all O u t l i n e P a c k a g e
UNIT : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0.150(0.0059)
0.050(0.0020)
0.80(0.0315)BSC
Rev. 0.5/Jun.01
0.400(0.016)
0.300(0.012)
1.194(0.0470)
0.991(0.0390)
5deg
0deg
0.597(0.0235)
0.406(0.0160)
0.210(0.0083)
0.120(0.0047)
12
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