APA3541/4
Class AB Stereo Headphone Driver with Mute
Features
Applications
•
•
•
•
•
•
•
•
•
•
•
•
High Signal-to-Noise Ratio
High Slew Rate
Low Distortion
Large Output Voltage Swing
Flexible Mute Function
Excellent Power Supply Ripple Rejection
Low Power Consumption
Short-circuit Elimination
Wide Temperature Range
No Switch ON/OFF Clicks
Integrated Voltage Divider (VDD/2) to Eliminate
External Resistors
Portable Digital Audio
General Description
The APA3541/4 is an integrated class AB stereo
headphone driver contained in an SO-8 or a DIP-8
plastic package with Mute feature . Besides the common Mute feature , the APA3541/4 further integrates
a voltage divider inside the chip . Thus , the external
resistors can be eliminated . The APA3541 has a fixed
gain of 0dB and the APA3544 has a fixed gain of 6dB
so that external gain setting is unnecessary. The device is fabricated in a CMOS process and has been
primarily developed for portable digital audio applications .
Ordering and Marking Information
A P A 3 5 4 1 /4
P ackage C ode
J : P D IP - 8
Y : C h ip F ro m
T em p. R ange
I : - 4 0 to 8 5 ° C
H a n d lin g C o d e
TU : Tube
H a nd lin g C o d e
T em p. R ange
P a ck a g e C o d e
A P A 3 5 4 1 /4 J :
A P A 3 5 4 1 /4
XXXXX
X X X X X - D a te C o d e
A P A 3 5 4 1 /4 K :
A P A 3 5 4 1 /4
XXXXX
X X X X X - D a te C o d e
K : SOP - 8
TR : Tape & Reel
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. B.1 - Apr., 2003
1
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APA3541/4
Block Diagram
M UTE
O ut A
1
0dB
(6dB )
M ute
Input A
2
A
B
+
+
3
V SS
V DD
7
O ut B
6
BIAS
5
Input B
0dB
(6dB )
B IAS
180k Ω
( 90k Ω )
8
180k Ω
( 90k Ω )
4
* The values in parenthessis are for the APA3544.
Function Pin Description
Pin Name
Out A
Mute
Input A
VSS
Input B
BIAS
OUT B
VDD
I/O
O
I
I
I
I
O
Function Description
A channel output pin
Chip disable control input, low active and high for normal operating
A channel input terminal
Power ground pin
B channel input terminal
Right channel bias input pin
B channel output pin
Power input pin
Absolute Maximum Ratings
Symbol
VDD
tSC(O)
Parameter
Supply Voltage
TA
Output Short-circuit Duration, at TA=25°C, Ptot=1W
Operating Ambient Temperature range
TJ
Maximum Junction Temperature
TSTG
TS
VESD
Storage Temperature Range
Soldering Temperature,10 seconds
Rating
7
Unit
V
20
S
-40 to 85
°C
150
°C
-65 to +150
°C
°C
V
300
Electrostatic Discharge
-3000 to 3000
*1
Note: 1. Human body model : C=100pF, R=1500Ω, 3 positive pulses plus 3 negative pulses
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
2
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APA3541/4
Thermal Characteristics
Symbol
RTHJA
RTHJC
Parameter
Thermal Resistance from Junction to Ambient in Free Air
DIP-8
SOP-8
Thermal Resistance from Junction to Case
DIP-8
SOP-8
Rating
Unit
108
210
K/W
45
40
K/W
Electrical Characteristics
VIN=0dBV, VCC=5V, TA=25°C, f=1kHz, RL=32Ω (unless otherwise noted)
APM3541/4
Symbol
Parameter
Test Condition
Unit
Min. Typ. Max.
VDD
IQ
Imute
VTM
∆GVCL
Supply Voltage
Quiescent Current
3.0
VIN= 0 Vrms
Mute Current
THD
Mute Terminal Voltage
PU2
V
3.5
5
mA
µA
0.3
0.7
1.6
V
-0.5
0
0.5
dB
APA3541
-2
0
2
Vin=0.5Vrms, f=1kHz,Rl=32Ω APA3544
4
6
8
0.03
0.1
Differential Channel
Voltage Gain
Voltage Gain
Total Harmonic Channel
Distortion Factor
PU1
6.0
200
Vin=1Vrms,f= 1kHz,RL=32Ω
GVCL
5.0
Rated Output Power1
Rated Output Power2
dB
BW<80kHz
RL=32Ω,THD+N=0.1%,BW<8 APA3541
50
55
0kHz
APA3544
75
80
RL=16Ω,THD+N=0.1%,BW<8 APA3541
105
110
0kHz
140
145
APA3544
VNO
Output Noise Voltage
BW=20~20kHz , Vin=0Vrms
CS
Channel Separation
F=1kHz
%
mW
mW
-93
APA3541
-90
-95
APA3544
-65
-70
-85
dBV
dB
ATT
Mute Attenuation
VIN=1Vrms,f=1kHz,Mute=L
65
70
dB
RR
Ripple Rejection
FRR=100Hz,VRR=-20dBV
50
60
dB
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
3
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APA3541/4
Test and Application Circuit
1µ F
220 µ F
V IN B
10µF
Input B
5
6
V DD
VDD
O ut B
B IAS
7
8
100 µ F
B IAS
0dB(6dB)
+
B
+
A
A PA 3541
(A PA 3544)
0dB(6dB)
M UT E
4
V SS
3
Input A
2
M ute
1
O ut A
1µ F
100k Ω
V IN A
V MU TE
H : S peaker Action
L : M ute on
1µ F
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
220 µ F
4
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APA3541/4
Typical Characteristics
5
Ω
RL=32Ω
7
Ω
RL=32Ω
Bias DC Voltage :Vbias (V)
Quiescent Current : IQ (mA)
8
6
5
MUTE : OFF
4
3
2
MUTE : ON
1
0
4
3
2
1
0
0
1
2
3
4
5
6
7
0
2
3
10
+8
0
+6
APA3541
+4
VDD=5V
-10
VDD=5V
-20
VIN=0dBv
-30
f =1 kHz
Ω
RL=32Ω
-40
4
5
6
7
Figure 2 : Supply Voltage : VDD (V)
Voltage Gain : GVC (dB)
Output Voltage : VOUT (dBV)
Figure 1 : Supply Voltage : VDD (V)
1
-50
-60
-70
+2
VIN=0dBv
+0
-2
-4
-6
-8
-10
-80
0
0.4
0.8
1.2
1.6
-12
10
2
Figure 3 : Mute Control Voltage : VTM (V)
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
100
1k
10k
100k
Figure 4 : Frequency :f (Hz)
5
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APA3541/4
Typical Characteristics Cont.
10
VDD= 5V
Ω
RL=32Ω
2
BW< 80kHz
1
0.5
0.2
f =10kHz
0.1
0.05
f =1kHz , 100Hz
0.02
0.01
-40
-30
-20
-10
+0
Total Harmonic Distortion : THD+N (%)
Total Harmonic Distortion : THD+N (%)
VDD= 5V
Ω
RL=16Ω
BW< 80kHz
1
0.5
f =10kHz
0.2
0.1
0.05
f =1kHz , 100Hz
0.02
0.01
-40
-30
-20
-10
+0
+10
Figure 7 : Output Voltage : VOUT (dBv)
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
2
Ω
RL=32Ω
BW< 80kHz
1
0.5
0.2
f =10KHz
0.1
0.05
f =1KHz , 100Hz
0.02
0.01
-40
-30
-20
-10
+0
+10
Figure 6 : Output Voltage : VOUT (dBv)
10
2
VDD= 3V
+10
Figure 5 : Output Voltage : VOUT (dBv)
5
5
(%)
5
Total Harmonic Distortion : THD+N
Total Harmonic Distortion : THD+N
(%)
10
10
VDD= 3V
5
Ω
RL=16Ω
2
BW< 80kHz
1
0.5
f =10kHz
0.2
0.1
0.05
f =1kHz , 100Hz
0.02
0.01
-40
-30
-20
-10
+0
+10
Figure 8 : Output Voltage : VOUT (dBv)
6
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APA3541/4
Typical Characteristics Cont.
+0
VDD=5V
-20
Ω
RL=32Ω
Mute Attenuationt : ATT(dB)
Channel Separation : CS (dB)
+0
-40
-60
-80
-100
-120
10
100
1k
10k
-10
VDD=5V
-20
VIN=0dBv
-30
Ω
RL=32Ω
-40
-50
-60
-70
-80
-90
100
10
100k
Figure 9 : Frequency :f (Hz)
50
100
1k
10k
100k
Figure 10 : Frequency :f (Hz)
0
Ripple Rejection : RR (dB)
-1 0
-2 0
fRR=100Hz
VRR=-20dBv
-3 0
-4 0
-5 0
-6 0
-7 0
-8 0
-9 0
-1 0 0
0
1
2
3
4
5
6
7
Figure 11 : Supply Voltage : VDD (V)
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
7
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APA3541/4
Application Note
pacitors are recommended for the best THD and
noise performance .
Input Capacitor , Ci
In the typical application an input capacitor , Ci , is
required to allow the amplifier to bias the input signal
to the proper DC level for optimum operation . In this
case , the external capacitor Ci and the internal resistance Ri form a high-pass filter with the corner frequency determined in the follow equation:
Output Coupling Capacitor, Cc
In the typical single-supply SE configuration , an output coupling capacitor (Cc) is required to block the
DC bias at the output of the amplifier thus preventing
DC currents in the load . As with the input coupling
capacitor , the output coupling capacitor and impedance of the load form a high-pass filter governed by
equation .
fc (highpass)= 1/ (2πRiCi)
(1)
The value of Ci is important to consider as it directly
affects the low frequency performance of the circuit.
Consider the APA3541 where Ri is 180kΩ and
APA3544 is 90kΩ internal fixed . Equation is
reconfigured as follow:
Ci= 1/(2π*180kΩ*fc) for APA3541
Ci= 1/(2π*90kΩ*fc) for APA3544
And the ceramic capacitor is recommanded.
fc(highpass)= 1/(2πRLCc)
(4)
For example , a 220µF capacitor with an 32Ω speaker
would attenuate low frequencies below 22Hz . The
main disadvantage , from a performance standpoint
, is the load impedance is typically small , which drives
the low-frequency corner higher degrading the bass
response . Large values of Cc are required to pass
low frequencies into the load .
(2)
Bias Capacitor , Cb
Optimizing Depop Circuitry
As with any power amplifier , proper supply bypassing is critical for low noise performance and high
power supply rejection . The capacitor location on
both the bypass and power supply pins should be as
close to the device as possible . The effect of a larger
half supply bias capacitor is improved PSRR due to
increased half-supply stability . Typical applications
employ a 5V regulator with 10µF and a 0 . 1µF bias
capacitors which aid in supply filtering .
When the amplifier is in mute mode , both of the output stage and input bypass continues to be biased .
And no pop noise will be heard during the transition
out of mute mode .
Power Supply Decoupling, Cs
APA3541/4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD)
is as low as possible . Power supply decoupling also
prevents the oscillations causing by long lead length
between the amplifier and the speaker . The optimum
decoupling is achieved by using two different type
capacitors that target on different type of noise on
the power supply leads . For higher frequency transients , spikes , or digital hash on the line , a good
low equivalent-series-resistance (ESR) ceramic
capacitor, typically 0.1µF placed as close as possible
to the device V lead works best . For filtering lowerDD
frequency noise signals , a large aluminum electrolytic capacitor of 10µF or greater placed near the audio
power amplifier is recommended .
This does not eliminate the need for bypassing the
supply nodes of the APA3541/4 . The selection of
bias capacitors , especially Cb , is thus dependent
upon desired PSRR requirements , click and pop performance . The capacitor is fed from a 95kΩ source
inside the amplifier . To keep the start-up pop as low
as possible , the relationship shown in equation should
be maintained .
1/(Cb*95kΩ)≤ 1/{Ci*Ri}
(3)
As an example , consider a circuit where Cb is
4.7µF, Ci is 1µF and APA3541 Ri is 180kΩ . Inserting
these values into the equation we get 2.24≤ 5.55
which satisfies the rule . Bias capacitor , Cb , values
of 2.2µF to 10µF ceramic or tantalum low-ESR ca-
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
8
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APA3541/4
Packaging Information
PDIP-8 pin ( Reference JEDEC Registration MS-001)
D
E1
E
1
1
A2
A
E3
A1
L
e2
e1
e3
Dim
Millimeters
Min.
A
A1
A2
D
e1
e2
e3
E
E1
E3
L
φ1
Inches
Max.
5.33
0.38
2.92
9.02
Min.
3.68
10.16
0.015
0.115
0.355
0.56
1.78
0.014
0.045
7.11
10.92
3.81
0.240
2.54BSC
0.36
1.14
2.92
0.022
0.070
0.300 BSC
0.280
0.430
0.150
0.115
15°
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
0.145
0.400
0.100BSC
7.62 BSC
6.10
Max.
0.210
15°
9
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APA3541/4
Packaging Information
E
e1
0.015X45
SOP-8 pin ( Reference JEDEC Registration MS-012)
H
e2
D
A1
1
L
0.004max.
Dim
A
Mi ll im et er s
Inche s
A
Min .
1. 35
Max .
1. 75
Min.
0. 053
Max .
0. 069
A1
D
E
0. 10
4. 80
3. 80
0. 25
5. 00
4. 00
0. 004
0. 189
0. 150
0. 010
0. 197
0. 157
H
L
e1
e2
5. 80
0. 40
0. 33
6. 20
1. 27
0. 51
0. 228
0. 016
0. 013
0. 244
0. 050
0. 020
φ 1
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
1. 27B S C
0. 50B S C
8°
8°
10
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APA3541/4
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
temperature
Reference JEDEC Standard J-STD-020A APRIL 1999
Peak temperature
183°C
Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/
Convection
Average ramp-up rate(183°C to Peak)
3°C/second max.
120 seconds max
Preheat temperature 125 ± 25°C)
60 – 150 seconds
Temperature maintained above 183°C
Time within 5°C of actual peak temperature 10 –20 seconds
Peak temperature range
220 +5/-0°C or 235 +5/-0°C
Ramp-down rate
6 °C /second max.
6 minutes max.
Time 25°C to peak temperature
VPR
10 °C /second max.
60 seconds
215-219°C or 235 +5/-0°C
10 °C /second max.
Package Reflow Conditions
pkg. thickness ≥ 2.5mm
and all bgas
Convection 220 +5/-0 °C
VPR 215-219 °C
IR/Convection 220 +5/-0 °C
pkg. thickness < 2.5mm and
pkg. volume ≥ 350 mm³
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
11
pkg. thickness < 2.5mm and pkg.
volume < 350mm³
Convection 235 +5/-0 °C
VPR 235 +5/-0 °C
IR/Convection 235 +5/-0 °C
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APA3541/4
Reliability test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245° C , 5 SEC
1000 Hrs Bias @ 125 ° C
168 Hrs, 100 % RH , 121 ° C
-65° C ~ 150° C , 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ao
D1
Ko
T2
J
C
A
B
T1
Application
SOP- 8
A
B
C
J
T1
T2
W
P
E
330 ± 1
62 +1.5
12.75+
0.15
2 ± 0.5
12.4 ± 0.2
2 ± 0.2
12± 0. 3
8± 0.1
1.75±0.1
F
D
D1
Po
P1
Ao
Bo
Ko
t
4.0 ± 0.1
2.0 ± 0.1
6.4 ± 0.1
5.2± 0. 1
2.1± 0.1
0.3±0.013
5.5± 1
1.55 +0.1 1.55+ 0.25
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
12
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APA3541/4
Cover Tape Dimensions
Application
SOP- 8
Carrier Width
12
Cover Tape Width
9.3
Devices Per Reel
2500
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ANPEC Electronics Corp.
Rev. B.1 -Apr., 2003
13
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