Integrated, Precision Battery Sensor for Automotive Systems ADuCM330/ADuCM331 Data Sheet FEATURES Memory 96 kB (ADuCM330)/128 kB (ADuCM331) Flash/EE memory, ECC 6 kB SRAM, ECC 4 kB data Flash/EE memory, ECC 10,000 cycle Flash/EE endurance 20 year Flash/EE retention In circuit download via SWD and LIN On-chip peripherals Serial port interface (SPI) General-purpose input/output (GPIO) port General-purpose timer Wake-up timer Watchdog timer On-chip, power-on reset Power Operates directly from 12 V battery supply Power consumption, 8 mA typical (16 MHz) Low power monitor mode Package and temperature range 32-lead, 6 mm × 6 mm LFCSP Fully specified for −40°C to +115°C operation; additional specifications for 115°C to 125°C Qualified for automotive applications High precision analog-to-digital converters (ADCs) Dual channel, simultaneous sampling I-ADC 20-bit Σ-Δ (minimizes range switching) VADC/TADC 20-bit Σ-Δ Programmable ADC conversion rate from 1 Hz to 8 kHz On-chip ±5 ppm/°C voltage reference Current channel Fully differential, buffered input Programmable gain (from 4 to 512) ADC absolute input range: −200 mV to +300 mV Digital comparator with current accumulator feature Voltage channel Buffered, on-chip attenuator for 12 V battery input Temperature channel External and on-chip temperature sensor options Microcontroller ARM Cortex-M3 32-bit processor 16.384 MHz precision oscillator with 1% accuracy Serial wire download (SWD) port supporting code download and debug Automotive qualified integrated local interconnect network (LIN) transceiver LIN 2.2-compatible slave, 100 kb fast download option SAE J-2602-compatible slave Low electromagnetic emissions (EME) High electromagnetic immunity (EMI) APPLICATIONS Battery sensing/management for automotive and light mobility vehicles Lead acid battery measurement for power supplies in industrial and medical domains FUNCTIONAL BLOCK DIAGRAM SWDIO PRECISION ANALOG ACQUISITION IIN+ ADuCM330/ADuCM331 20-BIT ADC BUF IIN– LDO POR MEMORY 96kB (ADuCM330)/ 128kB (ADuCM331) FLASH, 6kB SRAM, 4kB DATA CORTEX-M3 PROCESSOR 16MHz PREC OSC 1% LPM 1 × GP TIMER WD TIMER W/U TIMER GPIO PORT SPI PORT LIN VBAT LIN 11153-004 GPIO0/CS/LIN_RX GPIO2/MISO GPIO1/SCLK/LIN_TX GPIO3/IRQ0/MOSI/ LC_TX/LIN_TX PRECISION REFERENCE VSS AGND DVDD18 AVDD18 VDD 33VDD TEMPERATURE SENSOR DGND GND_SW 20-BIT ADC BUF IO_VSS MUX VTEMP RESET DIGITAL COMPARATOR GPIO5/LC_TX/LIN_TX RESULT ACCUMULATOR GPIO4/IRQ1/LC_RX/ ECLKIN/LIN_RX PGA SWCLK Figure 1. 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Technical Support www.analog.com ADuCM330/ADuCM331 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 14 Applications ....................................................................................... 1 Design Guidelines ...................................................................... 14 Functional Block Diagram .............................................................. 1 Power and Ground Recommendations ................................... 14 Revision History ............................................................................... 2 Exposed Pad Thermal Recommendations .............................. 14 General Description ......................................................................... 3 General Recommendations....................................................... 14 Specifications..................................................................................... 4 Recommended Schematic ............................................................. 15 Absolute Maximum Ratings.......................................................... 10 Outline Dimensions ....................................................................... 16 ESD Caution ................................................................................ 10 Ordering Guide .......................................................................... 16 Pin Configuration and Function Descriptions ........................... 11 Automotive Products ................................................................. 16 Terminology .................................................................................... 13 REVISION HISTORY 10/15—Rev. B to Rev. C Changes to Table 2 .......................................................................... 10 7/15—Revision B: Initial Version Rev. C | Page 2 of 16 Data Sheet ADuCM330/ADuCM331 GENERAL DESCRIPTION The ADuCM330/ADuCM331 are fully integrated, 8 kSPS, data acquisition systems that incorporate dual, high performance multichannel sigma-delta (Σ-Δ) ADCs, a 32-bit ARM® Cortex™-M3 processor, and flash. The ADuCM330 has 96 kB program flash and the ADuCM331 has 128 kB program flash. Both devices have 4 kB data flash. The ADuCM330/ADuCM331 are complete system solutions for battery monitoring in 12 V automotive applications. The ADuCM330/ADuCM331 integrate all of the required features to precisely and intelligently monitor, process, and diagnose 12 V battery parameters including battery current, voltage, and temperature over a wide range of operating conditions. Minimizing external system components, the devices are powered directly from a 12 V battery. On-chip, low dropout (LDO) regulators generate the supply voltage for two integrated Σ-Δ ADCs. The ADCs precisely measure battery current, voltage, and temperature to characterize the state of the health and the charge of the car battery. The devices operate from an on-chip, 16.384 MHz high frequency oscillator that supplies the system clock. This clock is routed through a programmable clock divider from which the core clock operating frequency is generated. The devices also contain a 32 kHz oscillator for low power operation. The analog subsystem consists of an ADC with a programmable gain amplifier (PGA) that allows the monitoring of various current and voltage ranges. It also includes a precision reference on chip. The ADuCM330/ADuCM331 integrate a range of on-chip peripherals that can be configured under core software control as required in the application. These peripherals include a SPI serial input/output communication controller, six GPIO pins, one general-purpose timer, a wake-up timer, and a watchdog timer. The ADuCM330/ADuCM331 are specifically designed to operate in battery-powered applications where low power operation is critical. The microcontroller core can be configured in normal operating mode, resulting in an overall system current consumption of <18.5 mA when all peripherals are active. The devices can also be configured in a number of low power operating modes under direct program control, consuming <100 μA. The ADuCM330/ADuCM331 also include a LIN physical interface for single wire, high voltage communications in automotive environments. The devices operate from an external 3.6 V to 18 V (on VDD, Pin 26) voltage supply and is specified over the −40°C to +115°C temperature range, with additional typical specifications at +115°C to +125°C. The information in this data sheet is relevant for silicon Revisions L6x, where x represents a number between 0 and 9. For more information and register details for the ADuCM330/ ADuCM331, see the user guide ADuCM330/ADuCM331 Hardware Reference Manual, UG-716. Rev. C | Page 3 of 16 ADuCM330/ADuCM331 Data Sheet SPECIFICATIONS VDD = 3.6 V to 18 V, fCORE = 16.384 MHz, CD = 0, normal mode, VREF = 1.2 V (internal), unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise stated. Parameters not specified in the 115°C to 125°C temperature range of operation are functional within this range but with degraded performance Table 1. Parameter ADC SPECIFICATIONS Conversion Rate1 Current Channel (IIN+/IIN− Only) No Missing Codes1 Integral Nonlinearity1, 2 Positive Integral Nonlinearity (INL)1, 2, 3 Negative INL1, 2, 3 Offset Error1, 4, 5 Offset Error Drift1, 2, 6 Total Gain Error1, 4, 5, 7 Gain Drift1, 8 PGA Gain Mismatch Error Output Noise1 Test Conditions/Comments Min ADC normal operating mode ADC low power mode, chop on 4 1 Valid for all ADC update rates and ADC modes 20 TA = −40°C to +115°C Typ Max 8000 656 Unit Hz Hz Bits ±10 Chop off, gain = 4, 8, or 16, external short, after user system calibration at 25°C, 1 LSB = (2.28/gain) μV Chop off, gain = 32 or 64, external short, after user system calibration at 25°C, 1 LSB = (2.28/gain) μV Chop off, gain = 512, external short, after user system calibration at 25°C, 1 LSB = (2.28/gain) μV Chop on, external short, low power mode, gain = 64 or 512, processor powered down Chop on, external short, after user system calibration at 25°C, VDD = 18 V Chop off, gains of 4 to 64, normal mode Chop on Factory calibrated at a gain of 8, normal mode Low power mode TA = +115°C to +125°C1 Typ ±200 ±200 ±80 ±80 ppm of FSR ppm of FSR ±80 ppm of FSR LSBs −100 ±24 ±200 +100 −160 ±48 +160 LSBs −1400 ±60 +1400 LSBs −300 ±50 +250 ±250 nV +1.5 ±0.1 μV +0.5 ±5 ±0.15 LSB/°C nV/°C % −1.5 −0.5 −1 ADC0CON[11:10], PGASCALE = 0x3 Gain = 64, ADCFLT = 0x08101 Gain = 64, ADCFLT = 0x00007 Gain = 32, ADCFLT = 0x08101 Gain = 32, ADCFLT = 0x00007 Gain = 16, ADCFLT = 0x08101 Gain = 16, ADCFLT = 0x00007 Gain = 8, ADCFLT = 0x08101 Gain = 8, ADCFLT = 0x00007 Gain = 4, ADCFLT = 0x08101 Gain = 4, ADCFLT = 0x00007 Gain = 64, ADCFLT = 0x10001 Gain = 32, ADCFLT = 0x10001 Gain = 16, ADCFLT = 0x10001 Gain = 8, ADCFLT = 0x10001 Gain = 4, ADCFLT = 0x10001 ADC low power mode, 221 Hz update rate, chop enabled, gain = 64 Rev. C | Page 4 of 16 ±0.48 ±5 ±0.1 ±0.2 ±3 ±0.1 +1 ±0.2 ±3 ±0.1 % ppm/°C % 0.80 0.75 1.00 0.80 1.50 1.10 2.10 1.60 3.40 2.60 1.60 1.70 2.00 2.40 4.35 0.6 1.3 1.1 1.5 1.2 2.6 1.9 4.1 2.4 5.1 3.9 3 3.45 4.2 5.1 9.6 0.9 1.2 μV rms μV rms μV rms μV rms μV rms μV rms μV rms μV rms μV rms μV rms μV rms μV rms μV rms μV rms μV rms μV rms 1.3 2.0 2.5 4.0 2.0 2.1 2.2 3.2 5.5 0.8 Data Sheet Parameter Voltage Channel1, 9 No Missing Codes INL Offset Error 4, 5 Offset Error Drift6 Total Gain Error4, 5, 7 Gain Drift8 Output Noise10 Temperature Channel1 No Missing Codes INL Offset Error4, 11 Offset Error4 Offset Error Drift Total Gain Error4, 11 Gain Drift8 Output Noise ADC SPECIFICATIONS, ANALOG INPUT Current Channel1 Absolute Input Voltage Range Input Voltage Range12 ADuCM330/ADuCM331 Test Conditions/Comments Min Valid at all ADC update rates From 6 V to 18 V Chop off, 1 LSB = 27.4 μV, after two point calibration Chop on, after two-point calibration, offset measured using 0 V differential into voltage ADC (VADC) auxiliary pins Chop off Includes resistor mismatch TA = −25°C to +65°C Includes resistor mismatch drift 10 Hz update rate, chop on ADCFLT = 0x00007 ADCFLT = 0x08101 ADCFLT = 0x10001 20 Valid at all ADC update rates ±150 −160 Bits ppm of FSR LSB −16 ±4.8 +16 ±4.8 LSB ±1 ±0.1 LSB/°C % % ppm/°C μV rms μV rms μV rms μV rms −0.25 −0.15 −160 −80 −0.25 1 kHz update rate, ADCFLT = 0x00007 PGASCALE[11:10] = 0x2 Applies to both IIN+ and IIN− Unit ±350 +160 ±0.48 ±0.06 ±0.03 ±3 50 180 280 400 +0.25 +0.15 ±3 80 270 350 730 300 470 20 Chop off, 1 LSB = 1.14 μV (unipolar mode), after two point calibration Chop on Chop off ±10 ±48 ±60 +160 ±15 Bits ppm of FSR LSB +16 ±0.48 ±0.06 3 7.5 +80 ±16 ±0.48 ±0.10 3 10 LSB LSB/°C % ppm/°C μV rms −200 6 VBAT = 18 V VREF = (AVDD18, GND_SW) 5 11.25 mV ±150 ±37.5 mV mV nA nA +3 0.6 0 to 28.8 9 0 to 1.4 2.5 13 ±5 100 V 11 V μA 1500 mV 10 V nA 1.2 0.5 Rev. C | Page 5 of 16 ±0.2 0.4 18 100 −0.15 −20 mV ±300 0.2 Voltage ADC specifications are valid in this range +0.25 +300 −3 Measured at TA = 25°C TA = +115°C to +125°C1 Typ ±10 ±16 Gain = 4, limited by absolute input voltage range Gain = 8 Gain = 32 Input Leakage Current13 Input Offset Current13 Voltage Channel Absolute Input Voltage Range1 Input Voltage Range1 VBAT Input Current Temperature Channel Absolute Input Voltage Range1, 14 Input Voltage Range1 VTEMP Input Current1 VOLTAGE REFERENCE Internal Reference Power-Up Time1 Initial Accuracy1 Temperature Coefficient1, 15 Long-Term Stability16 TA = −40°C to +115°C Typ Max 1.2 0.5 +0.15 +20 ±8 V ms % ppm/°C ppm/1000 hr ADuCM330/ADuCM331 Parameter ADC DIAGNOSTICS AVDD18/136 Accuracy1, 2, 17 Voltage Attenuator Current Source Accuracy RESISTIVE ATTENUATOR Divider Ratio Resistor Mismatch Drift ADC GROUND SWITCH Resistor to Ground TEMPERATURE SENSOR1, 18 Accuracy POWER-ON RESET (POR)1 POR Trip Level POR Hysteresis LOW VOLTAGE FLAG (LVF) LVF Level WATCHDOG TIMER (WDT) Shortest Timeout Period Longest Timeout Period FLASH/EE MEMORY Endurance 19 Data Retention 20 LOGIC INPUTS1 Input Voltage Low, VINL High, VINH LOGIC OUTPUTS1 Data Sheet Test Conditions/Comments Min At any gain setting Differential voltage increase on the attenuator when current is on 12 2.4 Processor in hibernate mode TA = 115°C to 125°C TA = −40°C to +115°C TA = −25°C to +85°C TA = −10°C to +55°C Refers to voltage at the VDD pin Refers to voltage at the VDD pin Logic 1 Input Current (Leakage Current) Logic 0 Input Current (Leakage Current) Input Capacitance ON-CHIP OSCILLATORS Low Frequency Oscillator (LFOSC) Accuracy Unit 13 2.8 mV V ppm/°C 45 60 75 −3.5 −3 −2.5 −2 ±1 ±1 ±0.5 ±0.5 +3.5 +3 +2.5 +2 ±1 °C °C °C °C 2.8 3.1 0.1 3.4 3.3 V V 2.6 2.75 3.00 32,768 Hz clock with a prescaler of 1 32,768 Hz clock with a prescaler of 4096 30.5 8192 kΩ V 30.5 8192 10,000 20 µs sec Cycles Years 0.4 2.0 V V All logic outputs, measured with ±1 mA load 33VDD − 0.4 All digital inputs except RESET, SWDIO, and SWCLK VINH = 3.3 V VINL = 0 V V 0.4 V ±1 ±10 µA ±1 ±10 µA 10 pF 32,768 Hz ±5 After a calibration from HFOSC High Frequency Oscillator (HFOSC) Accuracy (LINCAL)1, 21 Accuracy (High Precision Mode) Accuracy (Low Precision Mode) 14 3.2 TA = +115°C to +125°C 1 Typ 24 ±3 Implicit in the voltage channel gain error specification Output Voltage High, VOH Low, VOL DIGITAL INPUTS1 TA = −40°C to +115°C Typ Max −6 +6 % % MHz +0.75 +1 % % +3 % 16.384 −0.75 −1 −3 Rev. C | Page 6 of 16 ±0.5 Data Sheet Parameter PROCESSOR START-UP TIME1 At Power-On Brownout After Reset Event Wake-Up from LIN LIN INPUT/OUTPUT GENERAL1 Baud Rate VDD LIN Comparator Response Time LIN DC PARAMETERS ILIN_DOM_MAX ADuCM330/ADuCM331 Test Conditions/Comments Includes kernel power-on execution time, VDD drops to < 0.8 V VDD drops below power on reset voltage but not below 0.8 V Includes kernel power-on execution time Supply voltage range for which the LIN interface is functional VLIN_DOM1 VLIN_REC1 VLIN_CNT1 VHYS1 VHYS = VTH_REC − VTH_DOM VLIN_DOM_DRV_LOSUP1 LIN dominant output voltage, VDD = 7.0 V ILIN_PAS_DOM1 ILIN_NO_GND1, 22 IBUS_NO_BAT1 RL = 500 Ω RL = 1000 Ω VLIN_DOM_DRV_HISUP1 ms 1.25 ms 0.15 ms 40 20,000 18 Bits/sec V 90 µs 200 mA 20 µA −1 mA −1 0.5 × VDD +1 mA 30 µA 0.4 × VDD V V V 0.525 × VDD 0.175 × VDD V 1.2 V V 2 V V V V LIN dominant output voltage, VDD = 18 V 0.8 0.8 × VDD 0 LIN recessive output voltage GND Shift1, 22 RSLAVE VSERIAL_DIODE1 1.15 1000 7 0.6 VDD 0.475 × VDD Unit ms 0.6 RL = 500 Ω RL = 1000 Ω VLIN_RECESSIVE1 VBAT Shift1, 22 TA = +115°C to +125°C 1 Typ 18 38 Current limit for driver when LIN bus is in dominant state, VBAT = VBAT (maximum) Driver off, 7.0 V < VBUS < 18 V, VDD = VLIN − 0.7 V Input leakage, VLIN = 0 V, VBAT = 12 V, driver off Control unit disconnected from ground, GND = VDD, 0 V < VLIN < 18 V, VBAT = 12 V VBAT disconnected, VDD = GND, 0 V < VBUS < 18 V LIN receiver dominant state, VDD > 7.0 V LIN receiver recessive state, VDD > 7.0 V VLIN_CNT = (VTH_DOM + VTH_REC)/2, VDD > 7.0 V ILIN_PAS_REC1 Min TA = −40°C to +115°C Typ Max 0 Slave termination resistance Voltage drop at the serial diode, DSer_Int 20 0.4 Rev. C | Page 7 of 16 30 0.7 0.115 × VDD 0.115 × VDD 47 1 V 30 kΩ V ADuCM330/ADuCM331 Parameter LIN AC PARAMETERS1 D1 D2 D322 D422 tRX_PDR22 tRX_SYM22 PACKAGE THERMAL SPECIFICATIONS Thermal Impedance (θJA) 23 POWER REQUIREMENTS Power Supply Voltages VDD (Pin 26) DVDD33 (Pin 21) AVDD18 (Pin 19) DVDD18 (Pin 22) POWER CONSUMPTION IDD (Processor Normal Mode) 24 IDD (Processor Powered Down) IDD LIN IDD IADC Data Sheet Test Conditions/Comments Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ, 6.8 nF||660 Ω, 10 nF||500 Ω Duty Cycle 1 THREC(MAX) = 0.744 × VBAT THDOM(MAX) = 0.581 × VBAT VSUP = 7.0 V to 18 V, tBIT = 50 µs D1 = tBUS_REC(MIN)/(2 × tBIT) Duty Cycle 2 THREC(MIN) = 0.284 × VBAT THDOM(MIN) = 0.422 × VBAT VSUP = 7.0 V to 18 V, tBIT = 50 µs D2 = tBUS_REC(MAX)/(2 × tBIT) THREC(MAX) = 0.778 × VBAT THDOM(MAX) = 0.616 × VBAT VDD = 7.0 V to 18 V tBIT = 96 µs D3 = tBUS_REC(MIN)/(2 × tBIT) THREC(MIN) = 0.389 × VBAT THDOM(MIN) = 0.251 × VBAT VDD = 7.0 V to 18 V tBIT = 96 µs D4 = tBUS_REC(MAX)/(2 × tBIT) Propagation delay of receiver Symmetry of receiver propagation delay rising edge, with respect to falling edge (tRX_SYM = tRF_PDR − tRX_PDF) Min TA = −40°C to +115°C Typ Max TA = +115°C to +125°C 1 Typ Unit 0.396 0.581 0.417 0.590 6 +2 −2 JEDEC 4-layer board µs µs 40 3.6 °C/W 18 3.3 1.88 1.88 CD0 (PCLK = 16 MHz), 16 MHz 1% mode, ADCs off, reference buffer off, executing code from program flash CD1 (PCLK = 8 MHz), 16 MHz 1% mode, ADCs off, reference buffer off, executing code from program flash CD0 (PCLK = 16 MHz), 16 MHz 1% mode, ADCs on, reference buffer on, executing code from program flash Precision oscillator off, ADC off, external LIN master pull-up resistor present, measured with wake-up and watchdog timers clocked from low power oscillator, maximum value is at 105°C, and VDD = 18 V 8 6 9.5 18.5 60 100 500 700 800 350 Gain = 4, 8, or 16 Gain = 32 or 64 LPM, gain = 64 Rev. C | Page 8 of 16 17 3.3 1.88 1.88 V V V V 9 mA 7 mA 10 mA µA µA µA µA µA Data Sheet Parameter IDD ADC1 VADC IDD Internal Reference (1.2 V) IDD HFOSC ADuCM330/ADuCM331 Test Conditions/Comments Min Reduction from 1% to 3% mode TA = −40°C to +115°C Typ Max 550 150 50 TA = +115°C to +125°C 1 Typ Unit µA µA µA Not guaranteed by production test, but by design and/or characterization data at production release. Valid for PGA current ADC gain settings of 4, 8, 16, 32, and 64. System chopping enabled. 4 These specifications include temperature drift. 5 A user system calibration removes this error at a given temperature (and at a given gain for the current channel). 6 The offset error drift is included in the offset error. This typical specification is an indicator of the offset error due to temperature drift. This typical value is the mean of the temperature drift characterization data distribution. 7 Includes internal reference temperature drift. 8 The gain drift is included in the total gain error. This typical specification is an indicator of the gain error due to the temperature drift in the ADC. This typical value is the mean of the temperature drift characterization data distribution. 9 Voltage channel specifications include resistive attenuator input stage, unless otherwise stated. 10 RMS noise is referred to voltage attenuator input; for example, at fADC = 1 kHz, the typical rms noise at the ADC input is 7.5 µV, scaling by the attenuator (24) yields these input referred noise figures. 11 Valid after an initial self calibration. 12 It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach can also be used to reduce the ADC input range (LSB size). 13 Valid for a differential input less than 10 mV. 14 The absolute value of the voltage of VTEMP and GND_SW must be 100 mV (minimum) for accurate operation of the temperature analog-to-digital converter (T-ADC). 15 Measured using box method. 16 The long-term stability specification is accelerated and noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period. 17 Valid after an initial self gain calibration. 18 Die temperature. 19 Endurance is qualified to 10,000 cycles, as per JEDEC Standard 22 Method A117 and measured at −40°C, +25 °C, and +115°C. Typical endurance at +25°C is 100k cycles. 20 Data retention lifetime equivalent at junction temperature (TJ) = 85°C, as per JEDEC Standard 22 Method A117. Data retention lifetime derates with junction temperature. 21 Measured with LIN communication active. 22 These specifications are not production tested but are supported by LIN compliance testing. 23 Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature. 24 Typical additional supply current consumed during Flash/EE memory program and erase cycles is 3 mA and 1 mA, respectively. 1 2 3 Rev. C | Page 9 of 16 ADuCM330/ADuCM331 Data Sheet ABSOLUTE MAXIMUM RATINGS The ADuCM330/ADuCM331 operate directly from the 12 V battery supply and is fully specified over the −40°C to +115°C temperature range, unless otherwise noted. Table 2. Parameter AGND to DGND to VSS to IO_VSS VBAT to AGND VDD to VSS LIN to IO_VSS Digital Input/Output Voltage to DGND ADC Inputs to AGND ESD (Human Body Model) Rating HBM-ADI0082 (Based on ANSI/ ESD STM5.1-2007) All Pins Except LIN and VBAT LIN VBAT IEC 61000-4-2 LIN and VBAT Storage Temperature Range Junction Temperature Transient Continuous Lead Temperature Soldering Reflow1 Lifetime2 Normal Mode Standby Mode 1 2 Rating −0.3 V to +0.3 V −22 V to +40 V −0.3 V to +40 V −18 V to +40 V −0.3 V to DVDD33 + 0.3 V −0.3 V to AVDD18 + 0.3 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION ±2.0 kV ±6 kV ±4 kV ±8 kV −55°C to +150°C 150°C 130°C 260°C 480 hours at −40°C 1600 hours at +23°C 5200 hours at +60°C 640 hours at +85°C 80 hours at +105°C 12,648 hours at −40°C 60,000 hours at +25°C 50,000 hours at +50°C JEDEC standard J-STD-020. Using an activation energy of 0.7 eV, verified using high temperature operating life (HTOL) at 125°C for 1000 hours. Rev. C | Page 10 of 16 Data Sheet ADuCM330/ADuCM331 32 31 30 29 28 27 26 25 GPIO5/LC_TX/LIN_TX DGND VSS IO_VSS LIN VBAT VDD DGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADuCM330/ ADuCM331 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 DNC DGND DVDD18 DVDD33 33VDD AVDD18 AGND VREF NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT THIS PIN. 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO GROUND FOR THERMAL REASONS. 11153-005 GND_SW VTEMP IIN+_AUX IIN+ IIN– IIN–_AUX VINP_AUX VINM_AUX 9 10 11 12 13 14 15 16 RESET SWDIO SWCLK GPIO0/CS/LIN_RX GPIO1/SCLK/LIN_TX GPIO2/MISO GPIO3/IRQ0/MOSI/LC_TX/LIN_TX GPIO4/IRQ1/LC_RX/ECLKIN/LIN_RX Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 Mnemonic RESET SWDIO Type 1 I I/O 3 SWCLK I 4 GPIO0/CS/LIN_RX I/O 5 GPIO1/SCLK/LIN_TX I/O 6 GPIO2/MISO I/O 7 GPIO3/IRQ0/MOSI/ LC_TX/LIN_TX I/O Description Reset Input Pin. Active low. This pin has an internal pull-up resistor to 33VDD. Cortex-M3 Debug Data Input and Output Channel. At power-on, this output is disabled and pulled high via an internal pull-up resistor. This pin can be left unconnected when not in use. Cortex-M3 Debug Clock Input. This is an input pin only and has an internal pull-up resistor. This pin can be left unconnected when not in use. General-Purpose Input/Output 0 (P0.0) (GPIO0). By default, this pin is configured as an input. The pin has an internal 25 kΩ pull-up resistor to 33VDD and, when not in use, can be left unconnected. Chip Select (CS). When configured, this pin also operates the SPI chip select input. Local Interconnect Network Receiver (Rx) (LIN_RX). This pin can be configured as the Rx pin for LIN frames in external transceiver mode. General-Purpose Input/Output 1 (P0.1) (GPIO1). By default, this pin is configured as an input. This pin is used by the kernel in external mode. See the ADuCM330/ADuCM331 hardware reference manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD and, when not in use, can be left unconnected. Serial Clock Input (SCLK). When configured, this pin operates the SPI serial clock input. Local Interconnect Network Transmitter (Tx) (LIN_TX). This pin can be configured as the Tx pin for LIN frames in external transceiver mode. General-Purpose Input/Output 2 (P0.2) (GPIO2). By default, this pin is configured as an input. The pin has an internal 25 kΩ pull-up resistor to 33VDD and, when not in use, can be left unconnected. Master Input/Slave Output (MISO). When configured, this pin also operates the SPI master input/slave output. General-Purpose Input/Output 3 (P0.3) (GPIO3). By default, this pin is configured as an input. This pin is used by the kernel in external mode. See the ADuCM330/ADuCM331 hardware reference manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD and, when not in use, can be left unconnected. Interrupt Request (IRQ0). This pin can also be configured as External Interrupt Request 0. Master Output/Slave Input (MOSI). This pin can be configured as an SPI master output/slave input pin. LIN Conformance Tx (LC_TX). This pin can be connected to the LIN physical Tx for LIN conformance testing. Local Interconnect Network Tx (LIN_TX). This pin can also be connected as the Tx pin for LIN frames in external transceiver mode. Rev. C | Page 11 of 16 ADuCM330/ADuCM331 Pin No. 8 Mnemonic GPIO4/IRQ1/LC_RX/ ECLKIN/LIN_RX Type 1 I/O 9 GND_SW I 10 VTEMP I 11 12 13 14 15 16 17 IIN+_AUX IIN+ IIN− IIN−_AUX VINP_AUX VINM_AUX VREF S I I S S S S 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND AVDD18 33VDD DVDD33 DVDD18 DGND DNC DGND VDD VBAT LIN IO_VSS VSS DGND GPIO5/LC_TX/LIN_TX S S S S S S 33 EPAD 1 2 S S S I/O S S S I/O Data Sheet Description General-Purpose Input/Output 4 (P0.4) (GPIO4). By default, this pin is configured as an input. This pin is used by the kernel in external mode. See the ADuCM330/ADuCM331 hardware reference manual for more information. The pin has an internal 25 kΩ pull-up resistor to 33VDD and, when not in use, can be left unconnected. Interrupt Request (IRQ1). This pin can be configured as External Interrupt Request 1. LIN Conformance Rx (LC_RX). This pin can be connected to LIN physical RX for LIN conformance testing. External Clock (ECLKIN). This pin can be configured as the external clock input. Local Interconnect Network Rx (LIN_RX). This pin can be configured as the receiving pin for LIN frames in external transceiver mode. Switch to Internal Analog Ground Reference. This pin is the negative input for the external temperature channel. External Pin for Negative Temperature Coefficient (NTC)/Positive Temperature Coefficient (PTC) Temperature Measurement. Auxiliary IIN+ Pin. Connect this pin to AGND. Positive Differential Input for Current Channel. Negative Differential Input for Current Channel. Auxiliary IIN− Pin. Connect this pin to AGND. Auxiliary Input Voltage Positive Channel. Connect this pin to AGND. Auxiliary Input Voltage Negative Channel. Connect this pin to AGND. Voltage Reference Pin. Connect this pin via a 470 nF capacitor to ground. This pin can also be used to input an external voltage reference. This pin cannot be used to supply an external circuit. Ground Reference for On-Chip Precision Analog Circuits. Supply from Analog LDO. Do not connect this pin to an external circuit. 2 3.3 V Supply. Connect to Pin 21. Do not connect this pin to an external circuit.2 3.3 V Supply. Connect to Pin 20. Do not connect this pin to an external circuit.2 1.8 V Supply. Do not connect this pin to an external circuit.2 Ground Reference for On-Chip Digital Circuits. Do Not Connect. This pin is internally connected; therefore, do not externally connect to this pin. Ground Reference for On-Chip Digital Circuits. Battery Power Supply for On-Chip Regulator. Battery Voltage Input fo Resistor Divider. Local Interconnect Network (LIN) Physical Interface Input/Output. Ground Reference for the LIN Pin. Ground Reference. This is the ground reference for the internal voltage regulators. Ground Reference for On-Chip Digital Circuits. General-Purpose Input/Output 5 (P0.5) (GPIO5). By default, this pin is configured as an input. This pin is checked by the kernel on every reset. See the ADuCM330/ADuCM331 hardware reference manual for further information. The pin has an internal 25 kΩ pull-up resistor to 33VDD and, when not in use, can be left unconnected. LIN Conformance Tx (LC_TX). This pin can be connected to the LIN physical Tx for LIN conformance testing. Local Interconnect Network Tx (LIN_TX). This pin can be configured as the Tx pin for LIN frames in external transceiver mode. Exposed Pad. It is recommended that the exposed pad be soldered to ground for thermal reasons. I is input, O is output, and S is supply. Using the 1.8 V or 3.3 V supply to power an external circuit can have POR, EMC, and self heating implications. Device evaluation and testing completed without an external load attached. Rev. C | Page 12 of 16 Data Sheet ADuCM330/ADuCM331 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, after the ADC has settled. Offset Error Offset error is the deviation of the first code transition ADC input voltage from the ideal first code transition. The Σ-Δ conversion techniques used on this device means that although the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output, giving a valid 20-bit data conversion result at output rates from 1 Hz to 8 kHz. Offset Error Drift Offset error drift is the variation in absolute offset error with respect to temperature. This error is expressed as LSB/°C or nV/°C. Note that, when software switches from one input to another (on the same ADC), the digital filter must first be cleared and then allowed to average a new result. Depending on the configuration of the ADC and the type of filter, this averaging can require multiple conversion cycles. Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition (111…110 to 111…111). The error is expressed as a percentage of full scale. Positive INL is defined as the deviation from a straight line through ½ LSB above midscale code transition to ½ LSB above the last code transition. Negative INL is defined as the deviation from a straight line from a point ½ LSB below the first code transition to a point ½ LSB above the midscale code transition. Gain Error Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function. Output Noise The output noise is specified as the standard deviation (or 1 × Σ) of ADC output codes distribution collected when the ADC input voltage is at a dc voltage. It is expressed as μV rms or nV rms. The output, or rms noise, is used to calculate the effective resolution of the ADC as defined by the following equation: Effective Resolution = log2(Full-Scale Range/rms Noise) bits The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 × Σ of the distribution of ADC output codes collected when the ADC input voltage is at dc. The peak-to-peak noise is therefore calculated as 6.6 × the rms noise. The peak-to-peak noise can be used to calculate the ADC (noise free, code) resolution for which there is no code flicker within a 6.6 × Σ limit as defined by the following equation: No Missing Codes No missing codes is a measure of the differential nonlinearity of the ADC. The error is expressed in bits and specifies the number of codes (ADC results) as 2N bits, where N = no missing codes, guaranteed to occur through the full ADC input range. Rev. C | Page 13 of 16 Noise Free Code Resolution = log2(Full-Scale Range/Peakto-Peak Noise) bits ADuCM330/ADuCM331 Data Sheet APPLICATIONS INFORMATION DESIGN GUIDELINES EXPOSED PAD THERMAL RECOMMENDATIONS Before starting design and layout of the ADuCM330/ADuCM331 on a printed circuit board (PCB), it is recommended that the designer become familiar with the following guidelines that describe any special circuit considerations and layout requirements needed. It is required that the exposed pad on the underside of the ADuCM330/ADuCM331 be connected to ground to achieve the best electrical and thermal performance. It is recommended that the user connect an exposed continuous copper plane on the PCB to the ADuCM330/ADuCM331 exposed pad, and that the copper plane has several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. It is recommended that these vias be solder filled or plugged. POWER AND GROUND RECOMMENDATIONS Place capacitors that are connecting to the ADuCM330/ ADuCM331 as close to the pins of the device as possible, with minimal trace length. Capacitors connected to the 33VDD, AVDD18, and DVDD18 pins must have a low equivalent series resistance (ESR) rating. All components must be rated accordingly to the temperature range expected by the application. GENERAL RECOMMENDATIONS It is highly recommended to use the schematic given with component values specified (see Figure 3). The component values shown in Figure 3 are chosen from the characterization tests and evaluated for optimum performance of the ADuCM330/ ADuCM331. Configure the GPIOs as inputs with pull-up resistors enabled to obtain the lowest possible current consumption in hibernate mode. Set the Cortex-M3 core clock speed to the minimum required to meet the application requirements. Rev. C | Page 14 of 16 Data Sheet ADuCM330/ADuCM331 RECOMMENDED SCHEMATIC Figure 3 shows external components recommended for proper operation of the ADuCM330/ADuCM331. 11 IIN+_AUX 220Ω 1nF 220Ω 12 IIN+ 13 IIN– 100nF 100nF 14 IIN–_AUX 15 VINP_AUX 16 VINM_AUX 10 VTEMP 9 GND_SW 17 VREF * PESD1LIN (OPTIONAL) 33VDD 20 ADuCM330/ ADuCM331 1µF 100nF DVDD18 22 AVDD18 19 0.47µF DGND VSS IO_VSS DGND EPAD 10nF AGND 0.47µF LIN DGND 10nF 1 LIN 28 DNC 10kΩ NTC 1kΩ DVDD33 21 AVDD18 100kΩ RESET ECU MASTER 24 25 18 23 30 29 31 33 *LIN 2.2 PHYSICAL TEST PASSED WITH 220pF CAPACITOR. Figure 3. Recommended Schematic Rev. C | Page 15 of 16 0.47µF 11153-003 100µΩ SHUNT 3 SWDIO VDD 2 SWCLK 26 10nF 32 GPIO5/LC_TX/LIN_TX 10µF 8 GPIO4/IRQ1/LC_RX/ECLKIN/LIN_RX 100nF 7 GPIO2/MISO VBAT 6 GPIO3/IRQ0/MOSI/LC_TX/LIN_TX 27 OPTIONAL 5 GPIO0/CS/LIN_RX VBAT 4 GPIO1/SCLK/LIN_TX DVDD33 1kΩ ADuCM330/ADuCM331 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC *3.90 EXPOSED PAD 3.80 SQ 3.70 17 0.70 0.60 0.50 TOP VIEW PKG-003499/3916 1.00 0.95 0.85 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.15 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-7 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION. 07-14-2014-D PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 4. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-32-15) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 ADuCM330WDCPZ ADuCM330WDCPZ-RL ADuCM331WDCPZ ADuCM331WDCPZ-RL EVAL-ADUCM331QSPZ Temperature Range3 −40°C to +115°C −40°C to +115°C −40°C to +115°C −40°C to +115°C Program Flash/ Data Flash/SRAM 96 kB/4 kB/6 kB 96 kB/4 kB/6 kB 128 kB/4 kB/6 kB 128 kB/4 kB/6 kB Package Description 32-Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Frame Chip Scale Package [LFCSP_VQ] Socketed Evaluation Board with Switches and LEDs Package Option CP-32-15 CP-32-15 CP-32-15 CP-32-15 1 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. 3 The ADuCM330/ADuCM331 are functional but have degraded performance at temperatures from 115°C to 125°C. 2 AUTOMOTIVE PRODUCTS The ADuCM330W/ADuCM331W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11153-0-10/15(C) Rev. C | Page 16 of 16