AD AD568KQ 12-bit ultrahigh speed monolithic d/a converter Datasheet

a
FEATURES
Ultrahigh Speed: Current Settling to 1 LSB in 35 ns
High Stability Buried Zener Reference on Chip
Monotonicity Guaranteed Over Temperature
10.24 mA Full-Scale Output Suitable for Video
Applications
Integral and Differential Linearity Guaranteed Over
Temperature
0.3" “Skinny DIP” Packaging
Variable Threshold Allows TTL and CMOS
Interface
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTION
The AD568 is an ultrahigh-speed, 12-bit digital-to-analog converter (DAC) settling to 0.025% in 35 ns. The monolithic device is fabricated using Analog Devices’ Complementary Bipolar
(CB) Process. This is a proprietary process featuring high-speed
NPN and PNP devices on the same chip without the use of dielectric isolation or multichip hybrid techniques. The high speed
of the AD568 is maintained by keeping impedance levels low
enough to minimize the effects of parasitic circuit capacitances.
The DAC consists of 16 current sources configured to deliver a
10.24 mA full-scale current. Multiple matched current sources
and thin-film ladder techniques are combined to produce bit
weighting. The DAC’s output is a 10.24 mA full scale (FS) for
current output applications or a 1.024 V FS unbuffered voltage
output. Additionally, a 10.24 V FS buffered output may be generated using an onboard 1 kΩ span resistor with an external op
amp. Bipolar ranges are accomplished by pin strapping.
Laser wafer trimming insures full 12-bit linearity. All grades of
the AD568 are guaranteed monotonic over their full operating
temperature range. Furthermore, the output resistance of the
DAC is trimmed to 100 Ω ± 1.0%. The gain temperature coefficient of the voltage output is 30 ppm/°C max (K).
12-Bit Ultrahigh Speed
Monolithic D/A Converter
AD568
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. The ultrafast settling time of the AD568 allows leading edge
performance in waveform generation, graphics display and
high speed A/D conversion applications.
2. Pin strapping provides a variety of voltage and current output
ranges for application versatility. Tight control of the absolute output current reduces trim requirements in externallyscaled applications.
3. Matched on-chip resistors can be used for precision scaling in
high speed A/D conversion circuits.
4. The digital inputs are compatible with TTL and +5 V
CMOS logic families.
5. Skinny DIP (0.3") packaging minimizes board space requirements and eases layout considerations.
6. The AD568 is available in versions compliant with MILSTD-883. Refer to the Analog Devices Military Products
Databook or current AD568/883B data sheet for detailed
specifications.
The AD568 is available in three performance grades. The
AD568JQ and KQ are available in 24-pin cerdip (0.3") packages
and are specified for operation from 0°C to +70°C. The
AD568SQ features operation from –55°C to +125°C and is also
packaged in the hermetic 0.3" cerdip.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD568* PRODUCT PAGE QUICK LINKS
Last Content Update: 09/27/2017
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Data Sheet
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AD568–SPECIFICATIONS (@ = +258C, V , V
CC
Model
Min
AD568J
Typ
Max
EE
= 615 V unless otherwise noted)
AD568K
Typ
Max
Min
AD568S
Typ
Max
12
ACCURACY 1
Linearity
TMIN to TMAX
Differential Nonlinearity
TMIN to TMAX
Monotonicity
Unipolar Offset
Bipolar Offset
Bipolar Zero
Gain Error
–1/2
+1/2
–1/4
+1/4
–1/2
+1/2
–3/4
+3/4
–1/2
+1/2
–3/4
+3/4
–1
+1
–1/2
+1/2
–1
+1
–1
+1
–1
+1
–1
–1
GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE
–0.2
+0.2
*
*
*
*
–1.0
+1.0
*
*
*
*
–0.2
+0.2
*
*
*
*
–1.0
+1.0
*
*
*
*
LSB
LSB
LSB
LSB
TEMPERATURE COEFFICIENTS 2
Unipolar Offset
Bipolar Offset
Bipolar Zero
Gain Drift
Gain Drift (IOUT)
–5
–30
–15
–50
–150
+5
+30
+15
+50
+150
–3
–20
•
–30
*
+3
+20
•
+30
*
–5
–30
•
–50
*
+5
+30
•
+50
*
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
2.0
0.0
7.0
0.8
*
*
*
*
*
*
*
*
V
V
+10
–100
*
*
*
*
*
*
*
–200
µA
µA
V
–10
–0.5
0
–60
1.4
12
Units
RESOLUTION
DATA INPUTS
Logic Levels (TMIN to TMAX)
VIH
VIL
Logic Currents (T MIN to TMAX)
IIH
IIL
VTH Pin Voltage
12
Min
*
*
*
CODING
BINARY, OFFSET BINARY
CURRENT OUTPUT RANGES
0 to 10.24, ± 5.12
*
–100
*
COMPLIANCE VOLTAGE
–2
OUTPUT RESISTANCE
Exclusive of R L
Inclusive of R L
160
99
SETTLING TIME
Current to
± 0.025%
± 0.1%
Voltage
50 Ω Load3, 0.512 V p-p,
to 0.025%
to 0.1%
to 1%
75 Ω Load3, 0.768 V p-p,
to 0.025%
to 0.1%
to 1%
100 Ω (Internal RL)3, 1.024 V p-p,
to 0.025%
to 0.1%
to 1%
Glitch Impulse 4
Peak Amplitude
FULL-SCALE TRANSlTlON 5
10% to 90% Rise Time
90% to 10% Fall Time
POWER REQUIREMENTS
+13.5 V to +16.5 V
–13.5 V to –16.5 V
Power Dissipation
PSRR
+1.2
V
*
*
*
V
*
*
*
*
Ω
Ω
35
23
*
*
*
*
ns to 0.025% of FSR
ns to 0.1% of FSR
37
25
18
*
*
*
*
*
*
ns to 0.025% of FSR
ns to 0.1% of FSR
ns to 1% of FSR
40
25
20
*
*
*
*
*
*
ns to 0.025% of FSR
ns to 0.1% of FSR
ns to 1% of FSR
50
38
24
350
15
*
*
*
*
*
*
*
*
*
*
ns to 0.025% of FSR
ns to 0.1% of FSR
ns to 1% of FSR
pV-sec
% of FSR
11
11
*
*
*
*
ns
ns
200
100
27
–7
525
0
–65
*
% of FSR
% of FSR
% of FSR
% of FSR
mA
0 to 1.024, ± 0.512
VOLTAGE OUTPUT RANGES
TEMPERATURE RANGE
Rated Specification 2
Storage
Bits
240
101
*
*
*
32
–8
625
0.05
+70
+150
0
*
*
*
*
*
+70
*
*
*
*
–55
*
*
*
*
*
mA
mA
mW
% of FSR/V
+125
*
°C
°C
NOTES
*Same as AD568J.
Measured in IOUT mode.
2
Measured in V OUT mode, unless otherwise specified. See text for further information.
3
Total Resistance. Refer to Figure 3,
4
At the major carry, driven by HCMOS logic. See text for further explanation.
5
Measured in V OUT mode.
Specifications shown in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
1
–2–
REV. A
AD568
LSB
12
MSB
11
10
9
8
7
6
5
4
3
PNP
CURRENT
SOURCES
THRESHOLD
CONTROL
LADDER
COMMON
PIN CONFIGURATION
1
24
2X
4X
PNP
SWITCHES
23
IOUT
20
THIN-FILM R-2R LADDER
(100 - 200Ω)
200Ω
19
14
21
DIFFUSED R-2R LADDER
(10 - 20Ω)
17
BIPOLAR
CURRENT
GENERATOR
IOUT
VCC
BURIED
ZENER
REFERENCE
13
1.4V
BANDGAP
REF
THRESHOLD
COMMON
2
15
1kΩ
16
AD568
18
22
ANALOG
COMMON
VEE
REFERENCE
COMMON
IOUT
LOAD RESISTOR
(RL)
BIPOLAR
OFFSET (IBPO)
10V SPAN
RESISTOR
10V SPAN
RESISTOR
Figure 1. Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS 1
VCC to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
VEE to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V
REFCOM to LCOM . . . . . . . . . . . . . . . . . +100 mV to –10 V
ACOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mV
THCOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mV
SPANs to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 12 V
IBPO to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 V
IOUT to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to VTH
Digital Inputs to THCOM . . . . . . . . . . . . . –500 mV to +7.0 V
Voltage Across Span Resistor . . . . . . . . . . . . . . . . . . . . . . 12 V
VTH to THCOM . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +1.4 V
Logic Threshold Control Input Current . . . . . . . . . . . . . 5 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mW
Storage Temperature Range
Q (Cerdip) Package . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Thermal Resistance
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C/W
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Modell
Package Option2
Temperature
Range 8C
AD568JQ
AD568KQ
AD568SQ
24-Lead Cerdip (Q-24)
24-Lead Cerdip (Q-24)
24-Lead Cerdip (Q-24)
0 to +70
0 to +70
–55 to +125
Linearity
Error Max
@ 258C
Voltage
Gain T.C.
Max ppm/8C
± 1/2
± 1/4
± 1/2
± 50
± 30
± 50
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices
Military Products Databook or current AD568/883B data sheet.
2
Q = Cerdip.
Definitions
LINEARITY ERROR (also called INTEGRAL NONLINEARITY OR INL): Analog Devices defines linearity error as the
maximum deviation of the actual analog output from the ideal
output (a straight line drawn from 0 to FS) for any bit combination expressed in multiples of 1 LSB. The AD568 is laser
trimmed to 1/4 LSB (0.006% of FS) maximum linearity error at
+25°C for the K version and 1/2 LSB for the J and S versions.
DIFFERENTIAL LINEARITY ERROR (also called DIFFERENTIAL NONLINEARITY or DNL): DNL is the measure of
the variation in analog value, normalized to full scale, associated
with a 1 LSB change in digital input code. Monotonic behavior
requires that the differential linearity error not exceed 1 LSB in
the negative direction.
MONOTONICITY: A DAC is said to be monotonic if the output either increases or remains constant as the digital input
increases.
UNIPOLAR OFFSET ERROR: The deviation of the analog
output from the ideal (0 V or 0 mA) when the inputs are set to
all 0s is called unipolar offset error.
BIPOLAR OFFSET ERROR: The deviation of the analog output from the ideal (negative half-scale) when the inputs are set
to all 0s is called bipolar offset error.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD568 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
AD568
BIPOLAR ZERO ERROR: The deviation of the analog output
from the ideal half-scale output of 0 V (or 0 mA) for bipolar
mode when only the MSB is on (100 . . .00) is called bipolar
zero error.
their glitch impulse. It is specified as the net area of the glitch in
nV-sec or pA-sec.
COMPLIANCE VOLTAGE: The range of allowable voltage at
the output of a current-output DAC which will not degrade the
accuracy of the output current.
GAIN ERROR: The difference between the ideal and actual
output span of FS –1 LSB, expressed in % of FS, or LSB, when
all bits are on.
SETTLING TIME: The time required for the output to reach
and remain within a specified error band about its final value,
measured from the digital input transition.
GLITCH IMPULSE: Asymmetrical switching times in a DAC
give rise to undesired output transients which are quantified by
+15V
–15V
0.2µF
0.8
OUTPUT – VOLTS
0.1µF
0.6
1
+15V 24
2
REFCOM 23
3
–15V 22
4
IBPO 21
DIGITAL
INPUTS
0.4
AD568
ACOM 18
8
LCOM 17
9
SPAN 16 NC
50
100
150
TIME – ns
200
250
ANALOG
SUPPLY GROUND
ANALOG
GND PLANE
SPAN 15 NC
11
THCOM 14
12
VTH 13
REXT
(OPTIONAL)
ANALOG
OUTPUT
RL 19
7
10
0
0.1µF
IOUT 20
5
6
FERRITE BEADS
STACKPOLE 57-1392
OR
AMIDON FB-43B-101
OR EQUIVALENT
0.1µF
DIGITAL
GND PLANE
100pF
DIGITAL
SUPPLY
GROUND
RTH
1kΩ
Figure 2. Glitch Impulse
Connecting the AD568
+5V
Figure 3. Unipolar Output Unbuffered 0 V to +1.024 V
UNBUFFERED VOLTAGE OUTPUT
+15V
–15V
0.2µF
Unipolar Configuration
Figure 3 shows the AD568 configured to provide a unipolar 0 to
+1.024 V output range. In this mode, the bipolar offset terminal, Pin 21, should be grounded if not used for offset trimming.
0.1µF
The nominal output impedance of the AD568 with Pin 19
grounded has been trimmed to 100 Ω, ± 1%. Other output impedances can be generated with an external resistor, REXT, between Pins 19 and 20. An REXT equalling 300 Ω will yield a
total output resistance of 75 Ω, while an REXT of 100 Ω will provide 50 Ω of output resistance. Note that since the full-scale
output current of the DAC remains 10.24 mA, changing the
load impedance changes the unbuffered output voltage accordingly. Settling time and full-scale range characteristics for these
load impedances are provided in the specifications table.
1
+15V 24
2
REFCOM 23
3
–15V 22
4
IBPO 21
IOUT 20
5
DIGITAL
INPUTS
6
0.1µF
0.1µF
AD568
ANALOG
OUTPUT
RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16
10
SPAN 15
11
THCOM 14
12
VTH 13
ANALOG
GND PLANE
ANALOG
SUPPLY
GROUND
100pF
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
Bipolar Configuration
Figure 4 shows the connection scheme used to provide a bipolar
output voltage range of 1.024 V. The bipolar offset (–0.512 V)
occurs when all bits are OFF (00 . . . 00), bipolar zero (0 V) occurs when the MSB is ON with all other bits OFF (10 . . . 00),
and full-scale minus 1 LSB (0.51175 V) is generated when all
bits are ON (11 . . . 11). Figure 5 shows an optional bipolar
mode with a 2.048 V range. The scale factor in this mode will
not be as accurate as the configuration shown in Figure 4, because the laser-trimmed resistor RL is not used.
+5V
Figure 4. Bipolar Output Unbuffered ± 0.512 V
Figure 4 also demonstrates how the internal span resistor may
be used to bias the VTH pin (Pin 13) from a 5 V supply. This
eliminates the requirement for an external RTH in applications
that do not require the precision span resistor.
–4–
REV. A
AD568
+15V
–15V
full scale at the DAC output. Note: this may slightly compromise the bipolar zero trim.
0.2µF
0.1µF
1
+15V 24
2
REFCOM 23
3
–15V 22
4
IBPO 21
5
IOUT 20
AD568
6
DIGITAL
INPUTS
1 BIT 1
MSB
2
0.1µF
3
0.1µF
ANALOG
OUTPUT
RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16 NC
10
SPAN 15 NC
11
THCOM 14
12
VTH 13
ANALOG
GND PLANE
DIGITAL
GND PLANE
100pF
DIGITAL
INPUTS
ANALOG
SUPPLY
GROUND
DIGITAL
SUPPLY
GROUND
RTH
1kΩ
24
23
AD568
22
4
IBPO 21
5
IOUT 20
6
RL 19
7
ACOM 18
8
LCOM 17
9
16
10
15
11
14
12 BIT 12
LSB
13
VCC
GAIN
5.11kΩ
ZERO
20Ω
ANALOG
OUTPUT
(–0.512 TO
0.512V)
20kΩ
75Ω
VEE
Figure 7. Bipolar Unbuffered Gain and Zero Adjust
BUFFERED VOLTAGE OUTPUT
+5V
Figure 5. Bipolar Output Unbuffered ± 1.024 V
Optional Gan and Zero Adjustment
The gain and offset are laser trimmed to minimize their effects
on circuit performance. However, in some applications, it may
be desirable to externally reduce these errors further. In those
cases, the following procedures are suggested.
UNIPOLAR MODE: (Refer to Figure 6)
Step 1 – Set all bits (BIT 1–BIT 12) to Logic “0” (OFF)—note
the output voltage. This is the offset error.
For full-scale outputs of greater than 1 V, some type of external
buffer amplifier is required. The AD840 fills this requirement
perfectly, settling to 0.025% from a 10 V full-scale step in less
than 100 ns.
A 1 kΩ span resistor has been provided on chip for use as a
feedback resistor in buffered applications. Using RSPAN (Pins 15,
16) introduces a 100 mW code-dependent power source onto
the chip which may generate a slight degradation in linearity.
Maximum linearity performance can be realized by using an external span resistor.
+15V
–15V
0.2µF
Step 2 – Set all bits to Logic “1” (ON). Adjust the gain trim resistor so that the output voltage is equal to the desired full scale
minus 1 LSB plus the offset error measured in step 1.
0.1µF
Step 3 – Reset all bits to Logic “0” (OFF). Adjust the offset
trim resistor for 0 V output.
1 BIT 1
2 MSB
3
DIGITAL
INPUTS
24
23
AD568
DIGITAL
INPUTS
22
4
IBPO 21
5
IOUT 20
6
RL 19
7
ACOM 18
8
LCOM 17
9
16
10
15
11
14
12 BIT 12
LSB
13
GAIN
20Ω
5.11kΩ
100Ω
OFFSET
ANALOG
OUTPUT
(0 TO 1.024V)
Figure 6. Unbuffered Unipolar Gain and Zero Adjust
BIPOLAR MODE (Refer to Figure 7)
Step 1 – Set bits to offset binary “zero” (10 . . . 00). Adjust the
zero resistor to produce 0 V at the DAC output. This removes
the bipolar zero error.
Step 2 – Set all bits to Logic “1” (ON). Adjust gain trim resistor
so the output voltage is equal to the desired full-scale minus
l LSB .
Step 3 – (Optional) If precise trimming of the bipolar offset is
preferred to trimming of bipolar zero: set all bits to Logic “0”
(OFF). Trim the zero resistor to produce the desired negative
REV. A
1
+15V 24
2
REFCOM 23
3
–15V 22
4
IBPO 21
5
IOUT 20
6
AD568
0.1µF
–VS
0.1µF
+VS
AD840
100Ω
ANALOG
OUTPUT
RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16
10
SPAN 15
11
THCOM 14
12
VTH 13
ANALOG
GND PLANE
5pF
100pF
RTH
1kΩ
DIGITAL
GND PLANE
ANALOG
SUPPLY
GROUND
DIGITAL
SUPPLY
GROUND
AMPLIFIER NOISE GAIN: 11
+5V
Figure 8. Unipolar Output Buffered 0 to –10.24V
Unipolar Inverting Configuration
Figure 8 shows the connections for producing a – 10.24 V fullscale swing. This configuration uses the AD568 in the current
output mode into a summing junction at the inverting input terminal of the external op amp. With the load resistor RL
grounded, the DAC has an output impedance of 100 Ω. This
produces a noise gain of 11 from the noninverting terminal of
the op amp, and hence, satisfies the stability criterion of the
AD840 (stable at a gain of 10). The addition of a 5 pF compen–5–
AD568
sation capacitor across the 1 kΩ feedback resistor produces optimal settling. Lower noise gain can be achieved by connecting RL
to IOUT, increasing the DAC output impedance to approximately
200 Ω, and reducing the noise gain to 6 (illustrated in Figure 9).
While the output in this configuration will feature improved
noise performance, it is somewhat less stable and may suffer
from ringing. The compensation capacitance should be increased to 7 pF to maintain stability at this reduced gain.
+15V
Noninverting Configuration
If a positive full-scale output voltage is required, it can be implemented using the AD568 in the unbuffered voltage output mode
followed by the AD840 in a noninverting configuration (Figure
10). The noise gain of this topology is 10, requiring only 5 pF
across the feedback resistor to optimize settling.
+15V
–15V
0.2µF
–15V
0.1µF
0.2µF
0.1µF
1
+15V 24
2
REFCOM 23
3
–15V 22
4
IBPO 21
DIGITAL
INPUTS
–VS
0.1µF
AD568
+VS
AD840
IOUT 20
5
6
0.1µF
100Ω
ANALOG
OUTPUT
RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16
10
SPAN 15
11
THCOM 14
12
VTH 13
ANALOG
GND PLANE
ANALOG
SUPPLY
GROUND
5pF
100pF
DIGITAL
INPUTS
DIGITAL
GND PLANE
RTH
1kΩ
1
+15V 24
2
REFCOM 23
3
–15V 22
4
IBPO 21
5
IOUT 20
6
AD568
0.1µF
–VS
0.1µF
+VS
AD840
111Ω
ANALOG
OUTPUT
RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16
10
SPAN 15
11
THCOM 14
12
VTH 13
ANALOG
GND
PLANE
ANALOG
SUPPLY
GROUND
5pF
DIGITAL GND PLANE
100pF
DIGITAL
SUPPLY
GROUND
RTH
1kΩ
DIGITAL
SUPPLY
GROUND
AMPLIFIER NOISE GAIN: 10
+5V
AMPLIFIER NOISE GAIN: 11
Figure 10. Unipolar Output Buffered 0 V to +10.24 V
+5V
Guidelines for Using the AD568
Figure 8. Unipolar Output Buffered 0 to –10.24V
+15V
The designer who seeks to combine high speed with high precision faces a challenging design environment. Where tens of
milliamperes are involved, fractions of an ohm of misplaced
impedance can generate several LSBs of error. Increasing
bandwidths make formerly negligible parasitic capacitances and
inductances significant. As system performance reaches and exceeds that of the measurement equipment, time-honored test
methods may no longer be trustworthy. The DAC’s placement
on the boundary between the analog and digital domains introduces additional concerns. Proper RF techniques must be used
in board design, device selection, supply bypassing, grounding,
and measurement if optimal performance is to be realized. The
AD568 has been configured to be relatively easy to use, even in
some of the more treacherous applications. The device characteristics shown in this data sheet are readily achievable if proper
attention is paid to the details. Since a solid understanding of
the circuit involved is one of the designer’s best weapons against
the difficulties of RF design, the following sections provide illustrations, explanations, examples, and suggestions to facilitate
successful design with the AD568.
–15V
0.2µF
0.1µF
DIGITAL
INPUTS
1
+15V 24
2
REFCOM 23
3
–15V 22
4
IBPO 21
5
IOUT 20
6
AD568
0.1µF
–VS
0.1µF
+VS
AD840
200Ω
ANALOG
OUTPUT
RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16
10
SPAN 15
11
THCOM 14
12
VTH 13
ANALOG
GND PLANE
7pF
100pF
RTH
1kΩ
DIGITAL
GND PLANE
ANALOG
SUPPLY
GROUND
DIGITAL
SUPPLY
GROUND
AMPLIFIER NOISE GAIN: 6
Current Output vs. Voltage Output
+5V
As indicated in Figures 3 through 10, the AD568 has been
designed to operate in several different modes depending on the
external circuit configuration. While these modes may be
categorized by many different schemes, one of the most important distinctions to be made is whether the DAC is to be used to
generate an output voltage or an output current. In the current
output mode, the DAC output (Pin 20) is tied to some type of
summing junction, and the current flowing from the DAC into
this summing junction is sensed (e.g., Figures 8 and 9). In this
Figure 9. Bipolar Output Buffered ± 5.12 V
Bipolar Inverting Configuration
Figure 9 illustrates the implementation of a +5.12 V to –5.12 V
bipolar range, achieved by connecting the bipolar offset current,
IBPO, to the summing junction of the external amplifier. Note
that since the amplifier is providing an inversion, the full-scale
output voltage is –5.12 V, while the bipolar offset voltage (all
bits OFF) is +5.12 V at the amplifier output.
–6–
REV. A
AD568
mode, the DAC output scale is insensitive to whether the load
resistor, RL, is shorted (Pin 19 connected to Pin 20), or
grounded (Pin 19 connected to Pin 18). However, this does
affect the output impedance of the DAC current and may have a
significant impact on the noise gain of the external circuitry. In
the voltage output mode, the DAC’s output current flows
through its own internal impedance (perhaps in parallel with an
external impedance) to generate a voltage, as in Figures 3, 4, 5,
and 10. In this case, the DAC output scale is directly dependent
on the load impedance. The temperature coefficient of the
AD568’s internal reference is trimmed in such a way that the
drift of the DAC output in the voltage output mode is centered
on zero. The current output of the DAC will have an additional
drift factor corresponding to the absolute temperature coefficient of the internal thin-film resistors. This additional drift may
be removed by judicious placement of the 1 kΩ span resistor in
the signal path. For example, in Figures 8 and 9, the current
flowing from the DAC into the summing junction could suffer
from as much as 150 ppm/°C of thermal drift. However, since
this current flows through the internal span resistor (Pins 15 and
16) which has a temperature coefficient that matches the DAC
ladder resistors, this drift factor is compensated and the buffered
voltage at the amplifier output will be within specified limits for
the voltage output mode.
The threshold of the digital inputs is set at 1.4 V and does not
vary with supply voltage. This is provided by a bandgap reference generator, which requires approximately 3 mA of bias current achieved by tying RTH to any +VL supply where
 +V L –1.4V 
RTH = 
3 mA 

The input lines operate with small input currents to easily
achieve interface with unbuffered CMOS logic. The digital input signals to the DAC should be isolated from the analog output as much as possible. To minimize undershoot, ringing, and
possible digital feedthrough noise, the interconnect distances to
the DAC inputs should be kept as short as possible. Termination resistors may improve performance if the digital lines become too long. The digital input should be free from large
glitches and ringing and have maximum 10% to 90% rise and
fall times of 5 ns. Figure 12 shows the equivalent digital input
circuit of the AD568.
+VL
1.28mA
RTH
(EXTERNAL)
125Ω
BIT
INPUT
VTHRESHOLD
5pF
58pF
Output Voltage Compliance
The AD568 has a typical output compliance range of +1.2 V to
–2.0 V (with respect to the LCOM Pin). The currentsteering output stages will be unaffected by changes in the output terminal voltage over that range. However, as shown in Figure 11, there is an equivalent output impedance of 200 Ω in
parallel with 15 pF at the output terminal which produces an
equivalent error current if the voltage deviates from the ladder
common. This is a linear effect which does not change with input code. Operation beyond the maximum compliance limits
may cause either output stage saturation or breakdown resulting
in nonlinear performance. The positive compliance limit is not
affected by the positive power supply, but is a function of output
current and the logic threshold voltage at VTH, Pin 13.
IOUT = 10.24mA x
DIGITAL IN
4096
15pF
RLOAD IOUT
RLADDER
(200Ω)
LADDER
COMMON
RLADDER
(200Ω)
15pF
COMPLIANCE TO
LOGIC LOW VALUE
ANALOG
COMMON
Figure 11. Equivalent Output
Digital Input Considerations
The AD568 uses a standard positive true straight binary code
for unipolar outputs (all 1s full-scale output), and an offset binary code for bipolar output ranges. In the bipolar mode, with
all 0s on the inputs, the output will go to negative full scale;
with 111 . . . 11, the output will go to positive full scale less
1 LSB; and with 100 . . 00 (only the MSB on), the output will
go to zero.
REV. A
TO
IOUT
LADDER
COMMON
THRESHOLD
COMMON
Figure 12. Equivalent Digital Input
Due to the high-speed nature of the AD568, it is recommended
that high-speed logic families such as Schottky TTL, high-speed
CMOS, or the new lines of FAST* TTL be used exclusively.
Table I shows how DAC performance can vary depending on
the driving logic used. As this table indicates, STTL, HCMOS,
and FAST represent the most viable families for driving the
AD568.
Table I. DAC Performance vs. Drive Logic1
IN
(1 – DIGITAL
)
4096
10.24mA
COMPLIANCE
TO VTHRESHOLD
RLOAD
(200Ω)
IOUT = 10.24mA x
TO
TO ANALOG
THRESHOLD COMMON
COMMON
1.4V
BANDGAP
DIODE
Logic
Family
DAC
10-90%
Settling Time2, 3
DAC
1%
0.1% 0.025%
Rise Time2
Glitch4
Impulse
Maximum
Glitch
Excursion
TTL
LSTTL
STTL
HCMOS
FAST*
11 ns
11 ns
9.5 ns
11 ns
12 ns
2.5 nV-s
950 pV-s
850 pV-s
350 pV-s
1.0 nV-s
240 mV
160 mV
150 mV
115 mV
250 mV
18 ns
28 ns
16 ns
24 ns
16 ns
34 ns
46 ns
33 ns
38 ns
36 ns
50 ns
80 ns
50 ns
50 ns
42 ns
NOTES
1
All values typical, taken in rest fixture diagrammed in Figure 13.
2
Measurements are made for a 1 V full-scale step into 100 Ω DAC load
resistance.
3
Settling time is measured from the time the digit input crosses the threshold
voltage (1.4 V) to when the output is within the specified range of its final
value.
4
The worst case glitch impulse, measured on the major carry DAC full scale
is 1 V.
–7–
AD568
The variations in settling times can be attributed to differences
in the rise time and current driving capabilities of the various
families. Differences in the glitch impulse are predominantly dependent upon the variation in data skew. Variations in these
specs occur not only between logic families, but also between
different gates and latches within the same family. When selecting a gate to drive the AD568 logic input, pay particular attention to the propagation delay time specs: tPLH and tPHL.
Selecting the smallest delays possible will help to minimize the
settling time, while selection of gates where tPLH and tPHL are
closely matched to one another will minimize the glitch impulse
resulting from data skew. Of the common latches, the 74374 octal flip-flop provides the best performance in this area for many
of the logic families mentioned above.
DAC OUTPUT – VOLTS
1.026
1.024
1.022
0
*FAST is a registered trademark of Fairchild Camera and Instrumentation
Corporation.
20
40
60
TIME – ns
80
100
120
Figure 14. Zero to Full-Scale Settling
Glitch Considerations
CLOCK IN
+5V
In many high-speed DAC applications, glitch performance is a
critical specification. In a conventional DAC architecture such
as the AD568 there are two basic glitch mechanisms: data skew
and digital feedthrough. A thorough understanding of these
sources can help the user to minimize glitch in any application.
SELECT
1A
VCC
1B
2A
1V
74158
2V
2B
3V
3A
3B
4V
4A
STROBE
4B
GND
12
WORD A
SELECT
+15V –15V
VCC
2
REFCOM
3
VEE
1A
VCC
4
IBPO
1B
1V
5
IOUT
2V
6
RL
3V
7
ACOM
3B
4V
8
LCOM
4A
STROBE
9
RSPAN
4B
GND
2A
74158
2B
3A
12
WORD B
SELECT
1A
VCC
1B
1V
2A
2B
3A
74158
2V
DIGITAL FEEDTHROUGH—As with any converter product,
a high-speed digital-to-analog converter is forced to exist on the
frontier between the noisy environment of high-speed digital
logic and the sensitive analog domain. The problems of this interfacing are particularly acute when demands of high speed
(greater than 10 MHz switching times) and high precision (12
bits or more) are combined. No amount of design effort can
perfectly isolate the analog portions of a DAC from the spectral
components of a digital input signal with a 2 ns risetime. Inevitably, once this digital signal is brought onto the chip, some of
its higher frequency components will find their way to the sensitive analog nodes, producing a digital feedthrough glitch. To
minimize the exposure to this effect, the AD568 has intentionally omitted the on-board latches that have been included in
many slower DACs. This not only reduces the overall level of
digital activity on chip, it also avoids bringing a latch clock pulse
on board, whose opposite edge inevitably produces a substantial
glitch, even when the DAC is not supposed to be changing
codes. Another path for digital noise to find its way onto a converter chip is through the reference input pin. The completely
internal reference featured in the AD568 eliminates this noise
input, providing a greater degree of signal integrity in the analog
portions of the chip.
AD568
1
10
RSPAN
11
THCON
12
VTH
VOUT
1k
+5V
3V
3B
4V
4A
STROBE
4B
GND
Figure 13. Test Setup for Glitch Impulse and Settling
Time Measurements
Settling Time Considerations
As can be seen from Table I and the specifications page, the settling time of the AD568 is application dependent. The fastest
settling is achieved in the current-output mode, since the voltage output mode requires the output capacitance to be charged
to the appropriate voltage. The DAC’s relatively large output
current helps to minimize this effect, but settling-time sensitive
applications should avoid any unnecessary parasitic capacitance
at the output node of voltage output configurations. Direct measurement of the fine scale DAC settling time, even in the voltage
output mode, is extremely tricky: analog scope front ends are
generally incapable of recovering from overdrive quickly enough
to give an accurate settling representation. The plot shown in
Figure 14 was obtained using Data Precision’s 640 16-bit sampling head, which features the quick overdrive recovery characteristic of sampling approaches combined with high accuracy
and relatively small thermal tail.
DATA SKEW—The AD568, like many of its slower predecessors, essentially uses each digital input line to switch a separate,
weighted current to either the output (IOUT) or some other node
(ANALOG COM). If the input bits are not changed simultaneously, or if the different DAC bits switch at different speeds,
then the DAC output current will momentarily take on some incorrect value. This effect is particularly troublesome at the
“carry points”, where the DAC output is to change by only one
LSB, but several of the larger current sources must be switched
to realize this change. Data skew can allow the DAC output to
move a substantial amount towards full scale or zero (depending
upon the direction of the skew) when only a small transition is
desired. Great care was taken in the design and layout of the
AD568 to ensure that switching times of the DAC switches are
symmetrical and that the length of the input data lines are short
–8–
REV. A
AD568
and well matched. The glitch-sensitive user should be equally
diligent about minimizing the data skew at the AD568’s inputs,
particularly for the 4 or 5 most significant bits. This can be
achieved by using the proper logic family and gate to drive the
DAC, and keeping the interconnect lines between the logic outputs and the DAC inputs as short and as well matched as possible, particularly for the most significant bits. The top 6 bits
should be driven from the same latch chip if latches are used.
1.4 V, Pin 13 may be directly driven with a voltage source, leaving Pin 14 tied to the ground plane. As Note 2 in Table III indicates, lowering the threshold voltage may reduce output voltage
compliance below the specified limits, which may be of concern
in an unbuffered voltage output topology.
AD568
THCOM
RB
C1
Glitch Reduction Schemes
BIT-DESKEWING—Even carefully laid-out boards using the
proper driving logic may suffer from some degree of data-skew
induced glitch. One common approach to reducing this effect is
to add some appropriate capacitance (usually several pF) to
each of the 2 or 3 most significant bits. The exact value of each
capacitor for a given application should be determined experimentally, as it will be dependent on circuit board layout and the
type of driving logic used. Table II presents a few examples of
how the glitch impulse may be reduced through passive
deskewing.
Table II. Bit Delay Glitch Reduction Examples 1
Logic
Family
Gate
Uncompensated Compensation Compensated
Glitch
Used
Glitch
HCMOS 74157 350 pV-s
STTL
74158 850 pV-s
C2 = 5 pF
R1 = 50 Ω,
C1 = 7 pF
250 pV-s
600 pV-s
NOTE
1
Measurements were made using a modified version of the fixture shown in
Figure 13, with resistors and capacitors placed as shown in Figure 15. Resistance and capacitance values were set to zero except as noted.
As Figure 15 indicates, in some cases it may prove useful to
place a few hundred ohms of series resistance in the input line
to enhance the delay effect. This approach also helps to reduce
some of the digital feedthrough glitch, as the higher frequency
spectral components are being filtered out of the most significant bits’ digital inputs.
R – C BIT DESKEWING SCHEME
R1
FROM
DRIVING
LOGIC
1
BIT 1 (MSB)
2
BIT 2
3
BIT 3
4
BIT 4
5
BIT 5
6
BIT 6
R2
C1: 1000pF CHIP CAPACITOR
14
VTH
13
RA
ANALOG
GROUND
PLANE
+5V
Figure 16. Positive Threshold Voltage Shift
Table III shows the glitch reduction achieved by shifting the
threshold voltage for HCMOS, STTL, and FAST logic.
Table III. Threshold Shift for Glitch Improvement 1
Logic
Family
Gate
Uncompensated Modified
Glitch
Threshold2
HCMOS 74HC158 350 pV-s
STTL
74S158
850 pV-s
FAST
74F158
1000 pV-s
1.7 V
1.0 V
1.3 V
Resulting
Glitch
150 pV-s
200 pV-s
480 pV-s
NOTES
1
Measurements made on a modified version of the circuit shown in Figure 13,
with a 1 V full scale.
2
Use care in any scheme that lowers the threshold voltage since the output voltage compliance of the DAC is sensitive to this voltage. If the DAC is to be operating in the voltage output mode, it is strongly suggested that the threshold
voltage be set at least 200 mV above the output voltage full scale.
Deglitching
Some applications may prove so sensitive to glitch impulse that
reduction of glitch impulse by an order of magnitude or more is
required. In order to realize glitch impulses this low, some sort
of sample-and-hold amplifier (SHA)-based deglitching scheme
must be used.
There are high-speed SHAs available with specifications sufficient to deglitch the AD568, however most are hybrid in design
at costs which can be prohibitive. A high performance, low cost
alternative shown in Figure 17 is a discrete SHA utilizing a
high-speed monolithic op amp and high-speed DMOS FET
switches.
R3
AD568
Figure 15. R-C Bit Deskewing Scheme
THRESHOLD SHIFT—It is also possible to reduce the data
skew by shifting the level of logic voltage threshold, VTH (Pin
13). This can be readily accomplished by inserting some resistance between the THRESHOLD COM pin (Pin 14) and
ground, as in Figure 16. To generate threshold voltages below
REV. A
This SHA circuit uses the inverting integrator architecture. The
AD841 operational amplifier used (300 MHz gain bandwidth
product) is fabricated on the same high-speed process as the
AD568. The time constant formed by the 200 Ω resistor and the
100 pF capacitor determines the acquisition time and also band
limits the output signal to eliminate slew induced distortion.
A discrete drive circuit is used to achieve the best performance
from the SD5000 quad DMOS switch. This switch driving cell
is composed of MPS571 RF npn transistors and an MC10124
TTL to ECL translator. Using this technique provides both
high speed and highly symmetrical drive signals for the SD5000
switches. The switches are arranged in a single-throw doublepole (SPDT) configuration. The 360 pF “flyback” capacitor is
switched to the op amp summing junction during the hold mode
to keep switching transients from feeding to the output. The capacitor is grounded during sample mode to minimize its effect
on acquisition time.
–9–
AD568
ground for the AD568. The REFERENCE COMMON (and
Bipolar offset when not used), should also be connected to this
node.
Circuit layout for a high speed SHA is almost as critical as the
design itself. Figure 17 shows a recommended layout of the
deglitching cell for a double sided printed circuit board. The
layout is very compact with care taken that all critical signal
paths are short.
200Ω
13
+15V
12
14
IN4735
360Ω
All of the current that flows into the VTH terminal (Pin 13) from
the resistor tied to the 5 V logic supply (or other convenient
positive supply) flows out the THRESHOLD COMMON (Pin
14). This ground pin should be returned directly to the digital
ground plane on its own individual line.
200Ω
11
16
9
100pF
The +5 V logic supply should be decoupled to the THRESHOLD COMMON.
360Ω
AD841
4
MC
10124
6
249Ω
249Ω
169Ω
–5V
510Ω
–15V
–15V
OUTPUT
10
8
5
5
75Ω
In order to preserve proper operation of the DAC switches, the
digital and analog grounds need to eventually be tied together.
This connection between the ground planes should be made
within 1/2" of the DAC.
169Ω
–5V
3
4
500pF
1
20kΩ
1.6Ω
The Use of Ground and Power Planes
TO PIN 2
SD5000
0.39µF
If used properly, ground planes can perform a myriad of functions on high-speed circuit boards: bypassing, shielding, current
transport, etc. In mixed signal design, the analog and digital portions of the board should be distinct from one another, with the
analog ground plane covering analog signal traces and the digital
ground plane confined to areas covering digital interconnect.
Figure 17. High Performance Deglitcher
Grounding Rules
The AD568 brings out separate reference, output, and digital
power grounds. This allows for optimum management of signal
ground currents for low noise and high-speed-settling performance. The separate ground returns are provided to minimize
changes in current flow in the analog signal paths. In this way,
logic return currents are not summed into the same return path
with the analog signals.
The two ground planes should be connected at or near the
DAC. Care should be taken to insure that the ground plane is
uninterrupted over crucial signal paths. On the digital side, this
includes the digital input lines running to the DAC and any
clock lines. On the analog side, this incudes the DAC output
signal as well as the supply feeders. The use of side runs or
planes in the routing of power lines is also recommended. This
serves the dual function of providing a low series impedance
power supply to the part as well as providing some ‘‘free’’ capacitive decoupling to the appropriate ground plane. Figure
18 illustrates many of the points discussed above. If more layers
of interconnect are available, even better results are possible.
It is important to understand which supply and signal currents
are flowing in which grounds so that they may be returned to
the proper power supply in the best possible way.
The majority of the current that flows into the VCC supply (Pin
24) flows out (depending on the DAC input code) either the
ANALOG COMMON (Pin 18), the LADDER COMMON
(Pin 17), and/or IOUT (Pin 20).
Using the Right Bypass Capacitors
The current in the LADDER COMMON is configured to be
code independent when the output current is being summed
into a virtual ground. If IOUT is operated into its own output impedance (or in any unbuffered voltage output mode) the current
in LADDER COMMON will become partially code dependent.
The current in the ANALOG COMMON (Pin 18) is an approximate complement of the current in IOUT, i.e., zero when
the DAC is at full scale and approximately 10 mA at zero input
code.
A relatively constant current (not code dependent) flows out the
REFERENCE COMMON (Pin 23).
The current flowing out of the VEE supply (Pin 22) comes from
a combination of reference ground and BIPOLAR OFFSET
(Pin 21). The plus and minus 15 V supplies are decoupled to
the REFERENCE COMMON.
The ground side of the load resistor RL, ANALOG COMMON
and LADDER COMMON should be tied together as close to
the package pins as possible. The analog output voltage is then
referred to this node and thus it becomes the “high quality”
Because the VTH pin is connected directly to the DAC switches
it should be decoupled to the analog output signal common.
Probably the most important external components associated
with any high-speed design are the capacitors used to bypass
the power supplies. Both selection and placement of these capacitors can be critical and, to a large extent, dependent upon
the specifics of the system configurations. The dominant consideration in selection of bypass capacitors for the AD568 is minimization of series resistance and inductance. Many capacitors
will begin to look inductive at 20 MHz and above, the very frequencies we are most interested in bypassing. Ceramic and filmtype capacitors generally feature lower series inductance than
tantalum or electrolytic types. A few general rules are of universal use when approaching the problem of bypassing:
Bypass capacitors should be installed on the printed circuit
board with the shortest possible leads consistent with reliable
construction. This helps to minimize series inductance in the
leads. Chip capacitors are optimal in this respect.
Some series inductance between the DAC supply pins and the
power supply plane often helps to filter out high-frequency
power supply noise. This inductance can be generated using a
small ferrite bead.
–10–
REV. A
AD568
DIGITAL GROUND
PLANE
High-Speed Interconnect and Routing
ANALOG GROUND
PLANE
CLOCK
It is essential that care be taken in the signal and power ground
circuits to avoid inducing extraneous voltage drops in the signal
ground paths. It is suggested that all connections be short and
direct, and as physically close to the package as possible, so that
the length of any conduction path shared by external components will be minimized. When runs exceed an inch or so in
length, some type of termination resistor may be required. The
necessity and value of this resistor will be dependent upon the
logic family used.
+15V
–15V
INPUT
WORDS
OUTPUT
For maximum ac performance, the DAC should be mounted directly to the circuit board; sockets should not be used as they introduce unwanted capacitive coupling between adjacent pins of
the device.
5V
AD568
SETTLING/GLITCH
EVALUATION BOARD
5V
Applications
Component Side
1 ms, 12-BIT SUCCESSIVE APPROXIMATION A/D
CONVERTER
ANALOG VCC
ANALOG VEE
The AD568’s unique combination of high speed and true 12-bit
accuracy can be used to construct a 12-bit SAR-type A/D converter with a sub-µs conversion time. Figure 19 shows the configuration used for this application. A negative analog input
voltage is converted into current and brought into a summing
junction with the DAC current. This summing junction is
bidirectionally clamped with two Schottky diodes to limit its
voltage excursion from ground. This voltage is differentially amplified and passed to a high-speed comparator. The comparator
output is latched and fed back to the successive approximation
register, which is then clocked to generated the next set of codes
for the DAC.
ANALOG +5V
+5V
Foil Side
Figure 18. Printed Circuit Board Layout
+15V
VI N
0 TO –10.24V
–15V
+5V
2.5k
0.2µF
+5V
Q11 21
1
+15V 24
12 GND
Q10 20
2
REFCOM 23
Q9 19
SAR
23 Q11 2504 Q8 18
3
–15V 22
4
IBPO 21
2 D0
620
Q7 17
5
Q6 16
6
22 NC
Q5 9
7
13 CP
Q4 8
8
LCOM 17
DAC
AD568
620
150
0.1µF
0.1µF
Q3
0.01µF
D3
1k
COMPARATOR
LT1016
1 V+
OUT 8
2 +IN
OUT 7
3 –IN
GND 6
4
LCH 5
Q1
RL 19
D1
ACOM 18
Q2
D2
27k
ANALOG
GND PLANE
1 E
Q3 7
9
SPAN 16 NC
14 S
Q2 6
10
SPAN 15 NC
3 CC
Q1 5
11
THCOM 14
11 D
Q0 4
12
VTH 13
+5V
–15V
15kΩ
100pF
150kΩ
Q4
1k
INVERTER
74HC04
150kΩ
PARALLEL DATA
OUT
Q5
+5V
CONVERSION COMPLETE
START COMVERT
CHIP ENABLE
Figure 19. AD568 1 µ s Successive Approximation A/D Application
REV. A
V–
IN4148
IOUT 20
10 NC
15 NC
–5V
1k
0.1µF
24 VCC
–5V
–11–
AD568
Circuit Details
Figure 20 shows an approximate timing budget for the A/D converter. If 12 cycles are to be completed in 1 µs, approximately
80 ns is allowed for each cycle. Since the Schottky diodes clamp
the voltage of the summing junction, the DAC settling time approaches the current-settling value of 35 ns, and hence uses up
less than half the timing budget.
To maintain simplicity, a simple clock is used that runs at a
constant rate throughout the conversion, with a duty cycle of
approximately 90%. If absolute speed is worth the additional
complexity, the clock frequency can be increased as the conversion progresses since the DAC must settle from increasingly
smaller steps.
When seeking a cycle time of less than 100 ns, the delays generated by the older generation SAR registers become problematic.
Newer, high speed SAR logic chips are becoming available in
the classic 2504 pinout that cuts the logic overhead in half. One
example of this is Zyrel’s ZR2504.
Finding a comparator capable of keeping up with this DAC arrangement is fairly difficult: it must respond to an overdrive of
250 µV (1 LSB) in less than 25 ns. Since no inexpensive comparator exists with these specs, special arrangements must be
made. The LT106 comparator provides relatively quick response, but requires at least 5 mV of overdrive to maintain this
speed. A discrete preamplifier may be used to amplify the summing junction voltage to sufficiently overdrive the comparator.
Care must be exercised in the layout of the preamp/comparator
block to avoid introducing comparator instability with the
preamp’s additional gain.
SAR
DELAY
DAC SETTLING
10ns
35ns
PREAMP
DELAY
15ns
COMPARATOR
DELAY
10ns
10ns
20ns
30ns
40ns
50ns
START OF
CLOCK CYCLE
60ns
In the application shown in Figure 21, the AD568 is used in a
buffered voltage output mode to generate the input to the
AD539’s control channel. The speed of the AD568 allows
oversampling of the control signal waveform voltage, thereby
providing increased spectral purity of the amplitude envelope
that modulates the analog input channels.
The AD568 is configured in the unbuffered unipolar output
mode. The internal 200 Ω load resistor creates the 0-1 V FS
output signal, which is buffered and amplified to a 0-3 V range
suitable for the control channel of the AD539.
A 500 Ω input impedance exists at Pin 1, the input channel. To
provide a buffer for the 0-1 V output signal from the AD568
looking into the impedance and to achieve the full-scale range,
the AD841, high-speed, fast settling op amp is included. The
gain of 3 is achieved with a 2 kΩ resistor configured in follower
mode with a 1 kΩ pot and 500 Ω resistor. A 20 kΩ pot with
connections to Pins 3, 4 and 12 is provided for offset trim.
The AD539 can accept two separate input signals, each with a
nominal full-scale voltage range of ± 2 V. Each signal can then
be simultaneously controlled by the AD568 signal at the common input channels, Pins 11 and 14, applied to the AD5539 in
a subtracting configuration, provide the voltage output signal:
V OUT =
70ns
V Y1 –V Y 2
D
×
(0≤ D ≤4095)
2V
4096
For applications where only a single channel is involved, channel 2, VY2, is tied to ground. This provides:
10ns
V OUT =
CLOCK
PULSE
0
AD5539 wideband op amp, a high-speed multiplying DAC can
be built.
80ns
START OF NEXT
CLOCK CYCLE
LATCH COMPARATOR
Figure 20. Typical Clock Cycle for a 1 µ s SAR A/D
Converter
V Y1
D
×
(0≤ D ≤4095)
4096 2V
Some AD539 circuit details: The control amplifier compensation capacitor for Pin 2, CC, must have a minimum value of
300 pF to provide circuit stability. For improved bandwidth and
feedthrough, the feedthrough capacitor between Pins 1 and 2
should be 5-20% of CC. A Schottky diode at Pin 2 can improve
recovery time from small negative values of VX. Lead lengths
along the path of the high-speed signal from AD568 should be
kept at a minimum.
HIGH-SPEED MULTIPLYING DAC
A powerful use for the AD568 is found in multiplying applications, where the DAC controls the amplitude of a high-speed
signal. Specifically, using the AD568 as the control voltage
input signal for the AD539 60 MHz analog multiplier and
–12–
REV. A
AD568
+VS
12
+15V
–15V
0.2µF
20kΩ
4
6
3
AD841
0.1µF
DIGITAL
INPUTS
1
+15V 24
2
REFCOM 23
3
–15V 22
4
IBPO 21
5
IOUT 20
6
AD568
0.1µF
LCOM 17
9
SPAN 16 NC
ANALOG
GND PLANE
VTH 13
Cc
3000pF
DIGITAL
GND PLANE
100pF
HF
COMP
50k
(OPTIONAL)
OUTPUT
OFFSET
Z1 15
100k
AD568
3 CH1
INPUT
+9V
2.7Ω
180Ω
10Ω
ANALOG
SUPPLY
GROUND
4 +VS
+9V
1µF
–9V
DIGITAL
SUPPLY
GROUND
5
–VS
VOUT
AD5539N
12
8
7
14
180Ω
6 CH2
INPUT
10
1
VY1IN
RTH
1kΩ
0.47µF
13
BASE
COMMON
1µF
–9V
CH1 14
OUTPUT
75Ω
10Ω
SPAN 15 NC
12
VY1IN
500Ω
8
THCOM 14
2kΩ
ANALOG
OUTPUT
RL 19
+9V
2
1kΩ
W1 16
Cff
100pF
–VS
0.1µF
ACOM 18
11
1 CONTROL
10
5
D1
7
10
VX
11
3
–9V
CH2 11
OUTPUT
CF
75Ω
INPUT
COMMON
Z2 10
8 OUTPUT
COMMON
W2 9
7
0.25pF –
1.5pF
+5V
200Ω
GAIN
ADJUST
(±4% RANGE)
D1: THOMPSON CSFBAR – 10 OR SIMILAR SCHOTTKY DIODE
SHORT, DIRECT CONNECTION TO GROUND PLANE.
Figure 21. Wideband Digitally Controlled Multiplier
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Cerdip (Suffix Q)
REV. A
–13–
470Ω
2.7Ω
–9V
0.47µF
–14–
PRINTED IN U.S.A.
C1014a–9–7/87