TI1 MSP430G2302IPW1REP Mixed signal microcontroller Datasheet

MSP430G2302-EP
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MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
23
•
•
•
•
•
•
•
•
Low Supply Voltage Range: 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode: 220 µA at 1 MHz, 2.2 V
– Standby Mode: 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies
– Internal Very-Low-Power Low-Frequency
(LF) Oscillator
– 32-kHz Crystal
– External Digital Clock Source
One 16-Bit Timer_A With Three
Capture/Compare Registers
Up to 16 Touch-Sense Enabled I/O Pins
Universal Serial Interface (USI) Supporting SPI
and I2C
Brownout Detector
•
•
•
•
•
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
Family Members are Summarized in Table 1
Package Options
– TSSOP: 14 Pin
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(1)
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Extended (–40°C to 85°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Custom temperature ranges available
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2302 series of microcontrollers are ultra-low-power mixed signal microcontrollers with built-in
16-bit timers, and up to 16 I/O touch sense enabled pins and built-in communication capability using the
universal serial communication interface. For configuration details, see Table 1. Typical applications include lowcost sensor systems that capture analog signals, convert them to digital values, and then process the data for
display or for transmission to a host system.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Table 1. Available Options (1)
Device
MSP430G2302IPW1REP
(1)
EEM
Flash
(kB)
RAM
(B)
Timer_A
ADC10
Channel
USI
CLOCK
I/O
Package Type
1
4
256
1x TA3
-
1
LF, DCO, VLO
10
14-TSSOP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Table 2. ORDERING INFORMATION (1)
TA
PACKAGE
–40°C to 85°C
TSSOP - PW
(1)
2
ORDERABLE PART NUMBER
MSP430G2302IPW1EP
MSP430G2302IPW1REP
TOP-SIDE MARKING
VID NUMBER
G2302EP
V62/12623-01XE
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE PINOUTS
PW PACKAGE
(TOP VIEW)
DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREFP1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/TCK
P1.5/TA0.0/SCLK/A5/TMS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/SDI/SDA/A7/TDO/TDI
P1.6/TA0.1/SDO/SCL/A6/TDI/TCLK
NOTE: The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting P2REN.x = 1.
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FUNCTIONAL BLOCK DIAGRAMS
Functional Block Diagram, MSP430G2302
XIN
XOUT
DVCC
DVSS
P1.x
P2.x
up to 8
8
ACLK
Clock
System
Flash
RAM
8KB
4KB
2KB
1KB
256B
256B
256B
128B
SMCLK
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
JTAG
Interface
Port P1
Port P2
8 I/O
Interrupt
capability
pull-up/down
resistors
up to 8 I/O
Interrupt
capability
pull-up/down
resistors
USI
Brownout
Protection
Watchdog
WDT+
15-Bit
Spy-Bi
Wire
Timer0_A3
3 CC
Registers
Universal
Serial
Interface
SPI, I2C
RST/NMI
NOTE: Port P2: Two pins are available on the 14-pin package option. Eight pins are available on the 20-pin package option.
4
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TERMINAL FUNCTIONS
Table 3. Terminal Functions
TERMINAL
NAME
NO.
I/O
P1.0/
TA0CLK/
ACLK/
DESCRIPTION
PW14
General-purpose digital I/O pin
2
I/O
A0
Timer0_A, clock signal TACLK input
ACLK signal output
ADC10 analog input A0
P1.1/
TA0.0/
General-purpose digital I/O pin
3
I/O
A1
Timer0_A, capture: CCI0A input, compare: Out0 output
ADC10 analog input A1
P1.2/
TA0.1/
General-purpose digital I/O pin
4
I/O
Timer0_A, capture: CCI1A input, compare: Out1 output
A2
ADC10 analog input A2
P1.3/
General-purpose digital I/O pin
ADC10CLK/
A3/
5
I/O
ADC10, conversion clock output
ADC10 analog input A3
VREF-/VEREF
ADC10 negative reference voltage
P1.4/
General-purpose digital I/O pin
TA0.2/
Timer0_A, capture: CCI2A input, compare: Out2 output
SMCLK/
A4/
6
I/O
SMCLK signal output
ADC10 analog input A4
VREF+/VEREF+/
ADC10 positive reference voltage
TCK
JTAG test clock, input terminal for device programming and test
P1.5/
General-purpose digital I/O pin
TA0.0/
A5/
Timer0_A, compare: Out0 output
7
I/O
ADC10 analog input A5
SCLK/
USI: clk input in I2C mode; clk in/output in SPI mode
TMS
JTAG test mode select, input terminal for device programming and test
P1.6/
General-purpose digital I/O pin
TA0.1/
Timer0_A, compare: Out1 output
A6/
ADC10 analog input A6
SDO/
8
I/O
USI: Data output in SPI mode
SCL/
USI: I2C clock in I2C mode
TDI/
JTAG test data input or test clock input during programming and test
TCLK
P1.7/
General-purpose digital I/O pin
A7/
ADC10 analog input A7
SDI/
9
I/O
USI: Data input in SPI mode
SDA/
USI: I2C data in I2C mode
TDO/TDI (1)
JTAG test data output terminal or test data input during programming and test
XIN/
P2.6/
Input terminal of crystal oscillator
13
I/O
TA0.1
(1)
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
TDO or TDI is selected via JTAG instruction.
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Table 3. Terminal Functions (continued)
TERMINAL
NAME
XOUT/
P2.7
NO.
I/O
DESCRIPTION
PW14
12
I/O
10
I
RST/
Output terminal of crystal oscillator (2)
General-purpose digital I/O pin
Reset
NMI/
SBWTDIO/
TEST/
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
11
I
DVCC
1
NA
Supply voltage
AVCC
NA
NA
Supply voltage
DVSS
14
NA
Ground reference
AVSS
NA
NA
Ground reference
NC
-
NA
Not connected
QFN Pad
-
NA
QFN package pad connection to VSS recommended.
SBWTCK
(2)
6
Spy-Bi-Wire test clock input during programming and test
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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SHORT-FORM DESCRIPTION
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
Constant Generator
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 4 shows examples of the three types of
instruction formats; Table 5 shows the address
modes.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 4. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
FORMAT
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, un/conditional
Table 5. Address Mode Descriptions (1)
S
D
SYNTAX
EXAMPLE
Register
ADDRESS MODE
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) → M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) → M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
(1)
OPERATION
S = source, D = destination
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Operating Modes
The MSP430 devices have one active mode and five software selectable low-power modes of operation. An
interrupt event can wake up the device from any of the low-power modes, service the request, and restore back
to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– DCO's dc generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
8
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 6. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
Watchdog Timer+
Timer0_A3
Timer0_A3
(2)
(3)
(4)
(5)
TACCR0 CCIFG
(4)
TACCR2 TACCR1 CCIFG.
TAIFGTable 4 (4)
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
31, highest
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
0FFF6h
27
maskable
0FFF4h
26
maskable
0FFF2h
25
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
USI
USIIFG, USISTTIFG (2) (4)
maskable
0FFE8h
20
I/O Port P2 (up to eight flags)
P2IFG.0 to P2IFG.7 (2) (4)
maskable
0FFE6h
19
I/O Port P1 (up to eight flags)
(2) (4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
0FFDEh to
0FFC0h
15 to 0, lowest
See
(1)
WDTIFG
SYSTEM
INTERRUPT
(5)
P1IFG.0 to P1IFG.7
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 7. Interrupt Enable Register 1 and 2
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
2
1
0
01h
Table 8. Interrupt Flag Register 1 and 2
Address
7
6
5
02h
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault.
Power-On Reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
7
6
5
4
3
2
1
0
03h
10
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Memory Organization
Table 9. Memory Organization
MSP430G2302
Memory
Size
4kB
Main: interrupt vector
Flash
0xFFFF to 0xFFC0
Main: code memory
Flash
0xFFFF to 0xF000
Information memory
Size
256 Byte
Flash
010FFh to 01000h
Size
256 B
RAM
0x02FF to 0x0200
Peripherals
16-bit
01FFh to 0100h
8-bit
0FFh to 010h
8-bit SFR
0Fh to 00h
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
Calibration Data Stored in Information Memory Segment A
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.
Table 10. Tags Used by the ADC Calibration Tags
NAME
ADDRESS
VALUE
DESCRIPTION
TAG_DCO_30
0x10F6
0x01
DCO frequency calibration at VCC = 3 V and TA = 30°C at calibration
TAG_ADC10_1
0x10DA
0x10
ADC10_1 calibration tag
TAG_EMPTY
-
0xFE
Identifier for empty memory areas
Table 11. Labels Used by the ADC Calibration Tags
LABEL
SIZE
ADDRESS OFFSET
INCHx = 0x1010, REF2_5 = 1, TA = 85°C
word
0x0010
CAL_ADC_25T30
INCHx = 0x1010, REF2_5 = 1, TA = 30°C
word
0x000E
CAL_ADC_25VREF_FACTOR
12
CONDITION AT CALIBRATION / DESCRIPTION
CAL_ADC_25T85
REF2_5 = 1, TA = 30°C, I(VREF+) = 1 mA
word
0x000C
CAL_ADC_15T85
INCHx = 0x1010, REF2_5 = 0, TA = 85°C
word
0x000A
CAL_ADC_15T30
INCHx = 0x1010, REF2_5 = 0, TA = 30°C
word
0x0008
CAL_ADC_15VREF_FACTOR
REF2_5 = 0, TA = 30°C, I(VREF+) = 0.5 mA
word
0x0006
CAL_ADC_OFFSET
External VREF = 1.5 V, f(ADC10CLK) = 5 MHz
word
0x0004
CAL_ADC_GAIN_FACTOR
External VREF = 1.5 V, f(ADC10CLK) = 5 MHz
word
0x0002
CAL_BC1_1MHz
-
byte
0x0009
CAL_DCO_1MHz
-
byte
0x00008
CAL_BC1_8MHz
-
byte
0x0007
CAL_DCO_8MHz
-
byte
0x0006
CAL_BC1_12MHz
-
byte
0x0005
CAL_DCO_12MHz
-
byte
0x0004
CAL_BC1_16MHz
-
byte
0x0003
CAL_DCO_16MHz
-
byte
0x0002
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Main DCO Characteristics
• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
• DCO control bits DCOx have a step size as defined by parameter SDCO.
• Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are two 8-bit I/O ports implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition(port P1 and port P2 only) is possible.
• Edge-selectable interrupt input capability for all the eight bits of port P1 and port P2, if available.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
• Each I/O has an individually programmable pin-oscillator enable bit to enable low-cost touch sensing.
WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
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Timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. Timer0_A3 Signal Connections (1)
INPUT PIN NUMBER
PW14
P1.0-2
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
PinOsc
P1.1-3
P1.2-4
(1)
MODULE BLOCK
Timer
MODULE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
PW14
NA
INCLK
TA0.0
CCI0A
ACLK
CCI0B
VSS
GND
VCC
VCC
TA0.1
CCI1A
CAOUT
CCI1B
VSS
GND
VCC
VCC
P1.4-6
TA0.2
CCI2A
PinOsc
TA0.2
CCI2B
VSS
GND
VCC
VCC
P1.1-3
CCR0
TA0
P1.5-7
P1.2-4
CCR1
TA1
P1.6-8
P2.6-13
P1.4-6
CCR2
TA2
Only one pin-oscillator must be enabled at a time.
USI
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
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Peripheral File Map
Table 13. Peripherals With Word Access
MODULE
Timer0_A3
Flash Memory
Watchdog Timer+
REGISTER DESCRIPTION
REGISTER
NAME
OFFSET
Capture/compare register
TACCR2
0176h
Capture/compare register
TACCR1
0174h
Capture/compare register
TACCR0
0172h
Timer_A register
TAR
0170h
Capture/compare control
TACCTL2
0166h
Capture/compare control
TACCTL1
0164h
Capture/compare control
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
Watchdog/timer control
WDTCTL
0120h
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Table 14. Peripherals With Byte Access
MODULE
USI
Basic Clock System+
Port P2
Port P1
Special Function
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REGISTER DESCRIPTION
REGISTER
NAME
OFFSET
USI control 0
USICTL0
078h
USI control 1
USICTL1
079h
USI clock control
USICKCTL
07Ah
USI bit counter
USICNT
07Bh
USI shift register
USISR
07Ch
Basic clock system control 3
BCSCTL3
053h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P2 selection 2
P2SEL2
042h
Port P2 resistor enable
P2REN
02Fh
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection 2
P1SEL2
041h
Port P1 resistor enable
P1REN
027h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
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Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin (2)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
±2 mA
Storage temperature range, Tstg (3)
(1)
(2)
(3)
Unprogrammed device
–55°C to 150°C
Programmed device
–55°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Information
MSP430G2302
THERMAL METRIC
PW
UNITS
14 PINS
Junction-to-ambient thermal resistance (1)
θJA
(2)
98.7
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (3)
41.2
ψJT
Junction-to-top characterization parameter (4)
1.1
ψJB
Junction-to-board characterization parameter (5)
40.5
θJCbot
Junction-to-case (bottom) thermal resistance (6)
N/A
(1)
(2)
(3)
(4)
(5)
(6)
26.8
°C/W
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Recommended Operating Conditions
MIN
VCC
Supply voltage
VSS
Supply voltage
TA
Operating free-air temperature
(1)
(2)
MAX
1.8
3.6
During flash programming/erase
2.2
3.6
0
Processor frequency (maximum MCLK frequency
using the USART module) (1) (2)
fSYSTEM
NOM
During program execution
UNIT
V
V
-40
85
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
6
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC = 3.3 V,
Duty cycle = 50% ± 10%
dc
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency - MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
Note:
2.7 V
2.2 V
Supply Voltage - V
3.3 V 3.6 V
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
Active mode (AM)
current (1 MHz)
IAM,1MHz
(1)
(2)
TEST CONDITIONS
VCC
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
MIN
TYP
2.2 V
220
3V
320
MAX
UNIT
µA
400
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics – Active Mode Supply Current (Into VCC)
5.0
4.0
Active Mode Current − mA
Active Mode Current − mA
f DCO = 16 MHz
4.0
3.0
f DCO = 12 MHz
2.0
f DCO = 8 MHz
1.0
TA = 85 °C
3.0
TA = 25 °C
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
f DCO = 1 MHz
0.0
1.5
2.0
2.5
3.0
3.5
VCC = 2.2 V
4.0
VCC − Supply Voltage − V
Figure 2. Active Mode Current vs VCC, TA = 25°C
Copyright © 2012, Texas Instruments Incorporated
0.0
0.0
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 3. Active Mode Current vs DCO Frequency
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TA
VCC
Low-power mode 0
(LPM0) current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25°C
2.2 V
55
µA
ILPM2
Low-power mode 2
(LPM2) current (4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
ILPM3,LFXT1
Low-power mode 3
(LPM3) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.7
1.0
µA
ILPM3,VLO
Low-power mode 3
current, (LPM3) (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.5
0.7
µA
2.2 V
0.1
0.5
µA
ILPM4
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25°C
Low-power mode 4
(LPM4) current (5)
85°C
2.2 V
0.8
1.5
µA
ILPM0,1MHz
(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
MIN
(2)
TYP
MAX
UNIT
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
Typical Characteristics Low-Power Mode Supply Currents
2.0
1.0
1.8
0.9
ILPM4 − Low−power mode current − µA
ILPM3 − Low−power mode current − µA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
1.6
1.4
1.2
VCC = 3.6 V
1.0
VCC = 3 V
0.8
VCC = 2.2 V
0.6
0.4
VCC = 1.8 V
0.2
0.0
−40.0 −20.0 0.0
20.0 40.0 60.0 80.0 100.0 120.0
TA − Temperature − °C
Figure 4. LPM3 Current vs Temperature
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0.8
0.7
0.6
0.5
VCC = 3.6 V
0.4
VCC = 3 V
0.3
VCC = 2.2 V
0.2
0.1
0.0
−40.0 −20.0 0.0
VCC = 1.8 V
20.0 40.0 60.0 80.0 100.0 120.0
TA − Temperature − C
Figure 5. LPM4 Current vs Temperature
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Schmitt-Trigger Inputs – Ports Px (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
MIN
RPull
Pullup/pulldown resistor
CI
Input capacitance
VIN = VSS or VCC
TYP
MAX
0.45 VCC
0.75 VCC
1.35
2.25
3V
For pullup: VIN = VSS
For pulldown: VIN = VCC
(1)
VCC
UNIT
V
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1
V
3V
20
50
kΩ
35
V
5
pF
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int).
Leakage Current – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.x)
(1)
(2)
TEST CONDITIONS
High-impedance leakage current
See
(1)
and
VCC
(2)
MIN
3V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input, and the pullup/pulldown resistor is
disabled.
Outputs – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
I(OHmax) = –6 mA
VOL
Low-level output voltage
I(OLmax) = 6 mA (1)
(1)
VCC
(1)
MIN
TYP
MAX
UNIT
3V
VCC – 0.3
V
3V
VSS + 0.3
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPx.y
Port output frequency (with load)
fPort_CLK
(1)
(2)
Clock output frequency
TEST CONDITIONS
Px.y, CL = 20 pF, RL = 1 kΩ (1)
Px.y, CL = 20 pF
(2)
VCC
(2)
MIN
TYP
MAX
UNIT
3V
12
MHz
3V
16
MHz
A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW -LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOL TAGE
TYPICAL LOW -LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOL TAGE
50.0
VCC = 2.2 V
P1.7
TA = 25°C
25.0
TA = 85°C
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
30.0
VCC = 3 V
P1.7
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
TA = 25°C
VOL − Low-Level Output Voltage − V
0.5
1.0
Figure 6.
3.0
3.5
0.0
VCC = 2.2 V
P1.7
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−5.0
−10.0
−15.0
TA = 85°C
−20.0
TA = 25°C
0.5
1.0
1.5
2.0
VOH − High-Level Output Voltage − V
Figure 8.
22
2.0
Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−25.0
0.0
1.5
VOL − Low-Level Output Voltage − V
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2.5
VCC = 3 V
P1.7
−10.0
−20.0
−30.0
TA = 85°C
−40.0
TA = 25°C
−50.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 9.
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Pin-Oscillator Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
foP1.x
Port output oscillation frequency
foP2.x
Port output oscillation frequency
foP2.6/7
Port output oscillation frequency
(1)
(2)
P1.y, CL = 10 pF, RL = 100 kΩ
VCC
MIN
(1) (2)
3V
P1.y, CL = 20 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 10 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ (1) (2)
P2.6 and P2.7, CL = 20 pF, RL = 100 kΩ (1) (2)
3V
3V
TYP
MAX
1400
UNIT
kHz
900
1800
kHz
1000
700
kHz
A resistive divider with two 100-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage oscillates with a typical amplitude of 700 mV at the specified toggle frequency.
Typical Characteristics – Pin-Oscillator Frequency
TYPICAL OSCILLATING FREQUENCY
vs
LOAD CAPACITANCE
TYPICAL OSCILLATING FREQUENCY
vs
LOAD CAPACITANCE
1.50
VCC = 2.2 V
1.35
1.20
1.05
P1.y
0.90
P2.0 ... P2.5
0.75
P2.6, P2.7
0.60
0.45
0.30
0.15
0.00
fosc − Typical Oscillation Frequency − MHz
fosc − Typical Oscillation Frequency − MHz
1.50
VCC = 3.0 V
1.35
1.20
1.05
P1.y
0.90
P2.0 ... P2.5
0.75
P2.6, P2.7
0.60
0.45
0.30
0.15
0.00
10
50
100
CLOAD − External Capacitance − pF
Figure 10.
Copyright © 2012, Texas Instruments Incorporated
10
50
100
CLOAD − External Capacitance − pF
Figure 11.
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POR/Brownout Reset (BOR) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
See Figure 12
dVCC/dt ≤ 3 V/s
V(B_IT–)
See Figure 12 through Figure 14
dVCC/dt ≤ 3 V/s
1.40
V
Vhys(B_IT–)
See Figure 12
dVCC/dt ≤ 3 V/s
140
mV
td(BOR)
See Figure 12
t(reset)
Pulse length needed at RST/NMI pin to
accepted reset internally
(1)
0.7 × V(B_IT–)
V
2000
2.2 V
2
µs
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT–)is ≤ 1.8 V.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 12. POR/Brownout Reset (BOR) vs Supply Voltage
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Typical Characteristics – POR/Brownout Reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
t pw − Pulse Width − µs
1 ns
t pw − Pulse Width − µs
Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Supply voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
V
RSELx = 14
2.2
3.6
V
RSELx = 15
3
3.6
V
0.14
MHz
0.17
MHz
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
0.06
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3V
0.07
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3V
0.15
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3V
0.21
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3V
0.30
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3V
0.41
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3V
0.58
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3V
1.6
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3V
2.3
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3V
3.4
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3V
4.25
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
ratio
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
ratio
Measured at SMCLK output
3V
50
Duty cycle
26
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%
Copyright © 2012, Texas Instruments Incorporated
MSP430G2302-EP
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SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
Calibrated DCO Frequencies – Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over
temperature (1)
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
1-MHz tolerance over VCC
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
30°C
1.8 V to 3.6 V
-3
±2
+3
%
1-MHz tolerance overall
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
1.8 V to 3.6 V
-6
±3
+6
%
8-MHz tolerance over
temperature (1)
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
8-MHz tolerance over VCC
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
30°C
2.2 V to 3.6 V
-3
±2
+3
%
8-MHz tolerance overall
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.2 V to 3.6 V
-6
±3
+6
%
12-MHz tolerance over
temperature (1)
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
12-MHz tolerance over VCC
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
30°C
2.7 V to 3.6 V
-3
±2
+3
%
12-MHz tolerance overall
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.7 V to 3.6 V
-6
±3
+6
%
16-MHz tolerance over
temperature (1)
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3.3 V
-3
±0.5
+3
%
16-MHz tolerance over VCC
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
30°C
3.3 V to 3.6 V
-3
±2
+3
%
16-MHz tolerance overall
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
3.3 V to 3.6 V
-6
±3
+6
%
(1)
This is the frequency change from the measured frequency at 30°C over temperature.
Copyright © 2012, Texas Instruments Incorporated
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MSP430G2302-EP
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Wake-Up From Lower-Power Modes (LPM3/4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDCO,LPM3/4
DCO clock wake-up time from
LPM3/4 (1)
tCPU,LPM3/4
CPU wake-up time from LPM3/4 (2)
(1)
(2)
VCC
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
MIN
3V
TYP
1.5
MAX
UNIT
µs
1/fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4
DCO Wake Time − us
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 15. DCO Wake-Up Time From LPM3 vs DCO Frequency
28
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SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
CL,eff
Integrated effective load
capacitance, LF mode (2)
XTS = 0, LFXT1Sx = 0 or 1
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Oscillator fault frequency,
LF mode (3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
fFault,LF
(4)
10000
500
LF mode
(3)
1.8 V to 3.6 V
MAX
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
Duty cycle
(2)
TYP
1.8 V to 3.6 V
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
(1)
MIN
2.2 V
30
2.2 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TA
VCC
MIN
TYP
MAX
fVLO
VLO frequency (1)
PARAMETER
-40°C to 85°C
3V
4
12
20
dfVLO/dT
VLO frequency temperature drift
-40°C to 85°C
3V
dfVLO/dVCC
VLO frequency supply voltage drift
25°C
1.8 V to 3.6 V
(1)
UNIT
kHz
0.5
%/°C
4
%/V
Ensured by design on specified temperature.
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
SMCLK
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TA0, TA1
Copyright © 2012, Texas Instruments Incorporated
VCC
MIN
TYP
MAX
fSYSTEM
3V
20
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UNIT
MHz
ns
29
MSP430G2302-EP
SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
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USI, Universal Serial Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fUSI
USI module clock frequency
External: SCLK,
Duty cycle = 50% ± 10%
f(SCLK)
Serial clock frequency, slave mode
SPI slave mode
Low-level output voltage on SDA and SCL
USI module in I2C mode,
I(OLmax) = 1.5 mA
VOL,I2C
VCC
MIN
TYP
MAX
fSYSTEM
UNIT
MHz
3V
6
3V
VSS
+ 0.4
VSS
MHz
V
Typical Characteristics – USI Low-Level Output Voltage on SDA and SCL
5.0
5.0
VCC = 2.2 V
VCC = 3 V
I OL − Low-Level Output Current − mA
I OL − Low-Level Output Current − mA
TA = 25°C
4.0
TA = 25°C
3.0
TA = 85°C
2.0
1.0
0.0
0.0
0.2
0.4
0.6
0.8
4.0
TA = 85°C
3.0
2.0
1.0
0.0
0.0
1.0
VOL − Low-Level Output Voltage − V
0.2
0.4
0.6
0.8
1.0
VOL − Low-Level Output Voltage − V
Figure 16. USI Low-Level Output Voltage vs Output Current
Figure 17. USI Low-Level Output Voltage vs Output Current
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V, 3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V, 3.6 V
1
7
mA
tCPT
Cumulative program time (1)
2.2 V, 3.6 V
10
ms
tCMErase
Cumulative mass erase time
2.2 V, 3.6 V
tRetention
Data retention duration
20
104
Program and erase endurance
TJ = 25°C
ms
105
100
cycles
years
Word or byte program time
See
(2)
30
tFTG
Block program time for first byte or word
See
(2)
25
tFTG
tBlock, 1-63
Block program time for each additional
byte or word
See
(2)
18
tFTG
tBlock,
Block program end-sequence wait time
See
(2)
6
tFTG
Mass erase time
See
(2)
10593
tFTG
tWord
tBlock,
0
End
tMass Erase
(1)
(2)
30
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word or byte write mode and block write mode.
These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
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SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
Flash Memory (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSeg Erase
Segment erase time
Copyright © 2012, Texas Instruments Incorporated
TEST CONDITIONS
See
(2)
VCC
MIN
TYP
MAX
4819
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UNIT
tFTG
31
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RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
TEST CONDITIONS
(1)
MIN
CPU halted
MAX
1.6
UNIT
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V
15
100
fTCK
TCK input frequency (2)
2.2 V
0
5
MHz
RInternal
Internal pulldown resistance on TEST
2.2 V
25
90
kΩ
(1)
(2)
TEST CONDITIONS
VCC
MIN
TYP
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
32
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
PIN SCHEMATICS
Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL2.y
PxSEL.y
PxDIR.y
0
1
0
Direction
0: Input
1: Output
2
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
PxOUT.y
DVSS
DVCC
0
1
1
0
From Module
1
0
3
2
Bus
Keeper
EN
P1.0/TA0CLK/ACLK/A0*
P1.1/TA0.0/A1*
P1.2/TA0.1/A2*
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
* Note: MSP430G2x32 devices only. MSP430G2x02 devices have no ADC10.
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Table 15. Port P1 (P1.0 to P1.2) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
CONTROL BITS / SIGNALS (1)
P1DIR.x
P1SEL.x
P1SEL2.x
I: 0; O: 1
0
0
TA0.TACLK
0
1
0
ACLK/
ACLK
1
1
0
Pin Osc
Capacitive sensing
x
0
1
P1.1/
P1.x (I/O)
I: 0; O: 1
0
0
TA0.0
1
1
0
TA0.CCI0A
0
1
0
Pin Osc
Capacitive sensing
X
0
1
P1.2/
P1.x (I/O)
I: 0; O: 1
0
0
TA0.1
1
1
0
TA0.CCI1A
0
1
0
Capacitive sensing
X
0
1
P1.0/
P1.x (I/O)
TA0CLK/
TA0.0/
1
TA0.1/
2
Pin Osc
(1)
34
0
X = don't care
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SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger
SREF2 *
VSS
0
1
To ADC10 VREF- *
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL2.y PxSEL.y
PxDIR.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
PxSEL2.y
PxSEL.y
PxOUT.y
From ADC10 *
0
1
DVSS
DVCC
0
1
1
0
1
2
Bus
Keeper
EN
3
P1.3/ADC10CLK*/A3*/
VREF-*/VEREF-*
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
* Note: MSP430G2x32 devices only. MSP430G2x02 devices have no ADC10.
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Table 16. Port P1 (P1.3) Pin Functions
PIN NAME
(P1.x)
CONTROL BITS / SIGNALS (1)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.x=1)
0
P1.3/
P1.x (I/O)
I: 0; O: 1
0
0
ADC10CLK/
ADC10CLK
1
1
0
0
A3/
A3
X
X
X
1 (y = 3)
3
VREF-/
VREF-
X
X
X
1
VEREF-/
VEREF-
X
X
X
1
Pin Osc
Capacitive sensing
X
0
1
0
(1)
36
X = don't care
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SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger
From/To ADC10 Ref+ *
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
PxSEL2.y
PxSEL.y
PxOUT.y
SMCLK
0
1
from Timer
2
3
0
1
DVSS
0
DVCC
1
Bus
Keeper
EN
1
P1.4/SMCLK/TA0.2/A4*/
VREF+*/VEREF+*/TCK
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
EN
Q
Set
PxIRQ.y
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
* Note: MSP430G2x32 devices only. MSP430G2x02 devices have no ADC10.
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Table 17. Port P1 (P1.4) Pin Functions
CONTROL BITS / SIGNALS (1)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.x=1)
JTAG Mode
P1.4/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
SMCLK/
SMCLK
1
1
0
0
0
TA0.2/
TA0.2
1
1
1
0
0
TA0.CCI2A
0
1
1
0
0
VREF+
X
X
X
1
0
VEREF+/
VEREF+
X
X
X
1
0
A4/
A4
X
X
X
1 (y = 4)
0
TCK/
TCK
X
X
X
0
1
Pin Osc
Capacitive sensing
X
0
1
0
0
VREF+/
(1)
38
4
X = don't care
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SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
PxOUT.y
DVSS
DVCC
0
1
1
0
From Module
1
0
3
2
Bus
Keeper
EN
P1.5/TA0.0/SCLK/A5*/TMS
P1.6/TA0.1/SDO/SCL/A6*/TDI/TCLK
P1.7//SDI/SDA/A7*/TDO/TDI
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
* Note: MSP430G2x32 devices only. MSP430G2x02 devices have no ADC10.
Copyright © 2012, Texas Instruments Incorporated
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MSP430G2302-EP
SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
www.ti.com
Table 18. Port P1 (P1.5 to P1.7) Pin Functions
PIN NAME
(P1.x)
CONTROL BITS / SIGNALS (1)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
USIP.x
JTAG Mode
ADC10AE.x
(INCH.x=1)
I: 0; O: 1
0
0
0
0
0
1
1
0
0
0
0
from USI
1
0
1
0
0
A5
X
X
X
0
0
1 (y = 5)
TMS/
TMS
X
X
X
0
1
0
Pin Osc
Capacitive sensing
X
0
1
0
0
0
P1.6/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
0
TA0.1/
TA0.1
1
1
0
0
0
0
SDO/
SPI mode
from USI
1
0
!
0
0
I2C mode
P1.5/
P1.x (I/O)
TA0.0/
TA0.0
SCLK/
SPI mode
5
A5/
SCL/
from USI
1
0
!
0
0
A6/
6
A6
X
X
X
0
0
1 (y = 6)
TDI/TCLK/
TDI/TCLK
X
X
X
0
1
0
Pin Osc
Capacitive sensing
X
0
1
0
0
0
P1.7/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
0
SDI/
SPI mode
from USI
1
0
1
0
0
SDA/
SPI mode
from USI
1
0
1
0
0
A7
X
X
X
0
0
1 (y = 7)
TDO/TDI/
TDO/TDI
X
X
X
0
1
0
Pin Osc
Capacitive sensing
X
0
1
0
0
0
7
A7/
(1)
40
X = don't care
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2302-EP
www.ti.com
SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
PxSEL2.y
PxSEL.y
PxOUT.y
0
1
DVSS
0
DVCC
1
1
0
1
2
0
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
3
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Copyright © 2012, Texas Instruments Incorporated
Interrupt
Edge
Select
Submit Documentation Feedback
41
MSP430G2302-EP
SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
www.ti.com
Table 19. Port P2 (P2.0 to P2.5) Pin Functions
PIN NAME
(P2.x)
P2.0/
Pin Osc
P2.1/
Pin Osc
P2.2/
Pin Osc
P2.3/
Pin Osc
P2.4/
Pin Osc
P2.5/
Pin Osc
(1)
42
x
0
1
2
3
4
5
FUNCTION
P2.x (I/O)
Capacitive sensing
P2.x (I/O)
Capacitive sensing
P2.x (I/O)
Capacitive sensing
P2.x (I/O)
Capacitive sensing
P2.x (I/O)
Capacitive sensing
P2.x (I/O)
Capacitive sensing
CONTROL BITS / SIGNALS (1)
P2DIR.x
P2SEL.x
P2SEL2.x
I: 0; O: 1
0
0
X
0
1
I: 0; O: 1
0
0
X
0
1
I: 0; O: 1
0
0
X
0
1
I: 0; O: 1
0
0
X
0
1
I: 0; O: 1
0
0
X
0
1
I: 0; O: 1
0
0
X
0
1
X = don't care
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
MSP430G2302-EP
www.ti.com
SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
XOUT/P2.7
LF off
PxSEL.6 & PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
1
LFXT1CLK
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
1
1
0
1
From Module
2
XIN/P2.6/TA0.1
3
0
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Table 20. Port P2 (P2.6) Pin Functions
PIN NAME
(P2.x)
CONTROL BITS / SIGNALS (1)
x
XIN/
FUNCTION
XIN
P2.6/
P2.x (I/O)
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
0
1
1
0
0
I: 0; O: 1
0
X
0
0
6
TA0.1/
Timer0_A3.TA1
1
1
0
0
0
Pin Osc
Capacitive sensing
X
0
X
1
X
(1)
X = don't care
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
43
MSP430G2302-EP
SLAS868A – JUNE 2012 – REVISED NOVEMBER 2012
www.ti.com
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
XIN/P2.6/TA0.1
LF off
PxSEL.6 & PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
1
LFXT1CLK
from P2.6
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
1
1
0
1
From Module
2
XOUT/P2.7
3
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Table 21. Port P2 (P2.7) Pin Functions
PIN NAME
(P2.x)
CONTROL BITS / SIGNALS (1)
x
XOUT/
P2.7/
XOUT
7
Pin Osc
(1)
44
FUNCTION
P2.x (I/O)
Capacitive sensing
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
X
1
1
0
0
I: 0; O: 1
X
0
0
0
X
X
0
X
1
X = don't care
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430G2302IPW1EP
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
G2302EP
MSP430G2302IPW1REP
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
G2302EP
V62/12623-01XE
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
G2302EP
V62/12623-01XE-T
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
G2302EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430G2302-EP :
• Catalog: MSP430G2302
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Mar-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
MSP430G2302IPW1REP TSSOP
PW
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Mar-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430G2302IPW1REP
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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