SPANSION MBM29F800BA-70PFTN Flash memory Datasheet

TM
SPANSION Flash Memory
Data Sheet
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20841-6E
FLASH MEMORY
CMOS
8M (1M × 8/512K × 16) BIT
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ GENERAL DESCRIPTION
The MBM29F800TA/BA is a 8M-bit, 5.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words
of 16 bits each. The MBM29F800TA/BA is offered in a 48-pin TSOP(1) and 44-pin SOP packages. This device
is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not required
for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. The
standard MBM29LV800TA/BA offers access times 55 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
(Continued)
■ PRODUCT LINE UP
Part No.
MBM29F800TA/MBM29F800BA
VCC = 5.0 V ± 5 %
-55
—
—
VCC = 5.0 V ± 10 %
—
-70
-90
Max Address Access Time (ns)
55
70
90
Max CE Access Time (ns)
55
70
90
Max OE Access Time (ns)
30
30
40
Ordering Part No.
■ PACKAGES
48-pin, Plastic TSOP(1)
44-pin, Plastic SOP
Marking Side
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(FPT-44P-M16)
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
(Continued)
The MBM29F800TA/BA is pin and command set compatible with JEDEC standard E2PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from12.0 V Flash or EPROM devices.
The MBM29F800TA/BA is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margin.
Any individual sector is typically erased and verified in 1.0 second (if already completely preprogrammed.).
The devices also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29F800TA/BA is erased when shipped from the factory.
The devices features single 5.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F800TA/BA memory electrically erase the entire chip or
all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
2
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ FEATURES
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(1) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minimum 100,000 write/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low Vcc write inhibit ≤ 3.2 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
• Hardware RESET pin
Resets internal state machine to the read mode
• Sector protection
Hardware method disables any combination of sectors from write or erase operations
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin.
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
3
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ PIN ASSIGNMENT
SOP
(Top View)
TSOP(1)
A15
A14
A13
A12
A11
A10
A9
A8
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
MBM29F800TA/MBM29F800BA
Normal Bend
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
FPT-48P-M19
A1
A2
A3
A4
A5
A6
A7
A17
A18
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A8
A9
A10
A11
A12
A13
A14
A15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
MBM29F800TA/MBM29F800BA
Reverse Bend
FPT-48P-M20
4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16
RY/BY
1
44
RESET
A18
2
43
WE
A17
3
42
A8
A7
4
41
A9
A6
5
40
A10
A5
6
39
A11
A4
7
38
A12
A3
8
37
A13
A2
9
36
A14
A1
10
35
A15
A0
11
34
A16
CE
12
33
BYTE
VSS
13
32
VSS
OE
14
31
DQ15/A-1
DQ0
15
30
DQ7
DQ8
16
29
DQ14
DQ1
17
28
DQ6
DQ9
18
27
DQ13
DQ2
19
26
DQ5
DQ10
20
25
DQ12
DQ3
21
24
DQ4
DQ11
22
23
VCC
FPT-44P-M16
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ PIN DESCRIPTION
Pin name
Function
A18 to A0, A-1
Address Inputs
DQ15 to DQ0
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/Temporary Sector Unprotection
BYTE
Selects 8-bit or 16-bit mode
N.C.
No Internal Connection
VSS
Device Ground
VCC
Device Power Supply
5
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ BLOCK DIAGRAM
DQ15 to DQ0
RY/BY
Buffer
RY/BY
VCC
VSS
WE
BYTE
RESET
Input/Output
Buffers
Erase Voltage
Generator
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
OE
STB
Low VCC Detector
Timer for
Program/Erase
Address
Latch
A18 to A0
A-1
■ LOGIC SYMBOL
A-1
19
A18 to A0
16 or 8
DQ15 to DQ0
CE
OE
WE
RESET
BYTE
6
RY/BY
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ DEVICE BUS OPERATION
MBM29F800TA/BA User Bus Operation (BYTE = VIH)
Operation
CE
OE
WE
A0
A1
A6
A9
Auto-Select Manufacturer Code*1
L
L
H
L
L
L
VID
Code
H
Auto-Select Device Code*1
L
L
H
H
L
L
VID
Code
H
Read*3
L
L
H
A0
A1
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
High-Z
H
Write
L
H
L
A0
A1
A6
A9
DIN
H
Enable Sector Protection*2
L
VID
X
X
L
VID
X
H
Verify Sector Protection*2
L
L
H
L
H
L
VID
Code
H
Temporary Sector Unprotection
X
X
X
X
X
X
X
X
VID
Reset (Hardware)/Standby
X
X
X
X
X
X
X
High-Z
L
Legend: L = VIL, H = VIH, X = VIL or VIH,
DQ15 to DQ0 RESET
= Pulse input. See DC Characteristics for voltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence. See
MBM29F800TA/BA Command Definitions” in ■ DEVICE BUS OPERATION.
*2 : Refer to the section on Sector Protection.
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
MBM29F800TA/BA User Bus Operation (BYTE = VIL)
15
WE DQ
/A-1
CE
OE
A0
A1
A6
A9
DQ7 to DQ0
RESET
Auto-Select Manufacturer Code *1
L
L
H
L
L
L
L
VID
Code
H
Auto-Select Device Code *1
L
L
H
L
H
L
L
VID
Code
H
Read *3
L
L
H
A-1
A0
A1
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
X
High-Z
H
Write (Program/Erase)
L
H
L
A-1
A0
A1
A6
A9
DIN
H
Enable Sector Protection *2
L
VID
X
X
H
L
VID
X
H
Verify Sector Protection *2
L
L
H
L
L
H
L
VID
Code
H
Temporary Sector Unprotection
X
X
X
X
X
X
X
X
X
VID
Reset (Hardware)/Standby
X
X
X
X
X
X
X
X
High-Z
L
Operation
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
* 1 : Manufacturer and device codes may also be accessed via a command register write sequence. See
MBM29F800TA/BA Command Definitions” in ■ DEVICE BUS OPERATION.
*2 : Refer to the section on Sector Protection.
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
7
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
MBM29F800TA/BA Command Definitions
Command
Sequence
Read/
Reset*1
Word
Read/
Reset*1
Word
Autoselect
Byte/Word
Program
Chip Erase
Sector Erase
Bus
Write
Cycles
Req'd
Byte
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
1
3
3
4
6
6
Second
Bus Fifth Bus
First Bus
Third Bus Fourth
Sixth Bus
Bus
Read/Write
Write Cycle Write Cycle Write Cycle
Write
Cycle
Write
Cycle
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
XXXh F0h
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
AAh
AAh
AAh
AAh
AAh
—
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
—
55h
55h
55h
55h
55h
—
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
—
—
—
—
—
—
—
F0h
RA*2 RD*2
—
—
—
—
90h
IA*2
ID*2
—
—
—
—
A0h
PA
PD
—
—
—
—
80h
80h
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
55h
555h
AAAh
SA
Sector Erase Suspend
Erase can be suspended during sector erase with Addr (“H” or “L”). Data (B0h)
Sector Erase Resume
Erase can be resumed after suspend with Addr (“H” or “L”). Data (30h)
10h
30h
Notes : • Address bits A11 to A18 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA).
• Bus operations are defined in “MBM29F800TA/BA User Bus Operation (BYTE = VIH)” and
“MBM29F800TA/BA User Bus Operation (BYTE = VIH)” in ■DEVICE BUS OPERATION.
• RA = Address of the memory location to be read.
IA = Autoselect read address.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
• RD = Data read from location RA during read operation.
ID = Device code/manufacture code for the address located by IA.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
• The system should generate the following address patterns:
Word Mode: 555h or 2AAh to addresses A10 to A0
Byte Mode: AAAh or 555h to addresses A10 to A-1
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• Command combinations not described in Command Definitions table are illegal.
*1 : Both of these reset commands are equivalent.
*2 : The fourth bus cycle is only for read.
8
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
MBM29F800TA/BA Sector Protection Verify Autoselect Codes
A-1*1
Code
(HEX)
VIL
04h
X
0004h
VIL
D6h
X
22D6h
VIL
58h
Word
X
2258h
Byte
VIL
01h*2
X
0001h*2
Type
A18 to A12
A6
A1
A0
X
VIL
VIL
VIL
Byte
Manufacture’s Code
Word
Byte
MBM29F800TA
X
VIL
VIL
VIH
Word
Device Code
Byte
MBM29F800BA
X
Sector
Addresses
Word
Sector Protection
VIL
VIL
VIH
VIH
VIL
VIL
*1 : A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address.
*2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
Expanded Autoselect Code Table
Type
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
(B)*
04h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
D6h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
58h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
1
0
1
1
0
0
0
0
1
0
1
1
0
0
0
01h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
Manufacture’s Code
(W) 0004h 0
(B)*
0
0
0
0
0
0
0
MBM29F800TA
(W)
Device
Code
(B)*
22D6h
0
0
1
0
0
0
1
0
MBM29F800BA
(W) 2258h 0
(B)*
0
1
0
0
0
1
0
Sector Protection
(W) 0001h 0
0
0
0
0
0
0
0
0
(B) : Byte mode
(W) : Word mode
HI-Z : High-Z
* : At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A−1, the lowest address.
9
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.
• Individual-sector, multiple-sector, or bulk-erase capability.
• Individual or multiple-sector protection is user definable.
(×8)
(×16)
FFFFFh
7FFFFh
16K byte
(×16)
FFFFFh
7FFFFh
EFFFFh
77FFFh
64K byte
FBFFFh
7DFFFh
8K byte
64K byte
F9FFFh
DFFFFh 6FFFFh
7CFFFh
8K byte
64K byte
F7FFFh
CFFFFh 67FFFh
7BFFFh
32K byte
64K byte
EFFFFh
77FFFh
64K byte
BFFFFh
5FFFFh
AFFFFh
57FFFh
9FFFFh
4FFFFh
8FFFFh
47FFFh
7FFFFh
3FFFFh
6FFFFh
37FFFh
5FFFFh
2FFFFh
4FFFFh
27FFFh
3FFFFh
1FFFFh
2FFFFh
17FFFh
1FFFFh
0FFFFh
0FFFFh
07FFFh
07FFFh
03FFFh
05FFFh
02FFFh
03FFFh
01FFFh
00000h
00000h
64K byte
DFFFFh
6FFFFh
64K byte
64K byte
CFFFFh
67FFFh
64K byte
64K byte
BFFFFh
5FFFFh
64K byte
64K byte
AFFFFh
57FFFh
64K byte
64K byte
9FFFFh
4FFFFh
64K byte
64K byte
8FFFFh
47FFFh
64K byte
64K byte
7FFFFh
3FFFFh
64K byte
64K byte
6FFFFh
37FFFh
64K byte
64K byte
5FFFFh
2FFFFh
64K byte
64K byte
4FFFFh
27FFFh
64K byte
64K byte
3FFFFh
1FFFFh
64K byte
32K byte
2FFFFh
17FFFh
64K byte
8K byte
1FFFFh
0FFFFh
64K byte
8K byte
0FFFFh
07FFFh
64K byte
16K byte
00000h
MBM29F800TA Sector Architecture
10
(×8)
00000h
MBM29F800BA Sector Architecture
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
Sector Address Table (MBM29F800TA)
Sector
Address
A18
A17
A16
A15
A14
A13
A12
Address Range
SA0
0
0
0
0
X
X
X
00000h to 0FFFFh
SA1
0
0
0
1
X
X
X
10000h to 1FFFFh
SA2
0
0
1
0
X
X
X
20000h to 2FFFFh
SA3
0
0
1
1
X
X
X
30000h to 3FFFFh
SA4
0
1
0
0
X
X
X
40000h to 4FFFFh
SA5
0
1
0
1
X
X
X
50000h to 5FFFFh
SA6
0
1
1
0
X
X
X
60000h to 6FFFFh
SA7
0
1
1
1
X
X
X
70000h to 7FFFFh
SA8
1
0
0
0
X
X
X
80000h to 8FFFFh
SA9
1
0
0
1
X
X
X
90000h to 9FFFFh
SA10
1
0
1
0
X
X
X
A0000h to AFFFFh
SA11
1
0
1
1
X
X
X
B0000h to BFFFFh
SA12
1
1
0
0
X
X
X
C0000h to CFFFFh
SA13
1
1
0
1
X
X
X
D0000h to DFFFFh
SA14
1
1
1
0
X
X
X
E0000h to EFFFFh
SA15
1
1
1
1
0
X
X
F0000h to F7FFFh
SA16
1
1
1
1
1
0
0
F8000h to F9FFFh
SA17
1
1
1
1
1
0
1
FA000h to FBFFFh
SA18
1
1
1
1
1
1
X
FC000h to FFFFFh
11
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
Sector Address Table (MBM29F800BA)
12
Sector
Address
A18
A17
A16
A15
A14
A13
A12
Address Range
SA0
0
0
0
0
0
0
X
00000h to 03FFFh
SA1
0
0
0
0
0
1
0
04000h to 05FFFh
SA2
0
0
0
0
0
1
1
06000h to 07FFFh
SA3
0
0
0
0
1
X
X
08000h to 0FFFFh
SA4
0
0
0
1
X
X
X
10000h to 1FFFFh
SA5
0
0
1
0
X
X
X
20000h to 2FFFFh
SA6
0
0
1
1
X
X
X
30000h to 3FFFFh
SA7
0
1
0
0
X
X
X
40000h to 4FFFFh
SA8
0
1
0
1
X
X
X
50000h to 5FFFFh
SA9
0
1
1
0
X
X
X
60000h to 6FFFFh
SA10
0
1
1
1
X
X
X
70000h to 7FFFFh
SA11
1
0
0
0
X
X
X
80000h to 8FFFFh
SA12
1
0
0
1
X
X
X
90000h to 9FFFFh
SA13
1
0
1
0
X
X
X
A0000h to AFFFFh
SA14
1
0
1
1
X
X
X
B0000h to BFFFFh
SA15
1
1
0
0
X
X
X
C0000h to CFFFFh
SA16
1
1
0
1
X
X
X
D0000h to DFFFFh
SA17
1
1
1
0
X
X
X
E0000h to EFFFFh
SA18
1
1
1
1
X
X
X
F0000h to FFFFFh
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29F800TA/BA has two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins (Assuming the
addresses have been stable for at least tACC - tCE time).
Standby Mode
There are two ways to implement the standby mode on the MBM29F800TA/BA devices, one using both the CE
and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved with CE and
RESET pins held at VIH. Under this condition the current is reduced to approximately 1mA. During Embedded
Algorithm operation, VCC Active current (ICC2) is required even CE = VIH. The device can be read with standard
access time (tCE) from either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V
(CE = “H” or “L”). Under this condition the current is consumed is less than 5 µA. A TTL standby mode is achieved
with RESET pin held at VIL, (CE= “H” or “L”). Under this condition the current required is reduced to approximately
1 mA. Once the RESET pin is taken high, the device requires 500 ns of wake up time before outputs are valid
for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are don't cares except A0, A1, A6, and A-1 (See “MBM29F800TA/BA Sector Protection Verify Autoselect
Codes” in ■ DEVICE BUS OPERATION).
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29F800TA/BA is erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in “MBM29F800TA/BA Command Definitions” in ■ DEVICE BUS OPERATION
(refer to “Autoselect Command” in ■ COMMAND DEFINITIONS).
Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and A0 = VIH represents the device identifier
code (MBM29F800TA = D6h and MBM29F800BA = 58h for ×8 mode; MBM29F800TA = 22D6h and
MBM29F800BA = 2258h for ×16 mode). These two bytes/words are given in “MBM29F800TA/BA Sector
Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in ■ DEVICE BUS OPERATION.
All identifiers for manufacturers and device will exhibit odd parity with DQ7 defined as the parity bit. In order to
read the proper device codes when executing the autoselect, A1 must be VIL (See “MBM29F800TA/BA Sector
Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in ■ DEVICE BUS OPERATION).
13
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to “■ AC CHARACTERISTICDS” and “■ TIMING DIAGRAM” for specific timing parameters.
Sector Protection
The MBM29F800TA/BA features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 18). The sector protection feature is enabled using programming
equipment at the user’s site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5V), CE = VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to
the sector to be protected. “Sector Address Tables (MBM29F800TA)” and “Sector Address Tables
(MBM29F800BA)” in ■ FLEXIBLE SECTOR ERASE ARCHITECTURE define the sector address for each of
the nineteen (19) individual sectors. Programming of the protection circuitry begins on the falling edge of the
WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during
the WE pulse. See “Sector Protection Timing Diagram” in ■ TIMING DIAGRAM and “Sector Protection Algorithm”
in ■ FLOW CHART for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while
(A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the
devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6
are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
A-1 requires to apply to VIL on byte mode.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where the higher order addresses (A18, A17, A16, A15, A14, A13,
and A12) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See
“MBM29F800TA/BA Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in
■ DEVICE BUS OPERATION for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29F800TA/BA device in
order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. Refer to “Temporary Sector Unprotection Timing Diagram” in ■ TIMING DIAGRAM and “Temporary Sector
Unprotection Algorithm” in ■ FLOW CHART.
14
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to the
read mode. “MBM29F800TA/BA Command Definitions” in ■ DEVICE BUS OPERATION defines the valid register
command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only
while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally
equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0
and DQ15 to DQ8 bits are ignored.
Read/Reset Command
The read or eset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the
command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition.
Refer to “■ AC CHARACTERISTICS” and “■ TIMING DIAGRAM” for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle from address XX01h for ×16 (XX02h for ×8) returns the device code (MBM29F800TA = D6h and
MBM29F800BA = 58h for ×8 mode; MBM29F800TA = 22D6h and MBM29F800BA = 2258h for ×16 mode). (See
“MBM29F800TA/BA Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in
■ DEVICE BUS OPERATION.)
All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit.
Sector state (protection or unprotection) will be informed by address XX02h for ×16 (XX04h for ×8).
Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a
logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin
mode on the protected sector (See “MBM29F800TA/BA User Bus Operation (BYTE = VIH)” and “MBM29F800TA/
BA User Bus Operation (BYTE = VIH)” in ■ DEVICE BUS OPERATION).
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
Byte/Word Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming. Upon executing the Embedded ProgramTM Algorithm command sequence, the system is not
required to provide further controls or timings. The device will automatically provide adequate internally generated
program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched (See “Hardware
Sequence Flags”, Hardware Sequence Flags) Therefore, the devices require that a valid address to the devices
15
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the
memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“Embedded ProgramTM Algorithm” in ■ FLOW CHART illustrates the Embedded Programming AlgorithmTM using
typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded EraseTM
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (see Write Operation Status section) at which time the device returns to read the
mode.
“Embedded EraseTM Algorithm” in ■ FLOW CHART illustrates the Embedded Erase Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30h) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29F800TA/BA
Command Definitions” in ■ DEVICE BUS OPERATION. This sequence is followed with writes of the Sector
Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must
be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled
after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last WE will initiate
the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 µs timeout window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section
DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period
will reset the devices to the read mode, ignoring the previous command string. Resetting the device once
execution has begun will corrupt the data in that sector. In that case, restart the erase on those sectors and
allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading
the sector erase buffer may be done in any sequence and with any number of sectors (18 to 0).
Sector erase does not require the user to program the devices prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (see Write Operation Status section)
16
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased.
“Embedded EraseTM Algorithm” in ■ FLOW CHART illustrates the Embedded Erase Algorithm using typical
command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are “don’t cares” when writing
the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY
output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the
erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes
of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See “DQ2 Toggle Bit II”).
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended
Program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I (DQ6) which
is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6
can be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
17
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
Write Operation Status
Hardware Sequence Flags
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle
1
1
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7
Toggle*1
0
0
1*2
DQ7
Toggle
1
0
1
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
Status
Embedded Program Algorithm
Embedded Erase Algorithm
In
Progress
Erase Suspend Read
(Erase Suspended Sector)
Erase
Suspended
Mode
Embedded Program Algorithm
Exceeded
Time
Limits
Embedded Erase Algorithm
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
*1 : Performing successive read operations from any address will cause DQ6 to toggle.
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
Notes : • DQ0 and DQ1 are reserve pins for future use. DQ4 is Fujitsu internal use only.
• DQ15 to DQ8 are “DON’T CARES” because there is for × 16 mode.
DQ7
Data Polling
The MBM29F800TA/BA device feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device
will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in “Data Polling Algorithm” in ■ FLOW CHART.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29F800TA/BA data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation
and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out (See “Hardware Sequence Flags”).
See “Data Polling during Embedded Algorithm Operations” in ■ TIMING DIAGRAM for the Data Polling timing
specifications and diagrams.
18
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
DQ6
Toggle Bit I
The MBM29F800TA/BA also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit l will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See “Toggle Bit I during Embedded Algorithm Operations” in ■ TIMING DIAGRAM for the Toggle Bit I timing
specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in “MBM29F800TA/BA User Bus
Operation (BYTE = VIH)” and “MBM29F800TA/BA User Bus Operation (BYTE = VIH)” in ■ DEVICE BUS
OPERATION.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly
used. If this occurs, rest the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the
second status check, the command may not have been accepted.
Refer to “Hardware Sequence Flags” : Hardware Sequence Flags.
19
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address
of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
DQ7
DQ6
DQ2
DQ7
toggles
1
Erase
0
toggles
toggles
Erase Suspend Read
(Erase-Suspended Sector)*1
1
1
toggles
DQ7 *2
toggles
1 *2
Mode
Program
Erase Suspend Program
*1 : These status flags apply when outputs are read from a sector that has been erase-suspended.
*2 : These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode (DQ2 toggles while
DQ6 does not). See also “Hardware Sequence Flags” in ■ COMMAND DEFINITIONSand “Toggle Bit Algorithm”
in ■ FLOW CHART.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy
The MBM29F800TA/BA provides a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands. If
the MBM29F800TA/BA is placed in an Erase Suspend mode, the RY/BY output will be high. Also, since this is
an open drain output, many RY/BY pins can be tied together in parallel with a pull up resistor to VCC.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operations”
and “RESET/RY/BY Timing Diagram” in ■ TIMING DIAGRAM for a detailed timing diagram.
Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices may
be connected to the host system via more than one RY/BY pin in parallel.
RESET
Hardware Reset
The MBM29F800TA/BA device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
20
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
device requires time of tRH before it will allow read access. When the RESET pin is low, the device will be in the
standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset
occurs during a program or erase operation, the data at that particular location will be corrupted. Please note
that the RY/BY output signal should be ignored during the RESET pulse. Refer to “RESET/RY/BY Timing
Diagram” in ■ TIMING DIAGRAM for the timing diagram. Refer to “Temporary Sector Unprotection” in
■ FUNCTIONAL DESCRIPTION for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F800TA/BA device. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ15 to
DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ7 to DQ0 and the DQ15 to DQ8 bits are ignored. Refer
to “Timing Diagram for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE
Timing Diagram for Write Operations” in ■ TIMING DIAGRAM for the timing diagram.
Data Protection
The MBM29F800TA/BA are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and
power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 3.2 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sector Protection
Device user is able to protect each sector individually to store and protect data.
Protection circuit voids both write and erase commands that are addressed to protected sectors.
Any commands to write or erase addressed to protected sector are ignore. Refer to “Sector Protection” in
■ FUNCTIONAL DESCRIPTION.
21
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Storage Temperature
Max
Tstg
−55
+125
°C
TA
−40
+85
°C
VIN, VOUT
–2.0
+7.0
V
VIN
−2.0
+13.5
V
VCC
–2.0
+7.0
V
A9, OE, and RESET *2
1, 3
Power Supply Voltage * *
Unit
Min
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins except A9,
OE, RESET *1,*2
Rating
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on A9, OE, and RESET pins is –0.5 V. During voltage transitions, A9, OE, and RESET
pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply
voltage. (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE, and RESET pins is +13.5 V
which may overshoot to +14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Part No.
Ambient Temperatuer
TA

Power Supply Voltage*
VCC
Value
Unit
Min
Max
−40
+85
°C
MBM29F800TA/BA-55
+4.75
+5.25
V
MBM29F800TA/BA-70/-90
+4.50
+5.50
V
* : Voltage is defined on the basis of VSS = GND = 0 V.
Note : Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
22
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
+0.8 V
20 ns
20 ns
–0.5 V
–2.0 V
20 ns
Maximum Undershoot Waveform
20 ns
VCC+2.0 V
VCC+0.5 V
+2.0 V
20 ns
20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V
+13.5 V
VCC+0.5 V
20 ns
20 ns
Note: This waveform is applied for A9, OE, and RESET.
Maximum Overshoot Waveform 2
23
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ DC CHARACTERISTICS
Value
Parameter
Symbol
Conditions
Unit
Min
Max
Input Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
–1.0
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC Max
–1.0
+1.0
µA
A9, OE, RESET Inputs Leakage
Current
ILIT
VCC = VCC Max,
A9, OE, RESET = 12.5 V
—
50
µA
VCC Active Current *1
ICC1
CE = VIL, OE = VIH
Byte
38
—
Word
VCC Active Current *2
VCC Current (Standby)
VCC Current (Standby, Reset)
ICC2
ICC3
mA
45
CE = VIL, OE = VIH
—
50
mA
VCC = VCC Max, CE = VIH,
RESET = VIH
—
1
mA
VCC = VCC Max, CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V
—
5
µA
VCC = VCC Max,
RESET = VIL
—
1
mA
VCC = VCC Max,
RESET = VSS ± 0.3 V
—
5
µA
ICC4
Input Low Level
VIL
—
–0.5
0.8
V
Input High Level
VIH
—
2.0
VCC + 0.5
V
Voltage for Autoselect and
Sector Protection
(A9, OE, RESET) *3, *4
VID
—
11.5
12.5
V
Output Low Voltage Level
VOL
IOL = 5.8 mA, VCC = VCC Min
—
0.45
V
VOH1
IOH = –2.5 mA, VCC = VCC Min
2.4
—
V
VOH2
IOH = –100 µA
VCC – 0.4
—
V
3.2
4.2
V
Output High Voltage Level
Low VCC Lock-Out Voltage
VLKO
—
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component (at
6 MHz). The frequency component typically is 2 mA/MHz, with OE at VIH.
*2 : ICC active while Embedded Algorithm (program or erase) is in progress.
*3 : Applicable to sector protection function.
*4 : (VID – VCC) do not exceed 9 V.
24
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Value
Symbol
Parameter
Test
Setup
JEDEC Standard
-55*
1
-70*2
Unit
-90*2
Min
Max
Min
Max
Min
Max
55

70

90

ns
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
CE = VIL
OE = VIL

55

70

90
ns
Chip Enable to Output Delay
tELQV
tCE
OE = VIL

55

70

90
ns
Output Enable to Output Delay
tGLQV
tOE
—

30

30

40
ns
Chip Enable to Output High-Z
tEHQZ
tDF
—

15

20

20
ns
Output Enable to Output High-Z
tGHQZ
tDF
—

15

20

20
ns
Output Hold Time From
Addresses, CE or OE,
Whichever Occurs First
tAXQX
tOH
—
0

0

0

ns
RESET Pin Low to Read Mode
—
tREADY
—

20

20

20
µs
CE to BYTE Switching Low or
High
—
tELFL
tELFH
—

5

5

5
ns
—
*1 : Test Conditions:
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
*2 : Test Conditions:
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V or 2.4 V
Timing measurement reference level
Input: 0.8 V and 2.0 V
Output: 0.8 V and 2.0 V
5.0 V
Diode = 1N3064
or Equivalent
Device
Under
Test
2.7 kΩ
6.2 kΩ
CL
Diode = 1N3064
or Equivalent
Notes : • CL = 30 pF including jig capacitance (MBM29F800TA/BA-55)
• CL = 100 pF including jig capacitance (MBM29F800TA/BA-70/-90)
Test Conditions
25
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
• Write/Erase/Program Operations
Value
Symbol
Parameter
-55
-70
-90
Unit
JEDEC Standard Min Typ Max Min Typ Max Min Typ Max
Write Cycle Time
tAVAV
tWC
55


70


90


ns
Address Setup Time
tAVWL
tAS
0


0


0


ns
Address Hold Time
tWLAX
tAH
40


45


45


ns
Data Setup Time
tDVWH
tDS
25


30


45


ns
Data Hold Time
tWHDX
tDH
0


0


0


ns
—
tOES
0


0


0


ns
0


0


0


ns
10


10


10


ns
Output Enable Setup Time
Output Enable
Hold Time
Read
—
tOEH
Read Recover Time Before Write
tGHWL
tGHWL
0


0


0


ns
Read Recover Time Before Write
tGHEL
tGHEL
0


0


0


ns
CE Setup Time
tELWL
tCS
0


0


0


ns
WE Setup Time
tWLEL
tWS
0


0


0


ns
CE Hold Time
tWHEH
tCH
0


0


0


ns
WE Hold Time
tEHWH
tWH
0


0


0


ns
Write Pulse Width
tWLWH
tWP
30


35


45


ns
CE Pulse Width
tELEH
tCP
30


35


45


ns
Write Pulse Width High
tWHWL
tWPH
20


20


20


ns
CE Pulse Width High
tEHEL
tCPH
20


20


20


ns
tWHWH1
tWHWH1

8


8


8

µs

16


16


16

µs
tWHWH2
tWHWH2

1


1


1

s


8


8


8
s
VCC Setup Time
—
tVCS
50


50


50


µs
RiseTime to VID
—
tVIDR
500


500


500


ns
Voltage Transition Time *2
—
tVLHT
4


4


4


µs
Programming
Operation
Toggle and Data
Polling
Byte
Word
Sector Erase Operation *1
—
tWPP
100


100


100


µs
2
OE Setup Time to WE Active *
—
tOESP
4


4


4


µs
CE Setup Time to WE Active *2
—
tCSP
4


4


4


µs
Recover Time from RY/BY
—
tRB
0


0


0


ns
Write Pulse Width *2
(Continued)
26
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
(Continued)
Parameter
Value
Symbols
-55
-70
-90
Unit
JEDEC Standard Min Typ Max Min Typ Max Min Typ Max
RESET Pulse Width
—
tRP
500


500


500


ns
RESET Hold Time Before Read
—
tRH
50


50


50


ns
BYTE Switching Low to Output
High-Z
—
tFLQZ


30


30


40
ns
BYTE Switching High to Output
Active
—
tFHQV


55


70


90
ns
Program/Erase Valid to RY/BY
Delay
—
tBUSY


55


70


90
ns
Delay Time from Embedded
Output Enable
—
tEOE


55


70


90
ns
*1 : This does not include the preprogramming time.
*2 : These timing is for Sector Protection operation.
27
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
8
s
Excludes 00h programming
prior to erasure
16
200
µs
—
8
150
µs
—
8.4
20
s
100,000
—
—
cycle
Min
Typ
Max
Sector Erase Time
—
1
Word Programming Time
—
Byte Programming Time
Chip Programming Time
Erase/Program Cycle
Excludes system-level
overhead
Excludes system-level
overhead
■ TSOP PIN CAPACITANCE
Parameter
Symbol
Test Setup
Value
Typ
Max
Unit
Input Capacitance
CIN
VIN = 0
8
10
pF
Output Capacitance
COUT
VOUT = 0
8
10
pF
Control Pin Capacitance
CIN2
VIN = 0
8.5
12.5
pF
Notes : • Test conditions TA = +25°C, f = 1.0 MHz
• DQ15 /A-1 pin capacitance is stipulated by output capacitance.
■ SOP PIN CAPACITANCE
Parameter
Symbol
Test Setup
Typ
Max
Unit
Input Capacitance
CIN
VIN = 0
8
10.5
pF
Output Capacitance
COUT
VOUT = 0
8
10
pF
Control Pin Capacitance
CIN2
VIN = 0
8.5
12.5
pF
Notes : • Test conditions TA = +25°C, f = 1.0 MHz
• DQ15 /A-1 pin capacitance is stipulated by output capacitance.
28
Value
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
tRC
Addresses Stable
Address
tACC
CE
tDF
tOE
OE
tOEH
WE
tCE
Outputs
High-Z
tOH
Output Valid
High-Z
AC Waveforms for Read Operations
29
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
3rd Bus Cycle
Address
Data Polling
555h
PA
PA
tAH
tWC
tRC
tAS
CE
tCH
tGHWL
OE
tWP
tWHWH1
WE
tWPH
tCS
tDF
tDH
A0h
Data
tOE
PD
DQ7
DOUT
DOUT
tDS
tOH
5.0 V
tCE
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the × 16 mode.
AC Waveforms for Alternate WE Controlled Program Operations
30
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
3rd Bus Cycle
Address
Data Polling
555h
PA
PA
tAH
tWC
tAS
tWH
WE
tGHEL
OE
tWHWH1
tCP
CE
tCPH
tWS
tDH
Data
A0h
PD
DQ7
DOUT
tDS
5.0 V
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)
AC Waveforms for Alternate CE Controlled Program Operations
31
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
tAH
Address
555h
2AAh
555h
555h
2AAh
SA
tAS
CE
tCH
tGHWL
OE
tWP
WE
tCS
tWPH
10h for Chip Erase
tDH
Data
tDS
AAh
55h
80h
AAh
55h
10h/30h
VCC
tVCS
Notes : • SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
• These waveforms are for the × 16 mode. The addresses differ from × 8 mode.
AC Waveforms for Chip/Sector Erase Operations
32
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
tCH
CE
tDF
tOE
OE
tOEH
WE
tCE
*
DQ7
Data
High-Z
DQ7 =
Valid Data
DQ7
tWHWH1 or 2
DQ6 to DQ0
Data
DQ6 to DQ0 = Output Flag
High-Z
DQ6 to DQ0
Valid Data
*: DQ7 = Valid Data (The device has completed the Embedded operation).
AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
DQ6
Data
DQ6 = Toggle
DQ6 =
Stop Toggling
DQ6 = Toggle
DQ7 to DQ0
Valid
tOE
*: DQ6 stops toggling (The device has completed the Embedded operation).
AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
33
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
CE
Rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
RY/BY Timing Diagram during Program/Erase Operations
WE
RESET
tRP
tRB
RY/BY
tREADY
RESET/RY/BY Timing Diagram
34
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
CE
BYTE
Data Output
(DQ7 to DQ0)
DQ14 to DQ0
tELFH
DQ15/A-1
Data Output
(DQ14 to DQ0)
tFHQV
DQ15
A-1
Timing Diagram for Word Mode Configuration
CE
BYTE
tELFL
DQ14 to DQ0
DQ15/A-1
Data Output
(DQ14 to DQ0)
Data Output
(DQ7 to DQ0)
DQ15
A-1
tFLQZ
Timing Diagram for Byte Mode Configuration
Falling edge of the last write signal
CE or WE
BYTE
tSET
(tAS)
tHOLD (tAH)
BYTE Timing Diagram for Write Operations
35
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
A18, A17, A16
A15, A14
A13, A12
SAX
SAY
A0
A1
A6
VID
5V
A9
tVLHT
VID
5V
OE
tOESP
tVLHT
tWPP
tVLHT
tVLHT
WE
tCSP
CE
01h
Data
tVLHT
tOE
VCC
SAX = Sector Address for initial sector
SAY = Sector Address for next sector
Note : A-1 is VIL on byte mode.
AC Waveforms for Sector Protection Timing Diagram
36
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
VCC
tVIDR
tVCS
tVLHT
VID
3V
3V
RESET
CE
WE
tVLHT
Program or Erase Command Sequence
tVLHT
RY/BY
Unprotection period
Temporary Sector Unprotection Timing Diagram
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2*
Toggle
DQ2 and DQ6
with OE or CE
* : DQ2 is read from the erase-suspended sector.
DQ2 vs. DQ6
37
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ FLOW CHART
EMBEDDED ALGORITHMS
Start
Write Program Command
Sequence
(See Below)
Data Polling Device
Increment Address
No
Last Address
?
Yes
Programming Completed
Program Command Sequence* (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Embedded ProgramTM Algorithm
38
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
EMBEDDED ALGORITHMS
Start
Write Erase Command
Sequece
(See Below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence*
(Address/Command):
Individual Sector/Multiple Sector*
Erase Command Sequence
(Address/Command):
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
Sector Address/30h
555h/10h
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Sector Address/30h
Additional sector
erase commands
are optional.
Sector Address/30h
Embedded EraseTM Algorithm
39
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
VA = Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase operation
= Any of the sector addresses
within the sector not being
protected during chip erase
operation
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read Byte
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
Yes
No
Fail
Pass
Note : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Data Polling Algorithm
40
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
Start
Read DQ7 to DQ0
Addr. = "H" or "L"
*1
Read DQ7 to DQ0
Addr. = "H" or "L"
No
DQ6
= Toggle?
Yes
No
DQ5 = 1?
Yes
*1, *2
Read DQ7 to DQ0
Addr. = "H" or "L"
*1, *2
Read DQ7 to DQ0
Addr. = "H" or "L"
DQ6
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete.Write
Reset Command
Program/Erase
Operation
Complete
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.
Toggle Bit Algorithm
41
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
Start
Setup Sector Addr.
(A18, A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID,
A6 = CE = VIL, RESET = VIH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector
(Addr. = SA, A1 = 1, A0 = V6 = 0)*
No
No
PLSCNT = 25?
Yes
Remove VID from A9
Write Reset Command
Data = 01h?
Yes
Yes
Protect Another Sector?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Protection
Completed
* : A-1 is VIL on byte mode.
Sector Protection Algorithm
42
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
Start
RESET = VID *1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
*2
*1 : All protected sectors unprotected.
*2 : All previously protected sectors are protected once again.
Temporary Sector Unprotection Algorithm
43
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29F800
T
A
-55
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP (1) ) Normal Bend
PFTR = 48-Pin Thin Small Outline Package
(TSOP (1) ) Reverse Bend
PF =
44-Pin Small Outline Package
SPEED OPTION
See Product Selector Guide
A = Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29F800
8Mega-bit (1M × 8-Bit or 512K × 16-Bit) CMOS Flash Memory
5.0 V-only Read, Write, and Erase
44
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
■ PACKAGE DIMENSIONS
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15(.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin plastic TSOP(1)
(FPT-48P-M19)
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
24
25
* 12.00±0.20
20.00±0.20
(.787±.008)
* 18.40±0.20
(.724±.008)
"A"
0.10(.004)
(.472±.008)
+0.10
1.10 –0.05
+.004
.043 –.002
(Mounting
height)
+0.03
0.17 –0.08
+.001
.007 –.003
C
0.10±0.05
(.004±.002)
(Stand off height)
0.50(.020)
0.22±0.05
(.009±.002)
0.10(.004)
M
2003 FUJITSU LIMITED F48029S-c-6-7
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
45
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15(.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin plastic TSOP(1)
(FPT-48P-M20)
LEAD No.
1
48
Details of "A" part
INDEX
0.60±0.15
(.024±.006)
0~8˚
0.25(.010)
24
25
+0.03
0.17 –0.08
+.001
0.10(.004)
.007 –.003
0.50(.020)
0.22±0.05
(.009±.002)
M
0.10±0.05
(.004±.002)
(Stand off height)
+0.10
"A"
1.10 –0.05
+.004
* 18.40±0.20
(.724±.008)
20.00±0.20
(.787±.008)
C
0.10(.004)
.043 –.002
(Mounting height)
* 12.00±0.20(.472±.008)
2003 FUJITSU LIMITED F48030S-c-6-7
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
46
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
(Continued)
Note 1)
Note 2)
Note 3)
Note 4)
44-pin plastic SOP
(FPT-44P-M16)
+0.25
*1 : These dimensions include resin protrusion.
*2 : These dimensions do not include resin protrusion.
Pins width and pins thickness include plating thickness.
Pins width do not include tie bar cutting remainder.
+.010
+0.03
*1 28.45 –0.20 1.120 –.008
0.17 –0.04
+.001
.007 –.002
44
23
16.00±0.20
(.630±.008)
Details of "A" part
*2 13.00±0.10
(.512±.004)
2.35±0.15
(Mounting height)
(.093±.006)
INDEX
0.25(.010)
1
1.27(.050)
22
0.42
.017
+0.08
–0.07
+.0031
–.0028
0.13(.005)
"A"
0~8˚
M
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
+0.10
0.20 –0.15
+.004
.008 –.006
(Stand off)
0.10(.004)
C
2002 FUJITSU LIMITED F44023S-c-6-6
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
47
MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0404
 FUJITSU LIMITED Printed in Japan
Similar pages