Revised April 2002 CD4069UBC Inverter Circuits General Description Features The CD4069UB consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating range, low power consumption, high noise immunity, and symmetric controlled rise and fall times. ■ Wide supply voltage range: This device is intended for all general purpose inverter applications where the special characteristics of the MM74C901, MM74C907, and CD4049A Hex Inverter/Buffers are not required. In those applications requiring larger noise immunity the MM74C14 or MM74C914 Hex Schmitt Trigger is suggested. 3.0V to 15V ■ High noise immunity: 0.45 VDD typ. ■ Low power TTL compatibility: or 1 driving 74LS Fan out of 2 driving 74L ■ Equivalent to MM74C04 All inputs are protected from damage due to static discharge by diode clamps to VDD and VSS. Ordering Code: Order Number Package Number Package Description CD4069UBCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4069UBCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4069UBCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code. Connection Diagram © 2002 Fairchild Semiconductor Corporation Schematic Diagram DS005975 www.fairchildsemi.com CD4069UBC Inverter Circuits October 1987 CD4069UBC Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) (Note 2) −0.5V to +18 VDC DC Supply Voltage (VDD) DC Supply Voltage (VDD) −0.5V to VDD +0.5 VDC Input Voltage (VIN) −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW −55°C to +125°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and Electrical Characteristics table provide conditions for actual device operation. Lead Temperature (TL) Note 2: VSS = 0V unless otherwise specified. 260°C (Soldering, 10 seconds) 0V to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3V to 15VDC Input Voltage (VIN) DC Electrical Characteristics (Note 3) Symbol IDD Parameter Quiescent Device Current −55°C Conditions Min VDD = 5V, Max +25°C Min Typ +125°C Max Min Max 0.25 0.25 7.5 0.5 0.5 15 1.0 1.0 30 Units VIN = VDD or VSS VDD = 10V, VIN = VDD or VSS VDD = 15V, µA VIN = VDD or VSS VOL VOH VIL VIH IOL IOH IIN LOW Level Output Voltage HIGH Level Output Voltage LOW Level Input Voltage HIGH Level Input Voltage |IO| < 1 µA VDD = 5V 0.05 0 0.05 0.05 VDD = 10V 0.05 0 0.05 0.05 VDD = 15V 0.05 0 0.05 0.05 |IO| < 1 µA VDD = 5V 4.95 4.95 5 VDD = 10V 9.95 9.95 10 9.95 VDD = 15V 14.95 14.95 15 14.95 4.95 VDD = 5V, VO = 4.5V 1.0 1.0 1.0 VDD = 10V, VO = 9V 2.0 2.0 2.0 VDD = 15V, VO = 13.5V 3.0 3.0 3.0 V |IO| < 1 µA 4.0 4.0 4.0 VDD = 10V, VO = 1V 8.0 8.0 8.0 VDD = 15V, VO = 1.5V 12.0 12.0 12.0 LOW Level Output Current VDD = 5V, VO = 0.4V 0.64 0.51 0.88 (Note 4) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output Current VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 (Note 4) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4 V 0.36 mA mA VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0 VDD = 15V, VIN = 15V 0.1 10−5 0.1 1.0 Note 3: VSS = 0V unless otherwise specified. Note 4: IOH and IOL are tested one output at a time. www.fairchildsemi.com V |IO| < 1 µA VDD = 5V, VO = 0.5V Input Current V 2 µA (Note 5) TA = 25°C, CL = 50 pF, RL = 200 kΩ, tr and tf ≤ 20 ns, unless otherwise specified Symbol tPHL or tPLH tTHL or tTLH Typ Max Propagation Delay Time from Parameter VDD = 5V 50 90 Input to Output VDD = 10V 30 60 VDD = 15V 25 50 Transition Time Conditions Min VDD = 5V 80 150 VDD = 10V 50 100 VDD = 15V 40 80 15 CIN Average Input Capacitance Any Gate 6 CPD Power Dissipation Capacitance Any Gate (Note 6) 12 Units ns ns pF pF Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note— AN-90. AC Test Circuits and Switching Time Waveforms 3 www.fairchildsemi.com CD4069UBC AC Electrical Characteristics CD4069UBC Typical Performance Characteristics Gate Transfer Characteristics Propagation Delay vs. Ambient Temperature Power Dissipation vs. Frequency Propagation Delay vs. Ambient Temperature Propagation Delay Time vs. Load Capacitance www.fairchildsemi.com 4 CD4069UBC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com CD4069UBC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 CD4069UBC Inverter Circuits Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com