Ordering number : ENA0692 LV5609LP Bi-CMOS LSI Vertical Clock Driver for CCD http://onsemi.com Overview The LV5609LP is vertical clock driver for CCD. Functions • Ternary output ×2ch • Binary output ×2ch • SHT output ×1ch • Output ON resistance : 30Ω typ Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = VM = 0V Parameter Symbol Maximum supply voltage Allowable power dissipation Conditions Ratings Unit VDD max 6 V VH max 20 V VL max -10 V VH-VL max 24 V 0.8 W Pd max with specified substrate * Operating temperature Topr -20 to +80 °C Storage temperature Tstg -40 to +125 °C * : Specified substrate : 40×50×0.8mm3, glass epoxy four-layer (2S2P) board Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ratings at Ta = 25°C, VSS = VM = 0V Parameter Symbol Ratings Conditions min Supply voltage VDD typ 2.0 VH VL -8.5 VH-VL Unit max 3.3 5.5 15 17 V V -7.5 -4 V 23.5 V CMOS input High voltage VINH 0.8VDD VDD V CMOS input Low voltage VINL -0.1 0.4 V Semiconductor Components Industries, LLC, 2013 August, 2013 32207 MS PC 20060719-S00002 No.A0692-1/8 LV5609LP Electrical Characteristics at Ta = 25°C, VDD = 3.3V, VSS = 0V, VH = 15V, VL = -7.5V, VM = 0V, Unless otherwise specified Parameter Symbol Ratings Conditions min Static current drain Unit max 1 μA IH VH pin 10 μA IL VL pin 1 μA VDD pin See *1 and *2. 1 mA IDD Dynamic current drain typ IDD VDD pin IH VH pin See *1 and *2. 2.4 4.5 mA IL VL pin See *1 and *2. 3 5 mA RL IO = +10mA 20 30 Ω RM IO = ±10mA 30 45 Ω RH IO = -10mA 30 40 Ω RSHT IO = -10mA 30 40 Ω TPLM No load 200 ns TPMH No load 200 ns Output ON resistance Propagation delay time TPLH No load 200 ns TPML No load 200 ns TPHM No load 200 ns TPHL No load 200 ns TTLM VL → VM V1, V3 See *1. 800 ns VL → VM V2, V4 See *1. 800 ns TTMH VM → VL V1, V3 See *1. 800 ns TTLH VL → VH SHT See *1. 200 ns TTML VM → VL V1, V3 See *1. 800 ns VM → VL V2, V4 See *1. 800 ns TTHM VH → VM V1, V3 See *1. 800 ns TTHL VH → VL SHT See *1. 200 ns Rise time Fall time *1 : Refer to the CCD equivalent load shown below. *2 : Refer to the timing waveform on Page 7. 2000pF 2000pF 1000pF V1 (Ternary) V4 (Ternary) 3000pF SHT 3000pF 1600pF 1000pF V2 (Binary) V3 (Binary) 2000pF 2000pF No.A0692-2/8 LV5609LP Package Dimensions unit : mm (typ) 3322 SIDE VIEW TOP VIEW BOTTOM VIEW 13 18 12 19 3.5 (C0.116) (0.13) (0.125) 3.5 0.4 7 24 6 1 0.5 (0.5) 0.25 (0.035) 0.83 SIDE VIEW Allowable power dissipation, Pd max – W 1.0 Pd max – Ta Specified circuit board : 40×50×0.8mm3, glass epoxy four-layer (2S2P) board With specified substrate 0.8 0.6 0.4 0.2 0.15 0.36 Independent IC 0.07 0 – 20 SANYO : VCT24(3.5X3.5)X01 0 20 40 60 80 100 Ambient temperature, Ta – °C No.A0692-3/8 LV5609LP NC NC NC VSS VDD NC Pin Assignment 24 23 22 21 20 19 17 XV4 V4 3 16 XSG3 V3 4 15 XV3 V2 5 14 XV2 V1 6 13 XSG1 8 9 10 11 12 XV1 7 NC 2 NC SHT VH 18 XSHT NC 1 VM VL Top view Pin Function Pin No. Name Mode 1 VL 2 SHT Level shift output (binary VH, VL) 3 V4 Level shift output (binary VM, VL) 4 V3 Level shift output (ternary VH, VM, VL) 5 V2 Level shift output (binary VM, VL) 6 V1 Level shift output (ternary VH, VM, VL) 7 VM GND for output 8 NC 9 VH 10 NC 11 NC 12 XV1 13 XSG1 14 XV2 15 XV3 16 XSG3 Lo power for output (-7.5V system) Hi power supply for output (15V system) V1 transfer pulse input V1 read pulse input V2 transfer pulse input V3 transfer pulse input V3 read pulse input 17 XV4 18 XSHT V4 transfer pulse input 19 NC 20 VDD Power supply for input buffer (3.3V system) 21 VSS GND for input buffer 22 NC 23 NC 24 NC SHT pulse input No.A0692-4/8 LV5609LP Block Diagram VDD Level Shift & Output Buffer 20 Input Buffer 0.1μF 9 VH 1μF XV1 12 30 6 V1 30 5 V2 XSG1 13 XV2 14 7 VM XV3 15 30 4 V3 XV4 17 30 3 V4 XSHT 18 30 2 SHT XSG3 16 VSS 21 1 VL 1μF Logical Function Table Input Output XV1 XSG1 XV2 XV3 XSG3 XV4 L L X V1 V2 V3 V4 X VH X XSHT SHT X L H X X VM X X H L X X VL X X H H X X VL X X X X L X X VM X X X H X X VL X X X X L X X VH X X X H X X VL No.A0692-5/8 LV5609LP Timing Chart VDD 50% XV1 to XV4 XSG1 XSG3 50% VSS VDD TTHM VSS TPMH TTMH VH V1 V3 TPHM 50% TTLM TTML 90% TPLM TPML VM 90% 10% 10% VL TTLM TPLM V2 V4 TTML TPML VM 90% 10% VL VDD XSHT 50% 50% VSS TTLH TTHL TPLH VH SHT VL TPHL 90% 10% No.A0692-6/8 LV5609LP CCD Equivalent Load Measurement Timing Waveform 63.5μs 127μs 2μs XV1 XV2 XV3 XV4 XSG1 2.5μs XSG3 63.5μs 2.5μs 2μs 16.7ms XSHT Enlarged View of overlapped portion XV1 XV2 XV3 XV4 0μs 0.7μs 1.4μs 2.1μs 2.8μs 3.5μs 4.2μs 4.9μs No.A0692-7/8 LV5609LP ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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