CALMIRCO CM1216 6- and 8-channel low capacitance esd array Datasheet

PRELIMINARY
CM1216
6- and 8-Channel Low Capacitance ESD Arrays
Features
Product Description
•
•
The CM1216 family of diode arrays has been designed
to provide ESD protection for electronic components or
sub-systems requiring minimal capacitive loading.
These devices are ideal for protecting systems with
high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a
pair of diodes in series which steer the positive or negative ESD current pulse to either the positive (VP) or
negative (VN) supply rail. The CM1216 will protect
against ESD pulses up to +15kV per the IEC 61000-4-2
standard.
•
•
•
•
•
•
•
6 and 8 channels of ESD protection
Provides +15 kV ESD protection on each channel
per the IEC 61000-4-2 ESD requirements
Channel loading capacitance of 1.6 pF typical
Channel I/O to GND capacitance difference of
0.04pF typical
Mutual capacitance of 0.13pF typical
Minimal capacitance change with temperature and
voltage
Each I/O pin can withstand over 1000 ESD strikes
SOIC and MSOP packages
Lead-free versions available
Applications
•
•
•
•
•
IEEE1394 Firewire® ports at 400Mbps / 800Mbps
DVI ports, HDMI ports in notebooks, set top boxes,
digital TVs, LCD displays
Serial ATA ports in desktop PCs and hard disk
drives
PCI Express ports
General purpose high-speed data line ESD protection
This device is particularly well-suited for protecting systems using high-speed ports such as USB2.0,
IEEE1394 (Firewire®, iLink™), Serial ATA, DVI, HDMI
and corresponding ports in removable storage, digital
camcorders, DVD-RW drives and other applications
where extremely low loading capacitance with ESD
protection are required in a small package footprint.
The CM1216 family of devices is available with
optional lead-free finishing.
Simplified Electrical Schematic
VP
CH6
CH1
CH2
CH5
VN
CH4
CH8
CH7
CH3
CH1
CH2
CH6 CH5
VP
CH3
CH4
VN
CM1216-08MS/MR
CM1216-06MS/MR
CM1216-06SN/SM
© 2005 California Micro Devices Corp. All rights reserved.
06/30/05
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
1
PRELIMINARY
CM1216
PACKAGE / PINOUT DIAGRAM
Top View
Top View
2
VN
3
CH3
4
CH6
CH1
1
7
VP
CH2
2
6
CH5
VN
3
5
CH3
CH4
8-pin SOIC-8
4
CH1
1
10
CH8
8
CH6
CH2
2
9
CH7
7
VP
CH3
3
8
VP
6
CH5
CH4
4
CH4
VN
5
5
D168 /
E168
CH2
8
D166 /
E166
1
D166 /
E166
CH1
Top View
7
CH6
6
CH5
10-pin MSOP-10
8-pin MSOP-8
Note: This drawing is not to scale.
Pin Configuration
PIN DESCRIPTIONS
MSOP-8
SOIC-8
MSOP-10
PIN NO.
PIN NO.
PIN NO.
CH1
1
1
CH2
2
CH3
PIN
NAME
TYPE
DESCRIPTION
1
I/O
ESD Channel
2
2
I/O
ESD Channel
4
4
3
I/O
ESD Channel
CH4
5
5
4
I/O
ESD Channel
VN
3
3
5
GND
Negative voltage supply rail
CH5
6
6
6
I/O
ESD Channel
CH6
8
8
7
I/O
ESD Channel
VP
7
7
8
PWR
Positive voltage supply rail
CH7
−
−
9
I/O
ESD Channel
CH8
−
−
10
I/O
ESD Channel
Ordering Information
PART NUMBERING INFORMATION
Standard Finish
Lead-free Finish
Pins
Package
Ordering Part
Number1
Part Marking
Ordering Part
Number1
8
SOIC
CM1216-06SN
D166
CM1216-06SM
E166
8
MSOP
CM1216-06MS
D166
CM1216-06MR
E166
10
MSOP
CM1216-08MS
D168
CM1216-08MR
E168
Part Marking
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2005 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
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www.calmicro.com
06/30/05
PRELIMINARY
CM1216
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating Supply Voltage (VP-VN)
Diode Forward DC Current (Note 1)
DC Voltage at any Channel Input
Operating Temperature Range
Ambient
Junction
Storage Temperature Range
RATING
6
20
(VN-0.5) to (VP+0.5)
UNITS
V
mA
V
-40 to +85
-40 to +125
-40 to +150
°C
°C
°C
Standard Operating Condition
STANDARD OPERATING CONDITIONS
PARAMETER
Temperature Range (Ambient)
Package Power Rating
MSOP8 Package (CM1216-06MS/MR)
SOIC8 Package (CM1216-06SN/SM)
MSOP10 Package (CM1216-08MS/MR)
RATING
-40 to +85
UNITS
°C
400
600
400
mW
mW
mW
© 2005 California Micro Devices Corp. All rights reserved.
06/30/05
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
3
PRELIMINARY
CM1216
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS NOTE 1
SYMBOL
PARAMETER
CONDITIONS
TYP
MAX
UNIT
3.3
5.5
V
8
μA
0.8
0.8
0.95
0.95
V
V
TA = 25°C; VP= 5V, VN = 0V
±0.1
±1.0
μA
Channel Input Capacitance
At 1 MHz, VP=3.3V, VN =0V,
VIN=1.65V;Note2
1.6
2.0
pF
Channel Input Capacitance
Matching
Note 2
0.04
pF
Mutual Capacitance
(VP-VN) = 3.3V; Note 2
0.13
pF
ESD Protection
Peak Discharge Voltage at
any channel input, in system,
contact discharge per
IEC 61000-4-2 standard
Notes 2, 3, and 4; TA = 25°C
Channel Clamp Voltage
Positive Transients
Negative Transients
IPP = 1A, tP = 8/20μS;
TA=25°C; Notes 2
Dynamic Resistance
Positive transients
Negative transients
IPP = 1A, tP = 8/20μS;
TA=25°C; Notes 2
VP
Operating Supply Voltage
(VP-VN)
IP
Operating Supply Current
(VP-VN) = 3.3V
VF
Diode Forward Voltage
Top Diode
Bottom Diode
IF = 20mA; TA=25°C
Channel Leakage Current
CIN
ΔCIN
ILEAK
CMUTUAL
VESD
VCL
RDYN
Note 1:
Note 2:
Note 3:
Note 4:
MIN
0.6
0.6
±15
kV
+9.0
-1.5
V
V
0.6
0.4
Ω
Ω
All parameters specified at TA = -40°C to +85°C unless otherwise noted.
These parameters guaranteed by design and characterization.
Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 3.3V, VN grounded.
From I/O pins to VP or VN only. VP bypassed to VN with low ESR 0.2μF ceramic capacitor.
© 2005 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
06/30/05
PRELIMINARY
CM1216
Performance Characteristics
Figure 1. Typical Variation of CIN vs. VIN
(f = 1MHz, VP= 3.3V, VN = 0V, 0.1μF chip capacitor between VP and VN, TA = 25°C)
Figure 2. Typical Filter Performance (nominal conditions unless
specified otherwise, 50 Ohm Environment
© 2005 California Micro Devices Corp. All rights reserved.
06/30/05
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
5
PRELIMINARY
CM1216
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
the power supply is represented by L1 and L2. The
voltage VCL on the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY +
L1 x d(IESD) / dt+ L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY
is the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(IESD)/dt can be approximated by
d(ESD)/dt, or 30/(1x10-9). So just 10nH of series inductance (L1 and L2 combined) will lead to a 300V increment in VCL!
Similarly for negative ESD pulses, parasitic series
inductance from the VN pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the VP pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also California Micro Devices Application Note
AP-209, “Design Considerations for ESD Protection”,
in the Applications section at www.calmicro.com.
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
© 2005 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
06/30/05
PRELIMINARY
CM1216
Mechanical Details
The CM1216 is supplied in SOIC-8, MSOP-8 and
MSOP-10 packages with a lead-free finishing option.
These package drawings are presented on the follow
pages.
SOIC-8 Mechanical Specifications
CM1216-06SN/SM devices are supplied in 8-pin SOIC
packages. Dimensions are presented below.
Mechanical Package Diagrams
For complete information on the SOIC-8 package, see
the California Micro Devices SOIC Package Information document.
TOP VIEW
D
8
7
6
5
PACKAGE DIMENSIONS
Package
SOIC
Pins
8
Dimensions
H
Millimeters
Min
Max
Min
Max
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.19
0.150
0.165
1.27 BSC
1
5.80
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
2
3
4
SIDE VIEW
A
SEATING
PLANE
0.050 BSC
H
# per tape
and reel
E
Inches
A
e
Pin 1
Marking
A1
B
2500 pieces
e
END VIEW
Controlling dimension: inches
C
L
Package Dimensions for SOIC-8
© 2005 California Micro Devices Corp. All rights reserved.
06/30/05
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
7
PRELIMINARY
CM1216
Mechanical Details
MSOP-8 Mechanical Specifications:
CM1216-06MS/MR devices are supplied in 8-pin
MSOP packages. Dimensions are presented below.
Mechanical Package Diagrams
For complete information on the MSOP-8 package,
see the California Micro Devices MSOP Package Information document.
TOP VIEW
D
8
7
6
5
PACKAGE DIMENSIONS
Package
MSOP
Pins
Dimensions
8
Millimeters
Min
Max
Min
Max
A
0.87
1.17
0.034
0.046
A1
0.05
0.25
0.002
0.010
B
0.30 (typ)
0.012 (typ)
C
0.18
0.007
D
2.90
3.10
0.114
0.122
E
2.90
3.10
0.114
0.122
e
0.65 BSC
4.78
4.98
0.188
0.196
L
0.43
0.64
0.017
0.025
Pin 1
Marking
1
2
3
4
SIDE VIEW
A
0.025 BSC
H
# per tape
and reel
E
H
Inches
A1
SEATING
PLANE
B
e
4000 pieces
END VIEW
Controlling dimension: inches
C
L
Package Dimensions for MSOP-8
© 2005 California Micro Devices Corp. All rights reserved.
8
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
06/30/05
PRELIMINARY
CM1216
Mechanical Details (cont’d)
MSOP-10 Mechanical Specifications
CM1216-08MS/MR devices are supplied in 10-pin
MSOP packages. Dimensions are presented below.
Mechanical Package Diagrams
For complete information on the MSOP-10 package,
see the California Micro Devices MSOP Package Information document.
TOP VIEW
D
10
9
8
6
7
PACKAGE DIMENSIONS
Package
MSOP
Pins
Dimensions
10
Millimeters
Min
Max
Min
Max
A
0.75
0.95
0.028
0.038
A1
0.05
0.15
0.002
0.006
B
0.18
0.40
0.006
0.016
C
0.18
2.90
3.10
0.114
0.122
E
2.90
3.10
0.114
0.122
0.50 BSC
0.0196 BSC
H
4.76
5.00
0.187
0.197
L
0.40
0.70
0.0137
0.029
# per tape
and reel
Pin 1
Marking
1
0.007
D
e
E
H
Inches
2
3
5
4
SIDE VIEW
A
A1
SEATING
PLANE
B
e
4000
END VIEW
Controlling dimension: inches
C
L
Package Dimensions for MSOP-10
© 2005 California Micro Devices Corp. All rights reserved.
06/30/05
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
9
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