MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER DESCRIPTION The M37271MF-XXXSP is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 52-pin shrink plastic molded DIP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy programming. The M37271MF-XXXSP has a OSD function and a data slicer function, so it is useful for a channel selection system for TV with a closed caption decoder. The features of the M37271EF-XXXSP and the M37271EFSP are similar to those of the M37271MF-XXXSP except that these chips have a built-in PROM which can be written electrically. FEATURES • Number of basic instructions ..................................................... 71 • Memory size • • • • • • • • • • • • • • • • • ROM ........................................................60 K bytes RAM ........................................................ 1024 bytes ROM for OSD ....................................... 14464 bytes RAM for OSD ......................................... 1920 bytes The minimum instruction execution time .......................................... 0.5µs (at 8 MHz oscillation frequency) Power source voltage .................................................. 5 V ± 10 % Subroutine nesting ............................................. 128 levels (Max.) Interrupts ....................................................... 18 types, 16 vectors 8-bit timers .................................................................................. 6 Programmable I/O ports (Ports P0, P1, P2, P30, P31) .............. 26 Input ports (Ports P40–P46, P63, P64) ......................................... 9 Output ports (Ports P52–P55) ...................................................... 4 12 V withstand ports .................................................................. 11 LED drive ports ........................................................................... 2 Serial I/O ............................................................ 8-bit ✕ 1 channel Multi-master I2C-BUS interface ............................... 1 (2 systems) A-D converter (8-bit resolution) ................................... 4 channels PWM output circuit ........................................................... 8-bit ✕ 7 Interrupt interval determination circuit ......................................... 1 Power dissipation In high-speed mode .......................................................... 165mW (at VCC = 5.5V, 8MHz oscillation frequency, CRT on, and Data slicer on) In low-speed mode .......................................................... 0.33mW (at VCC = 5.5V, 32kHz oscillation frequency) Data slicer • OSD function Display characters ............................... 40 characters ✕ 16 lines Kinds of characters ..................................................... 320 kinds (In EXOSD mode, they can be combined with 32 kinds of extra fonts) Dot structure ........................................ CC mode : 16 ✕ 26 dots OSD mode : 16 ✕ 20 dots EXOSD mode : 16 ✕ 26 dots Kinds of character sizes ................................ CC mode : 2 types OSD mode : 14 types EXOSD mode : 6 types It can be specified by a character unit (maximum 7 kinds). Character font coloring, character background coloring It can be specified by a screen unit (maximum 7 kinds). Extra font coloring, raster coloring, border coloring Kinds of character colors ............... CC mode : 7 kinds (R, G, B) OSD mode : 15 kinds (R, G, B, I) EXOSD mode : 7 kinds (R, G, B, I1, I2) Display position Horizontal ................................................................ 256 levels Vertical .................................................................. 1024 levels Attribute ...................... CC mode : smooth italic, underline, flash OSD mode : border EXOSD mode : border, extra font (32 kinds) Automatic solid space function Window function Dual layer OSD function APPLICATION TV with a closed caption decoder MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PIN CONFIGURATION (TOP VIEW) HSYNC 1 52 P52/R VSYNC 2 51 3 50 P41/INT2 4 49 P55/OUT1 P42/TIM2 5 48 P04/PWM0 P43/TIM3 6 47 P05/PWM1 P24/AD3 7 46 P06/PWM2 P25/AD2 8 45 P26/AD1 9 44 P07/PWM3 P20 P27 P00/PWM4 10 43 P21 42 P22 P01/PWM5 12 41 P02/PWM6 P17/SIN 13 P44/INT1 P45/SOUT 15 38 P23 P10/OUT2 P11/SCL1 P12/SCL2 37 P13/SDA1 P46/SCLK AVCC 17 36 P14/SDA2 P15/I1 11 14 16 18 M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP P40/AD4 P53/G P54/B 40 39 35 HLF 19 RVCO 20 33 VHOLD 21 32 CVIN CNV SS XIN 22 31 P30 P31 23 30 RESET 24 29 XOUT VSS 25 28 P64/OSC2/XCOUT P63/OSC1/XCIN 26 27 VCC 34 Outline 52P4B 2 P16/I2/INT3 P03 14 34 35 36 37 38 39 40 I/O port P1 I/O ports P30, P3 1 P1 (8) Processor status register PS (8) 32 31 P3 (2) Data bus RAM 1024 bytes Accumulator A (8) Multi-master I2C-BUS interface 8-bit arithmetic and logical unit Address bus Clock generating circuit 25 Y (8) X (8) P2 (8) A-D converter 26 TIM3 TIM2 23 P0 (8) Stack pointer S (8) ROM 60 K bytes Index register PCL (8) PCH (8) 27 Index register Program counter 18 Progam counter 30 VSS CNVSS SI/O (8) I/O port P2 I/O port P0 10 9 8 7 41 42 43 44 45 46 47 48 33 13 12 11 OUT2 INT3 24 SDA2 SDA1 SCL2 SCL1 Reset input RESET AVCC VCC SIN SCLK SOUT XIN XOUT Input ports P4 0–P46 17 16 15 6 5 4 3 P4 (7) Timer 6 T6 (8) Timer 5 T5 (8) Timer 4 T4 (8) Timer 3 T3 (8) Timer 2 T2 (8) Timer 1 T1 (8) 20 19 8-bit PWM circuit Instruction register (8) Instruction decoder Control signal Data slicer 21 Timer count source selection circuit 22 VHOLD HLF CVIN RVCO PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Clock input Clock output INT1 INT2 P6 (2) 29 P5 (4) 49 50 51 52 Output port P5 CRT circuit 28 Input ports P6 3, P64 Clock input for OSD/ Clock output for OSD/ sub-clock input sub-clock output OSC1 OSC2 OUT1 B G R Pins for data slicer 1 H SYNC Sync signal input 2 VSYNC FUNCTIONAL BLOCK DIAGRAM of M37271MF-XXXSP MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 3 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONS Parameter Functions Number of basic instructions 71 Instruction execution time 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency) Clock frequency Memory size 8 MHz (maximum) ROM 60 K bytes RAM 1024 bytes OSD ROM 14464 bytes OSD RAM Input/Output ports I/O 7-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM output pins) P03 I/O 1-bit ✕ 1 (CMOS input/output structure) P10, P15–P17 I/O 4-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin, INT input pin, serial input pin) P11–P14 I/O 4-bit ✕ 1 (N-channel open-drain output structure, can be used as multimaster I2C-BUS interface) P2 I/O 8-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins) 2-bit ✕ 1 (CMOS input/output structure) P40–P44 I/O Input P45, P46 Input 2-bit ✕ 1 (N-channel open-drain output structure when serial I/O is used, can be used as serial I/O pins) P52–P55 Output P30, P31 4 1920 bytes P00–P02, P04–P07 5-bit ✕ 1 (can be used as A-D input pins, INT input pins, external clock input pins) 4-bit ✕ 1 (CMOS output structure, can be used as OSD output) P63 Input 1-bit ✕ 1 (can be used as sub-clock input pin, OSD clock input pin) P64 Input 1-bit ✕ 1 (CMOS output structure when LC is oscillating, can be used as sub-clock output pin, OSD clock output pin) Serial I/O 8-bit ✕ 1 Multi-master I2C-BUS interface 1 A-D converter 4 channels (8-bit resolution) PWM output circuit 8-bit ✕ 7 Timers 8-bit timer ✕ 6 Subroutine nesting 128 levels (maximum) Interrupt interval determination circuit 1 Interrupt External interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1, OSD interrupt ✕ 1, Multi-master I 2 C-BUS interface interrupt ✕ 1, Data slicer interrupt ✕ 1, f(XIN)/4092 interrupt ✕ 1, VSYNC interrupt ✕ 1, AD conversion interrupt ✕ 1, BRK instruction interrupt ✕ 1 Clock generating circuit 2 built-in circuits (externally connected a ceramic resonator or a quartzcrystal oscillator) Data slicer Built in MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONS (continued) OSD function Number of display characters 40 characters ✕ 16 lines Dot structure CC mode: 16 ✕ 26 dots (character part : 16 ✕ 20 dots) OSD mode: 16 ✕ 20 dots EXOSD mode: 16 ✕ 26 dots Kinds of characters 320 kinds (In EXOSDmode, they can be combined with 32 kinds of extra fonts) Kinds of character sizes CC mode: 2 kinds OSD mode: 14 kinds EXOSD mode: 6 kinds Kinds of character colors CC mode: 7 kinds (R, G, B) OSD mode: 15 kinds (R, G, B, I1) EXOSD mode: 7 kinds (R, G, B, I1, I2) Display position (horizontal, vertical) Power source voltage Power dissipation 256 levels (horizontal) ✕ 1024 levels (vertical) 5 V ± 10 % In high-speed OSD ON Data slicer ON 165 mW typ. (at oscillation frequency fCPU = 8 MHz, fOSD = 13 MHz) mode OSD OFF Data slicer OFF 82.5 mW typ. (at oscillation frequency fCPU = 8 MHz) In low-speed mode In stop mode OSD OFF Data slicer OFF 0.33mW typ. (at oscillation frequency fCLK = 32 kHz, f(XIN) = stopped) 0.055 mW (maximum) Operating temperature range –10 °C to 70 °C Device structure CMOS silicon gate process Package 52-pin shrink plastic molded DIP 5 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION Pin Name VCC, AVCC, VSS. Power source CNVSS CNVSS Input/ Output Name Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC, and 0 V to VSS. This is connected to VSS. _____ RESET Reset input Input To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time. XIN Clock input Input XOUT Clock output This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. P00/PWM4– P02/PWM6, P03, P04/PWM0– P07/PWM3 I/O port P0 P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/I1, P16/I2/INT3, P17/SIN Output I/O Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure of P03 is CMOS output, that of P00–P02 and P04–P07 are N-channel open-drain output. The note out of this Table gives a full of port P0 function. Output Pins P00–P02 and P04–P07 are also used as PWM output pins PWM4–PWM6 and PWM0– PWM3 respectively. The output structure is N-channel open-drain output. I/O port P1 I/O Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure of P10 and P15–P17 is CMOS output, that of P11–P14 is N-channel open-drain output. OSD output Output Pins P10, P15, P16 are also used as OSD output pins OUT2, I1, I2 respectively. The output structure is CMOS output. Multi-master I2C-BUS interface Output Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. PWM output Serial I/O data input Input P17 pin is also used as serial I/O data input pin SIN. P20–P23 P24/AD3– P26/AD1, P27 I/O port P2 P30, P31 I/O port P3 P40/AD4, P41/INT2, P42/TIM2, P43/TIM3, P44/INT1, P45/SOUT, P46/SCLK, Input port P4 Input Ports P40–P46 are a 7-bit input port. Analog input Input P40 pin is also used as analog input pin AD4. External interrupt input Input Pins P41, P44 are also used as external interrupt input INT2, INT1. Analog input External clock input Serial I/O data output Serial I/O synchronizing clock input/output P52/R,P53/G, Output port P5 P54/B, P55/OUT1 OSD output 6 I/O Input I/O Input Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P24–P26 are also used as analog input pins AD3–AD1 respectively. Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P42 and P43 are also used as external clock input pins TIM2, TIM3 respectively. Output P45 pin is used as serial I/O data output pin SOUT. The output structure is N-channel opendrain output. I/O P46 pin is used as serial I/O synchronizing clock input/output pin SCLK. The output structure is N-channel open-drain output. Output Ports P52–P55 are a 4-bit output port. The output structure is CMOS output. Output Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION (continued) P63/OSC1/ Input port XCIN, Clock input for OSD P64/OSC2/ Clock output for OSD XCOUT Sub-clock output Sub-clock input CVIN I/O for data slicer VHOLD Input Ports P63 and P64 are 2-bit input port. Input P63 pin is also used as OSD clock input pin OSC1. Output P64 pin is also used as OSD clock output pin OSC2. The output structure is CMOS output. Output P64 pin is also used as sub-clock output pin XCOUT. The output structure is CMOS output. Input P63 pin is also used as sub-clock input pin XCIN. Input Input composite video signal through a capacitor. Input Connect a capacitor between VHOLD and VSS. RVCO Connect a resistor between RVCO and VSS. HLF Connect a filter using of a capacitor and a resistor between HLF and VSS. HSYNC HSYNC input Input This is a horizontal synchronizing signal input for OSD. VSYNC VSYNC input Input This is a vertical synchronizing signal input for OSD. Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. 7 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) CPU Mode Register The M37271MF-XXXSP uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 < Software > User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used. 7 The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated at address 00FB16. 0 1 1 0 0 CPU mode register (CPUM (CM) : address 00FB16) Processor mode bits b1 b0 0 0 1 1 0 : Single-chip mode 1: 0 : Not available 1: Stack page selection bit (Note) 0 : Zero page 1 : 1 page Fix these bits to “1.” XCOUT drivability selection bit 0 : Low drive 1 : High drive Main colock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Internal system clock selection bit 0 : XIN–XOUT selected (high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) Note: Please beware of this bit when programming because it is set to “1” after the reset release. Fig. 1. Structure of CPU mode register 8 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER MEMORY Special Function Register (SFR) Area Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. Zero Page ROM The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. ROM is used for storing user programs as well as the interrupt vector area. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. RAM for OSD RAM for display is used for specifying the character codes and colors to display. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM for OSD ROM for display is used for storing character data. 000016 1000016 Not used 1080016 00C016 00FF16 RAM (1024 bytes) Zero page SFR1 area 020016 023F16 SFR2 area 1567F16 Not used Not used 030016 1800016 ROM for OSD (14464 bytes) 053F16 Not used RAM for OSD (Note) (1920 bytes) 080016 0FFF16 100016 ROM (60 K bytes) FF0016 FFDE16 FFFF16 1E43F16 Interrupt vector area Not used Special page 1FFFF16 Fig. 2. Memory map 9 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ■SFR1 area (addresses C016 to DF16) : Nothing is allocated : Fix this bit to “0” ( do not write “1”) 0 : “0” immediately after reset ? : undefined immediately after reset Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register Bit allocation b7 Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P4 (P4) Port P4 direction register (D4) Port P5 (P5) OSD port control register (PF) Port P6 (P6) OUT2 OUT1 B G R I2 I1 OSD control register (OC) OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0 Horizontal position register (HP) HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 Block control register 1 (BC1) BC18 BC 17 BC 16 BC15 BC 14 BC13 BC12 BC11 Block control register 2 (BC2) Block control register 3 (BC3) BC28 BC 27 BC 26 BC25 BC 24 BC23 BC22 BC21 BC38 BC 37 BC 36 BC35 BC 34 BC33 BC32 BC31 Block control register 4 (BC4) BC48 BC 47 BC 46 BC45 BC 44 BC43 BC42 BC41 Block control register 5 (BC5) BC58 BC 57 BC 56 BC55 BC 54 BC53 BC52 BC51 Block control register 6 (BC6) BC68 BC 67 BC 66 BC65 BC 64 BC63 BC62 BC61 BC78 BC 77 BC 76 BC75 BC 74 BC73 BC72 BC71 Block control register 7 (BC7) Block control register 8 (BC8) Block control register 9 (BC9) BC88 BC 87 BC 86 BC85 BC 84 BC83 BC82 BC81 BC98 BC 97 BC 96 BC95 BC 94 BC93 BC92 BC91 Block control register 10 (BC10) BC108 BC107 BC106 BC105 BC104 BC103 BC102 BC101 Block control register 11 (BC11) BC118 BC117 BC116 BC115 BC114 BC113 BC112 BC111 Block control register 12 (BC12) Block control register 13 (BC13) Block control register 14 (BC14) Block control register 15 (BC15) Block control register 16 (BC16) BC128 BC127 BC126 BC125 BC124 BC123 BC122 BC121 BC138 BC137 BC136 BC135 BC134 BC133 BC132 BC131 BC148 BC147 BC146 BC145 BC144 BC143 BC142 BC141 BC158 BC157 BC156 BC155 BC154 BC153 BC152 BC151 BC168 BC167 BC166 BC165 BC164 BC163 BC162 BC161 Fig. 3. Memory map of special function register 1 (SFR1) (1) 10 State immediately after reset b0 b7 ? 0 ? 0 ? 0 ? ? 0 ? 0 ? 0 ? ? 0 ? 0 ? 0 ? ? 0016 ? 0016 ? 0016 ? ? 0 0 ? ? 0 0 ? ? 0 0 ? ? ? 0016 0016 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? 0 ? 0 ? ? 0 ? 0 ? 0 ? b0 ? 0 ? 0 ? 0 ? MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ■SFR1 area (addresses E016 to FF16) : Nothing is allocated : Fix this bit to “0” ( do not write “1”) : Fix this bit to “1” ( do not write “0”) 0 : “0” immediately after reset 1 : “1” immediately after reset ? : undefined immediately after reset Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register Caption position register (CP) Start bit position register (SP) Window register (WN) Sync slice register (SSL) Data register 1 (CD1) Data register 2 (CD2) Clock run-in register 1 (CR1) Clock run-in register 2 (CR2) b7 Bit allocation State immediately after reset b0 b7 CP4 CP3 CP2 CP1 CP0 1 b0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 WN5 WN4 WN3 WN2 WN1 WN0 SSL7 CR11 CR21 Clock run-in detect register 1 (CRD1) CRD17 CRD15 CRD15 CRD15 CRD15 CRD12 CRD11 CRD10 Clock run-in detect register 2 (CRD2) CRD27 CRD25 CRD25 CRD25 CRD25 CRD22 CRD21 CRD20 Data slicer control register 1 (DSC1) Data slicer control register 2 (DSC2) DSC17 DSC15 DSC12 DSC11 DSC10 DSC27 DSC25 DSC22 DSC21 DSC20 ? 0 0 ADIN1 ADIN0 0 ? 0 TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Data register 3 (CD3) Data register 4 (CD4) A-D conversion register (AD) A-D control register (ADCON) Timer 1 (TM1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) ADV ADVREF ADSTR TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB BSEL1 BSEL0 10 BIT ALS ES0 BC2 BC1 BC0 SAD ACK FAST ACK BIT CCR4 CCR3 CCR2 CCR1 CCR0 MODE CM7 CM6 CM5 CM2 CM1 CM0 ADR VSCR CRTR TM4R TM3R TM2R TM1R T56R IICR INT2R CK01MSR SIOR DSR INT1R ADE VSCE CRTE TM4E TM3E TM2E TM1E T56S T56E IICE INT2E 1MSE SIOE DSE INT1E ? ? 0016 0 0 0 0 ? ? 1 0 1 1 0 0 0 1 ? 0 0 0016 0016 ? 0 0 FF16 0716 FF16 0716 0 0 0 0 ? 0016 1 0 0016 0016 1 1 0 0 CK0 0 0 0 0 0 0 ? ? ? 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Fig. 4. Memory map of special function register 1 (SFR2) (2) 11 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ■SFR2 area (addresses 20016 to 21F16) : Nothing is allocated : Fix this bit to “0” ( do not write “1”) 0 : “0” immediately after reset 1 : “1” immediately after reset ? : undefined immediately after reset Address Register Bit allocation State immediately after reset b0 b7 b7 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C16 21D16 21E16 21F16 PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5) ? PWM6 register (PWM6) 0 0 0 0 0 0 0 0 0 ? ? ? 0 ? ? 0716 FF16 ? 0 0 0016 ? 0016 0 ? ? ? 0 ? ? ? 0 ? 0 ? 0 0 0 0 0 0 0 ? ? 0 0 0016 0 0 ? 0 0 ? ? ? ? ? ? ? 0 ? 0 ? 0 0 0 0 0 0 0 ? ? ? ? ? ? ? Clock run-in detect register (CRD3) ENABLE POL PW6 PW5 PW4 PW3 PW2 PW1 PW0 0 ? ? 0 0 ? ? ? 0 ? ? ? SYC5 SYC4 SYC3 SYC2 SYC1 SYC0 ? ? 0 0 0 0 CRD35 CRD34 CRD33 CRD32 CRD31 Clock run-in register (CR3) PWM mode register 1 (PN) PWM mode register 2 (PW) Timer 5 (TM5) Timer 6 (TM6) Sync pulse counter register (SYC) Data slicer control register 3 (DSC3) DSC37 DSC36 DSC35 DSC34 DSC33 DSC32 DSC31 DSC30 Interrupt interval determination register (RI) Interrupt interval determination control register (RE) Serial I/O mode register (SM) AD/INT3 SEL AD/INT3 SEL INT3 POL INT3 POL RE5 RE4 RE3 RE2 RE1 RE0 RE5 SM4 SM3 SM5 RE3 SM2 RE2 SM1 RE1 SM0 AD/INT3 SEL AD/INT3 PC7 SEL AD/INT3 RC7 SEL AD/INT3 SEL INT3 RE5 RE3 RE2 RE1 CS6 POL CS5 CS4 CS3 CS2 CS1 CS0 0 1 ? 0 ? 0 RE3 RE2 RE1 ? ? ? FC4 FC3 FC2 FC1 FC0 ? ? ? Window L register 1 (WH1) Window H register 2 (WH2) WH21 WH20 Window L register 2 (WH2) WL21 WL20 ? ? ? ? ? ? Clock source control register (CS) I/O polarity control register (PC) Raster color register (RC) Extra font color register (EC) 0 ? ? Serial I/O register (SIO) INT3 PC6 RE5 PC4 PC3 PC5 RE3 PC2 RE2 PC1 RE1 PC0 POL INT3 RC6 RE5 RC4 RC3 RE3 RC2 RE2 RC1 RE1 RC0 POL RC5 INT3 POL RE5 Border color register (FC) Window H register 1 (WH1) Fig. 5. Memory map of special function register 2 (SFR2) (1) 12 b0 ? ? ? ? ? ? PWM0 register (PWM0) MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ■SFR2 area (addresses 22016 to 23F16) : Nothing is allocated ? : undefined immediately after reset Address Register b7 Bit allocation b0 b7 22016 Vertical position register 11 (VP11) 22116 Vertical position register 12 (VP12) VP1 18 VP117 VP116 VP115 VP114 VP1 13 VP1 12 VP1 11 22216 22316 22416 22516 22616 22716 22816 22916 22A16 22B16 22C16 22D16 22E16 22F16 23016 23116 23216 23316 23416 23516 23616 23716 23816 23916 23A16 23B16 23C16 23D16 23E16 23F16 Vertical position register 13 (VP13) VP1 38 VP137 VP136 VP135 VP134 VP1 33 VP1 32 VP1 31 Vertical position register 14 (VP14) VP1 48 VP147 VP146 VP145 VP144 VP1 43 VP1 42 VP1 41 Vertical position register 15 (VP15) Vertical position register 16 (VP16) VP1 58 VP157 VP156 VP155 VP154 VP1 53 VP1 52 VP1 51 Vertical position register 17 (VP17) VP1 78 VP177 VP176 VP175 VP174 VP1 73 VP1 72 VP1 71 Vertical position register 18 (VP18) Vertical position register 19 (VP19) VP1 88 VP187 VP186 VP185 VP184 VP1 83 VP1 82 VP1 81 Vertical position register 110 (VP110) VP1108 VP1 107 VP1106 VP1105 VP1104 VP1103 VP1102 VP1101 Vertical position register 111 (VP111) Vertical position register 112 (VP112) VP1118 VP1 117 VP1116 VP1115 VP1114 VP1113 VP1112 VP1111 Vertical position register 113 (VP113) Vertical position register 114 (VP114) VP1138 VP1 137 VP1136 VP1135 VP1134 VP1133 VP1132 VP1131 Vertical position register 115 (VP115) Vertical position register 116 (VP116) VP1158 VP1 157 VP1156 VP1155 VP1154 VP1153 VP1152 VP1151 State immediately after reset b0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? VP1 28 VP127 VP126 VP125 VP124 VP1 23 VP1 22 VP1 21 VP1 68 VP167 VP166 VP165 VP164 VP1 63 VP1 62 VP1 61 VP1 98 VP197 VP196 VP195 VP194 VP1 93 VP1 92 VP1 91 VP1128 VP1 127 VP1126 VP1125 VP1124 VP1123 VP1122 VP1121 VP1148 VP1 147 VP1146 VP1145 VP1144 VP1143 VP1142 VP1141 VP1168 VP1 167 VP1166 VP1165 VP1164 VP1163 VP1162 VP1161 Vertical position register 21 (VP21) VP2 12 VP2 11 Vertical position register 22 (VP22) VP2 22 VP2 21 Vertical position register 23 (VP23) VP2 32 VP2 31 Vertical position register 24 (VP24) VP2 42 VP2 41 Vertical position register 25 (VP25) Vertical position register 26 (VP26) Vertical position register 27 (VP27) VP2 52 VP2 51 Vertical position register 28 (VP28) Vertical position register 29 (VP29) VP2 82 VP2 81 Vertical position register 210 (VP210) VP2102 VP2101 Vertical position register 211 (VP211) Vertical position register 212 (VP212) VP2112 VP2111 Vertical position register 213 (VP213) VP2132 VP2131 Vertical position register 214 (VP214) VP2142 VP2141 Vertical position register 215 (VP215) Vertical position register 216 (VP216) VP2152 VP2151 VP2 62 VP2 61 VP2 72 VP2 71 VP2 92 VP2 91 VP2122 VP2121 VP2162 VP2161 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Fig. 6. Memory map of special function register 2 (SFR2) (2) 13 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER : Nothing is allocated 1 : “1” immediately after reset ? : undefined immediately after reset Register Bit allocation State immediately after reset b0 b7 b7 Processor status register (PS) Program counter (PCH) N V T B D I Z Program counter (PCL) Fig. 7. Internal state of processor status register and program counter at reset 14 C b0 ? ? ? ? ? 1 ? ? Contents of address FFFF 16 Contents of address FFFE 16 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER INTERRUPTS Interrupt Causes Interrupts can be caused by 18 different sources consisting of 4 external, 12 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities shown in Table 1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, (1) The contents of the program counter and processor status register are automatically stored into the stack. (2) The interrupt disable flag I is set to “1” and the corresponding interrupt request bit is set to “0.” (3) The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figure 8 shows the structure of the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,” and the interrupt disable flag is “0.” The interrupt request bit can be set to “0” by a program, but not set to “1.” The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 9 shows interrupt control. (1) VSYNC and OSD interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed. (2) INT1, INT2, INT3 interrupts With an external interrupt input, the system detects that the level of a pin changes from “L” to “H” or from “H” to “L,” and generates an interrupt request. The input active edge can be selected by bits 3, 4 and 6 of the interrupt interval determination control register (address 021216) : when this bit is “0,” a change from “L” to “H” is detected; when it is “1,” a change from “H” to “L” is detected. Note that all bits are cleared to “0” at reset. (3) Timer 1, 2, 3 and 4 interrupts An interrupt is generated by an overflow of timer 1, 2, 3 or 4. (4) Serial I/O interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 interrupt This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM mode register 1 to “0.” (6) Data slicer interrupt An interrupt occurs when slicing data is completed. (7) Multi-master I2C-BUS interface interrupt This is an interrupt request related to the multi-master I2C-BUS interface. (8) A-D conversion interrupt An interrupt occurs at the completion of A-D conversion. Since A-D conversion interrupt and the INT3 interrupt share the same vector, an interrupt source is selected by bit 7 of the interrupt interval determination control register (address 021216). Table 1. Interrupt vector addresses and priority Interrupt source Priority Vector addresses Reset 1 FFFF16, FFFE16 OSD interrupt 2 FFFD16, FFFC16 INT1 interrupt 3 FFFB16, FFFA16 Data slicer interrupt 4 FFF916, FFF816 Serial I/O interrupt 5 FFF716, FFF616 Timer 4 interrupt 6 FFF516, FFF416 f(XIN)/4096 interrupt 7 FFF316, FFF216 VSYNC interrupt 8 FFF116, FFF016 Timer 3 interrupt 9 FFEF16, FFEE16 Timer 2 interrupt 10 FFED16, FFEC16 Timer 1 interrupt 11 FFEB16, FFEA16 A-D convertion · INT3 interrupt 12 FFE916, FFE816 Active edge selectable INT2 interrupt 13 FFE716, FFE616 Active edge selectable I2C-BUS 14 FFE516, FFE416 Timer 5 · 6 interrupt 15 FFE316, FFE216 BRK instruction interrupt 16 FFDF16, FFDE16 Multi-master interface interrupt Remarks Non-maskable Active edge selectable Active edge selectable Non-maskable (software interrupt) 15 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (9)Timer 5 · 6 interrupt An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. (10)BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable). Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig. 9. Interrupt control 7 0 7 Interrupt request register 1 (IREQ1: address 00FC 16) 0 Interrupt request register 2 (IREQ2: address 00FD 16) 0 Timer 1 interrupt request bit INT1 interrupt request bit Timer 2 interrupt request bit Data slicer interrupt request bit Timer 3 interrupt request bit Serial I/O interrupt request bit Timer 4 interrupt request bit f(XIN)/4096 interrupt request bit OSD interrupt request bit INT2 interrupt request bit VSYNC interrupt request bit Multi-master I 2C-BUS interface interrupt request bit A-D conversion ⋅ INT3 interrupt request bit Timer 5 ⋅ 6 interrupt request bit Fix this bit to “0.” 0 : No interrupt request issued 1 : Interrupt request issued 7 0 7 Interrupt control register 1 ( ICON1: address 00FE 16) Interrupt control register 2 ( ICON2 : address 00FF 16) Timer 1 interrupt enable bit INT1 interrupt enable bit Timer 2 interrupt enable bit Data slicer interrupt enable bit Timer 3 interrupt enable bit Serial I/O interrupt enable bit Timer 4 interrupt enable bit f(XIN)/4096 interrupt enable bit OSD interrupt enable bit INT2 interrupt enable bit VSYNC interrupt enable bit Multi-master I 2C-BUS interface enable bit A-D conversion ⋅ INT3 interrupt request bit 0 : Interrupt disabled 1 : Interrupt enabled Fig. 8. Structure of interrupt-related registers 16 0 Timer 5 ⋅ 6 interrupt enable bit Timer 5 ⋅ 6 interrupt switch bit 0 : Timer 5 1 : Timer 6 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER TIMERS (5) Timer 5 The M37271MF-XXXSP has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 11. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. The value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses 020C16 and 020D16 : timers 5 and 6). The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse after the count value reaches “0016”. Timer 5 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 Timer 2 overflow signal Timer 4 overflow signal The count source of timer 3 is selected by setting bit 6 of the timer mode register 1 (address 00F416) and bit 7 of the timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow. (1) Timer 1 Timer 1 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 f(XIN)/4096 or f(XCIN)/4096 External clock from the P42/TIM2 pin The count source of timer 1 is selected by setting bits 5 and 0 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 1 interrupt request occurs at timer 1 overflow. • • • (2) Timer 2 Timer 2 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 Timer 1 overflow signal External clock from the P42/TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. • • • (3) Timer 3 Timer 3 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 f(XCIN) External clock from the P43/TIM3 pin The count source of timer 3 is selected by setting bit 0 of the timer mode register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow. • • • (6) Timer 6 Timer 6 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 Timer 5 overflow signal The count source of timer 6 is selected by setting bit 7 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for the timer 6, the timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow. • • At reset, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. The f(XIN) ✽ /16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow at these state, the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN) ✽ /16 is not selected as the timer 3 count source. So set both bit 0 of the timer mode register 2 (address 00F516) and bit 6 at address 00C716 to “0” before the execution of the STP instruction (f(XIN) ✽ /16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow at these state, the internal clock is connected. Because of this, the program starts with the stable clock. ✽ : When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) becomes f(XCIN). The structure of timer-related registers is shown in Figure 10. • • • (4) Timer 4 Timer 4 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 f(XIN)/2 or f(XCIN)/2 f(XCIN) The count source of timer 3 is selected by setting bits 4 and 1 of the timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. • • • 17 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 7 0 7 Timer mode register 1 (TMR1 : address 00F416) Timer 1 count source selection bit 1 0 : f(XIN)/16 or f(XCIN)/16 (Note) 1 : Count source selected by bit 5 of TMR1 Timer 2 count source selection bit 1 0 : Count source selected by bit 4 of TMR1 1 : External clock from P42/TIM2 pin Timer 1 count stop bit 0 : Count start 1 : Count stop Timer 2 count stop bit 0 : Count start 1 : Count stop Timer 2 count source selection bit 2 0 : f(XIN)/16 or f(XCIN)/16 (Note) 1 : Timer 1 overflow 0 Timer mode register 2 (TMR2 : address 00F516) Timer 3 count source selection bit (Bit 6 at address 00C716) b0 0 1 0 1 0 : f(XIN)/16 or f(XCIN)/16 (Note) 0 : f(XCIN) 1 : External clock from 1 : P43/TIM3 pin Timer 4 count source selection bits b4 b1 0 0 : Timer 3 overflow 0 1 : f(XIN)/16 or f(XCIN)/16 (Note) 1 0 : f(XIN)/2 or f(XCIN)/2 (Note) 1 1 : f(XCIN) Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 1 count source selection bit 2 0 : f(XIN)/4096 or f(XCIN)/4096 (Note) 1 : External clock from P42/TIM2 pin Timer 5 count source selection bit 2 0 : Timer 2 overflow 1 : Timer 4 overflow Timer 4 count stop bit 0 : Count start 1 : Count stop Timer 6 count source selection bit 0 : f(XIN)/16 or f(XCIN)/16 (Note) 1 : Timer 5 overflow Timer 6 count stop bit 0 : Count start 1 : Count stop Timer 5 count stop bit 0 : Count start 1 : Count stop Timer 5 count source selection bit 1 0 : f(XIN)/16 or f(XCIN)/16 (Note) 1 : Count source selected by bit 6 of TMR1 Note : Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Fig. 10. Structure of timer-related registers 18 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Data bus 8 XCIN CM7 TMR15 Timer 1 latch (8) 1/4096 8 X IN 1/2 1/8 Timer 1 interrupt request Timer 1 (8) TMR10 TMR12 8 TMR14 8 Timer 2 latch (8) 8 P42/TIM2 Timer 2 interrupt request Timer 2 (8) TMR11 TMR13 8 8 FF16 TM3EL Reset STP instruction Timer 3 latch (8) 8 Timer 3 interrupt request Timer 3 (8) P43/TIM3 TMR20 TMR22 8 8 07 16 TMR21 Timer 4 latch (8) 8 Timer 4 interrupt request Timer 4 (8) TMR21 TMR24 TMR23 8 8 TMR16 Timer 5 latch (8) Selection gate : Connected to black colored side at reset 8 Timer 5 interrupt request Timer 5 (8) TMR1 : Timer mode register 1 TMR2 : Timer mode register 2 TM3EL : Timer 3 count source switch bit (address 00C7 16) CM : CPU mode register TMR27 TMR25 8 8 Timer 6 latch (8) 8 Timer 6 interrupt request Timer 6 (8) TMR17 TMR26 8 Notes 1: “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. Fig. 11. Timer block diagram 19 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER SERIAL I/O The M37271MF-XXXSP has a built-in serial I/O which can either transmit or receive 8-bit data in serial in the clock synchronous mode. The serial I/O block diagram is shown in Figure 12. The synchronizing clock I/O pin (SCLK), and data output pin (SOUT) also function as port P4, data input pin (SIN) also functions as port P1. Bit 2 of the serial I/O mode register (address 021316) selects whether the synchronizing clock is supplied internally or externally (from the P46/SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) is divided by 8, 16, 32, or 64. To use P45/SOUT and P46/SCLK pins for serial I/O, set the corresponding bits of the port P4 direction register (address 00C916) to “0.” To use P17/SIN pin for serial I/O, set the corresponding bit of the port P1 direction register (address 00C316) to “0.” The operation of the serial I/O function is described below. The function of the serial I/O differs depending on the clock source; external clock or internal clock. XCIN 1/2 XIN 1/2 Data bus Frequency divider 1/2 CM7 1/2 Synchronization circuit P46/SCLK P45/SOUT 1/4 1/8 1/16 SM1 SM0 SM2 S CM : CPU mode register SM : Serial I/O mode register Serial I/O interrupt request Serial I/O counter (8) SM5 : LSB Selection gate: Connect to black colored side at reset. MSB (Note) P17/SIN Serial I/O shift register (8) 8 (Address 0214 16) Note : When the data is set in the serial I/O register (address 0214 16), the register functions as the serial I/O shift register. Fig. 12. Serial I/O block diagram 20 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Internal clock—the serial I/O counter is set to “7” during write cycle into the serial I/O register (address 021416), and transfer clock goes “H” forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at “H.” At this time the interrupt request bit is set to “1.” External clock—when an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has counted 8 times. However, transfer operation does not stop, so control the clock externally. Use the external clock of 500kHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 13. When using an external clock for transfer, the external clock must be held at “H” for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. 7 0 Serial I/O mode register (SM : address 021316) 0 0 Internal synchronizing clock selection bits b1 b0 0 0 : f(XIN)/8 or f(XCIN)/8 0 1 : f(XIN)/16 or f(XCIN)/16 1 0 : f(XIN)/32 or f(XCIN)/32 1 1 : f(XIN)/64 or f(XCIN)/64 Synchronizing clock selection bit 0 : External clock 1 : Internal clock Port function selection bit 0 : P11, P13 functions as port 1 : SCL1, SDA1 Port function selection bit 0 : P12, P14 functions as port 1 : SCL2, SDA2 Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions as SEB and CLB instructions. 2: When an external clock is used as the synchronizing clock, write transmit data to the serial I/O register at “H” of the transfer clock input level. Transfer direction selection bit 0 : LSB first 1 : MSB first Fix these bits to “0” Fig. 14. Structure of serial I/O mode register Synchroninzing clock Transfer clock Serial I/O register write signal (Note) Serial I/O output SOUT D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O input S IN Interrupt request bit is set to “1” Note : When an internal clock is selected, the S OUT pin is at high-impedance after transfer is completed. Fig. 13. Serial I/O timing (for LSB first) 21 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PWM OUTPUT FUNCTION The M37271MF-XXXSP is equipped with seven 8-bit PWMs (PWM0– PWM6). PWM0–PWM6 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 µs (for f(XIN) = 8 MHz) and repeat period of 1024 µs. Figure 15 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0–PWM6 using f(XIN) divided by 2 as a reference signal. (1) Data Setting When outputting PWM0–PWM6, set 8-bit output data in the PWMi register (i means 0 to 6; addresses 020016 to 020616). (2) Transmitting Data from Register to PWM circuit Data transfer from the 8-bit PWM register to 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register. (3) Operating of 8-bit PWM The following is the explanation about PWM operation. At first, set the bit 0 of PWM mode register 1 (address 020A16) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. PWM0–PWM3 are also used as pins P04–P07, PWM4–PWM6 are also used as pins P00–P02, respectively. Set the corresponding bits of the port P0 direction register to “1” (output mode). And select each output polarity by bit 3 of the PWM mode register 1 (address 020A16). Then, set bits 7 to 0 of the PWM output control register 2 to “1” (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 16 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses relative to the weight of each bit (bits 0 to 7) are output inside the circuit during 1 cycle. Refer to Figure 16 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 16 (b). 256 kinds of output (“H” level area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely “H” output cannot be output, i.e. 256/256. (4) Output after Reset At reset, the output of ports P00–P02 and P04–P07 is in the highimpedance state, port P50 outputs “L,” and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register. 22 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Data bus XIN 1/2 ENABLE PWM timing generating circuit PWM0 register (Address 0200 16) b7 b0 8 POL P04 D04 PWM0 D05 PWM1 D06 PWM2 D07 PWM3 D00 PWM4 D01 PWM5 D02 PWM6 8-bit PWM circuit PW0 P05 PWM1 register (Address 0201 16) PW1 P06 PWM2 register (Address 0202 16) PW2 P07 PWM3 register (Address 0203 16) PW3 P00 PWM4 register (Address 0204 16) PW4 P01 PWM5 register (Address 0205 16) PW5 P02 Selection gate : Connected to black colored side at reset. Inside of PWM6 register (Address 0206 16) is as same contents with the others. PW6 PN : PWM mode register 1 (address 020A 16) PW : PWM mode register 2 (address 020B 16) P0 : Port P0 register (address 00C0 16) D0 : Port P0 direction register (address 00C1 16) Fig. 15. PWM block diagram 23 24 Fig. 16. 8-bit PWM timing FF16 (255) 1816 (24) 0116 (1) 0016 (0) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 t 2 4 6 8 60 80 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 t = 4 µs T = 1024 µs f(XIN) = 8 MHz (b) Example of 8-bit PWM PWM output T = 256 t 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 224 220 228 232 236 240 244 248 252 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 96 94 100 (a) Pulses showing the weight of each bit 92 90 90 88 86 84 82 80 78 76 74 72 70 70 68 66 64 62 60 58 56 54 52 50 50 48 46 44 42 40 40 38 36 34 32 30 30 28 26 24 22 20 20 18 16 14 12 10 13579 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 7 PWM mode register 1 (PN: address 020A 16) PWM count source selection bit 0 : Count source supply 1 : Count source stop PWM output polarity selection bit 0 : Positive polarity 1 : Negative polarity 0 0 PWM mode register 2 (PW: address 020B 16) P04/PWM0 output selection bit 0 : P0 4 output 1 : PWM0 output P05/PWM1 output selection bit 0 : P0 5 output 1 : PWM1 output P06/PWM2 output selection bit 0 : P0 6 output 1 : PWM2 output P07/PWM3 output selection bit 0 : P0 7 output 1 : PWM3 output P00/PWM4 output selection bit 0 : P0 0 output 1 : PWM4 output P01/PWM5 output selection bit 0 : P0 1 output 1 : PWM5 output P02/PWM6 output selection bit 0 : P0 2 output 1 : PWM6 output Fix this bit to “0.” Fig. 17. Structure of PWM-related registers 25 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER A-D CONVERTER (1)A-D Conversion Register (AD) (5)Comparator and Control Circuit A-D conversion reigister is a read-only register that stores the result of an A-D conversion. This register should not be read during A-D conversion. The conversion result of the analog input voltage and the reference voltage “Vref” is stored in the A-D conversion register. The A-D conversion completion bit and A-D conversion interrupt request bit are set to “1” at the completion of A-D conversion. (2)A-D Control Register (ADCON) The A-D control register controls A-D conversion. Bits 1 and 0 of this register select analog input pins. When these pins are not used as anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D conversion completion bit, A-D conversion is started by writing “0” to this bit. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A-D conversion is completed. Bit 4 controls connection between the resistor ladder and VCC. When not using the A-D converter, the resistor ladder can be cut off from the internal VCC by setting this bit to “0.” This can realize the lowpower dissipation. 7 0 0 A-D control register (ADCON: address 00EF16) Analog input pin selection bits b1 b0 0 0 : P26/AD1 0 1 : P25/AD2 1 0 : P24/AD3 1 1 : P40/AD4 A-D conversion completion bit 0 : Conversion in purogress 1 : Conversion completed (3)Comparison Voltage Generator (Resistor Ladder) VCC connection selection bit 0 : OFF 1 : ON Fix this bit to “0.” The voltage generator divides the voltage between VSS and VCC by 256, and outputs the divided voltages to the comparator as the reference voltage Vref. (4)Channel Selector The channel selector connects an analog input pin selected by bits 1 and 0 of the A-D control register to the comparator. Fig. 18. Structure of A-D control register Data bus b7 b0 A-D control register (address 00EF 16) 2 P26/AD1 P25/AD2 P24/AD3 P40/AD4 Channel selector A-D control circuit Comparator A-D conversion register 8 (address 00EE16) Switch tree Resistor ladder VSS VCC Fig. 19. A-D comparator block diagram 26 A-D conversion interrupt request MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (6) Conversion Method (7) Internal Operation 1Set bit 7 of the interrupt interval determination control register (address 021216) to “1” to generate an interrupt request at completion of A-D conversion. 2Set the A-D conversion · INT3 interrupt request bit to “0” (even when A-D conversion is started, the A-D conversion · INT3 interrupt bit is not set to “0” automatically). 3When using A-D conversion interrupt, enable interrupts by setting A-D conversion · INT3 interrupt request bit to “1” and setting the interrupt disable flag to “0.” 4Set the VCC connection selection bit to “1” to connect VCC to the resistor ladder. 5Select analog input pins by setting the analog input selection bit of the A-D control register. 6Set the A-D conversion completion bit to “0.” This write operation starts the A-D conversion. Do not read the A-D conversion register during the A-D conversion. 7Verify the completion of the conversion by the state (“1”) of the A-D conversion completion bit, that (“1”) of A-D conversion · INT3 interrupt bit, or the occurrence of an A-D conversion interrupt. 8Read the A-D conversion register to obtain the conversion results. At the time when the A-D conversion starts, the following operations are automatically performed. 1The A-D conversion register is set to “0016.” 2The most significant bit of the A-D conversion register becomes “1, ” and the comparison voltage “Vref” is input to the comparator. At this point, Vref is compared with the analog input voltage “VIN .” 3Bit 7 is determined by the comparison result as follows. When Vref < VIN : bit 7 holds “1” When Vref > VIN : bit 7 becomes “0” With the above operations, the analog value is converted into a digital value. The A-D conversion terminates in a maximum 50 machine cycles (12.5 µs at f(XIN) = 8 MHz) after it starts, and the conversion result is stored in the A-D conversion register. An A-D conversion interrupt request occurs at the same time of A-D conversion completion, the A-D conversion · INT3 interrupt request bit becomes “1.” The A-D conversion completion bit also becomes “1.” Note : When the ladder resistor is disconnect from VCC, set the VCC connection selection bit to “0” between steps 7and 8. Table 2. Expression for Vref and VREF A-D conversion register contents “n” (decimal notation) Vref (V) 0 0 1 to 255 VREF ✕ (n – 0.5) 256 Note: VREF indicates the voltage of internal VCC. Contents of A-D conversion register Reference voltage (V ref) [V] A-D conversion start 0 0 0 0 0 0 0 0 0 1st comparison start 1 0 0 0 0 0 0 0 2nd comparison start 1 1 0 0 0 0 0 0 3rd comparison start 1 2 1 0 0 0 0 0 VREF – VREF 2 512 VREF VREF VREF ± – 2 4 512 VREF ± VREF ± VREF VREF – 2 4 8 512 8th comparison start 1 2 3 4 5 6 7 1 A-D conversion completion 1 2 3 4 5 6 7 8 (8th comparison completion) VREF ± VREF ± VREF ± ..... 2 4 8 ....... ± VREF – VREF 512 256 Digital value corresponding to analog input voltage. m : Value determined by mth (m = 1 to 8) result Fig. 20. Changes in A-D conversion register and comparison voltage during A-D conversion 27 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (8) Definition of A-D Conversion Accuracy · Differential non-linearity error The deviation of the input voltage required to change output data by “1,” from the corresponding ideal A-D conversion characteristics between 0 and VREF. The definition of A-D conversion accuracy is described below. 1Relative accuracy · Zero transition error (V0T) The deviation of the input voltage at which A-D conversion output data changes from “0” to “1,” from the corresponding ideal A-D conversion characteristics between 0 and VREF. V0T = Differential non-linearity error = [LSB] · Full-scale transition error (VFST) The deviation of the input voltage at which A-D conversion output data changes from “255” to “254,” from the corresponding ideal AD conversion characteristics between 0 and VREF. VFST = 1LSB Vn – 1LSBA ✕ (n+1/2) Absolute accuracy error = [LSB] 1LSBA (VREF – 3/2 ✕ VREF/256) – V254 Note: The analog input voltage “Vn” at which A-D conversion output data changes from “n” to “n + 1” (n ; 0 to 254) is as follows (refer to Figure 18). [LSB] 1LSB · Non-linearity error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between V0 and V254. 1LSB with respect to relative accuracy = Vn – (1LSB ✕ n + V0) Non-linearity error = Output data V254 – V0 254 1LSBA with respect to absolute accuracy = 256 255 Full-scale transition error (VFST) 254 3 LSBA 2 Differential nonlinearity error 1LSB n+1 n Actual A-D conversion characteristics Non-linearity error Absolute accuracy 1LSB A 1 LSB A 2 Ideal A-D conversion characteristics between V 0 and V254 1LSB 0 V0 V1 Vn Vn+1 Zero transition error (V 0T) Fig. 21. Definition of A-D conversion precision [V] VREF [LSB] 1LSB 28 [LSB] 2Absolute accuracy · Absolute accuracy error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between 0 and VREF. (V0 –1/2 ✕ VREF/256) 1LSB (Vn+1 – Vn) – 1LSB V254 VREF Analog input voltage (V) [V] MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER DATA SLICER When the data slicer function is not used, the data slicer circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00EA16) to “0.” Also, the timing signal generating circuit can be cut off by setting bit 0 of data slicer control register 2 (address 00EB16) to “0.” These settings can realize the low-power dissipation. The M37271MF-XXXSP includes the data slicer function for the closed caption decoder (referred to as the CCD). This function takes out the caption data superimposed in the vertical blanking interval of a composite video signal. A composite video signal which makes the sync chip’s polarity negative is input to the CVIN pin. Composite video signal 0.1µF 1 kΩ 470Ω 560 pF Hundred of kiloohms to 1 MΩ 1µF 15 kΩ Sync pulse counter register (address 020F 16) 200 pF HLF HSYNC CV IN RVCO Synchronizing signal counter Clamping circuit Low-pass filter Sync slice circuit Data slicer control register 2 (address 00EB 16) 0 0 0 Synchronizing separation circuit Timing signal generating circuit VHOLD Reference voltage generating 1000 pF circuit + Clock run-in determination circuit – Comparator Data slice line specification circuit Data slicer control register 3 (address 0210 16) Clock run-in detect register 3 (address 0208 16) Clock run-in register 3 (address 0209 16) External circuit Start bit detecting circuit Data clock generating circuit 16-bit shift register Note: Make the length of wiring which is connected to V HOLD , HLF, RVCO and CVIN pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin. high-order 0 0 0 0 1 0 1 Data slicer control register 1 (address 00EA 16) 0 0 0 Data slicer ON/OFF Window register (address 00E2 16) 0 0 0 1 0 1 Clock run-in register 1 (address 00E6 16) 1 0 0 Caption position register (address 00E0 16) Start bit position register (address 00E1 16) Clock run-in detect register 1 (address 00E8 16) low-order Clock run-in detect register 2 (address 00E9 16) Data register 2 (address 00E5 16) Sync slice register 3 (address 00E3 16) Clock run-in register 2 (address 00E7 16) 1 0 0 1 1 1 Data register 4 (address 00ED 16) Data register 1 (address 00E4 16) Interrupt request generating circuit Data slicer interrupt request Data register 3 (address 00EC 16) Data bus Fig. 22. Data slicer block diagram 29 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Figure 23 shows the structure of the data slicer control registers. 7 0 0 0 7 Data slicer control register 1 (DSC1: address 00EA 16) 0 0 0 0 Data slicer control register 2 (DSC2: address 00EB 16) 0 Data slicer control bit 0: Data slicer stopped 1: Data slicer operating Timing signal generating circuit control bit 0: Stopped 1: Operating Field to be sliced data selection bit b2 0 0 1 1 b1 0 1 0 1 Field of main data slice line Field for setting reference voltage F2 F1 F1 and F2 F1 and F2 F2 F1 F2 F1 Reference clock source selection bit 0: Video signal 1: HSYNC signal Test bit: read-only Fix these bits to “0.” Fix these bits to “0.” Field determination flag 0 : Hsep V-pulse shape determination flag 0: Match 1: Mismatch Vsep 1 : Hsep Fix this bit to “0.” Vsep Test bit: read-only Fix this bit to “0.” Data latch completion flag for caption data in main data slice line 7 0 Data slicer control register 3 (DSC3: address 0210 16) 0: Data is not yet latched 1: Data is latched Definition of fields 1 (F1) and 2 (F2) F1 : Line selection bit for slice voltage 0: Main data slice line 1: Sub-data slice line Hsep VSYNC Field to be sliced data selection bit Vsep F2 : Hsep VSYNC Vsep b2 0 0 1 1 b1 0 1 0 1 Field of sub-data Field for setting slice line reference voltage F2 F1 F1 and F2 F1 and F2 F2 F1 F2 F1 Setting bit of sub-data slice line Fig. 23. Structure of data slicer control registers 30 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (1) Clamping Circuit and Low-pass Filter This filter attenuates the noise of the composite video signal input from the CVIN pin. The CVIN pin to which composite video signal is input requires a capacitor (0.1 µF) coupling outside. Pull down the CVIN pin with a resistor of hundreds of kiloohms to 1 M . In addition, we recommend to install externally a simple low-pass filter using a resistor and a capacitor at the CVIN pin (refer to Figure 22). 7 0 0 0 1 0 1 Sync slice register (SSL : address 00E316) Vertical synchronizing signal (Vsep) generating method selection bit 0 : Method 1 1 : Method 2 This circuit takes out a composite sync signal from the output signal of the low-pass filter. Figure 24 shows the structure of the sync slice register. This circuit separates a horizontal synchronizing signal and a vertical synchronizing signal from the composite sync signal taken out in the sync slice circuit. 1Horizontal synchronizing signal (Hsep) A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync signal. 2 Vertical synchronizing signal (Vsep) As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit 7 of the sync slice register (address 00E316). •Method 1 The “L” level width of the composite sync signal is measured. If this width exceeds a certain time, a Vsep signal is generated in synchronization with the rising of the timing signal immediately after this “L” level. •Method 2 The “L” level width of the composite sync signal is measured. If this width exceeds a certain time, it is detected whether a falling of the composite sync signal exits or not in the “L” level period of the timing signal immediately after this “L” level. If a falling exists, a Vsep signal is generated in synchronization with the rising of the timing signal (refer to Figure 25). Figure 25 shows a Vsep generating timing. The timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the composite sync signal. As shown in Figure 26, when the A level matches the B level, this bit is “0.” In the case of a mismatch, the bit is “1.” For the pins RVCO and the HLF, connect a resistor and a capacitor as shown in Figure 22. Make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be generated. 0 Fix these bits to “00001012” (2) Sync Slice Circuit (3) Synchronizing Signal Separation Circuit 0 Fig. 24. Structure of sync slice register Composite sync signal Measure “L” period Timing signal Vsep signal A Vsep signal is generated at a rising of the timing signal immediately after the “L” level width of the composite sync signal exceeds a certain time. Fig. 25. Vsep generating timing (method 2) Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. In this period, various timing signals, Hsep signals and Vsep signals become unstable. For this reason, take stabilization time into consideration when programming. 31 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (4) Timing Signal Generating Circuit This circuit generates a reference clock which is 832 times as large as the horizontal synchronizing signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronizing signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer control register 2 (address 00EB16) to “1.” The reference clock can be used as a display clock for OSD function in addition to the data slicer. The HSYNC signal can be used as a count source instead of the composite sync signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the reference clock can be selected by bit 1 of data slicer control register 2 (address 00EB16). V-pulse (“L” pulse width is long, “H” pulse width is short) 0 Composite sync signal 1 1 A Fig. 26. Determination of V-pulse waveform 32 Bit 5 of DSC2 B MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (5) Data Slice Line Specification Circuit 2 Selection of field to be sliced data In the case of the main data slice line, the field to be sliced data is selected by bits 2 and 1 of the data slicer control register 1 (address 00EA16). In the case of the sub-data slice line, the field is selected by bits 2 and 1 of the data slicer control register 3. When bit 2 of the data slicer control register 1 is set to “1,” it is possible to slice data of both fields (refer to Figure 23). 3 Specification of line to set slice voltage The reference voltage for slicing (slice voltage) is generated by integrating the amplitude of the clock run-in pulse in the particular line (refer to Table 3). 4 Field determination The field determination flag can be read out by bit 5 of the data slicer control register 1. This flag charge at the falling edge of Vsep. 1 Specification of data slice line M37271MF-XXXSP has 2 data slice line specification circuits for slicing arbitrary 2 Hsep in 1 field. The following 2 data slice lines are specified . <Main data slice line> This line is specified by the caption position register (address 00E016). <Sub-data slice line> This line is specified by the data slicer control register 3 (address 00EB16). The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the counter value matched the value specified by bits 4 to 0 of the caption position register (in case of the sub-data slice line, by bits 3 to 7 of the data slicer control register 3), this Hsep is sliced. The values of “0016” to “1F16” can be set in the caption position register. Bit 7 to bit 5 are used for testing. Set “1002.” Figure 27 shows the signals in the vertical blanking interval. Figure 28 shows the structure of the caption position register. Table 3. Specifying of field whose sets reference voltage Bit 0 of DSC3 Field Line 0 Field specified by bit 1 of DSC1 0: F2 1: F1 Line specified by bits 4 to 0 of CP (Main data slice line) 1 Field specified by bit 1 of DSC3 0: F2 1: F1 Line specified by bits 7 to 3 of DSC3 (Sub-data slice line) DSC1 : Data slice control register 1 DSC3 : Data slice control register 3 CP : Caption position register Vertical blanking interval Video signal Composite video signal Vsep Line 21 Hsep Count value to be set in the caption position register (“1116” in this case) Magnified drawing Hsep Clock run-in Composite video signal Start bit + 16-bit data min. max. Start bit Time to be set in the start bit position register Fig. 27. Signals in vertical blanking interval 33 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (6) Reference Voltage Generating Circuit and Comparator The composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. 1Reference voltage generating circuit This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. Connect a capacitor between the VHOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage current may not be generated. 2Comparator The comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value. 7 0 Caption position register (CP : address 00E016) 1 0 0 Specification main data slice line Fix these bits to “1002” Fig. 28. Structure of caption position register (7) Start Bit Detecting Circuit This circuit detects a start bit at line decided in the data slice line specification circuit. For start bit detection, it is possible to select one of the following two types by using bit 1 of the clock run-in register 2 (address 00E716). 1After the lapse of the time corresponding to the set value of the start bit position register (address 00E116), the first rising of the composite video signal is detected as a start bit. The time is set in bits 0 to 6 of the start bit position register (address 00E116) (refer to Figure 26). Set a value fit for the following conditions. Figure 29 shows the structure of the start bit position register. 7 0 Start bit position register (SP : address 00E116) Start bit generating time Time from a falling of the horizontal synchronizing signal to occurrence of a start bit = 4 ✕ set value (“0016” to “7F16”) ✕ reference clock period DSC1 bit 7 control bit 0 : Generation of 16 pulses 1 : Generation of 16 pulses and detection of clock run-in Fig. 29. Structure of start bit position register Time from the falling of the horizontal synchronizing signal to the last rising of the clock run-in 34 < 4 ✕ set value of the start bit position register ✕ reference clock period < Time from the falling of the horizontal synchronizing signal to occurrence of the start bit MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 2After a falling of the clock run-in pulse set in bits 2 to 0 of clock runin detect register 2 (address 00E916) is detected, a start bit is detected by sampling a comparator output. A sampling clock for sampling is obtained by dividing the reference clock generated in the timing signal generating circuit by 13. Figure 31 shows the structure of clock run-in detect register 2. The contents of bits 2 to 0 of clock run-in detect register 2 and bit 1 of clock run-in register 2 are written at a falling of the horizontal synchronizing signal. For this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronizing signal. 7 0 Clock run-in detect register 2 (CRD2 : address 00E916) 7 0 1 0 0 1 1 1 1 Clock run-in pulses for sampling b2 b1 b0 0 0 0 : Not available 0 0 1 : 1st pulse 0 1 0 : 2nd pulse 0 1 1 : 3rd pulse 1 0 0 : 4th pulse 1 0 1 : 5th pulse 1 1 0 : 6th pulse 1 1 1 : 7th pulse Clock run-in register 2 (CR2 : address 00E716) Fix this bit to “1” Start bit detecting method selection bit 0 : Method 1 1 : Method 2 Data clock generating time Time from detection of a start bit to occurrence of a data clock = (13 + set value) ✕ reference clock period Fix these bits to “1001112” Fig. 30. Structure of clock run-in register 2 Fig. 31. Structure of clock run-in detect register 2 (8) Clock run-in determination circuit This circuit sets a window in the clock run-in portion in the composite video signal, and then determinates clock run-in by counting the number of pulses in this window. Set the time from a falling of the horizontal synchronizing signal to a start of the window by bits 0 to 5 of the window register (address 00E216; refer to Figure 32). The window ends according to the contents of the setting of the start bit position register (refer to Figure 29). 7 0 0 0 Window register (WN : address 00E216) Window start time Time from a falling of the horizontal synchronizing signal to a start of the window = 4 ✕ set value (“0016” to “3F16”) ✕ reference clock period Fix these bits to “0” Fig. 32. Structure of window register 35 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER For the main data slice line, the count value of pulses in the window is stored in clock run-in register 1 (address 00E6 16; refer to Figure 33). For the sub-data slice line, the count value of pulses in the window is stored in clock run-in register 3 (address 020916; refer to Figure 34). When this count value is 4 to 6, it is determined as a clock run-in. Accordingly, set the count value so that the window may start after the first pulse of the clock run-in (refer to Figure 35). The contents to be set in the window register are written at a falling of the horizontal synchronizing signal. For this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronizing signal. For the main data slice line, reference clock is counted in the period from a falling of the clock pulse set in bits 0 to 2 of the clock run-in detect register 2 (address 00E916) to the next falling. The count value is stored in bits 3 to 7 of the clock run-in detect register 1 (address 00E816) (When the count value exceeds “1F16,” “1F16” is held). For the sub-data slice line, the count value is stored in bits 3 to 7 of the clock run-in detect register 3 (address 020816). Read out these bits after the occurence of a data slicer interrupt (refer to (11) Interrupt Request Generating Circuit). Figure 36 shows the structure of clock run-in detect registers 1 and 3. 7 0 Clock run-in register 1 (CR1 : address 00E616) 0 1 0 1 Clock run-in count value of main-data slice line Fix these bits to “01012” Fig. 33. Structure of clock run-in register 1 7 0 Clock run-in register 3 (CR3 : address 0209 16) Clock run-in count value of sub-data slice line Data latch completion flag for caption data in sub-data slice line 0: Data is not latched yet 1: Data is latched Data slice line selection bit for interrupt request 0: Main data slice line 1: Sub-data slice line Interrupt mode selection bit 0: Interrupt occurs at end of data slice line 1: Interrupt occurs at completion of caption data latch Fig. 34. Structure of clock run-in register 3 Horizontal synchronizing signal Clock run-in Start bit data + 16-bit data Composite video signal Window Time to be set in the window register Time to be set in the start bit position register ✽When the count value in the window is 4 to 6, this is determined as a clock run-in. Fig. 35. Window setting 7 0 Clock run-in detect registers 1, 3 ( CRD1 : address 00E816) ( CRD3 : address 020816) Test bits : read-only Number of reference clocks to be counted in one clock run-in pulse period Fig. 36. Structure of clock run-in detect registers 1and 3 36 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (9) Data clock generating circuit This circuit generates a data clock phase-synchronized with the start bit detected in the start bit detecting circuit. Set the time from detection of the start bit to occurrence of the data clock in bits 3 to 7 of the clock run-in detect register 2 (address 00E916). The time to be set is represented by the following expression: Time = (13 + set value) ✕ reference clock period For a data clock, 16 pulses are generated. When just 16 pulses have been generated, bit 7 of the data slicer control register is set to “1” (refer to Figure 23). When method 1 is already selected as a start bit detecting method, this bit becomes a logical product (AND) value with a clock run-in determination result by setting bit 7 of the start bit position register to “1.” When method 2 is already selected as a start bit detecting method and 16 pulses are generated of a data clock regardless of bit 7 of the start bit position register, this bit is set to “1.” The contents of this bit are reset at a falling of the vertical synchronizing signal (Vsep). Table 4. Setting conditions for caption data latch completion flag Conditions for setting bit 7 of DSC1 to “1” Bit 7 of SP Conditions for setting bit 4 of DSC3 to “1” 0 Data clock of 16 pulses has occured in main data slaice line Data clock of 16 pulses has occured in sub-data slaice line 1 Data clock of 16 pulses has occured in main data slaice line Data clock of 16 pulses has occured in sub-data slaice line AND AND Clock run-in pulse are detected 4 to 6 times Clock run-in pulse are detected 4 to 6 times (10) 16-bit Shift Register (11) Interrupt Request Generating Circuit The caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. For the main data slice line, the contents of the high-order 8 bits of the stored caption data and the contents of the low-order 8 bits of the same data can be obtained by reading out the data register 2 (address 00E516) and data register 1 (address 00E416), respectively. For the sub-data slice line, the contents of the high-order 8 bits and the contents of the low-order 8 bits can be obtained by reading out the data register 4 (address 00ED16) and the data register 3 (address 00EC16), respectively. These registers are reset to “0” at a falling of Vsep. Read out data registers 1 and 2 after the occurence of a data slicer interrupt (refer to (11) Interrupt Request Generating Circuit). The occurence sources of interrupt request are selected by combination of the following bits; bits 5 and 6 of the clock run-in register 3 (address 020916), bit 1 of the clock run-in register 2 (address 00E716) (refer to Table 6). Read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect registers 1 and 3 after the occurence of a data slicer interrupt request. Table 5. Occurence sources of interrupt request CR3 b5 CR2 b6 b1 Occurence souces of interrupt request Slice line 0 0 1 Main data slice line 0 0 Data clock of 16 pulses has occured AND Clock run-in pulse are detected 4 to 6 times 1 Data clock of 16 pulses has occured 0 At end of data slice line 1 0 1 Sources At end of data slice line 1 0 1 1 Sub-data slice line Data clock of 16 pulses has occured AND Clock run-in pulse are detected 4 to 6 times Data clock of 16 pulses has occured 37 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (12) Synchronizing Signal Counter The synchronizing signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronizing signal Vsep as a count source. The count value in a certain time (T time) generated by f(XIN)/213 or f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count value exceeds “1F16,” “1F16” is stored into the latch. The latch value can be obtained by reading out the sync pulse counter register (address 020F16). A count source is selected by bit 5 of the sync pulse counter register. The synchronizing signal counter is used when bit 0 of the PWM mode register 1 (address 02EA16). Figure 37 shows the structure of the sync pulse counter and Figure 38 shows the synchronizing signal counter block diagram. 7 0 Sync pulse counter register (SYC : address 020F 16) Count value Count source 0: HSYNC signal 1: Composite sync signal Count time f(XIN)/213 (1024 µs, f(XIN) = 8 MHz) Fig. 37. Sync pulse counter register f(XIN)/213 Composite sync signal Reset HSYNC signal b5 Selection gate : connected to black colored side when reset. Fig. 38. Synchronizing signal counter block diagram 38 5-bit counter Counter Latch (5 bits) Sync pulse counter register Data bus MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Table 6. Multi-master I2C-BUS interface functions MULTI-MASTER I2C-BUS INTERFACE The multi-master I2C-BUS interface is a circuit for serial communications conformed with the Philips I2C-BUS data transfer format. This interface, having an arbitration lost detection function and a synchronous function, is useful for serial communications of the multi-master. Figure 39 shows a block diagram of the multi-master I2C-BUS interface and Table 6 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. Function Item Format In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode Communication mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception SCL clock frequency 16.1 kHz to 400 kHz (at φ = 4 MHz) φ : System clock = f(XIN)/2 Note: We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00F916) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2). I 2 C address register b7 b0 Interrupt generating circuit SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW S0D Interrupt request signal (IICIRQ) Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 b0 I 2 C data shift register b7 S0 b0 AL AAS AD0 LRB MST TRX BB PIN S1 AL circuit I 2 C status register Internal data bus BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 S2 I 2 C clock control register Clock division b7 BSEL1 BSEL0 b0 10BIT SAD ALS ES0 BC2 BC1 BC0 S1D I2 C clock control register System clock (φ) Bit counter Fig. 39. Block diagram of multi-master I2C-BUS interface 39 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (1) I2C Data Shift Register The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ES0 bit of the I2C control register (address 00F916) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 00F816) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. (2) I2C Address Register The I2C address register (address 00F716) consists of a 7-bit slave ___ address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. ____ ■ Bit 0: Read/write bit (RBW) Not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. ■ Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. 7 0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW I2 C address register (S0D: address 00F716) Read/write bit Slave address Fig. 40. Structure of I2C address register (3) I2C Clock Control Register The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency. ■ Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 7. ■ Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. ■ Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK return mode is set and make SDA “L” at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the “H” status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made “H”(ACK is not returned). ✽ACK clock: Clock for acknowledgement ■ Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA “H”) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transmitting. If data is written during transmitting, the I2C clock generator is reset, so that data cannot be transmitted normally. 40 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (4) I2C Control Register 7 ACK 0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE I2C clock control register (S2 : address 00FA16) SCL frequency control bits Refer to Table 7. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock Table 7. Set values of I2C clock control register and SCL frequency SCL frequency Setting value of (at φ = 4MHz, unit : kHz) CCR4–CCR0 Standard clock High-speed clock CCR4 CCR3 CCR2 CCR1 CCR0 mode mode 0 0 0 0 0 Setting disabled Setting disabled 0 0 0 0 1 Setting disabled Setting disabled 0 0 0 1 0 Setting disabled Setting disabled 0 0 0 1 1 Setting disabled 333 0 0 1 0 0 Setting disabled 250 0 0 1 0 1 100 0 0 1 1 0 400(Note) … … … … … 166 1 1 1 0 1 17.2 34.5 1 1 1 1 0 16.6 33.3 1 1 1 1 1 16.1 32.3 500/CCR value • • Fig. 41. Structure of I2C clock control register 83.3 The I2C control register (address 00F916) controls data communication format. ■ Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits. ■ Bit 3: I2C interface use enable bit (ES0) This bit enables to use the multimaster I2C BUS interface. When this bit is set to “0,” the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ES0 = “0,” the following is performed. PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register at address 00F816 ). Writing data to the I2C data shift register (address 00F616) is disabled. ■ Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “(5) I2C Status Register,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recognized. ■ Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00F716) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. ■ Bits 6 and 7: Connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 42). 1000/CCR value Note: At 400 kHz in the high-speed clock mode, the duty is 40%. In the other cases, the duty is 50%. 41 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER “0” “1” BSEL0 7 SCL1/P11 SCL Multi-master I2C-BUS interface SDA “0” “1” BSEL1 SCL2/P12 “0” “1” BSEL0 SDA1/P13 “0” “1” BSEL1 SDA2/P14 Note: When using multi-master I2C-BUS interface, set bits 3 and 4 of the serial I/O mode register (address 021316) to “1.” Fig. 42. Connection port control by BSEL0 and BSEL1 (5) I2C Status Register I2C I2C-BUS The status register (address 00F816) controls the interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. ■ Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00F616). ■ Bit 1: General call detecting flag (AD0) This bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition. ✽General call: The master transmits the general call address “0016” to all slaves. ■ Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data. 1In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions. The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I2C address register (address 00F716). A general call is received. 2In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition. When the address data is compared with the I 2C address register (8 bits consisted of slave address and RBW), the first bytes agree. 3The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00F616). • • • 42 BSEL1 BSEL0 10 BIT ALS SAD 0 ES0 BC2 BC1 BC0 I2C control register (S1D : address 00F916) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 I2C-BUS interface use enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format Connection control bits between I2C-BUS interface and ports b7 b6 Connection port 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1, SCL2, SDA2 Fig. 43. Structure of I2C control register MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ■ Bit 3: Arbitration lost✽ detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” In the case arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. ✽Arbitration lost: The status in which communication as a master is disabled. ■ Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 45 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions. Executing a write instruction to the I2C data shift register (address 00F616). When the ES0 bit is “0” At reset The conditions in which the PIN bit is set to “0” are shown below: Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) Immediately after completion of 1-byte data reception In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception In the slave reception mode, with ALS = “1” and immediately after completion of address data reception ■ Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ES0 bit of the I2C control register (address 00F9 16) is “0” and at reset, the BB flag is kept in the “0” state. ■ Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00F916) is “0” in the slave reception mode is selected, the TRX bit is set to “1” __ (transmit) if the least significant bit (R/W bit) of the address data trans- • • • • • • __ mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions. When arbitration lost is detected. When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication preventing function (Note). With MST = “0” and when a START condition is detected. With MST = “0” and when ACK non-return is detected. At reset ■ Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to “0” in one of the following conditions. Immediately after completion of 1-byte data transmission when arbitration lost is detected When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication preventing function (Note). At reset • • • • • • • • • • Note: The START condition duplication prevention function disables the occurence of a START condition, reset of bit counter and SCL output when the following condition is satisfied: • a START condition is set by another master device. • 43 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (6) START Condition Generating Method 7 0 I2C status register MST TRX BB PIN AL AAS AD0 LRB (S1 : address 00F816) Last receive bit (Note) 0 : Last bit = “0” 1 : Last bit = “1” General call detecting flag (Note) 0 : No general call detected 1 : General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected I2C-BUS interface interrupt request bit 0 : Interrupt request issued 1 : No interrupt request issued Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode When the ES0 bit of the I2C control register (address 00F916) is “1,” execute a write instruction to the I2C status register (address 00F816) for setting the MST, TRX and BB bits to “1.” Then a START condition occurs. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 46, the START condition generating timing diagram, and Table 8, the START condition/STOP condition generating timing table. I2C status register write signal SCL SDA AAA Setup time Set time for BB flag BB flag Setup time Fig. 46. START condition generating timing diagram (7) STOP Condition Generating Method When the ES0 bit of the I2C control register (address 00F916) is “1,” execute a write instruction to the I2C status register (address 00F816) for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. Then a STOP condition occurs. The STOP condition generating timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 47, the STOP condition generating timing diagram, and Table 8, the START condition/STOP condition generating timing table. Note: These bit and flags can be read out but cannot be written. Fig. 44. Structure of I2C status register I2C status register write signal SCL SDA BB flag SCL PIN IICIRQ Fig. 45. Interrupt request signal generating timing Hold time Setup time AAA AAA Hold time Reset time for BB flag Fig. 47. STOP condition generating timing diagram Table 8. START condition/STOP condition generating timing table Item Standard clock mode High-speed clock mode Setup time 5.0 µs (20 cycles) 2.5 µs (10 cycles) Hold time 5.0 µs (20 cycles) 2.5 µs (10 cycles) Set/reset time 3.0 µs (12 cycles) 1.5 µs (6 cycles) for BB flag Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. 44 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (9) Address Data Communication (8) START/STOP Condition Detecting Conditions There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. 1 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00F716) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 49, (1) and (2). 210-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, an address comparison between the RBW bit of the I2C address regis__ ter (address 00F716) and the R/W bit which is the last bit of the address data transmitted__from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. The START/STOP condition detecting conditions are shown in Figure 48 and Table 9. Only when the 3 conditions of Table 9 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” occurs to the CPU. AAA AAA AAA SCL release time SCL Setup time SDA (START condition) Setup time SDA (STOP condition) Hold time Hold time Fig. 48. START condition/STOP condition detecting timing diagram Table 9. START condition/STOP condition detecting conditions High-speed clock mode Standard clock mode 1.0 µs (4 cycles) < SCL 6.5 µs (26 cycles) < SCL release time release time 3.25 µs (13 cycles) < Setup time 0.5 µs (2 cycles) < Setup time 3.25 µs (13 cycles) < Hold time 0.5 µs (2 cycles) < Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. S Slave address R/W A Data A Data A/A P A P Data A 7 bits “0” 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W A Data A Data 7 bits “1” 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter S Slave address R/W 1st 7 bits A Slave address 2nd byte A Data A/A P 7 bits “0” 8 bits 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address S Slave address R/W 1st 7 bits A Slave address 2nd byte A Sr Slave address R/W 1st 7 bits Data 7 bits “0” 8 bits 7 bits “1” 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit A A Data A P 1 to 8 bits From master to slave From slave to master Fig. 49. Address data communication format 45 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00F616), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2 bytes matches the slave address, set the RBW bit of the I2C address register (address 00F716) to “1” by software. This pro__ cessing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 49, (3) and (4). (10) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. 1 Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and “0” in the RBW bit. 2 Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00FA16). 3 Set “1016” in the I2C status register (address 00F816) and hold the SCL at the “H” level. 4 Set a communication enable status by setting “4816” in the I2C control register (address 00F916). 5 Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00F616) and set “0” in the least significant bit. 6 Set “F016” in the I2C status register (address 00F816) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. 7 Set transmit data in the I2C data shift register (address 00F616). At this time, an SCL and an ACK clock automatically occurs. 8 When transmitting control data of more than 1 byte, repeat step 7. 9 Set “D016” in the I2C status register (address 00F816). After this, if ACK is not returned or transmission ends, a STOP condition occurs. (11) Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. 1 Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and “0” in the RBW bit. 2 Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00FA16). 3 Set “1016” in the I2C status register (address 00F816) and hold the SCL at the “H” level. 4 Set a communication enable status by setting “4816” in the I2C control register (address 00F916). 5 When a START condition is received, an address comparison is made. 46 6 •When all transmitted addresses are “0” (general call) AD0 of the I2C status register (address 00F816) is set to “1” and an interrupt request signal occurs. •When the transmitted addresses match the address set in 1 ASS of the I2C status register (address 00F816) is set to “1” and an interrupt request signal occurs. •In the cases other than the above AD0 and AAS of the I2C status register (address 00F816) are set to “0” and no interrupt request signal occurs. 7 Set dummy data in the I2C data shift register (address 00F616). 8 When receiving control data of more than 1 byte, repeat step 7. 9 When a STOP condition is detected, the communication ends. MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER OSD FUNCTIONS Table 10 outlines the OSD functions of the M37271MF-XXXSP. The M37271MF-XXXSP incorporates an OSD control circuit of 40 characters ✕ 16 lines. OSD is controlled by the OSD control register. There are 3 display modes and they are selected by a block unit. The display modes are selected by the block control register i (i = 1 to 6). The features of each mode are described below. Table 10. Features of each display mode Parameter Number of display characters Dot structure Kinds of characters Kinds of character sizes Pre-divide ratio (Note) Dot size CC mode (Closed caption mode) 40 characters ✕ 16 lines Display mode OSD mode (On-screen display mode) 40 characters ✕ 16 lines EXOSD mode (Extra on-screen display mode) 40 characters ✕ 16 lines 16 ✕ 26 dots 16 ✕ 20 dots 16 ✕ 26 dots (Character : 20 ✕ 16 dots) 320 kinds (In EXOSD mode, they can be combined with 32 kinds of extra fonts) 14 kinds 2 kinds 6 kinds ✕ 1, ✕ 2 ✕ 1, ✕ 2, ✕ 3 ✕ 1, ✕ 2, ✕ 3 1TC ✕ 1/2H 1TC ✕ 1/2H, 1TC ✕ 1H, 1.5TC ✕ 1/2H, 1.5TC ✕ 1H, 2TC ✕ 2H, 3TC ✕ 3H Border 1 screen : 7 kinds, Max. 15 kinds (a character unit) 1TC ✕ 1/2H, 1TC ✕ 1H Attribute Character font coloring Smooth italic, under line, flash 1 screen : 7 kinds, Max. 7 kinds (a character unit) Raster coloring Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) Character background coloring Possible (a character unit, 1 screen Possible (a character unit, 1 screen Possible (a character unit, 1 screen : : 7 kinds, max. 7 kinds) : 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) Border coloring Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) Extra font coloring OSD output Function Border, extra font (32 kinds) 1 screen : 7 kinds, Max. 7 kinds (a character unit) Possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) R, G, B, OUT1, OUT2 Auto solid space function Window function Dual layer OSD function (layer 1) Possible R, G, B, I1, OUT1, OUT2 Dual layer OSD function (layer 2) R, G, B, I1, I2, OUT1, OUT2 Display expansion Possible Possible (multiline display) Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter. 2: The character size is specified with dot size and pre-divide ratio (refer to (3) Dote size). 47 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER The OSD circuit has an extended display mode. This mode allows multiple lines (16 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 50 shows the configuration of OSD character. Figure 51 shows the block diagram of the OSD control circuit. Figure 52 shows the structure of the OSD control register. Figure 53 shows the structure of the block control register. CC mode OSD mode 16 dots 16 dots 20 dots 26 dots 20 dots Blank area+ Underline area+ Blank area+ + : Displayed only in CCD mode. EXOSD mode 16 dots 16 dots 26 dots 26 dots 20 dots 16 dots logical sum (OR) Character font Extra font Fig. 50. Configuration of OSD character 48 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Clock for OSD OSC1 OSC2 Data slicer clock HSYNC VSYNC Display oscillation circuit Control registers for OSD OSD Control circuit OSD control register Horizontal position register Block control registers Clock source control register I/O polarity control register Raster color register Extra font color register Border color register Window H/L registers Vertical registers RAM for OSD 20-bit ✕ 40 ✕16 (address 00CE 16) (address 00CF 16) (addresses 00D0 16 to 00DF16) (address 0216 16) (address 0217 16) (address 0218 16) (address 0219 16) (address 021B 16) (addresses 021C 16 to 021F 16) (addresses 0220 16 to 023F16) RAM for OSD (16-bit✕20✕320) + 16-bit✕26✕32) Shift register 1 16-bit Output circuit Shift register 2 16-bit R G B I1 I2 OUT1 OUT2 Data bus Fig. 51. Block diagram of OSD control circuit 49 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 7 7 0 Block control register i (i = 1 to 16) (BCi : addresses 00D0 16 to 00DF) 0 OSD control register (OC : address 00CE16) Display mode selection bits b1 b0 OSD control bit (Note 1) 0 : All-blocks display off 1 : All-blocks display on 0 0 1 1 Scan mode selection bit 0 : Normal scan mode 1 : Bi-scan mode 0 : Display OFF 1 : OSD mode 0 : CC mode 1 : EXOSD mode Border control bit 0 : Border OFF 1 : Border ON Border type selection bit 0 : All bordered 1 : Shadow bordered (Note 2) Dot size selection bit Refer to Table 11. Flash mode selection bit 0 : Color signal of character background part does not flash 1 : Color signal of character background part flashes Automatic solid space control bit 0 : OFF 1 : ON Pre-divide ratio Elayer selection bits Refer to Table 11. OUT 2 output control bit (Note) 0 : OUT2 output OFF 1 : OUT2 output ON Notes : Bit 4 of the color code 1 controls OUT1 output when bit 7 is “0.” Bit 4 of the color code 1 controls OUT2 output when bit 7 is “1.” Window control bit 0 : OFF 1 : ON Layer mixing control bits (Note 3) b7 b6 0 0 : Logical sum (OR) of layer 1’s color and layer 2’s color 0 1 : Layer 1’s color has priority 1 0 : Layer 2’s color has priority 1 1 : Do not set Fig. 53. Structure of block control registers Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC. 2 : Shadow border is output at right and bottom side of the font. 3 : Set “00” during displaying extra fonts. Table 11. Setting value of block control registers Fig. 52. Structure of OSD control register b6 b5 b4 b3 CS6 0 0 1 1 1 0 1 0 1 1 Pre-divide ratio Dot size Display layer 1TC ✕ 1/2H 0 0 0 1 1 0 1 1 3TC ✕ 3H 0 0 1TC ✕ 1/2H 0 1 1 0 1 1 3TC ✕ 3H 0 0 1TC ✕ 1/2H 0 1 1 0 1 1 — 0 — 1 0 0 1TC ✕ 1/2H 0 1 1TC ✕ 1H 1 0 1 1 — — — ✕1 ✕2 ✕3 1TC ✕ 1H 2TC ✕ 2H 1TC ✕ 1H Layer 1 2TC ✕ 2H 1TC ✕ 1H 2TC ✕ 2H 3TC ✕ 3H 0 1 ✕1 ✕2 1TC ✕ 1/2H 1TC ✕ 1H Layer 2 1.5TC ✕ 1/2H 1.5TC ✕ 1H Notes 1: CS6 : Bit 6 of clock control register (Address 021616) 2: TC : OSD clock cycle divided in the pre-divide circuit 3: H : HSYNC 50 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (1) Dual Layer OSD M37271MF-XXXSP has 2 layers; layer 1 and layer 2. These layers display the OSD for controlling TV and the closed caption display at the same time and overlayed on each other. Each block can be assigned to either layer by bits 6 and 5 of the block control register (refer to Figure 53). For example, only when both bits 5 and 6 are “1,” the block is assigned to layer 2. Other bit combinations assign the block to layer 1. When a block of layer 1 is overlapped with that of layer 2, a screen is combined (refer to Figure 55) by bits 7 and 6 of the OSD control register (refer to Figure 52). Layer 2 Block 13 Block 14 Block 15 Block 16 Block 1 Block 2 Block ... Note: When using the dual layer OSD, note Table 12. Block 11 Block 12 Block Layer 1 Fig. 54. Image of dual layer OSD Table 12. Conditions of dual layer Block Block in layer 1 Parameter Block in layer 2 Display mode CC mode OSD mode OSD Clock source Data slicer clock or OSC1 Same as layer 1 Pre-divide ratio ✕ 1 or ✕ 2 (all blocks) 1TC ✕ 1/2H Dot size Horizontal display start position Same as layer 1 (Note) Pre-divide ratio = 1 Pre-divide ratio = 2 1TC ✕ 1/2H 1TC ✕ 1/2H, 1.5TC ✕ 1/2H 1TC ✕ 1H 1TC ✕ 1H, 1.5TC ✕ 1H Same position as layer 1 Arbitrary Note: For the pre-divide ratio of the layer 2, select the same as the layer 1’s ratio by bit 6 of the clock control register. Display example of layer 1 = “HELLO,” layer 2 = “CH5” CH5 HELLO Logical sum (OR) of layer 1’s color and layer 2’s color Bit 7 = “0,” bit 6 = “0” CH5 HELLO Layer 1’s color has priority Bit 7 = “0”, bit 6 = “1” CH5 HELLO Layer 2’s color has priority Bit 7 = “1,” bit 6 = “0” Fig. 55. Display example of dual layer OSD 51 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (2) Display Position The display positions of characters are specified in units called a “block.” There are 16 blocks, blocks 1 to 16. Up to 40 characters can be displayed in each block (refer to (6) Memory for OSD). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 256-step display positions in units of 4 TOSC (TOSC = oscillating cycle for OSD). The display position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 TH ( TH = HSYNC cycle). Blocks are displayed in conformance with the following rules: 1 When the display position is overlapped with another block (Figure 56, (b)), a lower block number (1 to 16) is displayed on the front. 2 When another block display position appears while one block is displayed (Figure 56 (c)), the block with a larger set value as the vertical display start position is displayed. However, do not display block with the dot size of 2TC ✕ 2H or 3TC ✕ 3H during display period (✽) of another block. ✽ In the case of OSD mode block: 20 dots in vertical from the vertical display start position. ✽ In the case of CCD or EXOSD mode block: 26 dots in vertical from the vertical display start position. (HR) VP11, VP21 Block 1 VP12, VP22 Block 2 VP13, VP23 Block 3 (a) Example when each block is separated (HR) VP11, VP21 VP12, VP22 Block 1 (Block 3 is not displayed) (b) Example when block 3 overlaps with block 1 (HR) VP11, VP21 VP12, VP22 Block 1 Block 3 (c) Example when block 3 overlaps in process of block 1 Note: VP1i or VP2i (i : 1 to 6) indicates the contents of vertical position registers 1i or 2i. Fig. 56. Display position 52 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, it starts to count the rising edge (falling edge) of HSYNC signal from after about 1 machine cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the I/O polarity control register (address 021716). For details, refer to (15) OSD Output Pin Control. Note: When bits 0 and 1 of the I/O polarity control register (address 021716) are set to “1” (negative polarity), the vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer (refer to Figure 57). 7 0 Vertical position register 1i (i = 1 to 16) (VP1i : addresses 0220 16 to 022F16) Control bits of vertical display start positions (Note) Vertical display start positions (low-order 8 bits) TH✕(setting value of low-order 2 bits of VP2i ✕16 2 +setting value of low-order 4 bits of VP1i ✕16 1 +setting value of low-order 4 bits of VP1i ✕16 0 ) 7 0 Vertical position register 2i (i = 1 to 16) (VP2i : addresses 0230 16 to 023F16) Control bits of vertical display start positions (Note) Vertical display start positions (high-order 2 bits) TH✕(setting value of low-order 2 bits of VP2i ✕162 +setting value of low-order 4 bits of VP1i ✕161 +setting value of low-order 4 bits of VP1i ✕16 0 ) 0.25 to 0.50 [µs] ( at f(XIN) = 8MHz) VSYNC signal input Note : Set values except “00 16” and “01 16” to VP1i when VP2i is “00 16.” VSYNC control signal in microcomputer Period of counting HSYNC signal Fig. 58. Structure of vertical position registers (Note 1) HSYNC signal input 1 2 3 4 5 Not count When bits 0 and 1 of the I/O polarity control register (address 0217 16) are set to “1” (negative polarity) The horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4TC, TC being the oscillating cycle for display) as values “0016” to “FF16” in bits 0 to 7 of the horizontal position register (address 00CF16). The structure of the horizontal position register is shown in Figure 59. Notes 1 : Do not generate falling edge of H SYNC signal near rising edge of V SYNC control signal in microcomputer to avoid jitter. 2 : The pulse width of V SYNC and HSYNC needs 8 machine cycles or more. 7 0 Horizontal position register (HP : address 00CF 16) Fig. 57. Supplement explanation for display position Control bits of horizontal display start positions The vertical position for each block can be set in 1024 steps (where each step is 1TH (TH: HSYNC cycle)) as values “0016” to “FF16” in vertical position register 1i (i = 1 to 16) (addresses 022016 to 022F16) and values “0016” to “FF16” in the vertical position register 2i (i = 1 to 16) (addresses 023016 to 023F16). The structure of the vertical position registers is shown in Figure 58. Horizontal display start positions 4TOSC✕(setting value of high-order 4 bits ✕161 +setting value of low-order 4 bits✕160 ) Note : The setting value synchronizes with a rising (falling) of the V SYNC. Fig. 59. Structure of horizontal position register 53 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Notes 1 : 1TC (TC : OSD clock cycle divided by prescaler) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different predivide ratios, their horizontal display start position will not match. 2 : The horizontal start position is based on the OSD clock source cycle selected for each block. Accordingly, when 2 blocks have different OSD clock source cycles, their horizontal display start position will not match. HSYNC 1TC Note 1 Block 1 (Pre-divide ratio = 1, clock source = data slicer clock) 1TC 4TOSC✕N Block 2 (Pre-divide ratio = 2, clock source = data slicer clock) 1TC Block 3 (Pre-divide ratio = 3, clock source = data slicer clock) Note 2 4TOSC’✕N 1TC Block 4 (Pre-divide ratio = 3, clock source = OSC1) Fig. 60. Notes on horizontal display start position (3) Dot Size The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1TC. The dot size of the layer 1 is specified by bits 6 to 3 of the block control register. The dot size of the layer 2 is specified by the following bits : bits 3 and 4 of the block control register, bit 6 of the clock source control register. Refer to Figure 53 (the structure of the block control regis- ter), refer to Figure 62 (the structure of the clock source control register). The block diagram of dot size control circuit is shown in Figure 61. Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode. 2 : The pre-divide ratio of the OSD mode block on the layer 2 must be same as that of the CC mode block on the layer 1 by bit 6 of the clock source control register. 3 : In the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal mode. Refer to “(13) Scan Mode” about the scan mode. OSC1 Synchronization circuit Data slicer clock CS0 Clock cycle = 1TC Cycle✕2 Horizontal dot size control circuit Cycle ✕3 Pre-divide circuit HSYNC Vertical dot size control circuit OSD control circuit Fig. 61. Block diagram of dot size control circuit 54 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (4) Clock for OSD As a clock for display to be used for OSD, it is possible to select one of the following 3 types. Data slicer clock output from the data slicer (approximately 26 MHz) Clock from the LC oscillator supplied from the pins OSC1 and OSC2 Clock from the ceramic resonator or the quartz-crystal oscillator from the pins OSC1 and OSC2 This OSD clock for each block can be selected by the following bits : bit 7 of the port P3 direction register, bits 5 and 4 of the clock source control register (addresses 021616). A variety of character sizes can be obtained by combining dot sizes with OSD clocks. When not using the pins OSC1 and OSC2 for the OSD clock I/O pins, the pins can be used as sub-clock I/O pins or port P6. • • • 7 0 Clock source control register (CS : address 0216 16) CC mode clock selection bit 0 : Data slicer clock 1 : OSC1 clock OSD mode clock selection bits b2 b1 0 0 1 1 Table 13. Setting for P63/OSC1/XCIN, P64/OSC2/XCOUT OSD clock Sub-clock Input Function I/O pin I/O pin port Register 0 : Data slicer clock 1 : OSC1 clock 0: 1 : Do not set EXOSD mode clock selection bit 0 : Data slicer clock 1 : OSC1 clock OSD1 oscillating mode selection bits b7 Port P3 direction 0 0 1 b5 b4 0 0 1 1 register Clock source b5 0 1 1 0 0 control register b4 1 0 1 0 1 0 : 32 kH Z oscillating mode 1 : Input ports P6 3, P6 4 0 : LC oscillating mode 1 : Ceramic · quartz-crystal oscillating mode Pre-divide ratio of layer 2 selection bit 0 : ✕1 1 : ✕2 Test bit (Note) Note : Be sure to set bit 7 to “0” for program of the mask and the EPROM versions. For the emulator MCU version (M37270ERSS), be sure to set bit 7 to “1” when using the data slicer clock for software debugging. Fig. 62. Structure of clock control register Data slicer clock Data slicer circuit CC mode block “1” “00” 32 kHZ “0” CS 0 “0” OSD mode block OSC1 clock LC “10” CS5, CS 4 Ceramic · quartz-crystal “1” CS1 CS2 = “0” “0” EXOSD mode block “11” “1” CS3 Oscillating mode for OSD Fig. 63. Block diagram of OSD selection circuit 55 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (5) Field Determination Display To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to Figure 65) corresponding to the field is displayed alternately. In the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the VSYNC control signal (refer to Figure 57) in the microcomputer and then comparing this time with the time of the previous field. When the time is longer than the comparing time, it is regarded as even field. When the time is shorter, it is regarded as odd field The contents of this field can be read out by the field determination flag (bit 7 of the I/O polarity control register at address 021716). A dot line is specified by bit 6 of the I/O polarity control register (refer to Figure 65). However, the field determination flag read out from the CPU is fixed to “0” at even field or “1” at odd field, regardless of bit 6. 7 0 I/O polarity control register (PC : address 0217 16) HSYNC input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input VSYNC input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input R/G/B output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output I1, I2 output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output OUT1 output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output OUT2 output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output Display dot line selection bit (Note) 0: “ ” at even field “ ” at odd field 1: “ ” at even field “ ” at odd field Field determination flag 0 : Even field 1 : Odd field Note : Refer to Figure 65. Fig. 64. Structure of I/O polarity control register 56 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Both H SYNC signal and V SYNC signal are negative-polarity input HSYNC Field V SYNC and VSYNC control signal in microcomputer Upper : VSYNC signal (n–1) field (Odd-numbered) Field Display dot line determination selection bit flag(Note) Odd T1 0.25 to 0.50[ms] at f(XIN ) = 8 MHz (n) field (Even-numbered) Even (n+1) field (Odd-numbered) Odd When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 Dot line 1 1 Dot line 0 0 Dot line 0 1 Dot line 1 1 (T3 < T2) T3 1 0 0 (T2 > T1) T2 Lower : VSYNC control signal in microcomputer Display dot line 3 4 5 16) to “0.” 6 7 8 9 10 11 12 13 14 15 16 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OSD mode 24 25 26 CC mode · EXOSD mode When the display dot line selection bit is “0,” the “ ” font is displayed at even field, the “ ” font is displayed at odd field. Bit 7 of the I/O polarity control register can be read as the field determination flag : “1” is read at odd field, “0” is read at even field. Character ROM font configuration diagram Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in the microcomputer. Fig. 65. Relation between field determination flag and display font 57 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER The OSD ROM of the character font has a capacity of 12800 bytes. Since 40 bytes are required for 1 character data, the ROM can stores up to 320 kinds of characters. The OSD ROM of the extra font has a capacity of 1664 bytes. Since 52 bytes are required for 1 character data, the ROM can stores up to 32 kinds of characters. Data of the character font and extra font is specified shown in Figure 66. (6) Memory for OSD There are 2 types of memory for OSD : ROM for OSD (addresses 1080016 to 1567F16, 1800016 to 1E43F16) used to store character dot data (masked) and RAM for OSD (addresses 080016 to 0FFF16) used to specify the characters and colors to be displayed. The following describes each type of memory. 1 ROM for OSD (addresses 1080016 to 1567F16, 18000 16 to 1E43F16) The ROM for OSD contains dot pattern data for characters to be displayed. To actually display the character code and the extra code stored in this ROM, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the ROM for OSD) into the RAM for OSD. OSD ROM address of character font data OSD ROM address bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 Line number/character code/font bit 1 0 AD9 AD8 AD7 AD6 Line number AD5 AD4 AD3 AD2 AD1 AD0 Font bit Character code = “0216” to “1516” Line number Character code = “0016” to “13F 16” Font bit = 0 : left font 1 : right font OSD ROM address of extra font data OSD ROM address bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 Line number/extra code /font bit b7 1 AD7 AD6 0 0 0 0 Line number AD5 AD4 Left font b0 b7 Right font 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 b0 Data in Line OSD number ROM 000016 7FF016 7FF816 601C16 600C16 600C16 600C16 600C16 601C16 7FF816 7FF016 630016 638016 61C016 60E016 607016 603816 601C16 600C16 000016 Character font AD2 AD1 AD0 Font bit Extra code b7 Left font b0 b7 Fig. 66. OSD character data storing form Right font b0 Data in OSD ROM FFFE16 FFFF 16 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 FFFF 16 FFFE16 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0016 0016 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 000016 000016 Extra font 58 AD3 = “0016” to “19 16” = “0016” to “1F 16” = 0 : left font 1 : right font Line number Extra code Font bit Line number 1 AD8 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 2 RAM for OSD (addresses 080016 to 0FFF16) The RAM for OSD is allocated at addresses 080016 to 0FFF16, and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. Table 14 shows the contents of the RAM for OSD. For example, to display 1 character position (the left edge) in block 1, write the character code in address 080016, write the color code 1 at 084016, and write the color code 2 at 082816. The structure of the RAM for OSD is shown in Figure 68. Note: For the OSD mode block with dot size of 1.5TC ✕ 1/2H and 1.5TC ✕ 1H, the 3nth (n = 1 to 13) character is skipped as compared with ordinary block✽. Accordingly, maximum 26 characters are only displayed in 1 block. The RAM data for the 3nth character does not effect the display. Any character data can be stored here (refer to Figure 67). ✽ Blocks with dot size of 1TC ✕ 1/2H and 1TC ✕ 1H, or blocks on the layer 1 Table 14. Contents of OSD RAM Block Block 1 Block 2 Block 3 Block 4 Block 5 Display position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character Character code specification 080016 080116 : 081716 081816 : 082616 082716 088016 088116 : 089716 0E9816 : 08A616 08A716 090016 090116 : 091716 Color code 1 specification 084016 084116 : 085716 085816 : 086616 086716 08C016 08C116 : 08D716 08D816 : 08E616 08E716 094016 094116 : 095716 Color code 2 specification 082816 082916 : 083F16 086816 : 087616 087716 08A816 08A916 : 08BF16 08E816 : 08F616 08F716 092816 092916 : 093F16 091816 : 092616 092716 098016 098116 : 099716 099816 : 09A616 09A716 0A0016 0A0116 : 0A1716 0A1816 : 0A2616 0A2716 095816 : 096616 096716 09C016 09C116 : 09D716 08D816 : 09E616 09E716 0A4016 0A4116 : 0A5716 0A5816 : 0A6616 0A6716 096816 : 097616 097716 09A816 09A916 : 09BF16 09E816 : 09F616 09F716 0A2816 0A2916 : 0A3F16 0A6816 : 0A7616 0A7716 59 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Table 14. Contents of OSD RAM (continued) Block Block 6 Block 7 Block 8 Block 9 Block 10 Block 11 60 Display position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character Character code specification 0A8016 0A8116 : 0A9716 0A9816 : 0AA616 0AA716 0B0016 0B0116 : 0B1716 0B1816 : 0B2616 0B2716 0B8016 0B8116 : 0B9716 0B9816 : 0BA616 0BA716 0C0016 0C0116 : 0C1716 Color code 1 specification 0AC016 0AC116 : 0AD716 0AD816 : 0AE616 0AE716 0B4016 0B4116 : 0B5716 0B5816 : 0B6616 0B6716 0BC016 0BC116 : 0BD716 0BD816 : 0BE616 0BE716 0C4016 0C4116 : 0C5716 Color code 2 specification 0AA816 0AA916 : 0ABF16 0AE816 : 0AF616 0AF716 0B2816 0B2916 : 0B3F16 0B6816 : 0B7616 0B7716 0BA816 0BA916 : 0BBF16 0BE816 : 0BF616 0BF716 0C2816 0C2916 : 0C3F16 0C1816 : 0C2616 0C2716 0C8016 0C8116 : 0C9716 0C9816 : 0CA616 0CA716 0D0016 0D0116 : 0D1716 0D1816 : 0D2616 0D2716 0C5816 : 0C6616 0C6716 0CC016 0CC116 : 0CD716 0CD816 : 0CE616 0CE716 0D4016 0D4116 : 0D5716 0D5816 : 0D6616 0D6716 0C6816 : 0C7616 0C7716 0CA816 0CA916 : 0CBF16 0CE816 : 0CF616 0CF716 0D2816 0D2916 : 0D3F16 0D6816 : 0D7616 0D7716 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Table 14. Contents of OSD RAM (continued) Block Display position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character Block 12 Block 13 Block 14 Block 15 Block 16 Display sequence 1 2 3 4 5 6 RAM address order 1 2 4 5 7 8 7 8 Character code specification 0D8016 0D8116 : 0D9716 0D9816 : 0DA616 0DA716 0E0016 0E0116 : 0E1716 0E1816 : 0E2616 0E2716 0E8016 0E8116 : 0E9816 0E9916 : 0EA616 0EA716 0F0016 0F0116 : 0F1716 Color code 1 specification 0DC016 0DC116 : 0DD716 0DD816 : 0DE616 0DE716 0E4016 0E4116 : 0E5716 0E5816 : 0E6616 0E6716 0EC016 0EC116 : 0ED716 0ED816 : 0EE616 0EE716 0F4016 0F4116 : 0F5716 Color code 2 specification 0DA816 0DA916 : 0DBF16 0DE816 : 0DF616 0DF716 0E2816 0E2916 : 0E3F16 0E6816 : 0E7616 0E7716 0EA816 0EA916 : 0EBF16 0EE816 : 0EF616 0EF716 0F2816 0F2916 : 0F3F16 0F1816 : 0F2616 0F2716 0F8016 0F8116 : 0F9716 0F9816 : 0FA616 0FA716 0F5816 : 0F6616 0F6716 0FC016 0FC116 : 0FD716 0FD816 : 0FE616 0FE716 0F6816 : 0F7616 0F7716 0FA816 0FA916 : 0FBF16 0FE816 : 0FF616 0FF716 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 10 11 13 14 16 17 19 20 22 23 25 26 28 29 31 32 34 35 37 38 1.5Tc size block Display sequence 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 1617 18 19 20 21 22 23 242526 27 28 29 30 31 32 3334 35 36 37 38 39 40 RAM address order 1Tc size 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2526 27 28 29 30 31 32 33 34 35 36 37 38 39 40 block Fig. 67. RAM data for 3nth character 61 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Note: Do not read from and write to addresses in OSD RAM shown in Table 15. Table 15. List of access disable addresses 62 087816 087916 087A16 08F816 08F916 08FA16 097816 097916 097A16 09F816 09F916 09FA16 0A7816 0A7916 0A7A16 0AF816 0AF916 0AFA16 0B7816 0B7916 0B7A16 0BF816 0BF916 0BFA16 0C7816 0C7916 0C7A16 0CF816 0CF916 0CFA16 0D7816 0D7916 0D7A16 0DF816 0DF916 0DFA16 0E7816 0E7916 0E7A16 0EF816 0EF916 0EFA16 0F7816 0F7916 0F7A16 0FF816 0FF916 0FFA16 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Blocks 1 to16 b7 RF7 b0 RF6 RF5 RF4 RF3 RF2 b7 b0 Color code 1 CC mode Bit name b0 RF1 RF0 RC17 RC16 RC15 RC14 RC13 RC12 RC11 RC10 RC23 RC22 RC21 RC20 Character code Bit b3 OSD mode Function Bit name Color code 2 EXOSD mode Function Bit name Function RF0 RF1 RF2 RF3 Character code RF4 (Low-order 8 bits) RF5 Specification of character code in OSD ROM Character code (Low-order 8 bits) Specification of character code in OSD ROM Character code (Low-order 8 bits) Specification of character code in OSD ROM RF6 RF7 RC10 RC11 RC12 RC13 RC14 Character code Character code Character code (High-order 1 bit) (High-order 1 bit) (High-order 1 bit) Control of 0: Color signal output OFF Control of 0: Color signal output OFF character color R 1: Color signal output ON character color R 1: Color signal output ON Control of Control of character color G character color G Control of Control of character color B character color B OUT1 control RC15 Flash control RC16 Underline control 0: Character output Italic control RC21 RC22 (CC2) 0: Character output 1: Background output 0: Flash OFF Control of 0: Color signal output OFF 1: Flash ON character color I1 1: Color signal output ON 0: Underline OFF OUT1 control 0: Character output 1: Background output Extra code 0 Specification of (EX0) extra code in OSD ROM Extra code 1 (EX1) Not used 0: Italic OFF Extra code 2 (EX2) 0: Color signal output OFF Control of background 0: Color signal output OFF Background color code 0 color R 1: Color signal output ON 1: Color signal output ON color R Control of background Control of background color G color G Control of background Control of background color B color B Control of background Not used character color Character color code 2 Control of background RC23 Specification of (CC1) 1: Italic ON RC20 (CC0) Character color code 1 1: Background output 1: Underline ON RC17 OUT1 control Character color code 0 color I1 Specification of (BCC0) background color Background color code 1 (BCC1) Background color code 2 (BCC2) Extra code 3 Specification of (EX3) extra code in OSD ROM Notes 1: Read value of bits 4 to 7 of the color code 2 is undefined. 2: For “not used” bits, the write value is read. 3: The decode value of the extra code is “EX4.” Fig. 68. Structure of OSD RAM 63 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (7) Character color The color for each character is displayed by the color code 1. The kinds and specification method of character color are different depending on each mode. CC mode .................. 7 kinds Specified by bits 1 (R), 2 (G), and 3 (B) of the color code 1 OSD mode ............... 15 kinds Specified by bits 1 (R), 2 (G), 3 (B), and 5 (I1) of the color code 1 EXOSD mode .......... 7 kinds Specified by bits 1 (CC0), 2 (CC1), and 3 (CC2) of the color code 1 The correspondence Table of the color code 1 and color signal output in the EXOSD mode is shown in Table 16. • • • Table 16. Correspondence table of color code 1 and color signal output in EXOSD mode Color code 1 Bit 3 CC2 0 0 0 0 1 1 1 1 Bit 2 CC1 0 0 1 1 0 0 1 1 Color signal output Bit 1 CC0 0 1 0 1 0 1 0 1 R G B I1 I2 0 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 (8) Character background color The character background color can be displayed in the character display area. The character background color for each character is specified by the color code 2. The kinds and specification method of character background color are different depending on each mode. CC mode .................. 7 kinds Specified by bits 0 (R), 1 (G), and 2 (B) of the color code 2 OSD mode ............... 15 kinds Specified by bits 0 (R), 1 (G), 2 (B), and 3 (I1) of the color code 2 EXOSD mode .......... 7 kinds Specified by bits 0 (BCC0), 1 (BCC1), and 2 (BCC2) of the color code 2 The correspondence table of the color code 2 and color signal output in the EXOSD mode is shown in Table 17. • • • Note : The character background color is displayed in the following part : (character display area)–(character font)–(border)–(extra font). Accordingly, the character background color does not mix with these color signal. 64 Table 17. Correspondence table of color code 2 and color signal output in EXOSD mode Color code 2 Bit 2 BCC2 0 0 0 0 1 1 1 1 Bit 1 BCC1 0 0 1 1 0 0 1 1 Bit 0 BCC0 0 1 0 1 0 1 0 1 Color signal output R G B I1 I2 0 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (9) OUT1, OUT2 signals The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of the OUT1, OUT2 signals is controlled by bit 4 of the color code 1 (refer to Figure 68), bits 2 and Block control register OUT2 output control bit (b7) Border output control bit (b2) OUT1 control (b4 of color code 1) 0 7 of the block control register (refer to Figure 53). The setting values for controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 69. Output waveform OUT1 OUT2 0 1 OUT1 OUT2 0 0 OUT1 OUT2 1 1 OUT1 OUT2 0 OUT1 OUT2 0 1 OUT1 OUT2 1 0 OUT1 OUT2 1 OUT1 1 OUT2 Fig. 69. Setting value for controlling OUT1, OUT2 and corresponding output waveform 65 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (10) Attribute The attributes (flash, underline, italic) are controlled to the character font. The attributes for each character are specified by the color codes 1 and 2 (refer to Figure 68). The attributes to be controlled are different depending on each mode. CC mode ..................... Flash, underline, italic OSD mode .................. Border (all bordered, shadow bordered can be selected) EXOSD mode ............. Border (all bordered, shadow bordered can be selected) , extra font (32 kinds) 1 Under line The underline is output at the 23th and 24th dots in vertical direction only in the CC mode. The underline is controlled by bit 6 of the color code 1. The color of underline is the same color as that of the character font. 2 Flash The parts of the character font, the underline, and the character background are flashed only in the CC mode. The color signals (R, G, B, OUT1) of the character font and the underline are controlled by bit 5 of the color code 1. All of the color signals for the character font flash. However, the color signal for the character background can be controlled by bit 3 of the OSD control register (refer to Figure 52). The flash cycle bases on the VSYNC count. · VSYNC cycle ✕ 48 ; 768 ms (at flash ON) · VSYNC cycle ✕ 16 ; 256 ms (at flash OFF) 3 Italic The italic is made by slanting the font stored in OSD ROM only in the CC mode. The italic is controlled by bit 7 of the color code 1. The display example of the italic and underline is shown in Figure 70. In this case, 16 26 dots are used and “R” is displayed. Notes 1: When setting both the italic and the flash, the italic character flashes. 2: When the pre-divide ratio = 1, the italic character with slant of 1 dot ✕ 5 steps is displayed (refer to Figure 71 (c)). When the pre-divide ratio = 2, the italic character with slant of 1/2 dot ✕ 10 steps is displayed (refer to Figure 71 (d)). 3: The boundary of character color is displayed in italic. However, the boundary of character background color is not affected by the italic (refer to Figure 72). 4: The adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to Figure 72). 5: When displaying the italic character in the block with the pre-divide ratio = 1, set the OSD clock frequency to 11 MHz to 14 MHz. 66 4 Extra font There are 32 kinds of the extra fonts configured with 16 ✕ 26 dots in OSD ROM. 16 kinds of these fonts can be displayed by ORed with the character font by a character unit (refer to Figure 50). For the others, only the extra font is displayed (refer to Figure 50). In only the EXOSD mode, the extra font is controlled the following : bits 7 to 5 of the color code 1, bit 3 of the color code 2, and decode value (EX4) of the character code. When the character code = “0016” to “13F16,” EX4 is “0, ” when the character code = “14016,” EX4 is “1.” Since there is no font with the character code = “14016,” a blank is displayed. The extra font color for each screen is specified by the extra color register. When the character font overlaps with the extra font, the color of the area becomes the ORed color of both fonts. Note : When using the extra font, set bits 7 and 6 of the OSD control register to “0” (refer to Figure 52). 7 0 Extra font color register (EC : address 0218 16) Extra font color R control bit 0 : No output 1 : Output Extra font color G control bit 0 : No output 1 : Output Extra font color B control bit 0 : No output 1 : Output Extra font color I1 control bit 0 : No output 1 : Output Extra font color I2 control bit 0 : No output 1 : Output Fig. 70. Structure of extra font color register MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Color code 1 Color code 1 Bit 6 Bit 7 Bit 6 0 0 1 (a) Ordinary Bit 7 0 (b) Underline Color code 1 Bit 6 Color code 1 Bit 7 0 1 (c) Italic (pre-divide ratio = 1) Bit 6 Bit 7 0 1 (d) Italic (pre-divide ratio = 2) Fig. 71. Example of attribute display (in CC mode) Italic on one side Bit 7 of color code 1 1 0 0 Italic on both sides 1 1 0 1 Note : The wavy-lined is the boundary of character color Fig. 72. Example of italic display 67 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Notes 1 : There is no border for the extra font. 2 : The border dot area is the shaded area as shown in Figure 75. In the EXOSD mode, top and bottom of character font display area is not bordered. 3 : When the border dot overlaps on the next character font, the character font has priority (refer to Figure 76 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 76 B). 4 : The border is not displayed at right side of the most right dot in the display area of the 40th character (the character located at the most right of the block). 5 Border The border is output in the OSD mode and the EXOSD mode. The all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected (refer to Figure 73) by bit 2 of the OSD control register (refer to Figure 52). The border ON/OFF is controlled by bit 2 of the block control register (refer to Figure 53). The OUT1 signal is used for border output. The border color for each screen is specified by the border color register. The horizontal size (x) of border is 1TC (OSD clock cycle divided in the pre-divide circuit) regardless of the character font dot size. The vertical size (y) different depending on the screen scan mode and the vertical dot size of character font. All bordered Shadow bordered Fig. 73. Example of border display y x Scan mode Border dot size Vertical dot size of character font Normal scan mode 1/2H Horizontal size (x) Vertical size (y) Fig. 74. Horizontal and vertical size of border 68 1H, 2H, 3H Bi-scan mode 1/2H, 1H, 2H, 3H 1TC (OSD clock cycle divided in pre-divide circuit) 1/2H 1H 1H MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER OSD mode EXOSD mode 16 dots 16 dots 20 dots 20 dots Character font area 1 dot width of border 1 dot width of border 1 dot width of border 1 dot width of border Fig. 75. Border area 7 0 Border color register (FC : address 021B 16) Border color R control b 0 : No output 1 : Output Border color G control bit 0 : No output 1 : Output Border color B control bit 0 : No output 1 : Output Character boundary B Character boundary A Character boundary B Border color I1 control bit 0 : No output 1 : Output Border color I2 control bit 0 : No output 1 : Output Fig. 76. Border priority Fig. 77. Structure of border color register 69 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (11) Multiline Display The M37271MF-XXXSP can ordinarily display 16 lines on the CRT screen by displaying 16 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. The mode in which an OSD interrupt occurs is different depending on the setting of the raster color register (refer to Figure 84). · When bit 7 of the raster color register is “0” An OSD interrupt occurs at the end of block display in the OSD and the EXOSD mode. · When bit 7 of the raster color register is “1” An OSD interrupt occurs at the end of block display in the CC mode. Notes 1: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control register (addresses 00D016 to 00DF16), an OSD interrupt request does not occur (refer to Figure 78 (A)). 2: When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 78 (B)). 3: On the screen setting window, an OSD interrupt occurs even at the end of the CC mode block (off display) out of window (refer to Figure 78 (C)). Block 1 (on display) “OSD interrupt request” Block 1 (on display) “OSD interrupt request” Block 2 (on display) “OSD interrupt request” Block 2 (on display) “OSD interrupt request” Block 3 (off display) No “OSD interrupt request” No “OSD interrupt request” Block 3 (on display) Block 4 (on display) “OSD interrupt request” “OSD interrupt request” On display (OSD interrupt request occurs at the end of block display) Block 4 (off display) Off display (OSD interrupt request does not occur at the end of block display) (A) Block 1 “OSD interrupt request” Block 1 Block 2 No “OSD interrupt request” Block 2 “OSD interrupt request” “OSD interrupt request” Block 3 “OSD interrupt request” Window In CC mode (B) Fig. 78. Note on occurence of OSD interrupt 70 (C) MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (12) Automatic Solid Space Function Notes 1 : Blank is disabled on the left side of the 1st character and on the right side of the 40th character of each block. 2 : When using this function, set “00916” to the 40th character. This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area in the CC mode. The solid space is output in the following area : · the character area except character code “00916 ” · the character area on the left and right sides of the character area except character code “00916 ” This function is turned on and off by bit 4 of the OSD control register (refer to Figure 52). Table 18. Setting for automatic solid space Bit 4 of OSD control register 0 Bit 7 of block control register 1 0 1 0 1 Bit 4 of color code 1 0 1 OUT1 output signal Character Character Character Solid Character font part display font part space font part 0 1 0 1 0 1 area OUT2 output signal OFF OFF Character OFF Solid display space area When setting the character code “005 16” as the character A, “006 16” as the character B. Character to be displayed (Display memory) 009 005 009 009 009 006 006 16 16 16 16 16 16 • • • 16 006 009 009 009 16 16 16 16 (Display screen) • • • 1st (Note 1) character 2nd character No blank output 39th character 40th character (Note 2) (Note 1) Fig. 79. Display screen example of automatic solid space 71 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (13) Scan Mode M37271MF-XXXSP has the bi-scan mode for corresponding to HSYNC of double speed frequency. In the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the normal scan mode. The scan mode is selected by bit 1 of the OSD control register (refer to Figure 52). Table 19. Setting for scan mode Parameter Bit 1 of OSD control register Scan mode Vertical display start position 0 1 Value of vertical position register ✕ 1H Value of vertical position register ✕ 2H Vertical dot size 1TC ✕ 1/2H 1TC ✕ 1H 1TC ✕ 1H 1TC ✕ 2H 2TC ✕ 2H 2TC ✕ 4H 3TC ✕ 3H 3TC ✕ 6H (14) Window Function This function sets the top and bottom boundary of display limit on a screen. The window function is valid only in the CC mode. The top boundary is set by the window H registers 1 and 2. The bottom boundary is set by the window L registers 1 and 2. This function is turned on and off by bit 5 of the OSD control register (refer to Figure 52). The structure of the window H registers 1 and 2 is shown in Figure 81, the structure of the window L registers 1 and 2 is shown in Figure 82. D E EXOSD mode F I J CC mode M N O CC mode G H K L Q R S T U V W X Y Screen Fig. 80. Example of window function 72 Notes 1: Set values except “0016” and “0116” to the window H register 1 when the window H register 2 is “0016.” 2: Set the register value fit for the following condition : (WH1 + WH2) < (WL1 + WL2) A B C P Bi-scan Normal scan Top boundary of window Window CC mode OSD mode Bottom boundary of window MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 7 0 Window H register 1 (WH1 : address 021C16) Control bits of window top boundary (Note) Top boundary position (low-order 8bits) TH✕(setting value of low-order 2bits of WH2✕162 +setting value of high-order 4bits of WH1✕161 +setting value of 0 low-order 4bits of WH1 ✕16 ) 7 0 Window H register 2 (WH2 : address 021E16 ) Control bits of window top boundary (Note) Top boundary position (high-order 2bits) TH✕(setting value of low-order 2bits of WH2✕162 +setting value of high-order 4bits of WH1✕161 +setting value of low-order 4bits of WH1 ✕16 0 ) Note : Set values except “00 16” and “01 16” to the WH1 when the WH2 is “00 16.” Fig. 81. Structure of window H registers 7 0 Window L register 1 (WL1 : address 021D16) Control bits of window bottom boundary (Note) Bottom boundary position (low-order 8bits) TH✕(setting value of low-order 2bits of WL2✕16 2 +setting value of high-order 4bits of WL1✕161 +setting value of low-order 4bits of WL1 ✕160 ) 7 0 Window L register 2 (WL2 : address 021F16) Control bits of window bottom boundary (Note) Bottom boundary position (high-order 2bits) TH✕(setting value of low-order 2bits of WL2✕16 2 +setting value of high-order 4bits of WL1✕16 1 +setting value of low-order 4bits of WL1✕160 ) Note : Set values fit for the following condition : (WH1+WH2) < (WL1+WL2). Fig. 82. Structure of window L registers 73 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (15) OSD Output Pin Control The OSD output pins R, G, B, and OUT1 can also function as ports P52, P53, P54 and P55. Set the corresponding bit of the OSD port control register (address 00CB16) to “0” to specify these pins as OSD output pins, or set it to “1” to specify it as a general-purpose port P5 pins. The OUT2, I1, and I2 can also function as port P10, P15, P16. Set the corresponding bit of the port P1 direction register (address 00C316) to “1” (output mode). After that, switch between the OSD output function and the port function by the OSD port control register. Set the corresponding bit to “1” to specify the pin as OSD output pin, or set it to “0” to specify as port P1 pin. The input polarity of the HSYNC, VSYNC and output polarity of signals R, G, B, I1, I2, OUT1 and OUT2 can be specified with the I/O polarity control register (address 021716) . Set a bit to “0” to specify positive polarity; set it to “1” to specify negative polarity (refer to Figure 64). The structure of the OSD port control register is shown in Figure 83. 7 0 0 OSD port control register (PF : address 00CB 16) Port P15 output signal selection bit 0 : Port P1 5 output 1 : I1 signal output Port P16 output signal selection bit 0 : Port P1 6 output 1 : I2 signal output Port P52 output signal selection bit 0 : R signal output 1 : Port P5 2 output Port P53 output signal selection bit 0 : G signal output 1 : Port P5 3 output Port P54 output signal selection bit 0 : B signal output 1 : Port P5 4 output Port P55 output signal selection bit 0 : OUT1 signal output 1 : Port P5 5 output Port P10 output signal selection bit 0 : Port P1 0 output 1 : OUT2 signal output Fix this bit to “0.” Fig. 83. Structure of OSD port control register 74 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (16) Raster Coloring Function An entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. Since each of the R, G, B, I1, I2, OUT1, and OUT2 pins can be switched to raster coloring output, 7 raster colors can be obtained. If the OUT1 pin has been set to raster coloring output, a raster coloring signal is always output during 1 horizontal scanning period. This setting is necessary for erasing a background TV image. If the R, G, B, I1, and I2 pins have been set to output, a raster coloring signal is output in the part except a no-raster colored character (in Figure 85, a character “1”) during 1 horizontal scanning period. This ensures that character colors are not mixed with the raster color. The structure of the raster color register is shown in Figure 84, the example of raster coloring is shown in Figure 85. 7 0 Raster color register (RC : address 0218 16) Raster color R control bit 0 : No output 1 : Output Raster color G control bit 0 : No output 1 : Output Raster color B control bit 0 : No output 1 : Output Raster color I1 control bit 0 : No output 1 : Output Raster color I2 control bit 0 : No output 1 : Output Raster color OUT1 control bit 0 : No output 1 : Output Raster color OUT2 control bit 0 : No output 1 : Output OSD interrupt source selection bit 0 : Interrupt occurs at end of OSD or EXOSD block display 1 : Interrupt occurs at end of CC mode block display Fig. 84. Structure of raster color register AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA A AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA : Character color “RED” (R) : Border color “GREEN” (G) : Background color “MAGENTA” (R and B) : Raster color “BLUE” (R and OUT1) A HSYNC A' OUT1 R Signals across A-A' G B Fig. 85. Example of raster coloring 75 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER INTERRUPT INTERVAL DETERMINATION FUNCTION The M37271MF-XXXSP incorporates an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter as shown in Figure 86. Using this counter, it determines an interval or a pulse width on the INT1 or INT2 (refer to Figure 88). The following describes how the interrupt interval is determined. 1. The determination mode is selected by using bit 5 of the interrupt interval determination control register (address 021216). When this bit is set to “0,” the interrupt interval determination mode is selected; when the bit is set to “1,” the pulse width determination mode is selected. 2. The interrupt input to be determined (INT1 input or INT2 input) is selected by using bit 2 in the interrupt interval determination control register (address 021216). When this bit is cleared to “0,” the INT1 input is selected ; when the bit is set to “1,” the INT2 input is selected. 3. When the INT1 input is to be determined, the polarity is selected by using bit 3 of the interrupt interval determination control register ; when the INT2 input is to be determined, the polarity is selected by using bit 4 of the interrupt interval determination control register. 76 When the relevant bit is cleared to “0,” determination is made of the interval of a positive polarity (rising transition) ; when the bit is set to “1,” determination is made of the interval of a negative polarity (falling transition). 4. The reference clock is selected by using bit 1 of the interrupt interval determination control register. When the bit is cleared to “0,” a 32µs clock is selected ; when the bit is set to “1,” a 16µs clock is selected (based on an oscillation frequency of 8MHz in either case). 5. Simultaneously when the input pulse of the specified polarity (rising or falling transition) occurs on the INT1 pin (or INT2 pin), the 8-bit binary up counter starts counting up with the selected reference clock (32µs or 16µs). 6. Simultaneously with the next input pulse, the value of the 8-bit binary up counter is loaded into the interrupt interval determination register (address 021116) and the counter is immediately reset (“0016”). The reference clock is input in succession even after the counter is reset, and the counter restarts counting up from “0016”. 7. When count value “FE16” is reached, the 8-bit binary up counter stops counting. Then, simultaneously when the next reference clock is input, the counter sets value “FF16” to the interrupt interval determination register. The reference clock is generated by setting bit 0 of the PWM mode register 1 to “0.” MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 16µs 32µs RE1 Control circuit 8-bit binary up counter (8) RE0 8 INT2 (Note) INT1 (Note) Interrupt interval determination register(8) RE2 (Address 0211 16) 8 Selection gate : Connected to black colored side at rest. Data bus RE: Input interval determination control register Note: The pulse width of external interrupt INT1 and INT2 needs 5 or more machine cycles. Fig. 86. Block diagram of interrupt interval determination circuit 7 0 Interrupt interval determination control register (RE : address 0212 16) Interrupt interval determination circuit operation control bit 0 : Stopped 1 : Operating Reference clock control selection bit (at f(X IN) = 8MHz) 0 : 32µs 1 : 16µs External interrupt input pin selection bit 0 : INT1 input 1 : INT2 input INT1 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input INT2 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input INT1 or INT2 input RE5 0 0 1 1 REi 0 1 0 1 Count interval REi : Bit i (i = 3, 4) of interrupt interval determination control register (address 021116) Fig. 88. Setting value of interrpt interval determination control register and measuring interval Interrupt interval determination mode switch bit 0 : Interrupt interval determination mode 1 : Pulse width determination mode INT3 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input A-D conversion · INT3 interrupt source selection bit 0 : INT3 interrupt 1 : A-D conversion interrupt Fig. 87. Structure of interrupt interval determination control register 77 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER RESET CIRCUIT Poweron The M37271MF-XXXSP is reset according to the sequence shown in Figure 90. It starts the program from the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address, when the ______ RESET pin is held at “L” level for 2 µs or more while the power source voltage is 5 V ± 10 % and the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and then returned to “H” level. The internal state of microcomputer at reset are shown in Figures 3 to 7. An example of the reset circuit is shown in Figure 89. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V. 4.5 V Power source voltage 0 V 0.9 V Reset input voltage 0 V 33 Vcc 1 36 5 M51953AL RESET 4 3 0.1 µF 32 Vss M37271MF-XXXSP Fig. 89. Example of reset circuit XIN φ RESET Internal RESET SYNC Address ? 01, S ? 01, S-1 01, S-2 FFFE FFFF AD H, AD L Reset address from the vector table ? Data 32768 count of X IN clock cycle (Note 3) Fig. 90. Reset sequence 78 ? ? ? ? AD L ADH Notes 1 : f(XIN) and f(φ) are in the relation : f(X IN) = 2·f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected in hardware. At this time, “FF 16” is set in timer 3 and “07 16” is set to timer 4. Timer 3 counts down with f(X IN)/16, and reset state is released by the timer 4 overflow signal. MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Ports P03, P10, P15–P17, P2, P30, P31 Direction register CMOS output Data bus Port latch Ports P03, P10, P15–P17, P2, P30, P31 Note : Each port is also used as below : P10 : OUT2 P15 : I1 P16 : I2/INT3 P17 : SIN P24–P26 : AD3–AD1 Ports P00–P02, P04–P07 N-channel open-drain output Direction register Ports P00–P02, P04–P07 Data bus Port latch Note : Each port is also used as below : P0 0–P02 : PWM4–PWM6 P04–P07 : PWM0–PWM3 Ports P11–P14 N-channel open-drain output Direction register Port P11-P14 Data bus Port latch Note : Each port is also used as below : P11 : SCL1 P12 : SCL2 P13 : SDA1 P14 : SDA2 Fig. 91. I/O pin block diagram (1) 79 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER SOUT, SCLK N-channel open-drain output Direction register Ports SOUT, SCLK Note : Each pin is also used as below : SOUT : P45 SCLK : P46 Data bus HSYNC, VSYNC R, G, B, OUT1 Schmidt input Internal circuit CMOS output HSYNC, VSYNC Internal circuit Note : Each pin is also used as below : R : P52 B : P54 G : P53 OUT1 : P55 Ports P40–P4 4 Data bus Ports P40–P44 Note : Each port is also used as below : P40 : AD4 P41 : INT2 P42 : TIM2 P43 : TIM3 P44 : INT1 Fig. 92. I/O pin block diagram (2) 80 R, G, B, OUT1 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER CLOCK GENERATING CIRCUIT (3) Low-Speed Mode The M37271MF-XXXSP has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. When using XCIN-XCOUT as subclock, clear bits 5 and 4 of the clock source control register to “0.” To supply a clock signal externally, input it to the XIN (XCIN) pin and make the XOUT (XCOUT) pin open. When not using XCIN clock, connect the XCIN to VSS and make the XCOUT pin open. After reset has completed, the internal clock φ is half the frequency of XIN. Immediately after poweron, both the XIN and XCIN clock start oscillating. To set the internal clock φ to low-speed operation mode, set bit 7 of the CPU mode register (address 00FB16) to “1.” If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to “1.” When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the XCIN-XCOUT drivability can be reduced, allowing even lower power consumption (60µA with f (XCIN) = 32kHz). To reduce the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode register (00FB16) to “0.” At reset, this bit is set to “1” and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to “1” by software before executing. M37271MF-XXXSP Oscillation Control (1) Stop mode The built-in clock generating circuit is shown in Figure 93. When the STP instruction is executed, the internal clock φ stops at “H” level. At the same time, timers 3 and 4 are connected in hardware and “FF16” is set in the timer 3, “0716” is set in the timer 4. Select f(XIN)/16 or f(XCIN)/16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00C716 to “0” before the execution of the STP instruction). And besides, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before execution of the STP instruction. The oscillator restarts when external interrupt is accepted, however, the internal clock φ keeps its “H” level until timer 4 overflows. Because this allows time for oscillation stabilizing when a ceramic resonator or a quartz-crystal oscillator is used. XCIN Rf CCIN XIN XOUT Rd CCOUT CIN COUT Fig. 93. Ceramic resonator circuit example M37271MF-XXXSP (2) Wait mode When the WIT instruction is executed, the internal clock φ stops in the “H” level but the oscillator continues running. This wait state is released at reset or when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once. Note: In the wait mode, the following interrupts are invalid. (1) VSYNC interrupt (2) OSD interrupt (3) Timers 1 and 2 interrupts using P42/TIM2 pin input as count source (4) Timer 3 interrupt using P43/TIM3 pin input as count source (5) Data slicer interrupt (6) Multi-master I2C-BUS interface interrupt (7) f(XIN)/4096 interrupt (8) All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source (9) All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source (10) A-D conversion interrupt XCOUT XCIN XCOUT XIN Open External oscillation circuit or external pulse Vcc Vss XOUT Open External oscillation circuit Vcc Vss Fig. 94. External clock input circuit example 81 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER XCIN XCOUT OSC1 oscillating mode selection bits (Notes 1, 4) XOUT XIN “1” Timer 3 count stop bit (Notes 1, 2) Timer 4 count stop bit (Notes 1, 2) Timer 3 Timer 4 “1” 1/8 1/2 “0” Internal system clock selection bit (Notes 1, 3) “0” Timer 3 count source selection bit (Notes 1, 2) Timing φ (Internal clock) Main clock (X IN–XOUT) stop bit (Notes 1, 3) Internal system clock selection bit (Notes 1, 3) Q S R S STP instruction WIT instruction Q Q R S R Reset Interrupt disable flag I Interrupt request Notes 1 : The value at reset is “0.” 2 : Refer to the structure of timer mode register 2. 3 : Refer to the structure of CPU mode register (next page). 4 : Refer to the structure of clock source control register. Fig. 95. Clock generating circuit block diagram 82 Reset STP instruction MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER High-speed operation start mode Reset WIT instruction 8MHz oscillating 32kHz oscillating φ is stopped (“H”) Timer operating STP instruction 8MHz oscillating 32kHz oscillating f(φ ) = 4MHz Interrupt 8MHz stopped 32kHz stopped φ is stopped (“H”) Interrupt (Note 1) External INT, timer interrupt, or SI/O interrupt External INT CM 7 = 0 CM 7 = 1 WIT instruction 8MHz oscillating 32kHz oscillating φ is stopped (“H”) Timer operating (Note 3) STP instruction 8MHz oscillating 32kHz oscillating f(φ ) = 16kHz Interrupt 8MHz stopped 32kHz stopped φ is stopped (“H”) Interrupt (Note 2) CM 6 = 0 The program must allow time for 8MHz oscillation to stabilize CM 6 = 1 8MHz stopped 32kHz oscillating φ is stopped (“H”) Timer operating (Note 3) STP instruction WIT instruction 8MHz stopped 32kHz stopped φ = stopped (“H”) 8MHz stopped 32kHz oscillating f(φ ) = 16kHz Interrupt Interrupt (Note 2) CPU mode register (Address : 00FB 16) CM6 : Main clock (X IN–XOUT) stop bit 0 : Oscillating 1 : Stopped CM7 : Internal system clock selection bit 0 : X IN-XOUT selected (high-speed mode) 1 : X CIN-XCOUT selected (low-speed mode) The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. The φ indicates the internal clock. Notes 1: When the STP state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: The delay after the STP state ends is approximately 2s. 3: When the internal clock φ divided by 8 is used as the timer count source, the frequency of the count source is 2kHz. Fig. 96. State transitions of system clock 83 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER DISPLAY OSCILLATION CIRCUIT ADDRESSING MODE The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 5 and 4 of the clock source control register (address 021616). The memory access is reinforced with 17 kinds of addressing modes. Refer to the SERIES 740 <Software> User’s Manual for details. MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to the SERIES 740 <Software > User’s Manual for details. PROGRAMMING NOTES OSC1 (1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1 µF) directly between the VCC pin–VSS pin, AVCC pin–VSS pin, and the VCC pin–CNVSS pin using a thick wire. OSC2 L C2 C1 Fig. 97. Display oscillation circuit AUTO-CLEAR CIRCUIT When power source is supplied, the auto-clear function can be per______ formed by connecting the following circuit to the RESET pin. Circuit example 1 Vcc RESET Vss Circuit example 2 RESET Vcc Vss Note : Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage. Fig. 98. Auto-clear circuit example 84 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (32-pin DIP Type 27C101, three identical copies) PROM Programming Method The built-in PROM of the One Time PROM version (blank) and builtin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Product M37271EFSP Name of Programming Adapter PCA7400 The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 99 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Fig. 99. Programming and testing of One Time PROM version 85 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Ratings Unit All voltages are based on VSS. Output transistors are cut off. –0.3 to 6 V VCC, AVCC Power source voltage VCC, AVCC VI Input voltage CNVSS VI Input voltage P00–P07, P10–P17, P20–P27, P30, P31, P40–P46, P6 4, OSC1, ______ XIN, HSYNC, VSYNC, RESET, CVIN VO Output voltage P03, P10–P17, P20–P27, P30, P31, R, G, B, OUT1, SOUT, SCLK, XOUT, OSC2 VO Output voltage P00–P02, P04–P07 –0.3 to 13 V IOH Circuit current R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, P30, P31 0 to 1 (Note 1) mA IOL1 Circuit current R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, SOUT, SCLK 0 to 2 (Note 2) mA IOL2 Circuit current P11–P14 0 to 6 (Note 2) mA IOL3 Circuit current P00–P02, P04–P07 0 to 1 (Note 2) mA IOL4 Circuit current P30, P31 Pd Power dissipation Topr Tstg –0.3 to 6 V –0.3 to VCC + 0.3 V –0.3 to VCC + 0.3 V 0 to 10 (Note 3) mA 550 mW Operating temperature –10 to 70 °C Storage temperature –40 to 125 °C Ta = 25 °C RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) Symbol Parameter VCC, AVCC VCC, AVCC VSS VIH1 Power source voltage (Note 4), During CPU, OSD, data slicer operation RAM hold voltage (when clock is stopped) Power source voltage “H” input voltage P00–P07, P10–P17, P20–P27, P3 0, P31, ______ P40–P46, P64, HSYNC, VSYNC, RESET, XIN, OSC1 “H” input voltage P11–P14 (When using I2C-BUS) “L” input voltage P00–P07, P10–P17, P20–P27, P30, P31, P40–P46, P63, P64 “L” input voltage SCL1, SCL2, SDA1, SDA2, (When using I2C-BUS) “L” input voltage (Note 6) P41–P44, P46, P16, P17, HSYNC, VSYNC, ______ RESET, XIN, OSC1 “H” average output current (Note 1) R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, P30, P31 “L” average output current (Note 2) R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, SOUT, SCLK “L” average output current (Note 2) P11–P14 “L” average output current (Note 2) P00–P02, P04–P07 “L” average output current (Note 3) P30, P31 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for sub-clock operation) XCIN Oscillation frequency (for OSD) OSC1 LC oscillating mode Ceramic oscillating mode Input frequency TIM2, TIM3, INT1, INT2, INT3 Input frequency SCLK Input frequency SCL1, SCL2 Input frequency Horizontal sync. signal of video signal Input amplitude video signal CVIN VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 fCPU fCLK fOSD fhs1 fhs2 fhs3 fhs4 VI 86 Min. 4.5 2.0 0 0.8VCC Limits Typ. 5.0 0 Max. 5.5 5.5 0 VCC Unit V V V V 0.7VCC 0 VCC 0.4 VCC V V 0 0 0.3 VCC 0.2 VCC V V 7.9 29 11.0 26.5 15.262 1.5 8.0 32 27.0 15.734 2.0 1 mA 2 mA 6 1 10 8.1 35 27.0 27.5 100 1 400 16.206 2.5 mA mA mA MHz kHz MHz kHz MHz kHz kHz V MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Parameter Symbol ICC Power source current System operation Wait mode Stop mode Test conditions Limits Min. Typ. Max. VCC = 5.5 V, CRT OFF f(XIN) = 8 MHz Data slicer OFF 15 30 CRT ON Data slicer ON 30 45 VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM5 = “0”, CM6 = “1”) 60 200 Unit mA mA VCC = 5.5 V, f(XIN) = 8 MHz 2 4 VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, Low-power dissipation mode set (CM5 = “0”, CM6 = “1”) 25 100 VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 0 1 mA µA 10 VOH “H” output voltage R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, P30, P31 VCC = 4.5 V IOH = –0.5 mA 2.4 VOL “L” output voltage R, G, B, OUT1, OUT2, SOUT, SCLK, P00–P07, P15–P17, P20–P27 VCC = 4.5 V IOL = 0.5 mA 0.4 “L” output voltage P30, P31 VCC = 4.5 V IOL = 10.0 mA 3.0 “L” output voltage P11–P14 VCC = 4.5 V V V 0.4 IOL = 3 mA 0.6 IOL = 6 mA ______ VT+–VT– Hysteresis RESET Hysteresis (Note 6) HSYNC, VSYNC, P41–P44, P46, P11–P14, P17 VCC = 5.0 V 0.5 0.7 VCC = 5.0 V 0.5 1.3 V VCC = 5.5 V VI = 5.5 V 5 µA ______ IIZH “H” input leak current RESET, P03, P10–P17, P20–P27, P30, P31, P40–P46, P63, P64, HSYNC, VSYNC IIZL “L” input leak current RESET, P00–P07, P10–P17, P20–P27, P30, P31, P40–P46, P63, P64, HSYNC, VSYNC VCC = 5.5 V VI = 0 V 5 µA IIZH “H” input leak current VCC = 5.5 V VI = 12 V 10 µA RBS I2C-BUS·BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) VCC = 4.5 V 130 Ω ______ P00–P02, P04–P07 Notes 1: 2: 3: 4: The total current that flows out of the IC must be 20 or less. The total input current to IC (IOL1 + IOL2 + IOL3) must be 20 mA or less. The total average input current for ports P30, P31 to IC must be 10 mA or less. Connect 0.1 µF or more capacitor externally across the power source pins VCC–VSS and AVCC–VSS so as to reduce power source noise. Also connect 0.1 µF or more capacitor externally across the pins VCC–CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6: P16, P41–P44 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P17 and P46 have the hysteresis when these pins are used as serial I/O pins. 7: When using the sub-clock, set fCLK < fCPU/3. 87 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER A-D CONVERTER CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Symbol — Resolution — Non-linearity error — Differential non-linearity error Limits Test conditions Parameter VOT Zero transition error VCC = 5.12V IOL (SUM) = 0mA VFST Full-scale transition error VCC = 5.12V TCONV Conversion time VREF Reference voltage RLADDER Ladder resistor VIA Analog input current Min. Typ. Max. Unit 8 bits 0 ±2 LSB 0 ±0.9 LSB 0 2 LSB 4 LSB 0 12.25 12.5 µs VCC V kΩ 25 0 VREF V MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Symbol Standard clock mode High-speed clock mode Parameter Min. Max. Max. Min. Unit tBUF Bus free time 4.7 1.3 µs tHD:STA Hold time for START condition 4.0 0.6 µs tLOW “L” period of SCL clock 4.7 1.3 µs tR Rising time of both SCL and SDA signals tHD:DAT Data hold time tHIGH “H” period of SCL clock 1000 20+0.1Cb 300 ns 0 0 0.9 µs 4.0 0.6 300 µs tF 300 Falling time of both SCL and SDA signals tSU:DAT Data set-up time 250 100 ns tSU:STA Set-up time for repeated START condition 4.7 0.6 µs tSU:STO Set-up time for STOP condition 4.0 0.6 µs 20+0.1Cb Note: Cb = total capacitance of 1 bus line SDA tHD:STA tBUF tLOW p tR tF Sr S SCL tHD:STA tHD:DAT tHIGH tSU:DAT Fig. 100. Definition diagram of timing on multi-master I2C-BUS 88 tSU:STO tSU:STA p ns MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PACKAGE OUTLINE 89 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–44B < 5ZA0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37271MF-XXXSP MITSUBISHI ELECTRIC Receipt Date : Section head signature Supervisor signature Note : Please fill in all items marked *. Date issued Date : ) Issuance ( Customer Supervisor signature * Submitted by TEL Company name * 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) EPROM type (indicate the type used) 27C101 EPROM address 0000016 Product name 0000F16 01000 16 0FFFF 16 10800 16 ASCII code : ‘M37271MF –’ data ROM 60K bytes OSD ROM 1E43F16 (1) (2) Set “FF 16” in the shaded area. Write the ASCII codes that indicates the product name of “M37271MF–” to addresses 0000 16 to 000F 16. EPROM data check item (Refer the EPROM data and check “ ” in the appropriate box) ● Do you set “FF 16” in the shaded area ? → Yes ● Do you write the ASCII codes that indicates the product → Yes name of “M37271MF–” to addresses 0000 16 to 000F 16 ? * 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (52P4B for M37271MF-XXXSP) and attach to the mask ROM confirmation form. 90 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–44B < 5ZA0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37271MF-XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 00000 16 to 0000F 16 store the product name, and addresses 10800 16 to 1E43F 16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly. 1. Inputting the name of the product with the ASCII code ASCII codes ‘M37271MF-’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = ‘3’ = ‘7’ = ‘2’ = ‘7’ = ‘1’ = ‘M’ = ‘F’ = 4D 33 37 32 37 31 4D 46 16 16 16 16 16 16 16 16 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘–’ = 2 D FF FF FF FF FF FF FF 16 16 16 16 16 16 16 16 2. Inputting the character ROM Input the character ROM data to character ROM. For the character ROM data, see the next page and on. 91 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–44B < 5ZA0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37271MF-XXXSP MITSUBISHI ELECTRIC Font data must be stored in the proper OSD ROM address according to the following table. (1)OSD ROM address of character font data OSD ROM address bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Line number / Character code / Font bit 1 0 Line number Font bit Character code Line number = 02 16 to 1516 Character code = 00 16 to 13F 16 Font bit = 0 : Left font 1 : Right font Example) The font data “60” (shaded area ) of the character code “AA 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 2 16” is stored in address =12954 16. (2)OSD ROM address of extra font data AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 OSD ROM address bit Line number / Extra code / Font bit 1 1 Line number 0 0 0 Font bit Extra code 0 Line number = 00 16 to 19 16 Extra code = 00 16 to 1F 16 Font bit = 0 : Left font 1 : Right font Example) The font data “03” (shaded area ) of the extra code “0A 1 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 2 16” is stored in address =19415 16. Left font Right font DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Left font Right font DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Line number 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 (1) Character code “AA 16” Line number 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0016 0016 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 (2) Extra code “0A 16” (3/4) 92 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–44B < 5ZA0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37271MF-XXXSP MITSUBISHI ELECTRIC The following OSD ROM addresses must be set “FF.” There are no font data in these addresses. 10A8016 to 10BFF 16 13280 16 to 133FF 16 18040 16 to 183FF 16 1B04016 to 1B3FF 16 10E8016 to 10FFF 16 13680 16 to 137FF 16 18440 16 to 187FF 16 1B44016 to 1B7FF 16 11280 16 to 113FF 16 13A8016 to 13BFF 16 18840 16 to 18BFF 16 1B84016 to 1BBFF 16 11680 16 to 117FF 16 13E8016 to 13FFF 16 18C40 16 to 18FFF 16 1BC4016 to 1BFFF 16 11A8016 to 11BFF 16 14280 16 to 143FF 16 19040 16 to 193FF 16 1C04016 to 1C3FF 16 11E8016 to 11FFF 16 14680 16 to 147FF 16 19440 16 to 197FF 16 1C44016 to 1C7FF 16 12280 16 to 123FF 16 14A8016 to 14BFF 16 19840 16 to 19BFF 16 1C84016 to 1CBFF 16 12680 16 to 127FF 16 14E8016 to 14FFF 16 19C40 16 to 19FFF 16 1CC4016 to 1CFFF 16 12A8016 to 12BFF 16 15280 16 to 153FF 16 1A040 16 to 1A3FF 16 1D04016 to 1D3FF 16 12E8016 to 12FFF 16 15680 16 to 17FFF 16 1A440 16 to 1A7FF 16 1D44016 to 1D7FF 16 1A840 16 to 1ABFF 16 1D84016 to 1DBFF 16 1AC40 16 to 1AFFF 16 1DC4016 to 1DFFF 16 1E04016 to 1E3FF 16 93 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 52P4B (52-PIN SHRINK DIP) MARK SPECIFICATION FORM 94 MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER SHRINK DIP MARK SPECIFICATION FORM for one time PROM version microcomputers 95 Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials • • • • • • © 1997 MITSUBISHI ELECTRIC CORP. New publication, effective Nov. 1997. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP Revision Description DATA SHEET Rev. date 1.0 First Edition 9708 2.0 Information about copyright note, revision number, release date added (last page). 971130 (1/1)