AD AD1864P Complete dual 18-bit audio dac Datasheet

a
Complete Dual
18-Bit Audio DAC
AD1864
FEATURES
Dual Serial Input, Voltage Output DACs
No External Components Required
Operates at 8 3 Oversampling per Channel
65 V to 612 V Operation
Cophased Outputs
115 dB Channel Separation
60.3% Interchannel Gain Matching
0.0017% THD+N
DIP BLOCK DIAGRAMS
The AD1864 is a complete dual 18-bit DAC offering excellent
THD+N, while requiring no external components. Two complete signal channels are included. This results in cophased
voltage or current output signals and eliminates the need for
output demultiplexing circuitry. The monolithic AD1864 chip
includes CMOS logic elements, bipolar and MOS linear
elements and laser-trimmed thin-film resistor elements, all
fabricated on Analog Devices BiMOS II process.
The DACs on the AD1864 chip employ a partially-segmented
architecture. The first four MSBs of each DAC are segmented
into 15 elements. The 14 LSBs are produced using standard
R-2R techniques. Segment and R-2R resistors are lasertrimmed to provide extremely low total harmonic distortion.
This architecture minimizes errors at major code transitions
resulting in low output glitch and eliminating the need for an
external deglitcher. When used in the current output mode, the
AD1864 provides two cophased ± 1 mA output signals.
Each channel is equipped with a high performance output
amplifier. These amplifiers achieve fast settling and high slew
rate, producing ± 3 V signals at load currents up to 8 mA. Each
output amplifier is short-circuit protected and can withstand
indefinite short circuits to ground.
The AD1864 was designed to balance two sets of opposing
requirements, channel separation and DAC matching. High
channel separation is the result of careful layout techniques. At
the same time, both channels of the AD1864 have been designed
to ensure matched gain and linearity as well as tracking over time
and temperature. This assures optimum performance when used in
stereo and multi-DAC per channel applications.
1
2
24 +VS
AD1864
23
REFERENCE
APPLICATIONS
Multichannel Audio Applications:
Compact Disc Players
Multivoice Keyboard Instruments
DAT Players and Recorders
Digital Mixing Consoles
Multimedia Workstations
PRODUCT DESCRIPTION
–VS
TRIM
TRIM
REFERENCE
22 MSB
MSB
3
I OUT
4
21 I OUT
AGND
5
20
SJ
6
19 SJ
AGND
18 R F
RF
7
VOUT
8
+VL
9
16
–V L
DR 10
15
DL
LR
11
–
+
18-BIT
LATCH
–
+
18-BIT
D/A
CLK 12
18-BIT
D/A
18-BIT
LATCH
17 VOUT
14 LL
13
DGND
A versatile digital interface allows the AD1864 to be directly
connected to standard digital filter chips. This interface employs
five signals: Data Left (DL), Data Right (DR), Latch Left (LL),
Latch Right (LR) and Clock (CLK). DL and DR are the serial
input pins for the left and right DAC input registers. Input data
bits are clocked into the input register on the rising edge of
CLK. A low going latch edge updates the respective DAC
output. For systems using only a single latch signal, LL and LR
may be connected together. For systems using only one DATA
signal, DR and DL may be connected together.
The AD1864 operates from ± 5 V to ± 12 V power supplies. The
digital supplies, VL and –VL, can be separated from the analog
supplies, VS and –VS, for reduced digital feedthrough. Separate
analog and digital ground pins are also provided. The AD1864
typically dissipates only 225 mW, with a maximum power
dissipation of 265 mW.
The AD1864 is packaged in both a 24-pin plastic DIP and a
28-pin PLCC. Operation is guaranteed over the temperature
range of –25°C to +70°C and over the voltage supply range of
± 4.75 V to ± 13.2 V.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
The AD1864 is a complete dual 18-bit audio DAC.
108 dB signal-to-noise ratio for low noise operation.
THD+N is typically 0.0017%.
Interchannel gain and midscale matching.
Output voltages and currents are cophased.
Low glitch for improved sound quality.
Both channels are 100% tested at 8 × FS.
8. Low Power—only 225 mW typ, 265 mW max.
9. Five-wire Interface for individual DAC control.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
(TA = +258C, 6VL = 6VS = 65 V, FS = 352.8 kHz, without MSB adjustment
AD1864–SPECIFICATIONS unless otherwise noted)
Min
Typ
RESOLUTION
DIGITAL INPUTS
VIH
VIL
IIH, VIH = +VL
IIL, VIL = 0.4 V
Clock Input Frequency
Max
18
Bits
2.0
+VL
0.8
1.0
–10
V
V
µA
µA
MHz
1.0
0.8
% of FSR
% of FSR
mV
mV
dB
12.7
ACCURACY
Gain Error
Interchannel Gain Matching
Midscale Error
Interchannel Midscale Matching
Gain Linearity Error (0 dB to –90 dB)
0.4
0.3
4
5
<2
DRIFT (0°C to +70°C)
Gain Drift
Midscale Drift
± 25
±4
TOTAL HARMONIC DISTORTION + NOISE*
0 dB, 990.5 Hz
AD1864N, P
AD1864N-J, P-J
AD1864N-K
—20 dB, 990.5 Hz
AD1864N, P
AD1864N-J, P-J
AD1864N-K
—60 dB, 990.5 Hz
AD1864N, P
AD1864N-J, P-J
AD1864N-K
0.004
0.003
0.0017
0.010
0.010
0.010
1.0
1.0
1.0
Units
ppm of FSR/°C
ppm of FSR/°C
0.006
0.004
0.0025
0.040
0.020
0.020
4.0
2.0
2.0
%
%
%
%
%
%
%
%
%
CHANNEL SEPARATION*
0 dB, 990.5 Hz
110
115
dB
SIGNAL-TO-NOISE RATIO*
(20 Hz to 30 kHz) N, N-J, N-K
P, P-J
102
95
108
108
dB
dB
D-RANGE* (WITH A-WEIGHT FILTER)
–60 dB, 990.5 Hz
AD1864N, P
AD1864N-J, P-J
AD1864N-K
88
94
94
100
100
100
dB
dB
dB
62.88
± 3.0
0.1
OUTPUT
Voltage Output Configuration
Output Range (± 3%)
Output Impedance
Load Current
Short-Circuit Duration
Current Output Configuration
Bipolar Output Range (± 30%)
Output Impedance (± 30%)
POWER SUPPLY
+VL and +VS
–VL and –VS
+I, (+VL and +VS = +5 V)
–I, (–VL and –VS = –5 V)
±8
63.12
V
Ω
mA
Indefinite to Common
±1
1.7
4.75
–13.2
POWER DISSIPATION, ± VL = ± VS = ± 5 V
TEMPERATURE RANGE
Specification
Operation
Storage
0
–25
–60
WARM-UP TIME
1
mA
kΩ
5.0
–5.0
22
–23
13.2
–4.75
25
–28
V
V
mA
mA
225
265
mW
+25
+70
+70
+100
°C
°C
°C
min
NOTES
Specifications shown in boldface are tested on production units at final test without optional MSB adjustment.
*Tested in accordance with EIAJ Test Standard CP-307 with 18-bit data.
Specifications subject to change without notice.
–2–
REV. A
Typical Performance Data—AD1864
700
100
0dB
90
600
POWER DISSIPATION – mW
–20dB
80
THD+N – dB
70
60
50
–60dB
40
30
500
400
300
200
20
100
10
0
0
0
2
4
6
FREQUENCY – kHz
8
0
10
8
10
SUPPLY VOLTAGE – +V
12
Figure 4. Power Dissipation vs. Supply Voltage
Figure 1. THD+N vs. Frequency
130
100
120
90
110
80
100
70
90
80
THD+N – dB
CHANNEL SEPARATION – dB
6
70
60
60
50
40
50
40
30
30
20
20
10
10
0
5
0
10
0
500
15
1000
FREQUENCY – kHz
1500
2000
2500
3000
LOAD RESISTANCE – Ω
Figure 5. THD+N vs. Load Resistance
Figure 2. Channel Separation vs. Frequency
10
100
GAIN LINEARITY ERROR – dB
8
THD+N – dB
95
90
85
6
4
2
0
–2
–4
–6
–8
–10
80
0
20
40
TEMPERATURE – C
–100
60
–80
–70
–40 –30
–60 –50
INPUT AMPLITUDE – dB
–20
–10
0
Figure 6. Gain Linearity Error vs. Input Amplitude
Figure 3. THD+N vs. Temperature
REV. A
–90
–3–
AD1864
ABSOLUTE MAXIMUM RATINGS*
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 13.2 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 13.2 V
–VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –13.2 V to 0 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –13.2 V to 0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VL
Short-Circuit Protection . . . . . . . . Indefinite Short to Ground
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1864 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
DIP Package
1
24 +VS
TRIM
2
23 TRIM
MSB
3
22 MSB
I OUT
4
21 I OUT
AGND
5
RIGHT
CHANNEL
SJ
LEFT
CHANNEL
20 AGND
6
AD1864
19 SJ
TOP VIEW
(Not to Scale)
18 R F
RF
7
V OUT
8
17 VOUT
+VL
9
16 –V L
DR 10
15 DL
LR 11
14 LL
13 DGND
CLK 12
TRIM
–VS
NC
+VS
TRIM
MSB
MSB
PLCC Package
4
3
2
1
28 27
26
I OUT 5
Signal
Description
–VS
TRIM
MSB
IOUT
AGND
SJ
RF
VOUT
+VL
DR
LR
CLK
DGND
LL
DL
–VL
VOUT
RF
SJ
AGND
IOUT
MSB
TRIM
+VS
Negative Analog Supply
Right Channel Trim Network Connection
Right Channel Trim Potentiometer Connection
Right Channel Output Current
Right Channel Analog Common Pin
Right Channel Amplifier Summing Junction
Right Channel Feedback Resistor
Right Channel Output Voltage
Positive Digital Supply
Right Channel Data Input Pin
Right Channel Latch Pin
Clock Input Pin
Digital Common Pin
Left Channel Latch Pin
Left Channel Data Input Pin
Negative Digital Supply
Left Channel Output Voltage
Left Channel Feedback Resistor
Left Channel Amplifier Summing Junction
Left Channel Analog Common Pin
Left Channel Output Current
Left Channel Trim Potentiometer Wiper Connection
Left Channel Trim Network Connection
Positive Analog Supply
25 I OUT
24 AGND
AGND 6
SJ 7
AD1864
23 SJ
NC 8
TOP VIEW
(Not to Scale)
22 NC
RF
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
–V S
WARNING!
9
ORDERING GUIDE
21 RF
VOUT 10
20 VOUT
19 –VL
17
18
LL
DL
16
DGND
LR
14 15
NC
13
CK
12
DR
+VL 11
Model
THD+N
@ Full Scale
Package
Option*
AD1864N
AD 1864N-J
AD1864N-K
AD1864P
AD1864P-J
0.006%
0.004%
0.0025%
0.006%
0.004%
N-24
N-24
N-24
P-28A
P-28A
*N = Plastic DIP; P = Plastic Leaded Chip Carrier.
NC = NO CONNECT
–4–
REV. A
AD1864
TOTAL HARMONIC DISTORTION + NOISE
INTERCHANNEL MIDSCALE MATCHING
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the
amplitudes of the harmonics and noise to the value of the
fundamental input frequency. It is usually expressed in percent.
The midscale matching specification indicates how closely the
amplitudes of the output signals of the two channels match
when the twos complement input code representing half scale is
loaded into the input register of both channels. It is expressed in
mV and is measured with half-scale output signals.
THD+N is a measure of the magnitude and distribution of
linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending
on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small (–20 dB, –60 dB) signal amplitudes. THD+N measurements for the AD1864 are made using the first 19 harmonics
and noise out to 30 kHz.
The Signal-to-Noise Ratio is defined as the ratio of the amplitude of the output when a full- scale code is entered to the
amplitude of the output when a midscale code is entered. It is
measured using a standard A-Weight filter. SNR for the
AD1864 is measured for noise components up to 30 kHz.
D-Range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
60 dB below full-scale is reproduced. D-Range is tested with a
1 kHz input sine wave. This is measured with a standard
A-Weight filter as specified by EIAJ Standard CP-307.
GAIN ERROR
The gain error specification indicates how closely the output of
a given channel matches the ideal output for given input data. It
is expressed in % of FSR and is measured with a full-scale output
signal.
INTERCHANNEL GAIN MATCHING
The gain matching specification indicates how closely the
amplitudes of the output signals match when producing
identical input data. It is expressed in % of FSR (Full-Scale
Range = 6 V for the AD1864) and is measured with full-scale
output signals.
2
MSB
3
24 +VS
AD1864
23
TRIM
REFERENCE
22 MSB
I OUT
4
21 I OUT
AGND
5
20
SJ
6
19 SJ
RF
7
VOUT
8
+VL
9
DR 10
LR
11
AGND
18 R F
–
+
–
+
17 VOUT
16 –V L
18-BIT
LATCH
18-BIT
D/A
18-BIT
D/A
18-BIT
LATCH
15
DL
14 LL
13
CLK 12
CHANNEL SEPARATION
D-RANGE DISTORTION
1
REFERENCE
SIGNAL-TO-NOISE RATIO
Channel separation is defined as the ratio of the amplitude of a
full-scale signal appearing on one channel to the amplitude of
that same signal which couples onto the adjacent channel. It is
usually expressed in dB. For the AD1864 channel separation is
measured in accordance with EIAJ Standard CP-307, Section 5.5.
–VS
TRIM
DGND
DIP Block Diagram
FUNCTIONAL DESCRIPTION
The AD1864 is a complete, monolithic, dual 18-bit audio DAC.
No external components are required for operation. As shown in
the block diagram, each chip contains two voltage references,
two output amplifiers, two 18-bit serial input registers and two
18-bit DACs.
The voltage reference section provides a reference voltage for
each DAC circuit. These voltages are produced by low-noise
bandgap circuits. Buffer amplifiers are also included. This
combination of elements produces reference voltages that are
unaffected by changes in temperature and time.
The output amplifiers use both MOS and bipolar devices and
incorporate an all NPN output stage. This design technique
produces higher slew rate and lower distortion than previous
techniques. Frequency response is also improved. When
combined with the appropriate on-chip feedback resistor, the
output op amps convert the output current to output voltages.
MIDSCALE ERROR
The 18-bit D/A converters use a combination of segmented
decoder and R-2R architecture to achieve consistent linearity
and differential linearity. The resistors which form the ladder
structure are fabricated with silicon chromium thin film. Laser
trimming of these resistors further reduces linearity errors
resulting in low output distortion.
Midscale error is the deviation of the actual analog output of a
given channel from the ideal output (0 V) when the twos complement input code representing half scale is loaded into the input
register of the DAC. It is expressed in mV.
The input registers are fabricated with CMOS logic gates.
These gates allow the achievement of fast switching speeds and
low power consumption, contributing to the low glitch and low
power dissipation of the AD1864.
REV. A
–5–
AD1864
Though separate positive and negative power supply pins are
provided for the analog and digital portions of the AD1864, it is
also possible to use the AD1864 in systems featuring a single
positive and a single negative power supply. In this case, the
+VS and +VL input pins should be connected to the positive
power supply. –VS and –VL should be connected to the single
negative supply. This feature allows reduction of the cost and
complexity of the system power supply.
GROUNDING RECOMMENDATIONS
The AD1864 has three ground pins, two labeled AGND and
one labeled DGND. AGND, the analog ground pins, are the
“high quality” ground references for the device. To minimize
distortion and reduce crosstalk between channels, the analog
ground pins should be connected together only at the analog
common point in the system. As shown in Figure 7, the AGND
pins should not be connected at the chip.
–ANALOG
SUPPLY
1
–VS
2
TRIM
4 I OUT
I OUT 21
7 RF
The THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD+N specification, therefore,
provides a direct method to classify and choose an audio DAC
for a desired level of performance. Figure 1 illustrates the typical
THD+N performance of the AD1864 versus frequency. A load
impedance of at least 1.5 kΩ is recommended for best THD+N
performance.
SJ 19
R F 18
VOUT 17
9 +VL
–V L 16
10 DR
DL 15
11 LR
DISTORTION PERFORMANCE AND TESTING
AGND 20
8 VOUT
12 CLK
ANALOG
SUPPLY
TRIM 23
MSB 22
6 SJ
DIGITAL
SUPPLY
+VS 24
3 MSB
5 AGND
VOUT
As with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be
incorporated into the design of an audio system.
AD1864
VOUT
–DIGITAL
SUPPLY
LL 14
Analog Devices tests and grades all AD1864s on the basis of
THD+N performance. During the distortion test, a high speed
digital pattern generator transmits digital data to each channel
of the device under test. Eighteen-bit data is latched into the
DAC at 352.8 kHz (8 × FS). The test waveform is a 990.5 kHz
sine wave with 0 dB, –20 dB and –60 dB amplitudes. A 4096
point FFT calculates total harmonic distortion + noise,
signal-to-noise ratio, D-Range and channel separation. No
deglitchers or MSB trims are used.
DGND 13
DIGITAL
COMMON
Figure 7. Recommended DIP Circuit Schematic
The digital ground pin returns ground current from the digital
logic portions of the AD1864 circuitry. This pin should be
connected to the digital common pin in the system. Other
digital logic chips should also be referred to that point. The
analog and digital grounds should be connected together at one
point in the system, preferably at the power supply.
OPTIONAL MSB ADJUSTMENT
Use of optional adjust circuitry allows residual distortion error
to be eliminated. This distortion is especially important when
low amplitude signals are being reproduced. The MSB adjust
circuitry is shown in Figure 8. The trim pot should be adjusted
to produce the lowest distortion using an input signal with a
–60 dB amplitude.
POWER SUPPLIES AND DECOUPLING
The AD1864 has four power supply pins. ± VS provides the
supply voltages that operate the analog portions of the DAC,
including the voltage references, output amplifiers and control
amplifiers. The ± VS supplies are designed to operate from ± 5 V
to ± 12 V. These supplies should be decoupled to analog
common using 0.1 µF capacitors. Good engineering practice
suggests that the bypass capacitors be placed as close as possible
to the package pins. This minimizes the parasitic inductive
effects of printed circuit board traces.
AD1864
200kΩ 100kΩ
1
–VS
+VS 24
2
TRIM
TRIM 23
470kΩ
470kΩ 100kΩ 200kΩ
3 MSB
The ± VL supplies operate the digital portions of the chip,
including the input shift registers and the input latching
circuitry. These supplies should be bypassed to digital common
using 0.1 µF capacitors. ± VL operates with ± 5 V to ± 12 V
supplies. In order to assure proper operation of the AD1864,
–VS must be the most negative power supply voltage at all times.
4 I OUT
5 AGND
MSB 22
I OUT 21
AGND 20
6 SJ
SJ 19
7 RF
R F 18
8 V OUT
V OUT 17
9 +VL
–V L 16
10 DR
DL 15
11 LR
LL 14
12 CLK
DGND 13
Figure 8. Optional DIP THD+N Adjust Circuitry
–6–
REV. A
AD1864
CURRENT OUTPUT MODE
One or both channels of the ADl864 can be operated in current
output mode. IOUT can be used to directly drive an external
current-to-voltage (I-V) converter. The internal feedback
resistor, RF, can still be used in the feedback path of the external
I-V converter, thus assuring that RF tracks the DAC over time
and temperature.
Of course, the AD1864 can also be used in voltage output mode
utilizing the onboard I-V converter.
VOLTAGE OUTPUT MODES As shown in the ADl864
block diagram, each channel of the ADl864 is complete with an
I-V converter and a feedback resistor. These can be connected
externally to provide direct voltage output from one or both
AD1864 channels. Figure 7 shows these connections. IOUT is
connected to the summing junction, SJ. VOUT is connected to
the feedback resistor, RF. This implementation results in the
lowest possible component count and achieves the performance
shown on the specifications page while operating at 8 × FS.
INPUT DATA
Data is transmitted to the AD1864 in a bit stream composed of
18-bit words with a serial, twos complement, MSB first format.
Data Left (DL) and Data Right (DR) are the serial inputs for
the left and right DACs, respectively. Similarly, Latch Left (LL)
and Latch Right (LR) update the left and right DACs. The
falling edges of LL and LR cause the last 18 bits clocked into
the Serial Registers to be shifted into the DACs, thereby
updating the DAC outputs. Left and Right channels share the
Clock (CLK) signal. Data is clocked into the input registers on
the rising edge of CLK.
Figure 9 illustrates the general signal requirements for data
transfer for the AD1864.
CLK
DL
M
S
B
L
S
B
DR
M
S
B
L
S
B
LL
LR
Figure 9. Control Signals
TIMING
Figure 10 illustrates the specific timing requirements that must
be met in order for the data transfer to be properly accomplished.
The input pins of the AD1864 are both TTL and 5 V CMOS
compatible.
The minimum clock rate of the AD1864 is at least 12.7 MHz.
This clock rate allows data transfer rates of 2×, 4×, 8× and
16 × FS (where FS equals 44.1 kHz). The applications section
of this data sheet contains additional guidelines for using the
AD1864.
>80ns
>30ns
>30ns
CLK
>60ns
>40ns
>15ns
>40ns
LL/LR
>40ns
>15ns >15ns
DL/DR
MSB
1st BIT
INTERNAL DAC REGISTER
UPDATED WITH 18 MOST RECENT BITS
LSB
(18th BIT)
2nd BIT
NEXT
WORD
BITS CLOCKED
TOSHIFT REGISTER
Figure 10. Timing Diagram
REV. A
–7–
AD1864
+5V ANALOG SUPPLY
–5V ANALOG SUPPLY
AD1864
1
SM5813AP/A
28
PT
2
27
2 TRIM
TRIM 23
3
BCKO 26
3 MSB
MSB 22
4
WCKO 25
5
DOL 24
5 AGND
6
DOR 23
6 SJ
SJ 19
1
+VS 8
7
VDD 22
7 RF
R F 18
2
7
VOUT 17
3
6
–VL 16
4
8
VSS1
VSS2
1
C1
4 I OUT
8 VOUT
21
9
DG 20
10
19
11
18
12
OW18 17
13
OW20 16
14
15
–VS
9 +V L
10 DR
11 LR
12 CLK
+5V DIGITAL SUPPLY
+VS 24
I OUT
LEFT
CHANNEL
OUTPUT
C2
21
AGND 20
–VS
RIGHT
CHANNEL
OUTPUT
5
AD712
OR
NE5532
DL 15
LL 14
DGND 13
–5V DIGITAL SUPPLY
Figure 11. Complete 8 × FS 18-Bit CD Player
An AD712 or NE5532 dual op amp is used to provide the
output antialias filters required for adequate image rejection.
One 2-pole filter section is provided for each channel. An
additional pole is created from the combination of the internal
feedback resistors (RF) and the external capacitors C1 and C2.
For example, the nominal 3 kΩ RF with a 360 pF capacitor for
C1 and C2 will place a pole at approximately 147 kHz, effectively eliminating all high frequency noise components.
8-BIT CD PLAYER DESIGN
Figure 11 illustrates an 18-bit CD player design incorporating
an AD1864 D/A converter, an AD712 or NE5532 dual op amp
and the SM5813 digital filter chip manufactured by NPC. In
this design, the SM5813 filter transmits left and right digital
data to both channels of the AD1864. The left and right latch
signals, LL and LR, are both provided by the word clock signal
(WCKO) of the digital filter. The digital filter supplies data at
an 8 × FS oversample rate to each channel.
Close matching of the ac characteristics of the amplifiers on the
AD712 as well as their low distortion make it an ideal choice for
the task.
The digital data is converted to analog output voltages by the
output amplifiers on the AD1864. Note that no external
components are required by the AD1864. Also, no deglitching
circuitry is required.
LOW distortion, superior channel separation, low power
consumption and a low component count are all realized by this
simple design.
–8–
REV. A
AD1864
VOICE 1
OUTPUT
VOICE 2
OUTPUT
VOICE 4
OUTPUT
VOICE 3
OUTPUT
VOICE 5
OUTPUT
VOICE 6
OUTPUT
+5V ANALOG
SUPPLY
–5V ANALOG
SUPPLY
AD1864
AD1864
1 –VS
VOICE 1 LOAD
1 –VS
TRIM 23
2
3 MSB
MSB 22
4 I OUT
I OUT 21
2
ANALOG
COMMON
+VS 24
TRIM
5 AGND
AGND 20
AD1864
+VS 24
1 –VS
TRIM 23
2
3 MSB
MSB 22
3 MSB
4 I OUT
I OUT 21
4 I OUT
TRIM
5 AGND
AGND 20
TRIM
5 AGND
6 SJ
SJ 19
6 SJ
SJ 19
6 SJ
7 RF
R F 18
7 RF
R F 18
7 RF
8 V OUT
V OUT 17
8 VOUT
VOUT 17
+VS
24
TRIM 23
MSB 22
I OUT 21
AGND 20
SJ 19
R F 18
8 VOUT
VOUT 17
–V L 16
9 +VL
–V L 16
9 +VL
–V L 16
9 +VL
10 DR
DL 15
10 DR
DL 15
10 DR
DL 15
11 LR
LL 14
11 LR
LL 14
11 LR
LL 14
12 CLK
DGND 13
12 CLK
DGND 13
12 CLK
VOICE 6 LOAD
DGND 13
VOICE 2 LOAD
VOICE 5 LOAD
VOICE 3 LOAD
VOICE 4 LOAD
DATA
CLOCK
DIGITAL COMMON
–5V DIGITAL COMMON
+5V DIGITAL COMMON
Figure 12. Cascaded AD1864s in a Multichannel Keyboard Instrument
MULTICHANNEL DIGITAL KEYBOARD DESIGN
Figure 12 illustrates how to cascade AD1864s to add multiple
voices to an electronic musical instrument. In this example, the
data and clock signals are shared between all six DACs. As the
data representing an output for a specific voice is loaded, the
appropriate DAC is updated. For example, after the 18 bits
representing the next output value for Voice #4 is clocked out
on the data line, then “Voice 4 Load” is pulled low. This produces
a new output for Voice 4. Furthermore, all voices can be
returned to the same output by pulling all six load signals low.
In this application, the advantages of choosing the AD1864 are
clear. Its flexible digital interface allows the clock and data to
be shared among all DACs. This reduces printed circuit board
area requirements and also simplifies the actual layout of the
board. The low power requirement of the AD1864 (typically
215 mW) is an advantage in a multiple DAC system where its
power advantage is multiplied by the number of DACs used.
REV. A
The AD1864 requires no external components, simplifying the
design, reducing the total number of components required and
enhancing reliability.
ADDITIONAL APPLICATIONS
Figures 13 through 16 show connection diagrams for the
AD1864 and a number of standard digital filter chips from
Yamaha, NPC and Sony. Figure 13 shows the SM5814AP
operating with pipelined data. Cophase operation is not
available with the SM5814AP in 18-bit mode. Figures 14
through 16 are all examples of cophase operation. Each
application operates at 8 × FS for each channel. The 2-pole
Rauch low-pass filters shown in Figure 11 can be used with all
of the applications shown in this data sheet. The AD711 single
op amp can also be used in these applications in order to ensure
maximum channel separation.
–9–
AD1864
–5V ANALOG
SUPPLY
+5V ANALOG
SUPPLY
AD1864
1
SM5814AP
(22-PIN DIP)
+VS 24
–V S
1
22
21
2
3
20
3 MSB
MSB 22
4
SOMD1 19
4 I OUT
I OUT 21
5
SOMD2 18
5
2
TRIM
AGND
6 SJ
SJ 19
7
BCKO 16
7 RF
R F 18
8
WDCO 15
8 VOUT
V OUT 17
9
DOR 14
9 +VL
–V L 16
10
DOL 13
10 DR
DL 15
11
DGL 12
VSS
LPF
LEFT
CHANNEL
OUTPUT
LL 14
11 LR
12 CLK
RIGHT
CHANNEL
OUTPUT
AGND 20
VDD 17
6
LPF
TRIM 23
DGND 13
+5V DIGITAL
SUPPLY
–5V DIGITAL
SUPPLY
Figure 13. AD1864 with NPC SM5814AP Digital Filter
–5V ANALOG
SUPPLY
+5V ANALOG
SUPPLY
AD1864
1
–VS
2
TRIM
3 MSB
MSB 22
4 I OUT
I
5 AGND
YM3434
+VS 24
TRIM 23
OUT
SJ 19
2
16/18 15
7 RF
R F 18
3
ST 14
8 VOUT
V OUT 17
–V L 16
V SS 13
9 +VL
BCO 12
10 DR
DL 15
6
WCO 11
11 LR
LL 14
7
DRO 10
12 CLK
8 V DD1
DLO
5
LPF
LEFT
CHANNEL
OUTPUT
AGND 20
6 SJ
4 V DD2
RIGHT
CHANNEL
OUTPUT
21
SHR 16
1 SHL
LPF
DGND 13
9
+5V DIGITAL
SUPPLY
–5V DIGITAL
SUPPLY
Figure 14. AD1864 with Yamaha YM3434 Digital Filter
–10–
REV. A
AD1864
1
GND
TEST 40
2
TEST
TEST 39
3
TEST 38
4
TEST 37
5
6
16.9344
MHz
CXD1244S
+5V ANALOG
SUPPLY
–5V ANALOG
SUPPLY
AD1864
36
1
35
2 TRIM
TRIM 23
3 MSB
MSB 22
4 I OUT
I OUT 21
7
34
8
BCKO 33
+VS 24
–VS
XIN
DATAL 32
10 VDD
GND 31
6 SJ
SJ 19
11 VDD
GND 30
7 RF
R F 18
9
5
AGND
DATAR 29
8 VOUT
VOUT 17
13
28
9 +VL
–V L 16
14
LE/WS 27
10 DR
DL 15
15
OUT 16/18 26
11 LR
LL 14
25
RIGHT
CHANNEL
OUTPUT
LPF
LEFT
CHANNEL
OUTPUT
AGND 20
12
16
LPF
DGND 13
12 CLK
DPOL 24
17 LFS
23
18 SONY/12S
19
TEST 22
20 TEST
TEST 21
+5V DIGITAL
SUPPLY
–5V DIGITAL
SUPPLY
Figure 15. AD1864 with Sony CXD1244S Digital Filter
–5V ANALOG
SUPPLY
+5V ANALOG
SUPPLY
AD1864
+VS 24
1 –VS
2 TRIM
TRIM 23
3 MSB
MSB 22
4 I OUT
SM5818AP
(16-PIN DIP)
5 AGND
I
OUT
VDD 16
6 SJ
SJ 19
BCKO 15
7 RF
R F 18
WDCO 14
8 VOUT
V OUT 17
13
9 +VL
–V L 16
5
DOR 12
10 DR
DL 15
6
DOL 11
11 LR
LL 14
7
10
OMOD2
8
VSS
12 CLK
LPF
LEFT
CHANNEL
OUTPUT
21
2
3
RIGHT
CHANNEL
OUTPUT
AGND 20
1
4
LPF
DGND 13
OMOD1 9
+5V DIGITAL
SUPPLY
–5V DIGITAL
SUPPLY
Figure 16. AD1864 with NPC SM5818AP Digital Filter
REV. A
–11–
AD1864
C1405c–1–6/97
OTHER DIGITAL AUDIO COMPONENTS AVAILABLE
FROM ANALOG DEVICES
AD1856 16-BIT AUDIO DAC
AD1860 18-BIT AUDIO DAC
AD1862 20-BIT AUDIO DAC
Complete, No External Components
Required
0.0025% THD
Low Cost
16-Pin DIP or SOIC Package
Standard Pinout
Complete, No External Components
Required
0.002% THD+N
108 dB Signal-to-Noise Ratio
16-Pin DIP or SOIC Package
Standard Pinout
120 dB Signal-to-Noise Ratio
0.0012% THD+N
105 dB D-Range Performance
± 1 dB Gain Linearity
16-Pin DIP
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
PRINTED IN U.S.A.
24-Pin Plastic DIP
28-Pin PLCC
–12–
REV. A