-55LL/70LL/10LL
CXK581000ATM/AYM/AM/AP -55SL/70SL/10SL
131072-word × 8-bit High Speed CMOS Static RAM
For the availability of this product, please contact the sales office.
Description
The CXK581000ATM/AYM/AM/AP is a high speed
CMOS static RAM organized as 131072-words by
8 bits.
A polysilicon TFT cell technology realized extremely low
stand- by current and higher data retention stability.
Special feature are low power consumption, high
speed and broad package line-up.
The CXK581000ATM/AYM/AM/AP ia a suitable
RAM for portable equipment with battery back up.
Features
• Fast access time:
CXK581000ATM/AYM/AM/AP
(Access time)
-55LL/55SL
55ns (Max.)
-70LL/70SL
70ns (Max.)
-10LL/10SL
100ns (Max.)
• Low standby current:
CXK581000ATM/AYM/AM/AP
-55LL/70LL/10LL
20µA (Max.)
-55SL/70SL/10SL
12µA (Max.)
• Low data retention current
CXK581000ATM/AYM/AM/AP
-55LL/70LL/10LL
12µA (Max.)
-55SL/70SL/10SL
4µA (Max.)
• Single +5V supply: +5V ±10%
• Low voltage data retention: 2.0V (Min.)
• Broad package line-up
• CXK581000ATM/AYM
8mm × 20mm 32 pin TSOP package
• CXK581000AM
525mil 32 pin SOP package
• CXK581000AP
600mil 32 pin DIP package
CXK581000ATM
32 pin TSOP (Plastic)
CXK581000AYM
32 pin TSOP (Plastic)
CXK581000AM
32 pin SOP (Plastic)
CXK581000AP
32 pin DIP (Plastic)
Block Diagram
A10
A11
A9
A8
A13
A15
A16
A14
A12
A7
Buffer
A6
A5
A4
A3
A2
A1
A0
Buffer
VCC
Row
Decoder
Memory
Matrix
1024 × 1024
GND
I/O Gate
Column
Decoder
OE
Functions
131072-word × 8-bit static RAM
Buffer
WE
CE1
CE2
I/O Buffer
I/O 1
I/O 8
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E92756D53-PP
CXK581000ATM/AYM/AM/AP
Pin Description
Pin Configuration (Top View)
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A4
A5
A6
A7
A12
A14
A16
NC
VCC
A15
CE2
WE
A13
A8
A9
A11
1
2
32
31
3
4
30
29
5
6
28
27
7
8
26
25
CXK581000ATM
(Standard Pinout)
9
10
24
23
11
12
22
21
13
14
20
19
15
16
18
17
16
15
17
18
19
14
13
20
21
12
11
10
9
8
7
22
23
CXK581000AYM
(Mirror Image Pinout)
24
25
26
27
6
5
28
29
4
3
30
31
2
1
32
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
I/O4
I/O5
I/O6
I/O7
I/O8
CE1
A10
OE
NC
1
32
V CC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
CE1
A0
12
21
I/O8
I/O1
13
20
I/O7
I/O2
14
19
I/O6
I/O3
15
18
I/O5
GND
16
17
I/O4
Symbol
A0 to A16
Description
Address input
I/O1 to I/O8 Data input output
CE1, CE2
Chip enable 1, 2 input
WE
Write enable input
OE
Output enable input
Vcc
Power supply
GND
Ground
NC
No connection
CXK581000AM
CXK581000AP
Absolute Maximum Ratings
(Ta = 25°C, GND = 0V)
Item
Supply voltage
VCC
Symbol
Rating
Unit
Input voltage
VIN
–0.5 to +7.0
–0.5∗ to VCC +0.5
–0.5∗ to VCC +0.5
V
Input and output voltage
VI/O
Allowable power dissipation
PD
Operating temperature
Topr
0 to +70
Storage temperature
Tstg
–55 to +150
Soldering temperature
Tsolder
CXK581000AP
1.0
CXK581000ATM/AYM/AM
0.7
CXK581000AP
260 • 10
CXK581000ATM/AYM/AM
235 • 10
∗ VIN,VI/O = –3.0V Min. for pulse width less than 50ns.
Truth Table
CE1
H
CE2
×
OE
×
WE
×
Mode
Not selected
High Z
VCC Current
ISB1, ISB2
×
L
×
×
Not selected
High Z
ISB1, ISB2
L
H
H
H
Output disable
High Z
ICC1, ICC2, ICC3
L
H
L
H
Read
Data out
ICC1, ICC2, ICC3
H
×
L
Write
Data in
ICC1, ICC2, ICC3
L
I/O pin
×: "H" or "L"
DC Recommended Operating Conditions
Item
Supply voltage
Input high voltage
(Ta = 0 to +70°C, GND = 0V)
Symbol
VCC
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
VIH
2.2
—
VCC +0.3
V
–0.3∗
—
0.8
Input low voltage
VIL
∗ VIL = –3.0V Min. for pulse width less than 50ns.
–2–
W
°C
°C • s
CXK581000ATM/AYM/AM/AP
Electrical Characteristics
• DC Characteristics
Item
(VCC = 5V ±10%, GND = 0V, Ta = 0 to = +70°C)
Symbol
Test conditions
Min.
Typ.∗1
Max.
Input leakage current
ILI
VIN = GND to VCC
–1
—
1
Output leakage current
ILO
CE1 = VIH or CE2 = VIL or OE = VIH
or WE = VIL, VI/O = GND to VCC
–1
—
1
ICC1
CE1 = VIL, CE2 = VIH
VIN = VIH or VIL
IOUT = 0mA
—
7
15
55LL/55SL
—
45
90
ICC2
Min. cycle
Duty = 100%
IOUT = 0mA
70LL/70SL
—
40
70
10LL/10SL
—
35
60
—
10
20
0 to +70°C
—
—
20
0 to +40°C
—
—
4
+25°C
—
0.7
2
0 to +70°C
—
—
12
0 to +40°C
—
—
2.4
+25°C
—
0.3
1
Operating power
supply current
Average operating
current
ICC3
Cycle time 1µs
duty = 100%
IOUT = 0mA
CE1 ≤ 0.2V
CE2 ≥ VCC – 0.2V
VIL ≤ 0.2V
VIH ≥ VCC – 0.2V
LL∗2
CE2 ≤ 0.2V
Standby current
Output high
voltage
Output low
voltage
ISB1
or
CE1 ≥ VCC – 0.2V
{ CE2 ≥ V
CC
– 0.2V
SL∗3
ISB2
CE1 = VIH or CE2 = VIL
—
0.6
3
VOH
IOH = –1.0mA
2.4
—
—
Unit
µA
mA
µA
mA
V
VOL
—
IOL = 2.1mA
∗1 VCC = 5V, Ta = 25°C
∗2 For -55LL/70LL/10LL
∗3 For -55SL/70SL/10SL
–3–
—
0.4
CXK581000ATM/AYM/AM/AP
I/O Capacitance
(Ta = 25°C, f = 1MHz)
Item
Symbol
Input capacitance
I/O capacitance
CIN
CI/O
Test conditions
VIN = 0V
VI/O = 0V
Min.
Typ.
Max.
Unit
—
—
—
—
7
8
pF
Note) This parameter is sampled and is not 100% tested.
AC Characteristics
• AC test conditions
(VCC = 5V±10%, Ta = 0 to +70°C)
Item
Conditions
Input pulse high level
VIH = 2.2V
Input pulse low level
VIL = 0.8V
input rise time
tr = 5ns
tf = 5ns
input fall time
Input and output reference level
-55LL/55SL
Output load conditions
-70LL/70SL
-10LL/10SL
• Test circuit
TTL
CL
1.5V
CL∗ = 30pF, 1TTL
CL∗ = 100pF, 1TTL
∗ CL includes scope and jig capacitances.
–4–
CXK581000ATM/AYM/AM/AP
• Read cycle (WE = "H")
Item
Symbol
tRC
tAA
Address access time
tCO1
Chip enable access time (CE1)
tCO2
Chip enable access time (CE2)
tOE
Output enable to output valid
tOH
Output hold from address change
tLZ1, tLZ2
Chip enable to output in low Z (CE1, CE2)
tOLZ
Output enable to output in low Z (OE)
Chip disable to output in high Z (CE1, CE2) tHZ1, tHZ2∗
tOHZ∗
Output disable to output in high Z (OE)
Read cycle time
∗
-55LL/55SL
-70LL/70SL
-10LL/10SL
Min.
Max.
Min.
Max.
Min.
Max.
55
—
70
—
100
—
—
55
—
70
—
100
—
55
—
70
—
100
—
55
—
70
—
100
—
30
—
40
—
50
15
—
15
—
15
—
10
—
10
—
10
—
5
—
5
—
5
—
—
25
—
25
—
35
—
25
—
25
—
35
Unit
ns
tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
Item
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE1, CE2)
Output active from end of write
Write to output in high Z
∗
Symbol
tWC
tAW
tCW
tDW
tDH
tWP
tAS
tWR
tWR1
tOW
tWHZ∗
-55LL/55SL
-70LL/70SL
-10LL/10SL
Min.
Max.
Min.
Max.
Min.
Max.
55
—
70
—
100
—
50
—
60
—
70
—
50
—
60
—
70
—
25
—
30
—
40
—
0
—
0
—
0
—
40
—
50
—
70
—
0
—
0
—
0
—
0
—
0
—
0
—
0
—
0
—
0
—
10
—
10
—
10
—
—
25
—
25
—
30
Unit
ns
tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–5–
CXK581000ATM/AYM/AM/AP
Timing Waveform
• Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH
tRC
Address
tAA
tOH
Data out
Data valid
Previous data valid
• Read cycle (2) : WE = VIH
tRC
Address
tAA
CE1
tCO1
tHZ1
tLZ1
tCO2
CE2
tHZ2
tLZ2
OE
tOE
tOHZ
tOLZ
Data out
Data valid
High impedance
• Write cycle (1) : WE control
tWC
Address
tWR
tAW
OE
tCW
CE1
tCW
CE2
tAS
tWP
(∗1)
WE
tDW
tDH
Data valid
Data in
tWHZ
tOW
Data out
High impedance
(∗2)
–6–
(∗2)
CXK581000ATM/AYM/AM/AP
• Write cycle (2) : CE1 control
tWC
Address
tAW
OE
tWR1 (∗3)
tCW
tAS
CE1
tCW
CE2
tWP
WE
tDW
tDH
Data valid
Data in
Data out
High impedance
• Write cycle (3) : CE2 control
tWC
Address
tAW
OE
tCW
CE1
tAS
tWR1 (∗3)
tOW
CW
CE2
tWP
WE
tDW
tDH
Data valid
Data in
Data out
High impedance
∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.
∗2 Do not apply the data input voltage of the opposite phase to the output while the I/O pin is in output condition.
∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until
the end of the write cycle.
–7–
CXK581000ATM/AYM/AM/AP
Data Retention Waveform
• Low supply voltage data retention waveform (1) : CE1 control
tCDRS
Data retention mode
tR
VCC
4.5V
2.2V
VDR
CE1
CE1 ≥ VCC – 0.2V
GND
• Low supply voltage data retention waveform (2) : CE2 control
Data retention mode
VCC
4.5V
tCDRS
tR
CE2
VDR
0.4V
CE2 ≤ 0.2V
GND
Data Retention Characteristics
Item
Data retention voltage
(Ta = 0 to +70°C)
Symbol
VDR
Test conditions
LL∗2
ICCDR1
VCC = 3.0V∗1
Data retention current
SL∗3
ICCDR2 VCC = 2.0V to 5.5V∗1
Data retention setup
time
Recovery time
tCDRS
Min.
Typ.
Max.
Unit
2.0
—
5.5
V
0 to +70°C
—
—
12
0 to +40°C
+25°C
0 to +70°C
0 to +40°C
+25°C
—
—
2.4
—
0.4
1.2
—
—
4
—
—
0.8
—
0.15
0.3
—
0.7
20
—
0.3
12
0
—
—
ns
5
—
—
ms
∗1
LL∗2
SL∗3
Chip disable to data retention mode
tR
Note)
∗1 CE1 ≥ VCC – 0.2V, CE2 ≥ VCC – 0.2V [CE1 Control] or CE2 ≤ 0.2V [CE2 Control]
∗2 For -55LL/70LL/10LL
∗3 For -55SL/70SL/10SL
–8–
µA
CXK581000ATM/AYM/AM/AP
Example of Representative Characteristics
Supply current vs. Supply voltage
Supply current vs. Ambient temperature
1.2
lCC1, ICC2 — Supply current (Relative Value)
ICC1, ICC2 — Supply current (Relative Value)
1.5
1.25
ICC2
1.0
ICC1
0.75
Ta = 25°C
0.5
4.5
5
4.75
5.25
VCC — Supply voltage (V)
1.1
ICC2 (Read)
1.0
ICC1
0.9
VCC = 5.0V
0.8
5.5
ICC2 (Write)
0
40
20
60
Ta — Ambient temperature (°C)
80
100ns
ICC2 — Supply current (Relative Value)
1.0
70ns
TAA, TCO1, TCO2, TOE — Access time (Relative Value)
Supply current vs. Frequency
55ns
Write
0.8
Read
0.6
0.4
VCC = 5.0V
Ta = 25°C
0.2
0
0
4
12
8
16
20
Access time vs. Load capacitance
2.0
TOE
1.8
1.6
1.4
TAA, TCO1, TCO2
1.2
1.0
VCC = 5.0V
Ta = 25°C
0.8
0.6
0
Access time vs. Supply voltage
1.4
1.2
TOE
1.0
TAA, TCO1, TCO2
0.8
Ta = 25°C
0.6
4.5
4.75
5
5.25
100
200
300
400
CL — Load capacity (pF)
TAA, TCO1, TCO2, TOE — Access time (Relative Value)
TAA, TCO1, TCO2, TOE — Access time (Relative Value)
Frequency (1/tRC, 1/tWC) (MHz)
5.5
VCC — Supply voltage (V)
–9–
Access time vs. Ambient temperature
1.4
1.2
TOE
TCO1, TCO2, TAA
1.0
0.8
VCC = 5.0V
0.6
0
60
20
40
Ta — Ambient temperature (°C)
80
CXK581000ATM/AYM/AM/AP
Standby current vs. Ambient temperature
Standby current vs. Supply voltage
20
ISB1 — Standby current (Relative value)
ISB1, ISB2 — Standby current (Relative value)
2.0
1.5
1.0
ISB1
ISB2
0.5
Ta = 25°C
0
2.0
3.0
4.0
5.0
10
5
2
1
0.5
VCC = 5.0V
0.2
6.0
0
60
80
1.4
ISB2 — Standby current (Relative value)
VIL, VIH — Input voltage (Relative value)
40
Standby current vs. Ambient temperature
Input voltage level vs. Supply voltage
1.2
1.1
VIL, VIH
1.0
0.9
Ta = 25°C
0.8
20
Ta — Ambient temperature (°C)
VCC — Supply voltage (V)
4.5
5.25
5
4.75
VCC — Supply voltage (V)
1.2
1.0
0.8
VCC = 5.0V
0.6
5.5
0
20
40
60
Ta — Ambient temperature (°C)
80
Output low current vs. Output low voltage
Output high current vs. Output high voltage
IOL — Output low current (Relative value)
IOH — Output high current (Relative value)
1.4
1.2
1.0
0.8
VCC = 5.0V
Ta = 25°C
0.6
1
3
2
4
VOH — Output high voltage (V)
5
1.8
1.4
1.0
VCC = 5.0V
Ta = 25°C
0.6
0
0.2
0.4
0.6
VOL — Output low voltage (V)
– 10 –
0.8
CXK581000ATM/AYM/AM/AP
Package Outline
Unit: mm
CXK581000ATM
32PIN TSOP (I) (PLASTIC)
+ 0.2
1.07 – 0.1
8.0 ± 0.2
17
32
0.1
0.5 ± 0.1
20.0 ± 0.2
∗18.4 ± 0.2
0.1 ± 0.1
0° to 10°
DETAIL A
A
+ 0.08
0.2 – 0.03
1
16
+ 0.05
0.02
0.127 –
0.08 M
0.5
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
TSOP (I) -32P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
TSOP (I) 032-P-0820-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
CXK581000AYM
32PIN TSOP (PLASTIC)
+ 0.2
1.07 – 0.1
8.0 ± 0.2
17
0.1
20.0 ± 0.2
∗18.4 ± 0.2
32
A
+ 0.05
0.127 – 0.02
1
0.08 M
0.5
0.1 ± 0.1
0.5 ± 0.1
16
+ 0.08
0.2 – 0.03
0° to 10°
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
TSOP-32P-L01R
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
TSOP032-P-0820-B
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
– 11 –
CXK581000ATM/AYM/AM/AP
CXK581000AM
32PIN SOP (PLASTIC) 525mil
+ 0.4
20.5 – 0.1
+ 0.15
2.9 – 0.25
32
17
11.9
14.0 ± 0.4
+ 0.3
11.2 – 0.1
0.1
16
1
0.4 ± 0.1
A
+ 0.1
0.15 – 0.05
1.27
0.8 ± 0.2
0.2 ± 0.1
0° to 10°
0.12 M
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
SOP-32P-L02
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗SOP032-P-0525-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
JEDEC CODE
CXK581000AP
+ 0.1
05
0.25 – 0.
32PIN DIP (PLASTIC) 600mil
+ 0.4
40.2 – 0.1
32
15.24
+ 0.3
13.5 – 0.1
17
0° to 15°
16
1
0.5 ± 0.1
1.2 ± 0.15
3.0 MIN
0.5 MIN
+ 0.4
4.6 – 0.1
2.54
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
DIP-32P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗DIP32-P-0600-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
4.5g
JEDEC CODE
– 12 –