AD AD8605ART-REEL7 Precision low noise cmos rail-to-rail input/output operational amplifier Datasheet

Precision Low Noise CMOS Rail-to-Rail
Input/Output Operational Amplifiers
AD8605/AD8606/AD8608
FEATURES
APPLICATIONS
Low offset voltage: 65 µV maximum
Low input bias currents: 1 pA maximum
Low noise: 8 nV/√Hz
Wide bandwidth: 10 MHz
High open-loop gain: 120 dB
Unity gain stable
Single-supply operation: 2.7 V to 5.5 V
MicroCSP™
Photodiode amplification
Battery-powered instrumentation
Multipole filters
Sensors
Barcode scanners
Audio
FUNCTIONAL BLOCK DIAGRAMS
1
TOP VIEW
(BUMP SIDE DOWN)
OUT
V+
1
5
–IN A
12 +IN D
AD8608
11 V–
–IN
10 +IN C
4
–IN B 6
9 –IN C
OUT B
5
V+
OUT B
–IN B
+IN B
8 OUT C
7
Figure 4. 14-Lead SOIC (R Suffix)
02731-D-003
8
AD8606
4
13 –IN D
+IN B 5
Figure 3. 5-Bump MicroCSP
(CB Suffix)
1
14 OUT D
2
V+ 4
AD8605 ONLY
OUT A
–IN A
+IN A
V–
Figure 2. 8-Lead SOIC (R Suffix)
+IN A 3
2
3
5 +IN B
OUT A 1
V–
+IN
6 –IN B
V– 4
02731-D-004
02731-D-001
Figure 1. 5-Lead SOT-23 (RT Suffix)
7 OUT B
AD8608
+IN A 3
02731-D-005
–IN A 2
4 –IN
+IN 3
8 V+
OUT A 1
AD8605
V– 2
The combination of low offsets, low noise, very low input bias
currents, and high speed makes these amplifiers useful in a
wide variety of applications. Filters, integrators, photodiode
amplifiers, and high impedance sensors all benefit from the
combination of performance features. Audio and other ac
applications benefit from the wide bandwidth and low
distortion. Applications for these amplifiers include optical
control loops, portable and loop-powered instrumentation,
and audio amplification for portable devices.
The AD8605, AD8606, and AD8608 are specified over the
extended industrial temperature range (−40°C to +125°C). The
AD8605 single is available in the 5-lead SOT-23 and 5-bump
MicroCSP packages. The 5-bump MicroCSP offers the smallest
available footprint for any surface-mount operational amplifier.
The AD8606 dual is available in an 8-lead MSOP package and a
narrow SOIC surface-mount package. The AD8608 quad is
available in a 14-lead TSSOP and a narrow 14-lead SOIC
package. MicroCSP, SOT, MSOP, and TSSOP versions are
available in tape and reel only.
5 V+
OUT 1
02731-D-006
The AD8605, AD8606, and AD86081 are single, dual, and quad
rail-to-rail input and output, single-supply amplifiers. They
feature very low offset voltage, low input voltage and current
noise, and wide signal bandwidth. They use Analog Devices’
patented DigiTrim® trimming technique, which achieves
superior precision without laser trimming.
Figure 5. 8-Lead MSOP (RM Suffix)
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
1
14
AD8608
7
8
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
02731-D-002
GENERAL DESCRIPTION
Figure 6. 14-Lead TSSOP (RU Suffix)
Protected by U.S. Patent No. 5,969,657; other patents pending.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD8605/AD8606/AD8608
TABLE OF CONTENTS
5 V Electrical Specifications ............................................................ 3
Channel Separation.................................................................... 14
2.7 V Electrical Specifications ......................................................... 5
Capacitive Load Drive ............................................................... 14
Absolute Maximum Ratings............................................................ 6
Light Sensitivity .......................................................................... 15
ESD Caution.................................................................................. 6
MicroCSP Assembly Considerations....................................... 15
Typical Performance Characteristics ............................................. 7
I-V Conversion Applications ........................................................ 16
Application Information................................................................ 13
Photodiode Preamplifier Applications .................................... 16
Output Phase Reversal............................................................... 13
Audio and PDA Applications ................................................... 16
Maximum Power Dissipation ................................................... 13
Instrumentation Amplifiers ...................................................... 17
Input Overvoltage Protection ................................................... 13
D/A Conversion ......................................................................... 17
THD + Noise............................................................................... 13
Outline Dimensions ....................................................................... 18
Total Noise Including Source Resistors ................................... 14
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/04—Data Sheet Changed from Rev. C to Rev. D
Updated Format............................................................. Universal
Edit to Light Sensitivity Section ............................................... 16
Updated Outline Dimensions ................................................... 19
Changes to Ordering Guide ...................................................... 20
7/03—Data Sheet Changed from Rev. B to Rev. C
Changes to Features....................................................................... 1
Change to General Description ................................................... 1
Addition to Functional Block Diagrams .................................... 1
Addition to Absolute Maximum Ratings ................................... 4
Addition to Ordering Guide ........................................................ 4
Change to Equation In Maximum Power Dissipation
Section........................................................................................ 11
Added Light Sensitivity Section................................................. 12
Added New Figure 8 and Renumbered Subsequent Figures . 13
Added New MicroCSP Assembly Considerations Section .... 13
Changes to Figure 9..................................................................... 13
Change to Equation in Photodiode Preamplifier
Applications Section ................................................................ 13
Changes to Figure 12................................................................... 14
Change to Equation in D/A Conversion Section .................... 14
Updated Outline Dimensions ................................................... 15
3/03—Data Sheet Changed from Rev. A to Rev. B
Changes to Functional Block Diagram....................................... 1
Changes to Absolute Maximum Ratings .................................... 4
Changes to Ordering Guide ....................................................... 4
Changes to Figure 9 .................................................................... 13
Updated Outline Dimensions.................................................... 15
11/02—Data Sheet Changed from Rev. 0 to Rev. A
Change to Electrical Characteristics ........................................... 2
Changes to Absolute Maximum Ratings .................................... 4
Changes Ordering Guide ............................................................. 4
Change to TPC 6 .......................................................................... 5
Updated Outline Dimensions.................................................... 15
Rev. D | Page 2 of 20
AD8605/AD8606/AD8608
5 V ELECTRICAL SPECIFICATIONS
Table 1. @ VS = 5 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
AD8605/AD8606
AD8608
Input Bias Current
AD8605/AD8606
AD8605/AD8606
AD8608
AD8608
Input Offset Current
Symbol
Conditions
Min
Typ
Max
Unit
20
20
80
65
75
300
750
1
50
250
100
300
0.5
20
75
5
µV
µV
µV
µV
pA
pA
pA
pA
pA
pA
pA
pA
V
dB
dB
V/mV
4.5
6.0
µV/°C
µV/°C
VOS
VS = 3.5 V, VCM = 3 V
VS = 3.5 V, VCM = 2.7 V
VS = 5 V, VCM = 0 V to 5 V
−40°C < TA < +125°C
IB
0.2
−40°C < TA < +85°C
−40°C < TA < +125°C
−40°C < TA < +85°C
−40°C < TA < +125°C
IOS
0.1
−40°C < TA < +85°C
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Offset Voltage Drift
AD8605/AD8606
AD8608
INPUT CAPACITANCE
Common-Mode Input Capacitance
Differential Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
AD8605/AD8606
AD8608
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Full Power Bandwidth
Gain Bandwidth Product
Phase Margin
VCM = 0 V to 5 V
−40°C < TA < +125°C
VO = 0.5 V to 4.5 V
RL = 2 kΩ, VCM = 0 V
0
85
75
300
∆VOS/∆T
∆VOS/∆T
VOH
VOL
IOUT
ZOUT
100
90
1,000
1
1.5
IL = 1 mA
IL = 10 mA
−40°C < TA < +125°C
IL = 1 mA
IL= 10 mA
−40°C < TA < +125°C
4.96
4.7
4.6
8.8
2.59
pF
pF
4.98
4.79
V
V
V
mV
mV
mV
mA
Ω
20
170
40
210
290
±80
10
f = 1 MHz, AV = 1
PSRR
ISY
SR
tS
BWP
GBP
VS = 2.7 V to 5.5 V
VS = 2.7 V to 5.5 V
−40°C < TA < +125°C
VO = 0 V
−40°C < TA < +125°C
RL = 2 kΩ
To 0.01%, 0 V to 2 V step
< 1% distortion
80
77
70
95
92
90
1
1.2
1.4
5
<1
360
10
ϕO
65
Rev. D | Page 3 of 20
dB
dB
dB
mA
mA
V/µs
µs
kHz
MHz
Degrees
AD8605/AD8606/AD8608
Parameter
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
Voltage Noise Density
Current Noise Density
Symbol
Conditions
en p-p
en
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
f = 1 kHz
Rev. D | Page 4 of 20
Min
Typ
Max
Unit
2.3
8
6.5
0.01
3.5
12
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
AD8605/AD8606/AD8608
2.7 V ELECTRICAL SPECIFICATIONS
Table 2. @ VS = 2.7 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
AD8605/AD8606
AD8608
Input Bias Current
AD8605/AD8606
AD8605/AD8606
AD8608
AD8608
Input Offset Current
Symbol
Conditions
Min
Typ
Max
Unit
20
20
80
65
75
300
750
1
50
250
100
300
0.5
20
75
2.7
µV
µV
µV
µV
pA
pA
pA
pA
pA
pA
pA
pA
V
dB
dB
V/mV
4.5
6.0
µV/°C
µV/°C
VOS
VS = 3.5 V, VCM = 3 V
VS = 3.5 V, VCM = 2.7 V
VS = 2.7 V, VCM = 0 V to 2.7 V
−40°C < TA < +125°C
IB
0.2
−40°C < TA < +85°C
−40°C < TA < +125°C
−40°C < TA < +85°C
−40°C < TA < +125°C
IOS
0.1
−40°C < TA < +85°C
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
AD8605/AD8606
AD8608
INPUT CAPACITANCE
Common-Mode Input Capacitance
Differential Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
AD8605/AD8606
AD8608
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
Voltage Noise Density
Current Noise Density
CMRR
AVO
VCM = 0 V to 2.7 V
−40°C < TA < +125°C
RL = 2 kΩ, VO= 0.5 V to 2.2 V
0
80
70
110
∆VOS/∆T
∆VOS/∆T
VOH
VOL
IOUT
ZOUT
95
85
350
1
1.5
IL = 1 mA
−40°C < TA < +125°C
IL = 1 mA
−40°C < TA < +125°C
2.6
2.6
8.8
2.59
pF
pF
2.66
V
V
mV
mV
mA
Ω
25
40
50
±30
12
f = 1 MHz, AV = 1
PSRR
ISY
SR
tS
GBP
VS = 2.7 V to 5.5 V
VS = 2.7 V to 5.5 V
−40°C < TA < +125°C
VO = 0 V
−40°C < TA < +125°C
95
92
90
1.15
RL = 2 kΩ
To 0.01%, 0 V to 1 V step
5
< 0.5
9
50
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
f = 1 kHz
2.3
8
6.5
0.01
ϕO
en p-p
en
en
in
80
77
70
Rev. D | Page 5 of 20
1.4
1.5
dB
dB
dB
mA
mA
V/µs
µs
MHz
Degrees
3.5
12
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
AD8605/AD8606/AD8608
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration
to GND
Storage Temperature Range
All Packages
Operating Temperature Range
AD8605/AD8606/AD8608
Junction Temperature Range
All Packages
Lead Temperature Range
(Soldering, 60 sec)
Rating
6V
GND to VS
6V
Observe Derating Curves
Table 4. Package Type
Package Type
5-Bump MicroCSP (CB)
5-Lead SOT-23 (RT)
8-Lead MSOP (RM)
8-Lead SOIC (R)
14-Lead SOIC (R)
14-Lead TSSOP (RU)
1
θJA1
220
230
210
158
120
180
θJC
220
92
45
43
36
35
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA is specified for worst-case conditions, i.e., θJA is specified for device in
socket for PDIP packages; θJA is specified for device soldered onto a circuit
board for surface-mount packages.
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 6 of 20
AD8605/AD8606/AD8608
TYPICAL PERFORMANCE CHARACTERISTICS
300
4500
VS = 5V
TA = 25°C
INPUT OFFSET VOLTAGE (mV)
3000
2500
2000
1500
1000
–200
–100
0
100
OFFSET VOLTAGE (mV)
200
0
–100
–300
300
COMMON-MODE VOLTAGE (V)
Figure 7. Input Offset Voltage Distribution
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
(200 Units, 5 Wafer Lots, Including Process Skews)
24
VS = ±2.5V
320
INPUT BIAS CURRENT (pA)
20
NUMBER OF AMPLIFIERS
360
VS = 5V
TA = –40°C TO +125°C
VCM = 2.5V
16
12
8
02731-D-008
4
0
0
0.4
0.8
1.2
1.6
2.0 2.4 2.8 3.2
TCVOS (mV/°C)
3.6
4.0
4.4
280
240
AD8605/AD8606
200
160
AD8608
120
80
02731-D-011
0
–300
100
02731-D-010
500
200
–200
02731-D-007
NUMBER OF AMPLIFIERS
VS = 5V
4000 TA = 25°C
VCM = 0V TO 5V
3500
40
0
4.8
0
25
Figure 8. AD8608 Input Offset Voltage Drift Distribution
20
100
125
Figure 11. Input Bias Current vs. Temperature
1k
VS = 5V
TA = –40°C TO +125°C
VCM = 2.5V
18
50
75
TEMPERATURE (°C)
VS = 5V
TA = 25°C
100
VSY–VOUT (mV)
12
10
8
10
SOURCE
6
02731-D-009
4
2
0
SINK
1
0
0.1
0.001
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
TCVOS (mV/°C)
02731-D-012
NUMBER OF AMPLIFIERS
16
14
0.01
0.1
1
LOAD CURRENT (mA)
Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution
Figure 12. Output Voltage to Supply Rail vs. Load Current
Rev. D | Page 7 of 20
10
AD8605/AD8606/AD8608
5.000
6
VOH @ 1mA LOAD
5
VS = 5V
OUTPUT SWING (V p-p)
OUTPUT VOLTAGE (V)
4.950
4.900
4.850
4.800
VS = 5V
VIN = 4.9V p-p
TA = 25°C
RL = 2kΩ
AV = 1
4
3
2
VOH @ 10mA LOAD
–25
–10
5
20
35
50
65
80
95
110
0
125
02731-D-016
4.700
–40
1
02731-D-013
4.750
1k
10k
TEMPERATURE (°C)
100k
FREQUENCY (Hz)
10M
1M
Figure 16. Closed-Loop Output Voltage Swing
Figure 13. Output Voltage Swing vs. Temperature
100
0.250
VS = ±2.5V
VS = 5V
90
VOH @ 10mA LOAD
80
OUTPUT IMPEDANCE (Ω)
0.150
0.100
70
AV = 100
60
50
AV = 10
30
20
02731-D-014
0.050
VOH @ 1mA LOAD
0
–40
–25
–10
5
20
35
50
65
80
95
110
10
0
125
1k
10k
TEMPERATURE (°C)
VS = ±2.5V
RL = 2kV
CL = 20pF
fM = 648
60
120
180
110
135
100
90
0
CMRR (dB)
45
0
PHASE (Degrees)
20
80
70
60
–20
–45
–40
–90
50
–60
–135
40
–80
–180
1M
FREQUENCY (Hz)
10M
100M
VS = ±2.5V
–225
100M
02731-D-015
GAIN (dB)
225
90
40
100k
10M
02731-D-018
100
80
100k
1M
FREQUENCY (Hz)
Figure 17. Output Impedance vs. Frequency
Figure 14. Output Voltage Swing vs. Temperature
–100
10k
AV = 1
40
02731-D-017
OUTPUT VOLTAGE (V)
0.200
30
20
1k
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 18. Common-Mode Rejection Ratio vs. Frequency
Figure 15. Open-Loop Gain and Phase vs. Frequency
Rev. D | Page 8 of 20
AD8605/AD8606/AD8608
140
1.0
VS = 5V
120
PSRR (dB)
80
60
40
20
0
02731-D-019
–20
–40
–60
1k
100k
FREQUENCY (Hz)
10k
1M
0.8
0.7
0.6
0.5
0.4
0.3
0.2
02731-D-022
SUPPLY CURRENT/AMPLIFIER (mA)
0.9
100
0.1
0
10M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
Figure 19. PSRR vs. Frequency
Figure 22. Supply Current vs. Supply Voltage
45
VOLTAGE NOISE (1µV/DIV)
35
30
25
+OS
20
–OS
15
02731-D-023
10
02731-D-020
SMALL SIGNAL OVERSHOOT (%)
VS = 5V
VS = 5V
RL =
TA = 25°C
AV = 1
40
5
0
10
100
CAPACITANCE (pF)
1k
TIME (1s/DIV)
Figure 20. Small Signal Overshoot vs. Load Capacitance
Figure 23. 0.1 Hz to 10 Hz Input Voltage Noise
VS = ±2.5V
RL = 10kΩ
CL = 200pF
AV = 1
1.5
VOLTAGE (50mV/DIV)
VS = 2.7V
1.0
VS = 5V
0.5
0
–1.0
–1.5
–50
02731-D-024
–0.5
02731-D-021
SUPPLY CURRENT/AMPLIFIER (mA)
2.0
–35
–20
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
TIME (200ns/DIV)
125
Figure 21. Supply Current vs. Temperature
Figure 24. Small Signal Transient Response
Rev. D | Page 9 of 20
AD8605/AD8606/AD8608
36
VS = ±2.5V
RL = 10kΩ
CL = 200pF
AV = 1
28
24
20
16
12
02731-D-028
02731-D-025
VOLTAGE (1V/DIV)
VOLTAGE NOISE DENSITY (nV/√Hz)
VS = ±2.5V
32
8
4
TIME (400ns/DIV)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
8
9
10
80
90
100
FREQUENCY (kHz)
Figure 28. Voltage Noise Density
Figure 25. Large Signal Transient Response
53.6
VS = ±2.5V
RL = 10kΩ
AV = 100
VIN = 50mV
VS = ±2.5V
0V
0V
02731-D-026
–50mV
46.9
40.2
33.5
26.8
20.1
13.4
02731-D-029
VOLTAGE NOISE DENSITY (nV/√Hz)
+2.5V
6.7
0
TIME (400ns/DIV)
0
1
Figure 26. Negative Overload Recovery
3
4
5
6
FREQUENCY (kHz)
7
Figure 29. Voltage Noise Density
119.2
VS = ±2.5V
RL = 10kΩ
AV = 100
VIN = 50mV
VS = ±2.5V
0V
02731-D-027
–50mV
104.3
99.4
74.5
59.6
44.7
29.8
02731-D-030
+2.5V
VOLTAGE NOISE DENSITY (nV/√Hz)
0V
2
14.9
0
TIME (400ns/DIV)
0
Figure 27. Positive Overload Recovery
10
20
30
40
50
60
FREQUENCY (Hz)
70
Figure 30. Voltage Noise Density
Rev. D | Page 10 of 20
AD8605/AD8606/AD8608
1800
2.680
VS = 2.7V
TA = 25°C
VCM = 0V TO 2.7V
VS = 2.7V
2.675
1400
OUTPUT VOLTAGE (V)
NUMBER OF AMPLIFIERS
1600
1200
1000
800
600
2.670
2.665
VOH @ 1mA LOAD
2.660
400
0
100
–100
OFFSET VOLTAGE (µV)
–200
200
2.650
–40
300
02731-D-034
0
–300
2.655
02731-D-031
200
–25
–10
5
20
35
50
65
80
95
110
125
110
125
TEMPERATURE (°C)
Figure 31. Input Offset Voltage Distribution
Figure 34. Output Voltage Swing vs. Temperature
300
0.045
VS = 2.7V
TA = 25°C
VS = 2.7V
0.040
0.035
OUTPUT VOLTAGE (V)
100
0
–100
0.030
VOH @ 1mA LOAD
0.025
0.020
0.015
02731-D-032
0.9
1.8
0.005
0
–40
2.7
–25
–10
COMMON-MODE VOLTAGE (V)
5
20
35
50
Figure 32. Input Offset Voltage vs. Common-Mode Voltage
(200 Units, 5 Wafer Lots, Including Process Skews)
80
95
Figure 35. Output Voltage Swing vs. Temperature
225
100
1k
VS = 2.7V
TA = 25°C
VS = ±1.35V
RL = 2kΩ
CL = 20pF
fM = 52.5°
80
60
GAIN (dB)
100
SOURCE
10
SINK
180
135
40
90
20
45
0
0
–20
–45
–40
–90
–60
–135
–80
–180
1
0.1
0.001
02731-D-033
OUTPUT VOLTAGE (mV)
65
TEMPERATURE (°C)
PHASE (Degrees)
–300
0
0
02731-D-035
0.010
–200
0.01
0.1
LOAD CURRENT (mA)
1
10
–100
10k
100k
1M
FREQUENCY (Hz)
10M
–225
100M
Figure 36. Open-Loop Gain and Phase vs. Frequency
Figure 33. Output Voltage to Supply Rail vs. Load Current
Rev. D | Page 11 of 20
02731-D-036
INPUT OFFSET VOLTAGE (µV)
200
AD8605/AD8606/AD8608
3.0
VS = 2.7V
VOLTAGE NOISE (1µV/DIV)
VS = 2.7V
VIN = 2.6V p-p
TA = 25°C
RL = 2kΩ
AV = 1
2.0
1.5
1.0
02731-D-037
0.5
02731-D-040
OUTPUT SWING (V p-p)
2.5
0
1k
10k
100k
FREQUENCY (Hz)
1M
TIME (1s/DIV)
10M
Figure 40. 0.1 Hz to 10 Hz Input Voltage Noise
Figure 37. Closed-Loop Output Voltage Swing vs. Frequency
100
VS = ±1.35V
90
VOLTAGE (50mV/DIV)
OUTPUT IMPEDANCE (Ω)
80
70
AV = 100
60
50
AV = 10
40
30
VS = 1.35V
RL = 10kΩ
CL = 200pF
AV = 1
AV = 1
02731-D-038
02731-D-041
20
10
0
1k
10k
100k
1M
FREQUENCY (Hz)
10M
TIME (200ns/DIV)
100M
Figure 38. Output Impedance vs. Frequency
Figure 41. Small Signal Transient Response
VS = 1.35V
RL = 10kΩ
CL = 200pF
AV = 1
50
VOLTAGE (1V/DIV)
VS = 2.7V
TA = 25°C
AV = 1
40
–OS
30
+OS
10
02731-D-042
20
02731-D-039
SMALL SIGNAL OVERSHOOT (%)
60
0
10
100
CAPACITANCE (pF)
1k
TIME (400ns/DIV)
Figure 42. Large Signal Transient Response
Figure 39. Small Signal Overshoot vs. Load Capacitance
Rev. D | Page 12 of 20
AD8605/AD8606/AD8608
APPLICATION INFORMATION
OUTPUT PHASE REVERSAL
Phase reversal is defined as a change in polarity at the output of
the amplifier when a voltage that exceeds the maximum input
common-mode voltage drives the input.
Figure 44 compares the maximum power dissipation with
temperature for the various AD8605 family packages.
2.0
1.8
Phase reversal can cause permanent damage to the amplifier; it
may also cause system lockups in feedback loops. The AD8605
does not exhibit phase reversal even for inputs exceeding the
supply voltage by more than 2 V.
POWER DISSIPATION (W)
VS = ±2.5V
VIN = 5V p-p
AV = 1
RL = 10kΩ
SOIC-14
1.6
VOUT
1.4
SOIC-8
1.2
1.0
0.8
SOT-23
0.6
TSSOP
02731-D-044
VOLTAGE (2V/DIV)
0.4
MSOP
0.2
VIN
0
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 44. Maximum Power Dissipation vs. Temperature
02731-D-043
INPUT OVERVOLTAGE PROTECTION
The AD8605 has internal protective circuitry. However, if the
voltage applied at either input exceeds the supplies by more
than 2.5 V, external resistors should be placed in series with the
inputs. The resistor values can be determined by the formula
TIME (4µs/DIV)
Figure 43. No Phase Reversal
(VIN − VS ) ≤ 5mA
(RS + 200Ω )
MAXIMUM POWER DISSIPATION
Power dissipated in an IC causes the die temperature to
increase. This can affect the behavior of the IC and the
application circuit performance.
The absolute maximum junction temperature of the AD8605/
AD8606/AD8608 is 150°C. Exceeding this temperature could
cause damage or destruction of the device. The maximum
power dissipation of the amplifier is calculated according to
the following formula:
PDISS =
TJ − TA
θ JA
where:
TJ = junction temperature
TA = ambient temperature
θJA = junction to-ambient-thermal resistance
The remarkable low input offset current of the AD8605 (<1 pA)
allows the use of larger value resistors. With a 10 kΩ resistor at
the input, the output voltage has less than 10 nV of error
voltage. A 10 kΩ resistor has less than 13 nV/√Hz of thermal
noise at room temperature.
THD + NOISE
Total harmonic distortion is the ratio of the input signal in V
rms to the total harmonics in V rms throughout the spectrum.
Harmonic distortion adds errors to precision measurements
and adds unpleasant sonic artifacts to audio systems.
The AD8605 has a low total harmonic distortion. Figure 45
shows that the AD8605 has less than 0.005% or −86 dB of THD
+ N over the entire audio frequency range. The AD8605 is
configured in positive unity gain, which is the worst case, and
with a load of 10 kΩ.
Rev. D | Page 13 of 20
AD8605/AD8606/AD8608
0.1
The AD8606 has a channel separation of greater than −160 dB
up to frequencies of 1 MHz, allowing the two amplifiers to
amplify ac signals independently in most applications.
VSY = 2.5V
AV = 1
BW = 22kHz
0
THD + N (%)
0.01
CHANNEL SEPARATION (dB)
–20
100
1k
FREQUENCY (Hz)
10k
20k
–60
–80
–100
–120
–140
02731-D-046
0.0001
20
02731-D-045
0.001
–40
–160
Figure 45. THD + N
–180
100
TOTAL NOISE INCLUDING SOURCE RESISTORS
The low input current noise and input bias current of the
AD8605 make it the ideal amplifier for circuits with substantial
input source resistance such as photodiodes. Input offset voltage
increases by less than 0.5 nV per 1 kΩ of source resistance at
room temperature and increases to 10 nV at 85°C. The total
noise density of the circuit is
en,TOTAL = en2 + (in RS ) 2 + 4k TRS
where:
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
Figure 46. Channel Separation vs. Frequency
CAPACITIVE LOAD DRIVE
The AD8605 can drive large capacitive loads without oscillation.
Figure 47 shows the output of the AD8606 in response to a
200 mV input signal. In this case, the amplifier was configured
in positive unity gain, worst case for stability, while driving a
1,000 pF load at its output. Driving larger capacitive loads in
unity gain may require the use of additional circuitry.
en is the input voltage noise density of the AD8605
VS = ±2.5V
AV = 1
RL = 10kΩ
CL = 1
in is the input current noise density of the AD8605
VOLTAGE (100mV/DIV)
RS is the source resistance at the noninverting terminal
k is Boltzmann’s constant (1.38 × 10−23 J/K)
T is the ambient temperature in Kelvin (T = 273 + °C)
For example, with RS = 10 kΩ, the total voltage noise density is
roughly 15 nV/√Hz.
02731-D-047
For RS < 3.9 kΩ, en dominates and en,TOTAL ≈ en.
The current noise of the AD8605 is so low that its total density
does not become a significant term unless RS is greater than
6 MΩ. The total equivalent rms noise over a specific bandwidth
is expressed as
En = (en,TOTAL ) BW
where BW is the bandwidth in hertz.
Note that the analysis above is valid for frequencies greater than
100 Hz and assumes relatively flat noise, above 10 kHz. For
lower frequencies, flicker noise (1/f) must be considered.
CHANNEL SEPARATION
Channel separation, or inverse crosstalk, is a measure of the
signal feed from one amplifier (channel) to an other on the
same IC.
TIME (10µs/DIV)
Figure 47. Capacitive Load Drive without Snubber
A snubber network, shown in Figure 48, helps reduce the signal
overshoot to a minimum and maintain stability. Although this
circuit does not recover the loss of bandwidth induced by large
capacitive loads, it greatly reduces the overshoot and ringing.
This method does not reduce the maximum output swing of
the amplifier.
Figure 49 shows a scope photograph of the output at the
snubber circuit. The overshoot is reduced from over 70% to
less than 5%, and the ringing is eliminated by the snubber.
Optimum values for RS and CS are determined experimentally.
Rev. D | Page 14 of 20
AD8605/AD8606/AD8608
V+
shown in Figure 50 are not normal for most applications, i.e.,
even though direct sunlight can have intensities of 50 mW/cm2,
office ambient light can be as low as 0.1 mW/cm2.
4
2
AD8605
1
RS
8
RL
CL
CS
V–
Figure 48. Snubber Network Configuration
02731-D-048
VOLTAGE (100mV/DIV)
VS = ±2.5V
AV = 1
RL = 10kΩ
RS = 90Ω
CL = 1,000pF
CS = 700pF
TIME (10µs/DIV)
Figure 49. Capacitive Load Drive with Snubber
Table 5 summarizes a few optimum values for capacitive loads.
Table 5.
CL (pF)
500
1,000
2,000
RS (Ω)
100
70
60
CS (pF)
1,000
1,000
800
An alternate technique is to insert a series resistor inside the
feedback loop at the output of the amplifier. Typically, the value
of this resistor is approximately 100 Ω. This method also
reduces overshoot and ringing but causes a reduction in the
maximum output swing.
LIGHT SENSITIVITY
The AD8605ACB (MicroCSP package option) is essentially
a silicon die with additional post fabrication dielectric and
intermetallic processing designed to contact solder bumps on
the active side of the chip. With this package type, the die is
exposed to ambient light and is subject to photoelectric effects.
Light sensitivity analysis of the AD8605ACB mounted on
standard PCB material reveals that only the input bias current
(IB) parameter is impacted when the package is illuminated
directly by high intensity light. No degradation in electrical
performance is observed due to illumination by low intensity
(0.1 mW/cm2) ambient light. Figure 50 shows that IB increases
with increasing wavelength and intensity of incident light;
IB can reach levels as high as 4500 pA at a light intensity of
3 mW/cm2 and a wavelength of 850 nm. The light intensities
When the MicroCSP package is assembled on the board with
the bump-side of the die facing the PCB, reflected light from the
PCB surface is incident on active silicon circuit areas and results
in the increased IB. No performance degradation occurs due to
illumination of the backside (substrate) of the AD8605ACB.
The AD8605ACB is particularly sensitive to incident light with
wavelengths in the near infrared range (NIR, 700 nm to 1000
nm). Photons in this waveband have a longer wavelength and
lower energy than photons in the visible (400 nm to 700 nm)
and near ultraviolet bands (NUV, 200 nm to 400 nm); therefore,
they can penetrate more deeply into the active silicon. Incident
light with wavelengths greater than 1100 nm has no photoelectric effect on the AD8605ACB because silicon is transparent to wave lengths in this range. The spectral content of
conventional light sources varies: sunlight has a broad spectral
range, with peak intensity in the visible band that falls off in the
NUV and NIR bands; fluorescent lamps have significant peaks
in the visible but not in the NUV or NIR bands.
Efforts have been made at a product level to reduce the effect
of ambient light; the under bump metal (UBM) has been
designed to shield the sensitive circuit areas on the active side
(bump-side) of the die. However, if an application encounters
any light sensitivity with the AD8605ACB, shielding the bump
side of the MicroCSP package with opaque material should
eliminate this effect. Shielding can be accomplished using
materials such as silica filled liquid epoxies that are used in
flip chip underfill techniques.
5000
4500
4000
3500
3mW/cm2
3000
2500
2mW/cm2
2000
1500
1000
1mW/cm2
500
0
350
450
550
650
WAVELENGTH (nm)
750
02731-D-050
3
INPUT BIAS CURRENT (pA)
VIN
02731-D-049
200mV
850
Figure 50. AD8605ACB Input Bias Current Response to Direct Illumination of
Varying Intensity and Wavelength
MICROCSP ASSEMBLY CONSIDERATIONS
For detailed information on MicroCSP PCB assembly and
reliability, refer to ADI Application Note AN-617 on the ADI
website www.analog.com.
Rev. D | Page 15 of 20
AD8605/AD8606/AD8608
I-V CONVERSION APPLICATIONS
At room temperature, the AD8605 has an input bias current of
0.2 pA and an offset voltage of 100 µV. Typical values of RD are
in the range of 1 GΩ.
PHOTODIODE PREAMPLIFIER APPLICATIONS
The low offset voltage and input current of the AD8605 make it
an excellent choice for photodiode applications. In addition, the
low voltage and current noise make the amplifier ideal for
application circuits with high sensitivity.
For the circuit shown in Figure 9, the output error voltage is
approximately 100 µV at room temperature, increasing to about
1 mV at 85°C.
CF
10pF
Where ft is the unity gain frequency of the amplifier, the
maximum achievable signal bandwidth is
RF
10MΩ
PHOTODIODE
ID
CD
50pF
AD8605
ft
2πRF CT
AUDIO AND PDA APPLICATIONS
VOUT
The AD8605’s low distortion and wide dynamic range make it a
great choice for audio and PDA applications, including
microphone amplification and line output buffering.
02731-D-051
RD
f MAX =
+VOS–
Figure 51. Equivalent Circuit for Photodiode Preamp
Figure 52 shows a typical application circuit for headphone/line
out amplification.
The input bias current of the amplifier contributes an error
term that is proportional to the value of RF.
R1 and R2 are used to bias the input voltage at half the supply.
This maximizes the signal bandwidth range. C1 and C2 are used
to ac couple the input signal. C1 and R2 form a high-pass filter
whose corner frequency is 1/2πR1C1.
The offset voltage causes a dark current induced by the shunt
resistance of the diode RD. These error terms are combined at
the output of the amplifier. The error voltage is written as
⎛
R ⎞
EO = VOS ⎜⎜ 1 + F ⎟⎟ + RF I B
⎝ RD ⎠
The high output current of the AD8605 allows it to drive heavy
resistive loads.
The circuit of Figure 52 was tested to drive a 16 W headphone.
The THD + N is maintained at approximately −60 dB
throughout the audio range.
Typically, RF is smaller than RD, thus RF/RD can be ignored.
5V
C1
1µF
V1
500mV
R1
10kΩ
R2
10kΩ
8
3
1/2
AD8606
C3
100µF
R4
20Ω
1
R3 HEADPHONES
1kΩ
2
4
5V
C2
1µF
8
V2
500mV
1/2
AD8606
C4
100µF
R6
20Ω
7
6
4
R5
1kΩ
Figure 52. Single-Supply Headphone/Speaker Amplifier
Rev. D | Page 16 of 20
02731-D-052
5
AD8605/AD8606/AD8608
INSTRUMENTATION AMPLIFIERS
R
VREF
R
R
CF
RF
Difference amplifiers are widely used in high accuracy circuits
to improve the common-mode rejection ratio.
R2
R2
R2
Figure 53 shows a simple difference amplifier. The CMRR of the
circuit is plotted versus frequency. Figure 54 shows the
common-mode rejection for a unity gain configuration and for
a gain of 10.
AD8605
V–
Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields
a CMRR of 74 dB and minimizes the gain error at the output.
R1
1kΩ
V1
R4 R2
=
R3 R1
AD8605
R3
1kΩ
VOUT
R4
10kΩ
⎛
R ⎞
EO = VOS ⎜⎜ 1 + F ⎟⎟
Re
q⎠
⎝
02731-D-053
R2
(V2 – V1)
R1
V2
where Req is the equivalent resistance seen at the output of the
DAC. As mentioned above, Req is code dependant and varies
with the input. A typical value for Req is 15 kΩ. Choosing a
feedback resistor of 10 kΩ yields an error of less than 200 µV.
Figure 53. Difference Amplifier, AV = 10
120
VSY = ±2.5V
AV = 10
100
CMRR (dB)
Figure 56 shows the implementation of a dual-stage buffer at
the output of a DAC. The first stage is used as a buffer.
Capacitor C1, with Req, creates a low-pass filter and thus
provides phase lead to compensate for frequency response. The
second stage of the AD8606 is used to provide voltage gain at
the output of the buffer.
AV = 1
80
Figure 55. Simplified Circuit of the DAC8143 with AD8605 Output Buffer
To optimize the performance of the DAC, insert a capacitor in
the feedback loop of the AD8605 to compensate the amplifier
from the pole introduced by the output capacitance of the DAC.
Typical values for CF are in the range of 10 pF to 30 pF; it can be
adjusted for the best frequency response. The total error at the
output of the op amp can be computed by the formula:
R2
10kΩ
5V
VOUT =
V+
VOS
02731-D-055
The low offset voltage and low noise of the AD8605 make it a
great amplifier for instrumentation applications.
60
40
1k
10k
100k
FREQUENCY (Hz)
1M
10M
RCS
15V
Figure 54. Difference Amplifier CMRR vs. Frequency
R3
20kΩ
R2
10kΩ
C1
33pF
D/A CONVERSION
The low input bias current and offset voltage of the AD8605
make it an excellent choice for buffering the output of a current
output DAC.
VDD
VIN
Figure 55 shows a typical implementation of the AD8605 at the
output of a 12-bit DAC.
The DAC8143 output current is converted to a voltage by the
feedback resistor. The equivalent resistance at the output of the
DAC varies with the input code, as does the output capacitance.
Rev. D | Page 17 of 20
RP
VREF
RFB
AD7545
AGND
DB11
R1
10kΩ
OUT1
1/2
AD8606
R4
5kΩ10%
Figure 56. Bipolar Operation
VOUT
1/2
AD8606
02731-D-056
0
100
Grounding the positive input terminals in both stages reduces
errors due to the common-mode output voltage. Choosing R1,
R2, and R3 to match within 0.01% yields a CMRR of 74 dB and
maintains minimum gain error in the circuit.
02731-D-054
20
AD8605/AD8606/AD8608
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
8
5
4.00 (0.1574)
3.80 (0.1497) 1
4
3
1.27 (0.0500)
BSC
PIN 1
0.95 BSC
1.45 MAX
0.15 MAX
0.50
0.30
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
0.22
0.08
10°
5°
0°
SEATING
PLANE
0.60
0.45
0.30
0.50 (0.0196)
× 45°
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
1.90
BSC
1.30
1.15
0.90
6.20 (0.2440)
5.80 (0.2284)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 60. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8)
Figure 57. 5-Lead Small Outline Transistor Package [SOT-23] (RT-5)
5.10
5.00
4.90
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
0.25 (0.0098)
0.10 (0.0039)
14
8
1
7
6.20 (0.2441)
5.80 (0.2283)
1.27 (0.0500)
BSC
0.50 (0.0197)
× 45°
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
14
SEATING
PLANE
8
4.50
4.40
4.30
6.40
BSC
1
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
7
PIN 1
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
1.05
1.00
0.80
0.65
BSC
1.20
MAX
0.15
0.05
0.30
0.19
0.20
0.09
SEATING
COPLANARITY
PLANE
0.10
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 58. 14-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-14)
Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
3.00
BSC
8
0.94
0.90
0.86
5
4.90
BSC
3.00
BSC
0.50 REF
0.37
0.36
0.35
4
SEATING
PLANE
BOTTOM VIEW
0.87
PIN 1
IDENTIFIER
PIN 1
TOP VIEW
(BALL SIDE DOWN)
0.65 BSC
0.23
0.18
0.14
1.33
1.29
1.25
0.50
0.21
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8°
0°
0.17
0.14
0.12
0.80
0.60
0.40
0.20
0.50
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 59. 8-Lead Mini Small Outline Package [MSOP] (RM-8)
Figure 62. 5-Bump 2 × 1 × 2 Array MicroCSP [WLCSP] (CB-5)
Rev. D | Page 18 of 20
AD8605/AD8606/AD8608
ORDERING GUIDE
Model
AD8605ACB-REEL
AD8605ACB-REEL7
AD8605ART-R2
AD8605ART-REEL
AD8605ART-REEL7
AD8605ARTZ-REEL1
AD8605ARTZ-REEL71
AD8606ARM-R2
AD8606ARM-REEL
AD8606AR
AD8606AR-REEL
AD8606AR-REEL7
AD8608AR
AD8608AR-REEL
AD8608AR-REEL7
AD8608ARU
AD8608ARU-REEL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
5-Bump MicroCSP
5-Bump MicroCSP
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead TSSOP
14-Lead TSSOP
Z = Pb-free part.
Rev. D | Page 19 of 20
Package Option
CB-5
CB-5
RT-5
RT-5
RT-5
RT-5
RT-5
RM-8
RM-8
R-8
R-8
R-8
R-14
R-14
R-14
RU-14
RU-14
Branding
B3A
B3A
B3A
B3A
B3A
B3A
B3A
B6A
B6A
AD8605/AD8606/AD8608
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02731-0-5/04(D)
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