IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT2305B 3.3V ZERO DELAY CLOCK BUFFER FEATURES: • • • • • • • • • • • • DESCRIPTION: Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs Zero Input-Output Delay Output Skew < 250ps Low jitter <200 ps cycle-to-cycle IDT2305B-1 for Standard Drive IDT2305B-1H for High Drive No external RC network required Operates at 3.3V VDD Power down mode Available in SOIC package The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2305B enters power down. In this mode, the device will draw less than 25μA, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power. The IDT2305B is characterized for both Industrial and Commercial operation. FUNCTIONAL BLOCK DIAGRAM 8 CLKOUT REF 1 3 PLL CLK1 Control Logic 2 5 CLK2 CLK3 7 CLK4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SEPTEMBER 2007 1 c 2007 Integrated Device Technology, Inc. DSC 6994/4 IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol REF 1 8 CLKOUT CLK2 2 7 CLK4 CLK1 3 6 VDD GND 5 4 Rating Supply Voltage Range –0.5 to +4.6 V VI (2) Input Voltage Range (REF) –0.5 to +5.5 V VI Input Voltage Range –0.5 to V IIK (VI < 0) Input Clamp Current VDD+0.5 –50 mA IO (VO = 0 to VDD) Continuous Output Current ±50 mA VDD or GND Continuous Current ±100 mA TA = 55°C Maximum Power Dissipation 0.7 W TSTG Storage Temperature Range –65 to +150 °C Operating Commercial Temperature 0 to +70 °C Temperature Range Operating Industrial Temperature -40 to +85 °C Temperature Range (in still air) SOIC TOP VIEW Unit VDD (except REF) CLK3 Max. (3) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. APPLICATIONS: • • • • • SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs PIN DESCRIPTION Pin Name REF Pin Number Type Functional Description 1 IN Input reference clock, 5 Volt tolerant input CLK2(2) 2 Out Output clock CLK1 3 Out Output clock 4 Ground (1) (2) GND CLK3 (2) VDD CLK4 (2) CLKOUT (2) Ground 5 Out Output clock 6 PWR 3.3V Supply 7 Out Output clock 8 Out Output clock, internal feedback on this pin NOTES: 1. Weak pull down. 2. Weak pull down on all outputs. 2 IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES OPERATING CONDITIONS - COMMERCIAL Symbol Parameter Min. Max. Unit 3 3.6 V 0 70 °C — 30 pF VDD Supply Voltage TA Operating Temperature (Ambient Temperature) CL Load Capacitance < 100MHz Load Capacitance 100MHz - 133MHz — 10 Input Capacitance — 7 CIN pF DC ELECTRICAL CHARACTERISTICS - COMMERCIAL Symbol Parameter Conditions Min. Max. Unit VIL Input LOW Voltage Level — 0.8 V VIH Input HIGH Voltage Level 2 — V IIL Input LOW Current VIN = 0V — 50 μA IIH Input HIGH Current VIN = VDD — 100 μA VOL Output LOW Voltage Standard Drive — 0.4 V High Drive IOL = 12mA (-1H) VOH Output HIGH Voltage Standard Drive IOH = -8mA 2.4 — V High Drive IOH = -12mA (-1H) IDD_PD Power Down Current REF = 0MHz — 12 μA Supply Current Unloaded Outputs at 66.66MHz — 32 mA IDD IOL = 8mA SWITCHING CHARACTERISTICS (2305B-1) - COMMERCIAL Symbol t1 Parameter Output Frequency Conditions (1,2) Min. Typ. Max. Unit 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps tJ Cycle-to-Cycle Jitter, pk - pk Measured at 66.66MHz, loaded outputs — — 200 ps PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms tLOCK NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. 3 IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS (2305B-1H) - COMMERCIAL Symbol Min. Typ. Max. Unit Output Frequency 10pF Load 30pF Load 10 10 — — 133 100 MHz Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 % t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit #2 1 — — V/ns tJ Cycle-to-Cycle Jitter, pk - pk Measured at 66.66MHz, loaded outputs — — 200 ps PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms t1 tLOCK Parameter Conditions (1,2) NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. OPERATING CONDITIONS - INDUSTRIAL Symbol Parameter Min. Max. Unit VDD Supply Voltage 3 3.6 V TA Operating Temperature (Ambient Temperature) -40 +85 °C CL Load Capacitance < 100MHz — 30 pF Load Capacitance 100MHz - 133MHz — 10 Input Capacitance — 7 CIN pF DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL Symbol Parameter Conditions VIL Input LOW Voltage Level VIH Input HIGH Voltage Level IIL Input LOW Current VIN = 0V IIH Input HIGH Current VIN = VDD VOL Output LOW Voltage VOH IDD_PD IDD Output HIGH Voltage Standard Drive IOL = 8mA High Drive IOL = 12mA (-1H) Standard Drive IOH = -8mA High Drive IOH = -12mA (-1H) Min. Max. Unit — 0.8 V 2 — V — 50 μA — 100 μA — 0.4 V 2.4 — V Power Down Current REF = 0MHz — 25 μA Supply Current Unloaded Outputs at 66.66MHz — 35 mA 4 IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS (2305B-1) - INDUSTRIAL Symbol t1 Parameter Output Frequency (1,2) Conditions Min. Typ. Max. Unit 10pF Load 10 — 133 MHz 30pF Load 10 — 100 Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % t3 Rise Time Measured between 0.8V and 2V — — 2.5 ns t4 Fall Time Measured between 0.8V and 2V — — 2.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps tJ Cycle-to-Cycle Jitter, pk - pk Measured at 66.66MHz, loaded outputs — — 200 ps PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms tLOCK NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. SWITCHING CHARACTERISTICS (2305B-1H) - INDUSTRIAL Symbol t1 Parameter Conditions (1,2) Min. Typ. Max. Unit Output Frequency 10pF Load 30pF Load 10 10 — — 133 100 MHz Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66MHz 40 50 60 % Duty Cycle = t2 ÷ t1 Measured at 1.4V, FOUT <50MHz 45 50 55 % t3 Rise Time Measured between 0.8V and 2V — — 1.5 ns t4 Fall Time Measured between 0.8V and 2V — — 1.5 ns t5 Output to Output Skew All outputs equally loaded — — 250 ps t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 — 0 ±350 ps t7 Device-to-Device Skew Measured at VDD/2 on the CLKOUT pins of devices — 0 700 ps t8 Output Slew Rate Measured between 0.8V and 2V using Test Circuit #2 1 — — V/ns tJ Cycle-to-Cycle Jitter, pk - pk Measured at 66.66MHz, loaded outputs — — 200 ps PLL Lock Time Stable power supply, valid clock presented on REF pin — — 1 ms tLOCK NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs. 5 IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ZERO DELAY AND SKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay. For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally. REF TO CLKA/CLKB RELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS 1500 REF to CLKA/CLKB Delay (ps) 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 -500 -1000 -1500 OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF) 6 20 25 30 IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING WAVEFORMS 1.4V t1 Output t2 1.4V 1.4V 1.4V 1.4V Output t5 Output to Output Skew Duty Cycle Timing Output 0.8V 2V 2V 3.3V 0.8V VDD/2 REF 0V t4 t3 VDD/2 Output t6 Input to Output Propagation Delay All Outputs Rise/Fall Time CLKOUT Device 1 CLKOUT Device 2 VDD/2 VDD/2 t7 Device to Device Skew TEST CIRCUITS VDD 0.1μF VDD CLKOUT 0.1μF OUTPUTS 1KΩ CLKOUT OUTPUTS CLOAD 1KΩ VDD VDD 0.1μF 0.1μF GND GND GND GND Test Circuit 2 (t8, Output Slew Rate On -1H Devices) Test Circuit 1 (all Parameters Except t8) 7 10pF IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305B-1 Duty Cycle vs VDD (for 30pf loads over frequency - 3.3V, 25C) Duty Cycle vs VDD (for 10pF loads over frequency - 3.3V, 25C) 60 58 58 56 56 54 54 Duty Cycle (%) Duty Cycle (%) 60 52 33MHz 66MHz 100MHz 50 48 52 48 46 46 44 44 42 42 40 33MHz 66MHz 100MHz 133MHz 50 40 3 3.1 3.2 3.3 3.4 3.5 3 3.6 3.1 3.2 VDD (V) 3.5 3.6 Duty Cycle vs Frequency (for 10pF loads over temperature - 3.3V) 60 60 58 58 56 56 Duty Cycle (%) Duty Cycle (%) 3.4 VDD (V) Duty Cycle vs Frequency (for 30pf loads over temperature - 3.3V) 54 52 -40C 0C 25C 70C 85C 50 48 54 52 -40C 0C 25C 70C 85C 50 48 46 46 44 44 42 42 40 40 20 40 60 80 100 120 140 20 40 60 Frequency (MHz) 80 100 120 140 Frequency (MHz) IDD vs Number of Loaded Outputs (for 30pf loads over frequency - 3.3V, 25C) IDD vs Number of Loaded Outputs (for 10pF loads over frequency - 3.3V, 25C) 140 140 120 120 100 100 80 IDD (mA) IDD (mA) 3.3 33MHz 66MHz 100MHz 60 80 60 40 40 20 20 0 33MHz 66MHz 100MHz 0 0 2 4 6 0 8 Number of Loaded Outputs 2 4 6 Number of Loaded Outputs NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = Frequency (Hz)) 8 8 IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305B-1H Duty Cycle vs VDD (for 10pF loads over frequency - 3.3V, 25C) 60 60 58 58 56 56 54 54 Duty Cycle (%) Duty Cycle (%) Duty Cycle vs VDD (for 30pf loads over frequency - 3.3V, 25C) 52 33MHz 66MHz 100MHz 50 48 52 48 46 46 44 44 42 42 40 33MHz 66MHz 100MHz 133MHz 50 40 3 3.1 3.2 3.3 3.4 3.5 3 3.6 3.1 3.2 VDD (V) 3.5 3.6 Duty Cycle vs Frequency (for 10pF loads over temperature - 3.3V) 60 60 58 58 56 56 Duty Cycle (%) Duty Cycle (%) 3.4 VDD (V) Duty Cycle vs Frequency (for 30pf loads over temperature - 3.3V) 54 52 -40C 0C 25C 70C 85C 50 48 54 52 -40C 0C 25C 70C 85C 50 48 46 46 44 44 42 42 40 40 20 40 60 80 100 120 140 20 40 60 Frequency (MHz) 80 100 120 140 Frequency (MHz) IDD vs Number of Loaded Outputs (for 30pf loads over frequency - 3.3V, 25C) IDD vs Number of Loaded Outputs (for 10pF loads over frequency - 3.3V, 25C) 160 160 140 140 120 120 100 100 80 IDD (mA) IDD (mA) 3.3 33MHz 66MHz 100MHz 60 80 33MHz 66MHz 100MHz 60 40 40 20 20 0 0 0 2 4 6 0 8 2 4 6 8 Number of Loaded Outputs Number of Loaded Outputs NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = Frequency (Hz)) 9 IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX Device Type X Process XX Package Blank I Commercial (0oC to +70oC) Industrial (-40oC to +85oC) DC DCG Small Outline SOIC - Green 2305B-1 Zero Delay Clock Buffer 2305B-1H High Drive Output Ordering Code Package Type Operating Range IDT2305B-1DC 8-Pin SOIC Commercial IDT2305B-1DCG 8-Pin SOIC Commercial IDT2305B-1HDC 8-Pin SOIC Commercial IDT2305B-1HDCG 8-Pin SOIC Commercial IDT2305B-1HDCGI 8-Pin SOIC Industrial IDT2305B-1HDCI 8-Pin SOIC Industrial CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 10 for Tech Support: [email protected]