AD ADG432ABR Lc2mos precision quad spst switch Datasheet

a
FEATURES
44 V Supply Maximum Ratings
ⴞ15 V Analog Signal Range
Low On Resistance (<24 ⍀)
Ultralow Power Dissipation (3.9 ␮W)
Low Leakage (<0.25 nA)
Fast Switching Times
tON <165 ns
tOFF <130 ns
Break-Before-Make Switching Action
TTL/CMOS Compatible
Plug-in Replacement for DG411/DG412/DG413
LC2MOS
Precision Quad SPST Switches
ADG431/ADG432/ADG433
FUNCTIONAL BLOCK DIAGRAMS
S1
IN1
S1
IN1
D1
S2
IN2
D1
S2
IN2
ADG431
D2
S3
IN3
ADG432
IN3
D3
S4
IN4
D3
S4
IN4
D4
APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
D2
S3
D4
S1
IN1
D1
S2
IN2
ADG433
D2
S3
IN3
D3
S4
IN4
D4
GENERAL DESCRIPTION
The ADG431, ADG432 and ADG433 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC2MOS process which provides
low power dissipation yet gives high switching speed and low on
resistance.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipation making the parts ideally suited for portable and battery
powered instruments.
The ADG431, ADG432 and ADG433 contain four independent SPST switches. The ADG431 and ADG432 differ only in
that the digital control logic is inverted. The ADG431 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG432. The ADG433
has two switches with digital control logic similar to that of the
ADG431 while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when ON
and has an input signal range which extends to the supplies. In
the OFF condition, signal levels up to the supplies are blocked.
All switches exhibit break before make switching action for use
in multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital inputs.
SWITCHES SHOWN FOR A LOGIC "1" INPUT
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG431, ADG432 and ADG433 are fabricated on an
enhanced LC2MOS process giving an increased signal range
which extends fully to the supply rails.
2. Ultralow Power Dissipation
3. Low RON
4. Break-Before-Make Switching
This prevents channel shorting when the switches are configured as a multiplexer.
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG431, ADG432 and ADG433 can be operated from a
single rail power supply. The parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5 V.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ADG431/ADG432/ADG433–SPECIFICATIONS1
Dual Supply (V
DD
= +15 V ⴞ 10%, VSS = –15 V ⴞ 10%, V L = +5 V ⴞ 10%, GND = O V, unless otherwise noted)
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RON vs. VD (VS)
RON Drift
RON Match
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or I INH
CIN Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tON
B Versions
–40ⴗC to
+25ⴗC +85ⴗC
T Versions
–55ⴗC to
+25ⴗC +125ⴗC
VDD to VSS
17
24
15
0.5
5
± 0.05
± 0.25
± 0.05
± 0.25
± 0.1
± 0.35
26
±2
±2
±3
VDD to VSS
17
24
15
0.5
5
± 0.05
± 0.25
± 0.05
± 0.25
± 0.1
± 0.35
2.4
0.8
0.005
± 0.02
0.005
9
9
90
90
27
Units
V
Ω typ
VD = ± 8.5 V, IS = –10 mA;
Ω max
VDD = +13.5 V, VSS = –13.5 V
% typ
%/°C typ
% typ
VD = 0 V, IS = –10 mA
± 17
nA typ
nA max
nA typ
nA max
nA typ
nA max
2.4
0.8
V min
V max
± 0.02
µA typ
µA max
pF typ
± 15
± 15
Break-Before-Make Time Delay, tD 25
(ADG433 Only)
25
ns typ
ns max
ns typ
ns max
ns typ
Charge Injection
5
5
pC typ
OFF Isolation
68
68
dB typ
Channel-to-Channel Crosstalk
85
85
dB typ
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
35
9
9
35
pF typ
pF typ
pF typ
165
tOFF
60
175
60
130
145
POWER REQUIREMENTS
IDD
ISS
IL
Power Dissipation
0.0001
0.1
0.2
0.0001
0.1
0.2
0.0001
0.1
0.2
7.7
0.0001
0.1
0.2
0.0001
0.1
0.2
0.0001
0.1
0.2
7.7
Test Conditions/Comments
µA typ
µA max
µA typ
µA max
µA typ
µA max
µW max
VDD = +16.5 V, VSS = –16.5 V
VD = ± 15.5 V, VS = ⫿15.5 V;
Test Circuit 2
VD = ± 15.5 V, VS = ⫿15.5 V;
Test Circuit 2
VD = VS = ± 15.5 V;
Test Circuit 3
VIN = VINL or VINH
VDD = +15 V, VSS = –15 V
RL = 300 Ω, C L = 35 pF;
VS = ± 10 V; Test Circuit 4
RL = 300 Ω, C L = 35 pF;
VS = ± 10 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = +10 V;
Test Circuit 5
VS = 0 V, RS = 0 Ω, CL = 10 nF;
Test Circuit 6
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = +16.5 V, VSS = –16.5 V
Digital Inputs = 0 V or 5 V
NOTES
1
Temperature ranges are as follows: B Versions: –40 °C to +85°C; T Versions: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. B
ADG431/ADG432/ADG433
Single Supply (V
DD
= +12 V ⴞ 10%, VSS = O V, VL = +5 V ⴞ 10%, GND = O V, unless otherwise noted)
B Versions
–40ⴗC to
+25ⴗC +85ⴗC
Parameter
ANALOG SWITCH
Analog Signal Range
RON
T Versions
–55ⴗC to
+25ⴗC +125ⴗC
0 V to VDD
28
42
20
0.5
5
RON vs. VD (VS)
RON Drift
RON Match
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, Is (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 0.04
± 0.25
± 0.04
± 0.25
± 0.01
± 0.3
45
±2
±2
±3
0 V to VDD
28
42
20
0.5
5
± 0.04
± 0.25
± 0.04
± 0.25
± 0.01
± 0.3
2.4
0.8
0.005
CIN Digital Input Capacitance
± 0.01
0.005
9
9
165
165
45
Units
V
Ω typ
0 < VD < 8.5 V, IS = –10 mA;
Ω max
VDD = +10.8 V
% typ
%/°C typ
% typ
VD = 0 V, IS = –10 mA
± 17
nA typ
nA max
nA typ
nA max
nA typ
nA max
2.4
0.8
V min
V max
± 0.01
µA typ
µA max
pF typ
± 15
± 15
2
DYNAMIC CHARACTERISTICS
tON
Break-Before-Make Time Delay, tD 25
(ADG433 Only)
25
ns typ
ns max
ns typ
ns max
ns typ
Charge Injection
25
25
pC typ
OFF Isolation
68
68
dB typ
Channel-to-Channel Crosstalk
85
85
dB typ
CS (OFF)
CD (OFF)
CD, CS (ON)
9
9
35
9
9
35
pF typ
pF typ
pF typ
240
60
tOFF
240
60
115
115
POWER REQUIREMENTS
0.0001
0.03
0.1
0.0001
0.03
0.1
1.9
IDD
IL
Power Dissipation
0.0001
0.03
0.1
0.0001
0.03
0.1
1.9
Test Conditions/Comments
µA typ
µA max
µA typ
µA max
µW max
VDD = +13.2 V
VD = 12.2/1 V, VS = 1/12.2 V;
Test Circuit 2
VD = 12.2/1 V, VS = 1/12.2 V;
Test Circuit 2
VD = VS = +12.2 V/+1 V;
Test Circuit 3
VIN = VINL or VINH
VDD = +12 V, VSS = 0 V
RL = 300 Ω, CL = 35 pF;
VS = +8 V; Test Circuit 4
RL = 300 Ω, C L = 35 pF;
VS = +8 V; Test Circuit 4
RL = 300 Ω, C L = 35 pF;
VS1 = VS2 = +10 V;
Test Circuit 5
VS = 0 V, RS = 0 Ω, CL = 10 nF;
Test Circuit 6
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = +13.2 V
Digital Inputs = 0 V or 5 V
VL = +5.25 V
NOTES
1Temperature ranges are as follows: B Versions: –40 °C to +85°C; T Versions: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
Truth Table (ADG431/ADG432)
Truth Table (ADG433)
ADG431 In
ADG432 In
Switch Condition
Logic
Switch 1, 4
Switch 2, 3
0
1
1
0
ON
OFF
0
1
OFF
ON
ON
OFF
REV. B
–3–
ADG431/ADG432/ADG433
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
VL to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Analog, Digital Inputs2 . . . . . . . . . . VSS – 2 V to VDD + 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG431/ADG432/ADG433 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
D1 2
S1 3
ADG431
ADG432
ADG433
16
IN2
15
D2
14
S2
VDD
TOP VIEW
GND 5 (Not to Scale) 12 VL
VSS 4
13
S4 6
11
S3
D4 7
10
D3
IN4 8
9
IN3
ESD SENSITIVE DEVICE
ORDERING GUIDE
PIN CONFIGURATION
(DIP/SOIC)
IN1 1
WARNING!
Model1
Temperature Range
Package Options2
ADG431BN
ADG431BR
ADG431TQ
ADG431ABR
ADG432BN
ADG432BR
ADG432TQ
ADG432ABR
ADG433BN
ADG433BR
ADG433ABR
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
Q-16
R-16A3
N-16
R-16A
Q-16
R-16A3
N-16
R-16A
R-16A3
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers.
2
N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.
3
Trench isolated, latch-up proof parts. See Trench Isolation section.
TERMINOLOGY
VDD
Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may be
connected to GND.
Logic power supply (+5 V).
VL
GND
Ground (0 V) reference.
S
Source terminal. May be an input or output.
D
Drain terminal. May be an input or output.
IN
Logic control input.
Ohmic resistance between D and S.
RON
RON vs. VD (VS) The variation in RON due to a change in the analog input voltage with a constant load current.
Change in RON vs. temperature.
RON Drift
Difference between the R ON of any two switches.
RON Match
Source leakage current with the switch “OFF.”
IS (OFF)
Drain leakage current with the switch “OFF.”
ID (OFF)
Channel leakage current with the switch “ON.”
ID , IS (ON)
VD (V S)
Analog voltage on terminals D, S.
VSS
CS (OFF)
CD (OFF)
CD , CS (ON)
CIN
tON
tOFF
tD
Crosstalk
Off Isolation
Charge
Injection
–4–
“OFF” switch source capacitance.
“OFF” switch drain capacitance.
“ON” switch capacitance.
Input Capacitance to ground of a digital input.
Delay between applying the digital control input
and the output switching on.
Delay between applying the digital control input
and the output switching off.
“OFF” time or “ON” time measured between the
90% points of both switches, when switching
from one address state to another.
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
A measure of unwanted signal coupling through an
“OFF” switch.
A measure of the glitch impulse transferred from the
digital input to the analog output during switching.
REV. B
ADG431/ADG432/ADG433
Typical Performance Graphs
50
50
TA = +258C
VL = +5V
TA = +258C
VL = +5V
40
40
VDD = +5V
VSS = 0V
30
VDD = +10V
VSS = –10V
RON – V
RON – V
VDD = +5V
VSS = –5V
VDD = +12V
VSS = –12V
20
10
30
VDD = +10V
VSS = 0V
VDD = +12V
VSS = 0V
20
10
VDD = +15V
VSS = 0V
VDD = +15V
VSS = –15V
0
–20
0
–10
0
10
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
20
0
Figure 1. On Resistance as a Function of VD (VS) Dual
Supplies
5
10
15
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
20
Figure 4. On Resistance as a Function of VD (VS ) Single
Supply
100mA
50
VDD = +15V
VSS = –15V
VL = +5V
40
10mA
VDD = +15V
VSS = –15V
VL = +5V
4 SW
1 SW
I+, I–
ISUPPLY
RON – V
1mA
30
+1258C
100mA
20
10mA
+858C
IL
+258C
10
1mA
0
–20
–10
0
10
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
100nA
10
20
Figure 2. On Resistance as a Function of
VD (VS) for Different Temperatures
0.04
LEAKAGE CURRENT – nA
LEAKAGE CURRENT – nA
VDD = +15V
VSS = –15V
VL = +5V
VS = 615V
VD = 615V
IS (OFF)
0.1
ID (OFF)
0.01
ID (ON)
40
60
80
100
TEMPERATURE – 8C
120
140
Figure 3. Leakage Currents as a Function of Temperature
REV. B
0.02
1M
10M
VDD = +15V
VSS = –15V
TA = +258C
VL = +5V
ID (ON)
IS (OFF)
0.00
ID (OFF)
–0.02
–0.04
–20
0.001
20
1k
10k
100k
FREQUENCY – Hz
Figure 5. Supply Current vs. Input Switching Frequency
10
1
100
0
10
–10
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
20
Figure 6. Leakage Currents as a Function of V D (V S)
–5–
ADG431/ADG432/ADG433
120
T
R
E
N
C
H
100
OFF ISOLATION – dB
VG
VS
VDD = +15V
VSS = –15V
VL = +5V
P+
VD
P-CHANNEL
P+
N–
80
VG
VS
T
R
E
N
C
H
N-CHANNEL
N+
VD
N+
P–
T
R
E
N
C
H
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
60
Figure 9. Trench Isolation
APPLICATION
40
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 7. Off Isolation vs. Frequency
110
CROSSTALK – dB
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit shown is
typically 30 µV/µs.
VDD = +15V
VSS = –15V
VL = +5V
100
90
80
70
60
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 10 illustrates a precise, fast sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output VOUT follows the input signal VIN. In the hold
mode, SW1 is opened and the signal is held by the hold capacitor CH.
10M
Figure 8. Crosstalk vs. Frequency
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differential effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensation network RC and CC. This compensation network also
reduces the hold time glitch while optimizing the acquisition
time. Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the ± 10 V
input range. Both the acquisition and settling times are 850 ns.
+15V
TRENCH ISOLATION
+5V
2200pF
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
+15V
SW2
+15V
S
VIN
SW1
AD845
In junction isolation, the N and P wells of the PMOS and
NMOS transistors from a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch up. With trench isolation, this diode is removed, the result
being a latch-up proof switch.
D
S
D
–15V
RC
75V
CC
1000pF
CH
2200pF
AD711
VOUT
–15V
ADG431
ADG432
ADG433
–15V
Figure 10. Fast, Accurate Sample-and-Hold
–6–
REV. B
ADG431/ADG432/ADG433
Test Circuits
IDS
V1
S
VS
S
A
D
Test Circuit 1. On Resistance
S
A
+15V
+5V
0.1mF
3V
VS
VDD
VL
S
D
VIN
ADG431
VIN
ADG432
VOUT
RL
300V
IN
50%
50%
50%
50%
3V
CL
35pF
90%
90%
VOUT
VSS
GND
0.1mF
–15V
tON
tOFF
Test Circuit 4. Switching Times
+15V
+5V
0.1mF
0.1mF
3V
VDD
VS1
VS2
VIN
VL
S1
D1
S2
D2
RL2
300V
IN1, IN2
VIN
GND
50%
0V
VOUT1
VOUT2
RL1
300V
50%
90%
90%
VOUT1
CL1
35pF
0V
CL2
35pF
VSS
90%
VOUT2
90%
0V
tD
0.1mF
–15V
tD
Test Circuit 5. Break-Before-Make Time Delay
RS
VS
+15V
+5V
VDD
VL
S
D
3V
VOUT
VIN
CL
10nF
IN
GND
VSS
VOUT
Test Circuit 6. Charge Injection
REV. B
DVOUT
QINJ = CL 3 DVOUT
–15V
–7–
A
Test Circuit 3. On Leakage
Test Circuit 2. Off Leakage
0.1mF
D
VD
VS
VD
VS
RON = V1/IDS
ID (ON)
ID (OFF)
IS (OFF)
D
ADG431/ADG432/ADG433
+15V
+15V
+5V
VDD
VL
S
D
VOUT
RL
50V
VS
GND
VL
S
D
50V
VIN2
VOUT
VSS
VDD
VIN1
VS
IN
VIN
0.1mF
0.1mF
RL
50V
D
S
GND
VSS
NC
0.1mF
–15V
0.1mF
–15V
Test Circuit 7. Off Isolation
CHANNEL TO CHANNEL
CROSSTALK = 20 3 LOG VS/VOUT
C1826b–0–11/98
0.1mF
+5V
0.1mF
Test Circuit 8. Channel-to-Channel Crosstalk
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Cerdip
(Q-16)
0.005 (0.13) MIN
16-Lead SOIC
(R-16A)
0.080 (2.03) MAX
16
0.3937 (10.00)
0.3859 (9.80)
9
0.310 (7.87)
0.220 (5.59)
1
0.1574 (4.00)
0.1497 (3.80)
8
PIN 1
0.060 (1.52)
0.015 (0.38)
0.840 (21.34) MAX
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.150
(3.81)
MIN
SEATING
0.070 (1.78)
PLANE
0.030 (0.76)
16
9
1
8
0.2440 (6.20)
0.2284 (5.80)
0.320 (8.13)
0.290 (7.37)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
15°
0°
0.015 (0.38)
0.008 (0.20)
0.0500
SEATING (1.27)
PLANE BSC
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.0196 (0.50)
x 458
0.0099 (0.25)
88
0.0099 (0.25) 08 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
16-Lead Plastic DIP (Narrow)
(N-16)
0.840 (21.34)
0.745 (18.92)
9
1
8
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.280 (7.11)
0.240 (6.10)
0.130
(3.30)
MIN
0.100
(2.54)
BSC
0.070 (1.77) SEATING
0.045 (1.15) PLANE
0.325 (8.26)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
PRINTED IN U.S.A.
16
0.015 (0.381)
0.008 (0.204)
–8–
REV. B