MC74F161A MC74F163A SYNCHRONOUS PRESETTABLE BINARY COUNTER The MC74F161A and MC74F163A are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74F161A has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The MC74F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. • Synchronous Counting and Loading • High-Speed Synchronous Expansion • Typical Count Frequency of 120 MHz SYNCHRONOUS PRESETTABLE BINARY COUNTER FAST SHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM 16 VCC TC Q0 Q1 Q2 Q3 CET PE 16 15 14 13 12 11 10 9 1 N SUFFIX PLASTIC CASE 648-08 16 1 1 2 3 4 5 6 7 8 *R CP P0 P1 P2 P3 CEP GND *MR for MC74F161A *SR for MC74F163A D SUFFIX SOIC CASE 751B-03 16 1 FUNCTION TABLE SR PE CET CEP ACTION ON THE RISING CLOCK EDGE ( L X X X Reset (Clear) H L X X Load (Pn º H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) ) ORDERING INFORMATION MC74FXXXAJ Ceramic MC74FXXXAN Plastic MC74FXXXAD SOIC Qn) LOGIC SYMBOL H = HIGH Voltage Level; L = LOW Voltage Level; X = Don’t Care 9 STATE DIAGRAM 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 7 10 2 3 4 5 PE P0 P1 P2 P3 CEP TC CET CP *R Q0 Q1 Q2 Q3 1 14 13 12 VCC = PIN 16 GND = PIN 8 8 *MR for MC74F161A *SR for MC74F163A FAST AND LS TTL DATA 4-75 6 11 15 MC74F161A • MC74F163A LOGIC DIAGRAM P0 P2 P1 P3 PE MC74F161A MC74F163A CEP CET MC74F163A ONLY CP TC CP CP D CP D CD Q Q MC74F161A ONLY Q0 Q0 DETAIL A DETAIL A Q1 Q2 Q3 DETAIL A MR (MC74F161A) SR (MC74F163A) DETAIL A Q0 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FUNCTIONAL DESCRIPTION all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (MC74F161A) or SR (MC74F163A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The MC74F161A and MC74F163A use D-type edge-triggered flip-flops and changing the SR, PE, CEP, and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The MC74F161A and MC74F163A count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the MC74F161A) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (MC74F161A), synchronous reset (MC74F163A), parallel load, count-up and hold. Five control inputs Master Reset (MR, MC74F161A), Synchronous Reset (SR, MC74F163A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) — determine the mode of operation, as shown in the Function Table. A LOW signal on MR overrides FAST AND LS TTL DATA 4-76 MC74F161A • MC74F163A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 74 0 25 70 °C IOH Output Current — High 74 – 1.0 mA IOL Output Current — Low 74 20 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current Min Typ Max 2.0 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs 0.8 V Guaranteed Input LOW Voltage for All Inputs –1.2 V VCC = MIN, IIN = – 18 mA 74 2.5 3.4 V IOH = –1.0 mA VCC = 4.50 V 74 2.7 3.4 V IOH = –1.0 mA VCC = 4.75 V 0.5 V IOL = 20 mA VCC = MIN 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V –0.6 –1.2 mA VCC = MAX, VIN = 0.5 V – 150 mA VCC = MAX, VOUT = 0 V 55 mA VCC = MAX IIL Input LOW Current Data, CEP, Clock PE, CET, SR IOS Output Short Circuit Current (Note 2) ICC Power Supply Current 0.35 –60 37 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. fore not recommended for use as a clock or asynchronous reset for flip-flops, counters, or registers. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. The TC output is subject to decoding spikes due to internal race conditions and is there- FAST AND LS TTL DATA 4-77 MC74F161A • MC74F163A AC CHARACTERISTCS Symbol Parameter 74F 74F TA = +25°C TA = 0°C to 70°C VCC = +5.0 V VCC = 5.0 V ± 10% CL = 50 pF CL = 50 pF Min Max Min 6.0 3.5 Max 90 Unit fmax Maximum Count Frequency 100 tPLH Propagation Delay, Count 3.5 MHz tPHL CP to Qn (PE Input HIGH) 3.5 10 3.5 11 tPLH Propagation Delay 3.5 7.0 3.5 9.5 tPHL CP to Qn (PE Input LOW) 4.0 8.5 4.0 9.5 tPLH Propagation Delay 5.0 14 5.0 15 tPHL CP to TC 4.5 14 4.5 15 tPLH Propagation Delay 2.5 7.5 2.5 8.5 tPHL CET to TC 2.5 7.5 2.5 8.5 tPHL Propagation Delay MR to Qn (MC74F161A) 5.5 12 5.5 13 ns tPHL Propagation Delay MR to TC (MC74F161A) 4.5 10.5 4.5 11.5 ns 7.0 ns ns ns AC OPERATING REQUIREMENTS 74F 74F TA = +25°C TA = 0°C to 70°C VCC = +5.0 V VCC = 5.0 V ± 10% CL = 50 pF Symbol Parameter Min Max CL = 50 pF Min ts(H) Setup Time, HIGH or LOW 5.0 5.0 ts(L) Pn to CP 5.0 5.0 th(H) Hold Time, HIGH or LOW 2.0 2.0 th(L) Pn to CP 2.0 2.0 ts(H) Setup Time, HIGH or LOW 11 11.5 ts(L) PE or SR to CP 8.5 9.5 th(H) Hold Time, HIGH or LOW 2.0 2.0 th(L) PE or SR to CP 0 0 ts(H) Setup Time, HIGH or LOW 11 11.5 ts(L) CEP or CET to CP 5.0 5.0 th(H) Hold Time, HIGH or LOW 0 0 th(L) CEP or CET to CP 0 0 tw(H) Clock Pulse Width (Load) 5.0 5.0 tw(L) HIGH or LOW 5.0 5.0 tw(H) Clock Pulse Width (Count) 4.0 4.0 tw(L) HIGH or LOW 6.0 7.0 tw(L) MR Pulse Width, LOW (MC74F161A) 5.0 5.0 Recovery Time, MR to CP (MC74F161A) 6.0 trec Max Unit ns ns ns ns ns ns FAST AND LS TTL DATA 4-78 6.0