AMD AM29PL160CB-90EI

Am29PL160C
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new designs, S29GL016A
supersedes Am29PL160C. Please refer to the S29GL-A family data sheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes
only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 22143
Revision C
Amendment 7
Issue Date May 9, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29PL160C
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
This product has been retired and is not recommended for designs. For new designs, S29GL016A supersedes Am29PL160C. Please refer to the S29GL-A family data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■ 16 Mbit Page Mode device
— Byte (8-bit) or word (16-bit) mode selectable via
BYTE# pin
— Page size of 16 bytes/8 words: Fast page read
access from random locations within the page
■ Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ 5 V-tolerant data, address, and control signals
■ High performance read access times
— Page access times as fast as 25 ns at industrial
temperature range
— Random access times as fast as 65 ns
■ Power consumption (typical values at 5 MHz)
— 30 mA read current
— 20 mA program/erase current
— 1 µA standby mode current
— 1 µA Automatic Sleep mode current
■ Flexible sector architecture
— Sector sizes: One 16 Kbyte, two 8 Kbyte, one
224 Kbyte, and seven sectors of 256 Kbytes
each
— Supports full chip erase
■ Bottom boot block configuration only
■ Sector Protection
— A hardware method of locking a sector to prevent
any program or erase operations within that
sector
— Sectors can be locked via programming
equipment
— Temporary Sector Unprotect command
sequence allows code changes in previously
locked sectors
■ Minimum 1 million write cycles guarantee
per sector
■ 20-year data retention
■ Manufactured on 0.32 µm process technology
■ Software command-set compatible with JEDEC
standard
— Backward compatible with Am29F and Am29LV
families
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■ Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Package Options
— 44-pin SO (mask-ROM compatible pinout)
— 48-pin TSOP
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22143 Rev: C Amendment: 7
Issue Date: May 9, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29PL160C is a 16 Mbit, 3.0 Volt-only Page
mode Flash memory device organized as 2,097,152
bytes or 1,048,576 words.The device is offered in a 44pin SO or a 48-pin TSOP package. The word-wide
data (x16) appears on DQ15–DQ0; the byte-wide (x8)
data appears on DQ7–DQ0. This device can be programmed in-system or with in standard
EPROM programmers. A 12.0 V VPP or 5.0 VCC are
not required for write or erase operations.
The device offers access times of 65, 70, and 90 ns, allowing high speed microprocessors to operate without
wait states. To eliminate bus contention the device has
separate chip enable (CE#), write enable (WE#), and
output enable (OE#) controls.
The sector sizes are as follows: one 16 Kbyte, two
8 Kbyte, one 22 4 Kbyte an d seven sectors of
256 Kbytes each. The device is available in both top
and bottom boot versions.
Page Mode Features
The device is AC timing, pinout, and package compatible with 16 Mbit x 16 page mode Mask ROM. The
page size is 8 words or 16 bytes.
After initial page access is accomplished, the page
mode operation provides fast read access speed of
random locations within that page.
Standard Flash Memory Features
The device requires only a single 3.0 volt power supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an inter nal algorithm that
2
automatically times the program pulse widths and
verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only
two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a
program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memo r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a
programming equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29PL160C Device Bus Operations ................................8
Word/Byte Configuration .......................................................... 8
Requirements for Reading Array Data ..................................... 8
Read Mode ............................................................................... 8
Random Read (Non-Page Mode Read) ............................................8
Page Mode Read ...................................................................... 9
Table 2. Word Mode ..........................................................................9
Table 3. Byte Mode ...........................................................................9
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
Output Disable Mode .............................................................. 10
Table 4. Sector Address Table, Bottom Boot (Am29PL160CB) ......11
Autoselect Mode ..................................................................... 12
Table 5. Am29PL160C Autoselect Codes (High Voltage Method) ..12
Sector Protection/Unprotection ............................................... 12
Common Flash Memory Interface (CFI) . . . . . . . 13
Table 6. CFI Query Identification String ..........................................13
Table 7. System Interface String .....................................................14
Table 8. Device Geometry Definition ..............................................14
Table 9. Primary Vendor-Specific Extended Query ........................15
Hardware Data Protection . . . . . . . . . . . . . . . . . . 15
Low VCC Write Inhibit ......................................................................15
Write Pulse “Glitch” Protection ........................................................15
Logical Inhibit ..................................................................................15
Power-Up Write Inhibit ....................................................................15
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 16
Reading Array Data ................................................................ 16
Reset Command ..................................................................... 16
Autoselect Command Sequence ............................................ 16
Word/Byte Program Command Sequence ............................. 16
Unlock Bypass Command Sequence ..............................................17
Figure 1. Program Operation .......................................................... 17
Chip Erase Command Sequence ........................................... 17
Sector Erase Command Sequence ........................................ 18
Erase Suspend/Erase Resume Commands ........................... 18
Temporary Unprotect Enable/Disable Command Sequence .. 19
Figure 2. Erase Operation............................................................... 19
Command Definitions ............................................................. 20
Table 10. Am29PL160C Command Definitions ..............................20
Write Operation Status . . . . . . . . . . . . . . . . . . . . 21
DQ7: Data# Polling ................................................................. 21
Figure 3. Data# Polling Algorithm ................................................... 21
DQ6: Toggle Bit ...................................................................... 22
DQ2: Toggle Bit ...................................................................... 22
Reading Toggle Bits DQ6/DQ2 .............................................. 22
DQ5: Exceeded Timing Limits ................................................ 22
May 9, 2006 22143C7
Figure 4. Toggle Bit Algorithm........................................................ 23
DQ3: Sector Erase Timer ....................................................... 23
Table 11. Write Operation Status ................................................... 24
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25
Figure 5. Maximum Negative Overshoot Waveform ...................... 25
Figure 6. Maximum Positive Overshoot Waveform........................ 25
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 27
Figure 8. Typical ICC1 vs. Frequency ............................................. 27
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9. Test Setup....................................................................... 28
Table 12. Test Specifications ......................................................... 28
Key to Switching Waveforms . . . . . . . . . . . . . . . 28
Figure 10. Input Waveforms and Measurement Levels ................. 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. Conventional Read Operations Timings .......................
Figure 12. Page Read Timings ......................................................
Figure 13. BYTE# Timings for Read Operations............................
Figure 14. BYTE# Timings for Write Operations............................
Figure 15. Program Operation Timings..........................................
Figure 16. AC Waveforms for Chip/Sector Erase Operations........
Figure 17. Data# Polling Timings (During Embedded Algorithms).
Figure 18. Toggle Bit Timings (During Embedded Algorithms)......
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ............................................................
Figure 20. Alternate CE# Controlled Write Operation Timings ......
30
30
31
31
33
34
34
35
35
37
Erase and Programming Performance . . . . . . . 38
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 38
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 38
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 39
TS 048—48-Pin Standard Thin Small Outline Package ......... 39
SO 044—44-Pin Small Outline Package, Standard Pinout .... 40
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 41
Revision A (August 1998) ....................................................... 41
Revision A+1 (September 1998) ............................................ 41
Revision B (January 1999) ..................................................... 41
Revision B+1 (February 1999) ................................................ 41
Revision B+2 (March 5, 1999) ................................................ 41
Revision B+3 (May 14, 1999) ................................................. 41
Revision B+4 (June 25, 1999) ................................................ 41
Revision B+5 (July 26, 1999) .................................................. 41
Revision B+6 (September 2, 1999) ........................................ 41
Revision B+7 (February 4, 2000) ............................................ 41
Revision C (February 21, 2000) .............................................. 41
Revision C+1 (June 20, 2000) ................................................ 41
Revision C+2 (June 28, 2000) ................................................ 41
Revision C+3 (November 14, 2000) ....................................... 41
Revision C+4 (June 12, 2002) ................................................ 41
Revision C+5 (June 10, 2004) ................................................ 41
Revision C+6 (February 16, 2006) ......................................... 41
Revision C7 (May 9, 2006) ..................................................... 42
Am29PL160C
3
D A T A
S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Am29PL160C
Regulated Voltage Range: VCC =3.0–3.6 V
-65R
-70R
Full Voltage Range: VCC = 2.7–3.6 V
-90
Max access time, ns (tACC)
65
70
90
Max CE# access time, ns (tCE)
65
70
90
Max page access time, ns (tPACC)
25
25
30
Max OE# access time, ns (tOE)
25
25
30
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15
VCC
VSS
Erase Voltage
Generator
WE#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A19
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A-1
4
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
CONNECTION DIAGRAMS
BYTE#
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
WE#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin Standard TSOP
WE#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
May 9, 2006 22143C7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-Pin
Standard SO
Am29PL160C
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
VCC
VSS
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
NC
NC
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
5
D A T A
PIN CONFIGURATION
A0–A19
S H E E T
LOGIC SYMBOL
= 20 address inputs
20
DQ0–DQ15 = 16 data inputs/outputs
DQ15/A-1
BYTE#
A0–A19
= In word mode, functions as DQ15
(MSB data input/output)
In byte mode, functions as A-1
(LSB address input)
DQ0–DQ15
(A-1)
CE#
OE#
= Byte enable input
When low, enables byte mode
When high, enables word mode
WE#
BYTE#
CE#
= Chip Enable input
OE#
= Output Enable input
WE#
= Write Enable input
VCC
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS
= Device ground
NC
= Pin not connected internally
6
16 or 8
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29PL160C
B
-65R
S
I
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
F
= Industrial (–40°C to +85°C) with Pb-free package
PACKAGE TYPE
E
= 48-Pin Standard Thin Small Outline Package (TS 048)
(bottom boot devices only)
S
= 44-Pin Small Outline Package, Standard Pinout (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
B
=
Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29PL160C
16 Megabit (1 M x 16-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
Valid Combinations
(Bottom Boot)
Valid Combinations
Voltage Range
AM29PL160CB-65R
AM29PL160CB-70R
AM29PL160CB-90
May 9, 2006 22143C7
EI, SI,
EF, SF
VCC = 3.0–3.6 V
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
VCC = 2.7–3.6 V
Am29PL160C
7
D A T A
S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memor y
location. The register is composed of latches that store
the commands, along with the address and data information needed to execute the command. The contents
Table 1.
of the register serve as inputs to the internal state machine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the resulting output. The following subsections describe
each of these operations in further detail.
Am29PL160C Device Bus Operations
DQ8–DQ15
Operation
Read
Write
Standby
Output Disable
CE#
OE#
WE#
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
BYTE#
= VIL
L
L
H
AIN
DOUT
DOUT
L
H
L
AIN
DIN
DIN
DQ8–DQ14 = High-Z,
DQ15 = A-1
VCC ±
0.3 V
X
X
X
High-Z
High-Z
High-Z
L
H
H
X
High-Z
High-Z
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to Figure 11 for the timing diagram. ICC1 in
the DC Characteristics table represents the active current specification for reading array data.
Read Mode
Requirements for Reading Array Data
Random Read (Non-Page Mode Read)
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE# is
the power control and should be used for device selection. OE# is the output control and should be used to
gate data to the output pins if the device is selected.
The internal state machine is set for reading array data
upon device power-up, or after a reset command
(when not executing a program or erase operation).
This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this mode to obtain array data.
8
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
tACC–tOE time).
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
Page Mode Read
Table 2.
The Am29PL160C is capable of fast Page mode read
and is compatible with the Page mode Mask ROM
read operation. This mode provides faster read access
speed for random locations within a page. The Page
size of the Am29PL160C device is 8 words, or 16
bytes, with the appropriate Page being selected by the
higher address bits A3–A19 and the LSB bits A0–A2
(in the word mode) and A-1 to A2 (in the byte mode)
determining the specific word/byte within that page.
This is an asynchronous operation with the microprocessor supplying the specific word or byte location.
The random or initial page access is equal to tACC or
tCE and subsequent Page read accesses (as long as
the locations specified by the microprocessor falls
within that Page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Here again, CE# selects
the device and OE# is the output control and should be
used to gate data to the output pins if the device is selected. Fast Page mode accesses are obtained by
keeping A3–A19 constant and changing A0 to A2 to
select the specific word, or changing A-1 to A2 to select the specific byte, within that page.
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
Table 3.
Byte Mode
Byte
A2
A1
A0
A-1
Byte 0
0
0
0
0
Byte 1
0
0
0
1
Byte 2
0
0
1
0
Byte 3
0
0
1
1
Byte 4
0
1
0
0
Byte 5
0
1
0
1
Byte 6
0
1
1
0
Byte 7
0
1
1
1
Byte 8
1
0
0
0
Byte 9
1
0
0
1
Byte 10
1
0
1
0
Byte 11
1
0
1
1
Byte 12
1
1
0
0
Byte 13
1
1
0
1
Byte 14
1
1
1
0
Byte 15
1
1
1
1
The following tables determine the specific word and
byte within the selected page:
May 9, 2006 22143C7
Word Mode
Am29PL160C
9
D A T A
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes
or words. Refer to “Word/Byte Configuration” for
more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
10
S H E E T
bits on DQ7–DQ0. Standard read cycle timings and
ICC read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# pin is both held at VCC ± 0.3 V. (Note that this is a
more restricted voltage range than VIH.) If CE# is held
at VIH, but not within VCC ± 0.3 V, the device will be in
the standby mode, but the standby current will be
greater. The device requires standard access time
(tCE) for read access when the device is in either of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this
mode when addresses remain stable for tACC + 30 ns.
The automatic sleep mode is independent of the CE#,
WE#, and OE# control signals. Standard address access
timings provide new data when addresses are changed.
While in sleep mode, output data is latched and always
available to the system. Note that during Automatic Sleep
mode, OE# must be at VIH before the device reduces
current to the stated sleep mode specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
Table 4. Sector Address Table, Bottom Boot (Am29PL160CB)
Sector
A19
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
0
0
0
0
0
0
0
X
16/8
000000–003FFF
00000–01FFF
SA1
0
0
0
0
0
0
1
0
8/4
004000–005FFF
02000–02FFF
SA2
0
0
0
0
0
0
1
1
8/4
006000–007FFF
03000–03FFF
SA3
0
0
0
224/112
008000–03FFFF
04000–1FFFF
SA4
0
0
1
X
X
X
X
X
256/128
040000–07FFFF
20000–3FFFF
SA5
0
1
0
X
X
X
X
X
256/128
080000–0BFFFF
40000–5FFFF
SA6
0
1
1
X
X
X
X
X
256/128
0C0000–0FFFFF
60000–7FFFF
SA7
1
0
0
X
X
X
X
X
256/128
100000–13FFFF
80000–9FFFF
SA8
1
0
1
X
X
X
X
X
256/128
140000–17FFFF
A0000–BFFFF
SA9
1
1
0
X
X
X
X
X
256/128
180000–1BFFFF
C0000–DFFFF
SA10
1
1
1
X
X
X
X
X
256/128
1C0000–1FFFFF
E0000–FFFFF
May 9, 2006 22143C7
01000–11111
Am29PL160C
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
11
D A T A
S H E E T
Autoselect Mode
Table 5. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (Table 4). Table 5 shows the
remaining address bits that are don’t care. When all
necessary bits have been set as required, the prog r a m m i n g e q u i p m e n t m ay t h e n r e a d t h e
corresponding identifier code on DQ7-DQ0.
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed
with its corresponding programming algorithm. However, the autoselect codes can also be accessed insystem through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 5.
Description
Mode
Manufacturer ID: AMD
Device ID:
Am29PL160C
(Bottom Boot Block)
Word
Byte
Sector Protection Verification
Am29PL160C Autoselect Codes (High Voltage Method)
A19 A11
to
to
WE# A12 A10
CE#
OE#
L
L
H
L
L
H
L
L
L
L
A6
A5
to
A2
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
X
01h
22h
45h
X
45h
X
01h
(protected)
X
00h
(unprotected)
X
X
VID
X
L
X
L
L
X
X
VID
X
L
X
L
H
H
H
A9
A8
to
A7
SA
X
VID
X
L
X
H
L
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 10.
Sector Protection/Unprotection
The hardware sector protection feature disables both
p r o gra m a n d e ra s e o p e ra t i o n s i n a ny s e c t o r.
The hardware sector unprotection feature re-enables
both program and erase operations in previously
protected sectors.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
12
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Sector protection and unprotection must be implemented using programming equipment. The procedure
requires VID on address pin A9 and OE#. Details on
this method are provided in a supplement, publication
number 22239. Contact an AMD representative to request a copy.
The device features a temporary unprotect command
sequence to allow changing array data in-system. See
“Temporary Unprotect Enable/Disable Command Sequence” for more information.
Am29PL160C
22143C7 May 9, 2006
D A T A
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of dev i c e s. S o f t wa r e s u p p o r t c a n t h e n b e d ev i c e independent, JEDEC ID-independent, and forwardand backward-compatible for the specified flash device families. Flash vendors can standardize their
existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The system
Table 6.
S H E E T
can read CFI information at the addresses given in Tables 6–9. To terminate reading CFI data, the system
must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/overv i ew / c f i . h t m l . A l t e r n a t i ve l y, c o n t a c t a n A M D
representative for copies of these documents.
CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
May 9, 2006 22143C7
Description
Am29PL160C
13
D A T A
Table 7.
S H E E T
System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
1Bh
36h
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
38h
0036h
VCC Max. (write/erase), D7–D4: volt, D3–D0: 100 millivolt
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0004h
Typical timeout per single byte/word write 2N µs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 8.
Description
Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
27h
4Eh
0015h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0003h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0006h
0000h
0000h
0004h
Erase Block Region 4 Information
14
Description
Am29PL160C
22143C7 May 9, 2006
D A T A
Table 9.
S H E E T
Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
86h
0031h
Major version number, ASCII
44h
88h
0030h
Minor version number, ASCII
45h
8Ah
0000h
Address Sensitive Unlock
0 = Required, 1 = Not Required
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
90h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
94h
0000h
Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = 4 Word Linear Burst, 02 = 8 Word Linear Burst,
03 = 32 Linear Burst, 04 = 4 Word Interleave Burst
4Ch
98h
0002h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Description
HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 10 for command definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must pro-
May 9, 2006 22143C7
vide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
Am29PL160C
15
D A T A
S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device
operations. Table 10 defines the valid register command sequences. Writing incorrect address and
data values or writing them in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parameters, and Figure 11 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
16
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 10 shows the address and data requirements.
This method is an alternative to that shown in Table 5,
which is intended for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect mode,
and the system may read at any address any number of
times, without initiating another command sequence.
A r e a d c y c l e a t a d d r e s s X X 0 0 h r e t r ieve s t h e
manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector
address (SA) and the address 02h in word mode (or
04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 4 for
valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command. The program address and data are written next,
which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically generates the program pulses and verifies the programmed
cell margin. Table 10 shows the address and data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 or DQ6. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored.
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
START
Write Program
Command Sequence
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the
standard program command sequence. The unlock bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program address and data. Additional data is
programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the
standard program command sequence, resulting in
faster total programming time. Table 10 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Figure 1 illustrates the algorithm for the program operation. See the Program/Erase Operations table in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note: See Table 10 for program command sequence.
Figure 1.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
May 9, 2006 22143C7
Am29PL160C
17
D A T A
device returns to reading array data and addresses are
no longer latched.
Figure 2 illustrates the algorithm for the erase operation. See the Program/Erase Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 10 shows the address and data
requirements for the sector erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector
for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Suspend during the time-out period resets the device
to reading array data. The system must rewrite the
command sequence and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2.
(Refer to “Write Operation Status” for information on
these status bits.)
18
S H E E T
Figure 2 illustrates the algorithm for the erase operation. Refer to the Program/Erase Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 16 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard
program operation. See “Write Operation Status” for
more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase sus-
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
pend mode and continue the sector erase operation.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after
the device has resumed erasing.
START
Temporary Unprotect Enable/Disable
Command Sequence
Write Erase
Command Sequence
The temporary unprotect command sequence is a
four-bus-cycle operation. The sequence is initiated by
writing two unlock write cycles. A third write cycle sets
up the command. The fourth and final write cycle enables or disables the temporary unprotect feature. If
the temporary unprotect feature is enabled, all sectors
are temporarily unprotected. The system may program
or erase data as needed. When the system writes the
temporary unprotect disable command sequence, all
sectors return to their previous protected or unprotected settings. See Table 10 for more information.
Data Poll
from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 2.
May 9, 2006 22143C7
Am29PL160C
Erase Operation
19
D A T A
S H E E T
Command Definitions
Cycles
Table 10.
Command
Sequence
(Note 1)
Am29PL160C Command Definitions
First
Addr Data
1
RA
RD
Reset (Note 7)
1
XXX
F0
Autoselect (Note 8)
Read (Note 6)
Manufacturer ID
Device ID,
Bottom Boot Block
Sector Protect Verify
(Note 9)
CFI Query (Note 10)
Program
Unlock Bypass
Word
Byte
Word
Byte
4
4
Word
555
AAA
555
AAA
AAA
Word
55
Byte
Word
Byte
1
4
3
2AA
555
2AA
555
AA
555
AAA
555
AAA
55
55
2AA
AA
Byte
Word
AA
555
4
Byte
AA
Second
Addr Data
555
AA
AA
2AA
555
2AA
555
55
55
XXX
A0
PA
PD
XXX
90
XXX
00
Sector Erase
Word
Byte
6
6
AAA
555
AAA
AA
AA
Erase Suspend (Note 13)
1
XXX
B0
Erase Resume (Note 14)
1
XXX
30
Temporary Unprotect Enable
Temporary Unprotect
Disable
Word
Byte
Word
Byte
4
4
555
AAA
555
AAA
90
X00
01
X01
2245
X02
45
(SA)
X02
XX00
(SA)
X04
00
PA
PD
Fifth
Addr Data
Sixth
Addr Data
XX01
01
98
2
Byte
90
AAA
2
Chip Erase
555
AAA
90
555
Unlock Bypass Reset (Note 12)
555
555
AAA
55
Unlock Bypass Program (Note 11)
Word
Bus Cycles (Notes 2–5)
Third
Fourth
Addr
Data Addr Data
AA
AA
2AA
555
2AA
555
2AA
555
2AA
555
55
55
55
55
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
A0
20
80
80
555
AAA
555
AAA
AA
AA
E0
XXX
01
E0
XXX
00
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
Legend:
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles.
5. Address bits A19–A11 are don’t cares for unlock and command
cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data
when device is in the autoselect mode, or if DQ5 goes high (while
the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read
cycle.
20
9. The data is 00h for an unprotected sector and 01h for a protected
sector. See “Autoselect Command Sequence” for more
information.
10. Command is valid when device is ready to read array data or
when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
14. The Erase Resume command is valid only during the Erase Suspend mode.
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 11 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ6 while Output Enable (OE#) is asserted low. See
Figure 16 in the “AC Characteristics” section.
Table 11 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge
of the final WE# pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
No
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to
“1”; prior to this, the device outputs the “complement,”
or “0.” The system must provide an address within any
of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected.
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5
Figure 3.
May 9, 2006 22143C7
Yes
Am29PL160C
Data# Polling Algorithm
21
D A T A
DQ6: Toggle Bit
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
Table 11 shows the outputs for Toggle Bit I on DQ6.
Figure 4 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. Figure 18 in the “AC Characteristics” section shows the toggle bit timing diagrams.
Figure 19 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit”.
DQ2: Toggle Bit
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
22
S H E E T
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for
erasure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 11 to compare outputs
for DQ2 and DQ6.
Figure 4 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit
subsection. Figure 18 shows the toggle bit timing diagram. Figure 19 shows the differences between DQ2
and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system
must write the reset command to return to reading
array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
condition that indicates the program or erase cycle
was not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
START
Read DQ7–DQ0
Read DQ7–DQ0
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
(Note 1)
DQ3: Sector Erase Timer
Toggle Bit
= Toggle?
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3 if
the system can guarantee that the time between additional sector erase commands will always be less than
50 μs. See also the “Write Operation Status” section.
No
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read
DQ3. If DQ3 is “1”, the internally controlled erase cycle
has begun; all further commands (other than Erase
Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional
sector erase commands. To ensure the command has
been accepted, the system software should check the
status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second
status check, the last command might not have been
accepted. Table 11 shows the outputs for DQ3.
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 4.
May 9, 2006 22143C7
Toggle Bit Algorithm
Am29PL160C
23
D A T A
Table 11.
Erase
Suspend
Mode
Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ7#
Toggle
0
N/A
No toggle
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
Operation
Standard
Mode
S H E E T
Embedded Program Algorithm
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
24
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . -65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
A9 and OE# (Note 2) . . . . . . . . . . –0.5 V to +13.0 V
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
All other pins (Note 1). . . . . . . . . . . –0.5 V to +5.5 V
20 ns
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Figure 5. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input at I/O pins may overshoot VSS to
-2.0 V for periods of up to 20 ns. Maximum DC voltage on
output and I/O pins is VCC + 0.5 V. During voltage
transitions output pins may overshoot to VCC + 2.0 V for
periods up to 20 ns.
2. Minimum DC input voltage on pins A9 and OE# is –0.5 V.
During voltage transitions, A9 and OE# may overshoot
VSS to -2.0 V for periods of up to 20 ns. Maximum DC
input voltage on pin A9 and OE# is +13.0 V which may
overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns
20 ns
Figure 6. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC for regulated voltage range. . . . . . . 3.0 V to 3.6 V
VCC for full voltage range . . . . . . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
May 9, 2006 22143C7
Am29PL160C
25
D A T A
S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Description
Test Conditions
Min
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
ILI
Input Load Current
VIN = VSS to 5.5 V,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to 5.5 V,
VCC = VCC max
ICC1
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH
30
50
mA
ICC2
VCC Active Write Current
(Notes 2, 4, 5)
CE# = VIL, OE# = VIH
20
30
mA
ICC3
VCC Standby Current (Note 2)
CE# = VCC±0.3 V
1
5
µA
Automatic Sleep Mode
(Notes 2, 3, 6)
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V
OE# = VIH
1
5
ICC4
OE# = VIL
8
20
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
5.5
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 3.3 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
0.45
V
VOH1
Output High Voltage
VOH2
VLKO
µA
IOH = –2.0 mA, VCC = VCC min
0.85 x VCC
IOH = –100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage
(Note 4)
2.3
V
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. The Automatic Sleep Mode current is dependent on the state of OE#.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 200 nA.
6. Not 100% tested.
26
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
DC CHARACTERISTICS (Continued)
Zero Power Flash
Supply Current in mA
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 7.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
3.6 V
Supply Current in mA
8
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 8. Typical ICC1 vs. Frequency
May 9, 2006 22143C7
Am29PL160C
27
D A T A
S H E E T
TEST CONDITIONS
Table 12.
Test Specifications
3.3 V
Test Condition
2.7 kΩ
Device
Under
Test
CL
-70R,
-90
-65R
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
6.2 kΩ
Input Rise and Fall Times
5
ns
0.0–3.0
V
Input timing measurement
reference levels
1.5
V
Output timing measurement
reference levels
1.5
V
Input Pulse Levels
Note: Diodes are IN3064 or equivalent
Figure 9.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
3.0 V
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
1.5 V
Measurement Level
1.5 V
Output
0.0 V
Figure 10.
28
Input Waveforms and Measurement Levels
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address Access Time
tELQV
tCE
Chip Enable to Output Delay
tPACC
Test Setup
-65R
-70R
-90
Unit
Min
65
70
90
ns
CE#=VIL,
OE#=VIL
Max
65
70
90
ns
OE#=VIL
Max
65
70
90
ns
Page Access Time
Max
25
25
30
ns
25
25
30
ns
tGLQV
tOE
Output Enable to Output Valid
Max
tEHQZ
tDF
Chip Enable to Output High Z
Max
20
ns
tGHQZ
tDF
Output Enable to Output High Z
Max
20
ns
Read
0
ns
Toggle and
Data# Polling
10
ns
0
ns
tAXQX
tOEH
Output Enable
Hold Time (Note 1)
tOH
Output Hold Time from Addresses
Min
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 12 for test specifications.
May 9, 2006 22143C7
Am29PL160C
29
D A T A
S H E E T
AC CHARACTERISTICS
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
0V
Figure 11.
Conventional Read Operations Timings
Same Page
A3-A19
A-1-A2
Aa
Ab
tPACC
tACC
Data Bus
Qa
Ad
Ac
tPACC
Qb
tPACC
Qc
Qd
CE#
OE#
Note: Word Configuration: Toggle A0, A1, A2. Byte Configuration: Toggle A-1, A0, A1, A2.
Figure 12.
30
Page Read Timings
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std
Speed Options
Description
-65R
-70R
-90
5
Unit
tELFL/tELFH
CE# to BYTE# Switching Low or High
Max
ns
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
25
25
30
ns
tFHQV
BYTE# Switching High to Output Active
Min
65
70
90
ns
CE#
OE#
BYTE#
BYTE#
Switching
from word
to byte
mode
tELFL
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Figure 13.
BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 14.
May 9, 2006 22143C7
BYTE# Timings for Write Operations
Am29PL160C
31
D A T A
S H E E T
AC CHARACTERISTICS
Program/Erase Operations
Parameter
Speed Options
Unit
JEDEC
Std
Description
-65R
-70R
-90
tAVAV
tWC
Write Cycle Time (Note 1)
Min
65
70
90
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
45
45
ns
tDVWH
tDS
Data Setup Time
Min
35
35
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
0
ns
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
30
ns
Byte
Typ
7
µs
tWHWH1
tWHWH1
Programming Operation (Note 2)
Word
Typ
9
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
5
sec
VCC Setup Time (Note 1)
Min
50
µs
tVCS
35
35
35
ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
32
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
Read Status Data (last two cycles)
PA
PA
PA
tAH
CE#
tCH
tGHWL
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
DOUT
tVCS
VCC
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 15.
May 9, 2006 22143C7
Program Operation Timings
Am29PL160C
33
D A T A
S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tGHWL
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 16.
AC Waveforms for Chip/Sector Erase Operations
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle
Figure 17.
34
Data# Polling Timings (During Embedded Algorithms)
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ6/DQ2
High Z
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle
Figure 18.
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Toggle Bit Timings (During Embedded Algorithms)
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations
May 9, 2006 22143C7
Am29PL160C
35
D A T A
S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-65R
-70R
-90
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
65
70
90
ns
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
45
45
ns
tDVEH
tDS
Data Setup Time
Min
35
35
45
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
30
Typ
7
tWHWH1
Programming Operation (Note
2)
Byte
tWHWH1
Word
Typ
9
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
5
0
35
35
ns
35
ns
ns
µs
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
36
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
AC CHARACTERISTICS
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tDH
DQ7#
Data
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
Figure 20.
May 9, 2006 22143C7
Alternate CE# Controlled Write Operation Timings
Am29PL160C
37
D A T A
S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Sector Erase Time
5
60
s
Chip Erase Time
40
Byte Programming Time
7
300
µs
Word Programming Time
9
360
µs
Comments
Excludes 00h programming
prior to erasure (Note 4)
s
Chip Programming Time
Byte Mode
14
42
s
(Note 3)
Word Mode
9
27
s
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 10 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9 and OE#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
TSOP
7.5
9
pF
CIN2
Control Pin Capacitance
SO
8
10
pF
VIN = 0
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
* For reference only. BSC is an ANSI standard for Basic Space Centering.
38
Am29PL160C
22143C7 May 9, 2006
D A T A
S H E E T
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
May 9, 2006 22143C7
Am29PL160C
39
D A T A
S H E E T
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package, Standard Pinout
Dwg rev AC; 10/99
40
Am29PL160C
22143C7 May 9, 2006
D A T A
REVISION SUMMARY
S H E E T
Revision B+6 (September 2, 1999)
Connection Diagrams
Revision A (August 1998)
Initial release.
Corrected the pinouts of pins 1, 2, 43, and 44 on the
reverse SO diagram.
Revision A+1 (September 1998)
Revision B+7 (February 4, 2000)
Sector Protection/Unprotection
Global
Added reference to Temporary Unprotect Enable/Disable command sequence.
Added 48-pin TSOP.
Common Flash Memory Interface (CFI)
Revision C (February 21, 2000)
Deleted reference to upper address bits in word mode.
Global
The “preliminary” designation has been removed from
the document. Parameters are now stable, and only
speed, package, and temperature range combinations
are expected to change in future data sheet revisions.
Revision B (January 1999)
Ordering Information
Deleted commercial temperature rating.
Added dash to ordering part numbers.
DC Characteristics
Corrected ICC1 test condition for OE# to VIH.
Revision C+1 (June 20, 2000)
Revision B+1 (February 1999)
Global
DC Characteristics
Deleted the SOR44 package. Deleted references to
top boot configuration.
Replaced TBDs for ICC4 with specifications.
Product Selector Guide, Ordering Information
Revision B+2 (March 5, 1999)
Added -90R speed option.
Distinctive Characteristics
In the first subbullet under the Flexible Sector Architecture bullet, deleted the reference to “one 8 Kbyte”
sector.
Revision B+3 (May 14, 1999)
Global
Deleted the 60R speed option and added the 65R
speed option.
Revision C+2 (June 28, 2000)
Command Definitions
Command Definitions table: Corrected address in the
sixth cycle of the chip erase command sequence from
2AA to AAA.
Revision C+3 (November 14, 2000)
Added table of contents.
Common Flash Memory Interface (CFI)
Revision C+4 (June 12, 2002)
Corrected the data for the following CFI hex addreses:
38, 39, 3C, 4C.
Global
Absolute Maximum Ratings
Corrected the maximum rating for all other pins to +5.5
V.
Deleted references to hardware reset (RESET#) input.
Added reverse pinout SO package. Deleted 90R
speed option.
TSOP and SO Pin Capacitance
Revision B+4 (June 25, 1999)
Added TSOP pin capacitance.
Changed data sheet status to preliminary. Deleted the
70 ns, full voltage range speed option.
Revision C+5 (June 10, 2004)
Revision B+5 (July 26, 1999)
Added Pb-free package OPNs
Global
Revision C+6 (February 16, 2006)
Added the reverse pinout SO package. Deleted the
TSOP package.
Global
Physical Dimensions
Ordering Information
Deleted 120 ns speed option.
Restored section.
May 9, 2006 22143C7
Am29PL160C
41
D A T A
S H E E T
Revision C7 (May 9, 2006)
Added migration and obsolescence information.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products
Trademarks
Copyright © 2004–2006 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
42
Am29PL160C
22143C7 May 9, 2006