IDT IDT49C460DFF 32-bit cmos error detection and correction unit Datasheet

IDT49C460
IDT49C460A
IDT49C460B
IDT49C460C
IDT49C460D
IDT49C460E
32-BIT CMOS
ERROR DETECTION
AND CORRECTION UNIT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Fast
Detect
10ns (max.)
12ns (max.)
16ns (max.)
25ns (max.)
30ns (max.)
40ns (max.)
•
•
•
•
•
•
•
•
•
The IDT49C460s are high-speed, low-power, 32-bit Error
Detection and Correction Units which generate check bits on
a 32-bit data field according to a modified Hamming Code and
correct the data word when check bits are supplied. The
IDT49C460s are performance-enhanced functional replacements for 32-bit versions of the 2960. When performing a read
operation from memory, the IDT49C460s will correct 100% of
all single bit errors and will detect all double bit errors and
some triple bit errors.
The IDT49C460s are easily cascadable to 64-bits. Thirtytwo-bit systems use 7 check bits and 64-bit systems use 8
check bits. For both configurations, the error syndrome is
made available.
The IDT49C460s incorporate two built-in diagnostic modes.
Both simplify testing by allowing for diagnostic data to be
entered into the device and to execute system diagnostics
functions.
They are fabricated using a CMOS technology designed for
high-performance and high-reliability. The devices are packaged in a 68-pin ceramic PGA, PLCC and Ceramic Quad
Flatpack.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
Correct
14ns (max.)
18ns (max.)
24ns (max.)
30ns (max.)
36ns (max.)
49ns (max.)
— IDT49C460E
— IDT49C460D
— IDT49C460C
— IDT49C460B
— IDT49C460A
— IDT49C460
Low-power CMOS
— Commercial: 95mA (max.)
— Military: 125mA (max.)
Improves system memory reliability
— Corrects all single bit errors, detects all double and some
triple-bit errors
Cascadable
— Data words up to 64-bits
Built-in diagnostics
— Capable of verifying proper EDC operation via software
control
Simplified byte operations
— Fast byte writes possible with separate byte enables
Functional replacement for 32- and 64-bit configurations of
the AM29C60 and AM29C660
Available in PGA, PLCC and Fine Pitch Flatpack
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962–88533
FUNCTIONAL BLOCK DIAGRAM
CB0–7
8
DATA0–31
DATA
LATCH
OE BYTE0–3
32
ERROR
CORRECT
ERROR
DECODE
8
MUX
4
8
32
32
DATA
LATCH
CHECK BIT
GENERATE
SC0–7
8
OESC
MUX
MUX
8
CHECK BIT
IN LATCH
LE IN
13
MUX
DIAGNOSTIC
LATCH
ERROR
DETECT
ERROR
MULT ERROR
8
LEDIAG
LEOUT/GENERATE
CORRECT
CODE ID1,0
DIAG MODE1,0
SYNDROME
GENERATE
5
CONTROL
LOGIC
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2584 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1995 Integrated Device Technology, Inc.
11.6
AUGUST 1995
DSC-9017/8
1
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
D 31
D30
D29
D28
D 27
D26
D 25
GND
OE3
LEIN
DIAG MODE1
DIAG MODE 0
CODE ID 1
CODE ID0
D1
D0
OE 0
PIN CONFIGURATIONS
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
J68–1
D24
D23
D22
D21
D20
D19
D18
D17
VCC
D16
OE2
LEOUT/GENERATE
CORRECT
LEDIAG
ERROR
MULT ERROR
GND
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OE SC
OE1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CB 7
CB 6
CB5
CB 4
CB3
CB 2
CB1
CB0
SC 0
SC 1
SC 2
SC 3
SC4
SC 5
SC6
SC 7
VCC
D2
D3
D4
D5
D6
D7
D8
GND
D9
D10
D11
D12
D13
D14
D15
DESIGNATES
PIN 1 FOR
PLCC ONLY
2584 drw 02
PLCC
TOPVIEW
11.6
2
OE3
D 31
D30
D29
D28
D 27
D26
D 25
GND
CODE ID 0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LEIN
DIAG MODE1
DIAG MODE0
CODE ID1
D1
D0
OE 0
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN 1 IDENTIFICATION
F68 - 2
D24
D23
D22
D21
D20
D19
D18
D17
VCC
D16
OE2
LEOUT/GENERATE
CORRECT
LEDIAG
ERROR
MULT ERROR
GND
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2584 drw 03
OE SC
OE1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CB 7
CB 6
CB5
CB 4
CB3
CB 2
CB1
CB0
SC 0
SC 1
SC2
SC 3
SC4
SC 5
SC6
SC 7
VCC
D2
D3
D4
D5
D6
D7
D8
GND
D9
D10
D11
D12
D13
D14
D15
FINE PITCH FLATPACK
TOPVIEW
11.6
3
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
51
53
52
DIAG MODE0
CODE ID1
LEIN
DIAG MODE1
D0
OE 0
D1
68
46
44
42
40
38
49
47
45
43
41
39
37
36
34
35
55
54
32
33
57
56
30
31
59
58
28
29
61
60
26
27
63
62
24
25
65
64
22
23
67
66
20
21
G68 – 1
1
3
5
7
9
11
13
15
18
2
4
6
8
10
12
14
16
17
OESC
SC7
SC6
SC5
SC4
SC3
SC2
SC1
SC0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
19
2584 drw 04
OE 1
OE3
48
VCC
D2
D3
D4
D5
D6
D7
D8
GND
D9
D10
D11
D12
D13
D14
D 15
CB7
D25
D27
D26
D29
D28
D31
D30
CODE ID0
50
GND
ERROR
MULT ERROR
LEOUT/GENERATE
CORRECT
LEDIAG
OE 2
D 24
GND
D 23
D22
D 21
D20
D 19
D18
D 17
VCC
D 16
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PGA
TOPVIEW
11.6
4
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Pin Name
I/O
Description
I/O
32 bidirectional data lines provide input to the Data Input Latch and Diagnostic Latch and also receive output from
the Data Output Latch. DATA0 is the LSB; DATA31 is the MSB.
CB0–7
I
Eight check bit input lines input check bits for error detection and also used to input syndrome bits for error
correction in 64-bit applications.
LEIN
I
Latch Enable is for the Data Input Latch. Controls latching of the input data. Data Input Latch and Check Bit Input
Latch are latched to their previous state when LOW. When HIGH, the Data Input Latch and Check Bit Input Latch
follow the input data and input check bits.
DATA0–31
LEOUT/
A multifunction pin which, when LOW, is in the Check Bit Generate Mode. In this mode, the device generates the
check bits or GENERATE partial check bits specific to the data in the Data Input Latch. The generated check bits
are placed on the SC outputs. Also, when LOW, the Data Out Latch is latched to its previous state.
GENERATE
When HIGH, the device is in the Detect or Correct Mode. In this mode, the device detects single and multiple
errors and generates syndrome bits based upon the contents of the Data Input Latch and Check Bit Input Latch.
In the Correct Mode, single bit errors are also automatically corrected and the corrected data is placed at the
inputs of the Data Output Latch. The syndrome result is placed on the SC outputs and indicates in a coded form
the number of errors and the specific bit-in-error. When HIGH, the Data Output Latch follows the output of the
Data Input Latch as modified by the correction logic network. In Correct Mode, single bit errors are corrected by
the network before being loaded into the Data Output Latch. In Detect Mode, the contents of the Data Input Latch
are passed through the correction network unchanged into the Data Output Latch. The Data Output Latch is
disabled, with its contents unchanged, if the EDC is in the Generate Mode.
SC0–7
O
Syndrome Check Bit outputs. Eight outputs which hold the check bits and partial check bits when the EDC is in
the Generate Mode and will hold the syndrome/partial syndrome bits when the device is in the Detect or Correct
modes. All are 3-state outputs.
OESC
I
Output Enable—Syndrome Check Bits. In the HIGH condition, the SC outputs are in the high impedance state.
When LOW, all SC output lines are enabled.
ERROR
O
In the Detect or Correct Mode, this output will go LOW if one or more data or check bits contain an error. When
HIGH, no errors have been detected. This pin is forced HIGH in the Generate Mode.
MULT
ERROR
O
In the Detect or Correct Mode, this output will go LOW if two or more bit errors have been detected. A HIGH level
indicates that either one or no errors have been detected. This pin is forced HIGH in the Generate Mode.
CORRECT
I
The correct input which, when HIGH, allows the correction network to correct any single-bit error in the Data Input
Latch (by complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the device will
drive data directly from the Data Input Latch to the Data Output Latch without correction.
OE BYTE0–3
I
Output Enable—Bytes 0, 1, 2, 3. Data Output Latch. Control the three-state output buffers for each of the four
bytes of the Data Output Latch. When LOW, they enable the output buffer of the Data Output Latch. When HIGH,
they force the Data Output Latch buffer into the high impedance mode. One byte of the Data Output Latch is
easily activated by separately selecting the four enable lines.
DIAG
MODE1,0
I
Select the proper diagnostic mode. They control the initialization, diagnostic and normal operation of the EDC.
CODE ID1,0
I
These two code identification inputs identify the size of the total data word to be processed. The two allowable
data word sizes are 32 and 64 bits and their respective modified Hamming Codes are designated 32/39 and
64/72. Special CODE ID1,0, input 01 is also used to instruct the EDC that the signals CODE ID1,0, DIAG MODE1,0
and CORRECT are to be taken from the Diagnostic Latch rather than from the input control lines.
LEDIAG
I
This is the Latch Enable for the Diagnostic Latch. When HIGH, the Diagnostic Latch follows the 32-bit data on the
input lines. When LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic
Latch holds diagnostic check bits and internal control signals for CODE ID1,0, DIAG MODE1,0 and CORRECT.
2584 tbl 01
11.6
5
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
EDC ARCHITECTURE SUMMARY
ERROR DETECTION LOGIC
The IDT49C460s are high-performance cascadable EDCs
used for check bit generation, error detection, error correction
and diagnostics. The function blocks for this 32-bit device
consist of the following:
• Data Input Latch
• Check Bit Input Latch
This part of the device decodes the syndrome bits
generated by the Syndrome Generation Logic. With no errors
in either the input data or check bits, both the ERROR and
MULTERROR outputs are HIGH. ERROR will go low if one
error is detected. MULTERROR and ERROR will both go low
if two or more errors are detected.
•
•
•
•
ERROR CORRECTION LOGIC
Check Bit Generation Logic
Syndrome Generation Logic
Error Detection Logic
Error Correction Logic
• Data Output Latch
• Diagnostic Latch
• Control Logic
In single error cases, this logic complements (corrects) the
single data bit-in-error. This corrected data is loaded into the
Data Output Latch, which can then be read onto the bidirectional data lines. If the error is resulting from one of the check
bits, the correction logic does not place corrected check bits
on the syndrome/check bit outputs. If the corrected check bits
are needed, the EDC must be switched to the Generate Mode.
DATA INPUT/OUTPUT LATCH
DATA OUTPUT LATCH AND OUTPUT BUFFERS
The Latch Enable Input, LEIN, controls the loading of 32 bits
of data to the Data In Latch. The data from the DATA lines can
be loaded in the Diagnostic Latch under control of the
Diagnostic Latch Enable, LEDIAG, giving check bit information
in one byte and control information in another byte. The
Diagnostic Latch is used in the Internal Control Mode or in one
of the diagnostic modes. The Data Output Latch has buffers
that place data on the DATA lines. These buffers are split into
four 8-bit buffers, each having their own output enable controls. This feature facilitates byte read and byte modify
operations.
CHECK BIT GENERATION LOGIC
This generates the appropriate check bits for the 32 bits of
data in the Data Input Latch. The modified Hamming Code is
the basis for generating the proper check bits.
SYNDROME GENERATION LOGIC
In both the Detect and Correct modes, this logic does a
comparison on the check bits read from memory against the
newly generated set of check bits produced for the data read
in from memory. Matching sets of check bits mean no error
was detected. If there is a mismatch, one or more of the data
or check bits is in error. Syndrome bits are produced by an
exclusive-OR of the two sets of check bits. Identical sets of
check bits mean the syndrome bits will be all zeros. If an error
results, the syndrome bits can be decoded to determine the
number of errors and the specific bit-in-error.
The Data Output Latch is used for storing the result of an
error correction operation. The latch is loaded from the
correction logic under control of the Data Output Latch Enable, LEOUT. The Data Output Latch may also be directly
loaded from the Data Input Latch in the PASSTHRU mode.
The Data Output Latch buffer is split into 4 individual buffers
which can be enabled by OE0–3 separately for reading onto
the bidirectional data lines.
DIAGNOSTIC LATCH
The diagnostic latch is loadable under control of the
Diagnostic Latch Enable, LEDIAG, from the bidirectional data
lines. Check bit information is contained in one byte while the
other byte contains the control information. The Diagnostic
Latch is used for driving the device when in the Internal Control
Mode, or for supplying check bits when in one of the diagnostic
modes.
CONTROL LOGIC
Specifies in which mode the device will be operating in.
Normal operation is when the control logic is driven by external
control inputs. In the Internal Control Mode, the control signals
are read from the Diagnostic Latch. Since LEOUT and
GENERATE are controlled by the same pin, the latching action
(LEOUT from high to low) of the Data Output Latch causes the
EDC to go into the Generate Mode.
11.6
6
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED PRODUCT DESCRIPTION
The IDT49C460 EDC units contain the logic necessary to
generate check bits on 32 bits of data input according to a
modified Hamming Code. The EDC can compare internally
generated check bits against those read with the 32-bit data
to allow correction of any single bit data error and detection of
all double (and some triple) bit errors. The IDT49C460s can
be used for 32-bit data words (7 check bits) and 64-bit (8 check
bits) data words.
Correct
Diag
Diag
Mode0 Mode1
X
0
0
Non-diagnostic Mode. Normal
EDC function in this mode.
X
0
1
Diagnostic Generate. The con
tents of the Diagnostic Latch are
substituted for the
normally
generated check bits when in the
Generate Mode.
The EDC
functions normally in the Detect or
Correct modes.
0/1
1
0
Diagnostic Detect/Correct.
In
either mode, the contents of the
Diagnostic Latch are substituted
for the check bits normally read
from the Check Bit Input Latch.
The EDC functions normally in the
Generate Mode.
1
1
1
Initialize. The Data Input Latch
outputs are forced to zeros and
latched upon removal of Initialize
Mode.
0
1
1
PASSTHRU.
WORD SIZE SELECTION
The two code identification pins, CODE ID1, 0, are used to
determine the data word size that is 32 or 64 bits. They also
select the Internal Control Mode. Table 4 defines all possible
slice identification codes.
CHECK AND SYNDROME BITS
The IDT49C460s provide either check bits or syndrome
bits on the three-state output pins, SC0–7. Check bits are
generated from a combination of the Data Input bits, while
syndrome bits are an exclusive-OR of the check bits generated from read data with the read check bits stored with the
data. Syndrome bits can be decoded to determine the single
bit in error or that a double (some triple) error was detected.
The check bits are labeled:
C0, C1, C2, C3, C4, C5, C6
C0, C1, C2, C3, C4, C5, C6, C7
Diagnostic Mode Selected
2584 tbl 02
Table 2. Diagnostic Mode Control
for the 32-bit configuration
for the 64-bit configuration
Syndrome bits are similarly labeled S0 through S7.
Operating
Mode
SC0–7
(OESC = LOW)
ERROR
MULT ERROR
DM0
DM1
Generate
Correct
DATAOUT Latch
Generate
0
1
0
0
0
X
LEOUT = LOW (1)
Check Bits Generated from
DATAIN Latch
High
Detect
0
0
0
1
1
0
DATAIN Latch
Syndrome Bits DATAIN/
Check Bit Latch
Error Dep (2)
Correct
0
0
0
1
1
1
DATAIN Latch w/
Single Bit Correction
Syndrome Bits DATAIN/
Check Bit Latch
Error Dep
PASSTHRU
1
1
1
0
DATAIN Latch
Check Bit Latch
High
Diagnostic
Generate
0
1
0
X
—
Check Bits from Diagnostic Latch
High
Diagnostic Detect
1
0
1
0
DATAIN Latch
Syndrome Bits DATAIN/
Diagnostic Latch
Error Dep
Diagnostic Correct
1
0
1
1
DATAIN Latch w/
Single Bit Correction
Syndrome Bits DATAIN/
Diagnostic Latch
Error Dep
Initialization
1
1
1
1
DATAIN Latch
Set to 0000(3)
—
—
Internal
CODE ID1,0 = 01 (Control Signals CODE ID1,0, DIAG MODE1,0 and CORRECT are taken from Diagnostic Latch.)
2584 tbl 03
NOTES:
1. In Generate Mode, data is read into the EDC unit and the check bits are generated. The same data is written to memory along with the check bits. Since
the DATAOUT Latch is not used in the Generate Mode, LEOUT (being LOW since it is tied to Generate) does not affect the writing of check bits.
2. Error Dep (Error Dependent): ERROR will be low for single or multiple errors, with MULT ERROR low for double or multiple errors. Both signals are high
for no errors.
3. LEIN is LOW.
Table 3. IDT49C460 Operating Modes
11.6
7
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
check bits stored in the diagnostic latch rather than with the
check bit latch contents.
Correct Mode is similar to the Detect Mode except that
single bit errors will be complemented (corrected) and made
available as input to the Data Out Latches. Again, the
Diagnostic Correct Mode will correct single bit errors as
determined by syndrome bits generated from the data input
and contents of the diagnostic latches.
The Initialize Mode provides check bits for all zero bit data.
Data Input Latches are set, latched to a logic zero and made
available as input to the Data Out Latches.
The Internal Mode disables the external control pins DIAG
MODE0,1 and CORRECT to be defined by the Diagnostic
Latch. Even CODE ID1,0, although externally set to the 01
code, can be redefined from the Diagnostic Latch data.
OPERATING MODE SELECTION
Tables 2 and 3 describe the nine operating modes of the
IDT49C460s. The Diagnostic Mode pins — DIAG MODE0,1
— define four basic areas of operation. GENERATE and
CORRECT further divide operation into 8 functions, with
CODE ID1,0 defining the ninth mode as the Internal Mode.
Generate Mode is used to display the check bits on the
outputs SC0–7. The Diagnostic Generate Mode displays
check bits as stored in the Diagnostic Latch.
Detect Mode provides an indication of errors or multiple
errors on the outputs ERROR and MULT ERROR. Single bit
errors are not corrected in this mode. The syndrome bits are
provided on the outputs SC0–7. For the Diagnostic Detect
Mode, the syndrome bits are generated by comparing the
internally generated check bits from the Data In Latch with
Code ID1
Code ID0
Slice Selected
0
0
1
1
0
1
0
1
32-Bit
Internal Control Mode
64-Bit, Lower 32–Bit (0–31)
64-Bit, Upper 32-Bit (32–63)
OESC
CHECK–BIT INPUTS
1/8
IDT74FCT240
DATA INPUT
DATA32–63 DATA0–31
32
8
2584 tbl 04
DATA
Table 4. Slice Identification
DATA0–31 HIGH
C6
C5
C4
C3
C2
C1
SC0–7
DATA0–31
DATA
IDT49C460
SC7
SC6
SC5
NC
SC4
S5/C5
S6/C6
SC3
CODE ID1,0
SC2
S3/C 3
S4/C4
SC1
0,0
CB0–7
MULT
ERROR ERROR
SC0
2584 drw 05
S0/C0
OESC
IDT49C460
(UPPER 32 BITS)
S1/C1
S2/C2
1,0
CODE ID1,0
8
CB6 CB5 CB4 CB3 CB2 CB1 CB0
CB7
OESC
IDT49C460
(LOWER 32 BITS)
32
C0
CB0–7
ERROR
CODE ID1,0
SC0–7
1,1
8
MULT
ERROR
SYNDROME/
CHECK BITS
Figure 1. 32-Bit Configuration
2584 drw 06
Figure 2. 64-Bit Configuration
DATA
BYTE3
31
BYTE2
24 23
CHECK BITS
BYTE1
16 15
BYTE0
87
C0
C1
C2
C3
C4
C5
0
2584 drw 07
Figure 3. 32-Bit Data Format
DATA
BYTE7
63
BYTE6
56 55
BYTE5
48 47
BYTE4
40 39
CHECK BITS
BYTE3
32 31
C6
BYTE2
24 23
BYTE1
16 15
BYTE0
87
C0
C1
C2
C3
C4
C5
C6
C7
0
2584 drw 08
Figure 4. 64-Bit Data Format
11.6
8
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
32-BIT DATA WORD CONFIGURATION
A single IDT49C460 EDC unit, connected as shown in
Figure 1, provides all the logic needed for single bit error
correction and double bit error detection of a 32-bit data field.
The identification code indicates 7 check bits are required.
The CB7 pin should be HIGH.
Figure 3 indicates the 39-bit data format for two bytes of
data and 7 check bits. Table 3 describes the operating mode
available.
Table 6 indicates the data bits participating in the check bit
generation. For example, check bit C0 is the exclusive-OR
function of the 16 data input bits marked with an X. Check bits
are generated and output in the Generate and Initialization
Mode. Check bits from the respective latch are passed,
unchanged, in the PASSTHRU or Diagnostic Generate Mode.
Syndrome bits are generated by an exclusive-OR or the
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13–31
generated check bits with the read check bits. For example,
Sn is the XOR of check bits Cn from those read with those
generated. Table 7 indicates the decoding of the seven
syndrome bits to identify the bit-in-error for a single bit error,
or whether a double or triple bit error was detected. The all
zero case indicates no errors detected.
In the Correct Mode, the syndrome bits are used to
complement (correct) single bit errors in the data bits. For
double or multiple error detection, the data available as input
to the Data Out Latch is not defined.
Table 5 defines the bit definition for the Diagnostic Latch.
As defined in Table 3, several modes will use the diagnostic
check bits to determine syndrome bits or to pass as check bits
to the SC0–7 outputs. The Internal Mode substitutes the
indicated bit position for the external control signals.
CB0 DIAGNOSTIC
CB1 DIAGNOSTIC
CB2 DIAGNOSTIC
CB3 DIAGNOSTIC
CB4 DIAGNOSTIC
CB5 DIAGNOSTIC
CB6 DIAGNOSTIC
CB7 DIAGNOSTIC
CODE ID0
CODE ID1
DIAG MODE0
DIAG MODE1
CORRECT
DON'T CARE
2584 drw 05
Table 5. 32-Bit Diagnostic Latch Coding Format
Participating Data Bits
Generated
Check Bits
Parity
0
C0
Even (XOR)
X
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
C5
Even (XOR)
C6
Even (XOR)
1
X
2
3
X
X
4
6
7
8
9
X
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
11
13
15
X
X
X
14
X
X
X
X
12
X
X
X
X
X
10
X
X
X
X
X
X
X
X
X
X
2584 tbl 06
Participating Data Bits
Generated
Check Bits
Parity
C0
Even (XOR)
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
C5
Even (XOR)
X
X
X
X
X
C6
Even (XOR)
X
X
X
X
X
16
17
18
19
X
X
X
X
X
20
X
X
X
22
23
24
25
X
X
X
X
X
21
X
X
X
X
X
X
X
X
X
X
26
28
29
X
27
X
X
X
X
X
X
X
X
X
X
30
31
X
X
X
X
X
X
X
X
X
2584 tbl 07
Table 6. 32–Bit Modified Hamming Code–Check Bit Encode Chart
11.6
9
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
Syndrome
Bits
Hex S3
S2
S1
S0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Hex 0
S6 0
1
0
2
0
3
0
4
1
5
1
6
1
7
1
S5
0
0
1
1
0
0
1
1
S4
0
1
0
1
0
1
0
1
0
0
0
0
0
*
T
C6
T
T
30
1
0
0
0
1
C0
C4 C5
T
T
14
T
M
M
T
2
0
0
1
0
C1
T
T
M
T
2
24
T
3
0
0
1
1
T
18
8
T
M
T
T
M
4
0
1
0
0
C2
T
T
15
T
3
25
T
5
0
1
0
1
T
19
9
T
M
T
T
31
6
0
1
1
0
T
20
10
T
M
T
T
M
7
0
1
1
1
M
T
T
M
T
4
26
T
8
1
0
0
0
C3
T
T
M
T
5
27
T
9
1
0
0
1
T
21
11
T
M
T
T
M
A
1
0
1
0
T
22
12
T
1
T
T
M
B
1
0
1
1
17
T
T
M
T
6
28
T
C
1
1
0
0
T
23
13
T
M
T
T
M
D
1
1
0
1
M
T
T
M
T
7
29
T
E
1
1
1
0
16
T
T
M
T
M
M
T
F
1
1
1
1
T
M
M
T
0
T
T
M
NOTES:
1. * = No errors detected
2. Number = The number of the single bit-in-error
3. T = Two errors detected
4. M = Three or more errors detected
Table 3 describes the operating modes available for the 64/
72 configuration.
Table 11 indicates the data bits participating in the check bit
generation. For example, check bit C0 is the exclusive-OR
function of the 32 data input bits marked with an X. Check bits
are generated and output in the Generate and Initialization
modes. Check bits are passed as stored in the PASSTHRU or
Diagnostic Generate modes.
Syndrome bits are generated by an exclusive-OR of the
generated check bits with the read check bits. For example,
Sn is the XOR of check bits Cn from those read with those
generated. Table 9 indicates the decoding of the 8 syndrome
bits to determine the bit in error for a single bit error or whether
a double or triple bit error was detected. The all zero case
indicates no errors detected.
In the Correct Mode, the syndrome bits are used to
complement (correct) single bit errors in the data bits. For
double or multiple error detection, the data available as input
to the Data Out Latch is not defined.
Tables 8A and 8B define the bit definition for the Diagnostic
Latch. As defined in Table 3, several modes will use the
Diagnostic Check Bits to determine syndrome bits or to pass
as check bits to the SC0–7 outputs. The Internal Mode substitutes the indicated bit position for the external control
signals.
Performance data is provided in Table 10, relating a single
IDT49C460 EDC with the two cascaded units of Figure 2. As
indicated, a summation of propagation delays is required from
the cascading arrangement of EDC units.
2584 tbl 08
Bit
Table 7. Syndrome Decode to Bit-in-Error (32-Bit)
64-BIT DATA WORD CONFIGURATION
Two IDT49C460 EDC units, connected as shown in Figure
2, provide all the logic needed for single bit error detection and
double bit error detection of a 64-bit data field. Table 4 gives
the CODE ID1,0 values needed for distinguishing the upper 32
bits from the lower 32 bits. Valid syndrome, check bits and the
ERROR and MULT ERROR signals come from the IC with the
CODE ID1,0 = 11. Control signals not indicated are connected
to both units in parallel. The EDC with the CODE ID1,0 = 10
has the OESC grounded. The OESC selects the syndrome bits
from the EDC with CODE ID1,0 = 11 and also controls the
check bit buffers from memory.
Data In bits 0 through 31 are connected to the same
numbered inputs of the EDC unit with CODE ID1,0 = 10, while
Data In bits 32 through 63 are connected to Data Inputs 0 to
31, respectively, for the EDC unit with CODE ID1,0 = 11.
Figure 4 indicates the 72-bit data format of 8 bytes of data
and 8 check bits. Check bits are input to the EDC unit with
CODE ID1,0 = 10 through a three-state buffer unit such as the
IDT74FCT244. Correction of single bit errors of the 64-bit
configuration requires a feedback of syndrome bits from the
upper EDC unit to the lower EDC unit. The MUX shown on the
functional block diagram is used to select the CB0–7 pins as
the syndrome bits rather than internally generated syndrome
bits.
11.6
Internal Function
0
CB0 DIAGNOSTIC
1
CB1 DIAGNOSTIC
2
CB2 DIAGNOSTIC
3
CB3 DIAGNOSTIC
4
CB4 DIAGNOSTIC
5
CB5 DIAGNOSTIC
6
CB6 DIAGNOSTIC
7
CB7 DIAGNOSTIC
8
CODE ID0 LOWER 32-BIT
9
CODE ID1 LOWER 32-BIT
10
DIAG MODE0 LOWER 32-BIT
11
DIAG MODE1 LOWER 32-BIT
12
CORRECT LOWER 32-BIT
13–31
DON'T CARE
32–39
DON'T CARE
40
CODE ID0 UPPER 32-BIT
41
CODE ID1 UPPER 32-BIT
42
DIAG MODE0 UPPER 32-BIT
43
DIAG MODE1 UPPER 32-BIT
44
CORRECT UPPER 32-BIT
45–63
DON'T CARE
2584 tbl 09
Table 8A. 64-Bit Diagnostic Latch–Coding Format
(Diagnostic and Correct Mode)
10
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Bit
0–7
8
9
10
11
12
13–31
32
33
34
35
36
37
38
39
40
41
42
43
44
45–63
Internal Function
DON'T CARE
CODE ID0 LOWER 32-BIT
CODE ID1 LOWER 32-BIT
DIAG MODE0 LOWER 32-BIT
DIAG MODE1 LOWER 32-BIT
CORRECT LOWER 32-BIT
DON'T CARE
CB0 DIAGNOSTIC
CB1 DIAGNOSTIC
CB2 DIAGNOSTIC
CB3 DIAGNOSTIC
CB4 DIAGNOSTIC
CB5 DIAGNOSTIC
CB6 DIAGNOSTIC
CB7 DIAGNOSTIC
CODE ID0 UPPER 32-BIT
CODE ID1 UPPER 32-BIT
DIAG MODE0 UPPER 32-BIT
DIAG MODE1 UPPER 32-BIT
CORRECT UPPER 32-BIT
DON'T CARE
2584 tbl 10
Table 8B. 64-Bit Diagnostic Latch–Coding Format (Diagnostic and Correct Mode)
Syndrome
Bits
Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
S7
S6
S5
S4
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Hex
S3
S2
S1
S0
0
0
0
0
0
*
C4
C5
T
C6
T
T
62
C7
T
T
46
T
M
M
T
1
0
0
0
1
C0
T
T
14
T
M
M
T
T
M
M
T
M
T
T
30
2
0
0
1
0
C1
T
T
M
T
34
56
T
T
50
40
T
M
T
T
M
3
0
0
1
1
T
18
8
T
M
T
T
M
M
T
T
M
T
2
24
T
4
0
1
0
0
C2
T
T
15
T
35
57
T
T
51
41
T
M
T
T
31
5
0
1
0
1
T
19
9
T
M
T
T
63
M
T
T
47
T
3
25
T
6
0
1
1
0
T
20
10
T
M
T
T
M
M
T
T
M
T
4
26
T
7
0
1
1
1
M
T
T
M
T
36
58
T
T
52
42
T
M
T
T
M
8
1
0
0
0
C3
T
T
M
T
37
59
T
T
53
43
T
M
T
T
M
9
1
0
0
1
T
21
11
T
M
T
T
M
M
T
T
M
T
5
27
T
A
1
0
1
0
T
22
12
T
33
T
T
M
49
T
T
M
T
6
28
T
B
1
0
1
1
17
T
T
M
T
38
60
T
T
54
44
T
1
T
T
M
C
1
1
0
0
T
23
13
T
M
T
T
M
M
T
T
M
T
7
29
T
D
1
1
0
1
M
T
T
M
T
39
61
T
T
55
45
T
M
T
T
M
E
1
1
1
0
16
T
T
M
T
M
M
T
T
M
M
T
0
T
T
M
F
1
1
1
1
T
M
M
T
32
T
T
M
48
T
T
M
T
M
M
NOTES:
* = No errors detected
Number = The number of the single bit-in-error
T
2584 tbl 11
T = Two errors detected
M = Three or more errors detected
Table 9. Syndrome Decode to Bit–In–Error (64–Bit Configuration)
11.6
11
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
64–Bit
Propagation Delay
From
Component Delay for IDT49C460 AC Specifications
To
DATA
Check Bits Out
(DATA TO SC) + (CB TO SC, CODE ID 11)
DATA
Corrected DATAOUT
(DATA TO SC) + (CB TO SC, CODE ID 11) + (CB TO DATA, CODE ID 10)
DATA
Syndromes Out
(DATA TO SC) + (CB TO SC, CODE ID 11)
ERROR for 64 Bits
MULT ERROR for 64 Bits
(DATA TO SC) + (CB TO ERROR, CODE ID 11)
DATA
DATA
(DATA TO SC) + (CB TO MULT ERROR, CODE ID 11)
2584 tbl 12
Table 10. Key Calculations for the 64–Bit Configuration
11.6
12
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Participating Data Bits
Generated
Check Bits
Parity
C0
Even (XOR)
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
C5
Even (XOR)
C6
Even (XOR)
X
C7
Even (XOR)
X
0
1
2
3
X
X
X
X
X
4
5
X
X
6
7
X
X
X
X
8
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
10
11
X
X
X
13
15
X
X
X
14
X
X
X
X
12
X
X
X
X
X
X
X
X
X
X
X
2584 tbl 13
Participating Data Bits
Generated
Check Bits
Parity
C0
Even (XOR)
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
C5
Even (XOR)
X
X
X
X
X
C6
Even (XOR)
X
X
X
X
X
C7
Even (XOR)
X
X
X
X
X
16
17
18
19
X
X
X
X
X
20
X
X
X
22
23
X
X
X
X
X
21
X
24
25
X
X
X
X
X
X
X
X
X
X
26
27
X
X
28
29
X
30
31
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2584 tbl 14
Participating Data Bits
Generated
Check Bits
Parity
32
C0
Even (XOR)
X
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
C5
Even (XOR)
C6
Even (XOR)
C7
Even (XOR)
33
34
X
X
36
38
39
X
X
X
X
X
X
X
X
X
X
X
X
35
X
X
X
X
37
40
X
X
X
X
X
X
X
X
X
X
41
X
42
43
44
45
X
X
X
X
X
X
X
X
X
X
X
46
47
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2584 tbl 15
Participating Data Bits
Generated
Check Bits
Parity
48
49
C0
Even (XOR)
X
C1
Even (XOR)
X
C2
Odd (XNOR)
X
C3
Odd (XNOR)
X
C4
Even (XOR)
C5
Even (XOR)
X
X
C6
Even (XOR)
X
X
C7
Even (XOR)
X
50
X
X
52
54
55
X
X
X
X
X
X
X
X
53
X
X
X
X
X
51
X
X
56
X
X
X
X
X
X
X
X
X
X
57
X
58
59
60
61
X
X
X
X
X
X
X
X
X
62
63
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOTE:
1. The check bit is generated as either an XOR or XNOR of the 32 data bits noted by an “X” in the table.
2584 tbl 16
Table 11. 64–Bit Modified Hamming Code–Check Bit Encoding
11.6
13
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SC OUTPUTS
The tables below indicate how the SC0–7 outputs are
generated in each control mode of various CODE IDs (Internal
Control Mode not applicable).
CODE ID1,0
CODE ID1,0
Correct/
Generate
00
10
11
Detect
00
10
11
SC0 ←
PH0
PH1
PH2 ⊕ CB0
SC0 ←
PH0 ⊕ C0
PH1 ⊕ C0
PH2 ⊕ CB0
SC1 ←
PA
PA
PA ⊕ CB1
SC1 ←
PA ⊕ C1
PA ⊕ C1
PA ⊕ CB1
SC2 ←
PB
PB
PB ⊕ CB2
SC2 ←
PB ⊕ C2
PB ⊕ C2
PB ⊕ CB2
SC3 ←
PC
PC
PC ⊕ CB3
SC3 ←
PC ⊕ C3
PC ⊕ C3
PC ⊕ CB3
SC4 ←
PD
PD
PD ⊕ CB4
SC4 ←
PD ⊕ C4
PD ⊕ C4
PD ⊕ CB4
SC5 ←
PE
PE
PE ⊕ CB5
SC5 ←
PE ⊕ C5
PE ⊕ C5
PE ⊕ CB5
SC6 ←
PF
PF
PF ⊕ CB6
SC6 ←
PF ⊕ C6
PF ⊕ C6
PF ⊕ CB6
SC7 ←
—
PF
PG ⊕ CB7
SC7 ←
—
PF ⊕ C7
PG ⊕ CB7
Final
Check Bits
Partial
Check Bits
Final
Check Bits
Final
Syndrome
Partial
Syndrome
Final
Syndrome
2584 tbl 17
CODE ID1,0
Diagnostic
Generate
2584 tbl 19
Diagnostic
Correct/
Detect
00
10
11
CODE ID1,0
00
10
11
SC0 ←
DL0
DL0
DL32
SC1 ←
SC0 ←
PH0 ⊕ DL0
PH1 ⊕ DL0
PH2 ⊕ CB0
DL1
DL1
DL33
SC2 ←
SC1 ←
PA ⊕ DL1
PA ⊕ DL1
PA ⊕ CB1
DL2
DL2
DL34
SC3 ←
SC2 ←
PB ⊕ DL2
PB ⊕ DL2
PB ⊕ CB2
DL3
DL3
DL35
SC4 ←
SC3 ←
PC ⊕ DL3
PC ⊕ DL3
PC ⊕ CB3
DL4
DL4
DL36
SC5 ←
SC4 ←
PD ⊕ DL4
PD ⊕ DL4
PD ⊕ CB4
DL5
DL5
DL37
SC6 ←
SC5 ←
PE ⊕ DL5
PE ⊕ DL5
PE ⊕ CB5
DL6
DL6
DL38
SC7 ←
SC6 ←
PF ⊕ DL6
PF ⊕ DL6
PF ⊕ CB6
—
DL7
DL39
SC7 ←
—
Final
Check Bits
Partial
Check Bits
Final
Check Bits
PF ⊕ DL7
PG ⊕ CB7
Final
Syndrome
Partial
Syndrome
Final
Syndrome
2584 tbl 18
2584 tbl 20
CODE ID1,0
PASSTHRU
00
10
11
SC0 ←
C0
C0
CB0
SC1 ←
C1
C1
CB1
SC2 ←
C2
C2
CB2
SC3 ←
C3
C3
CB3
SC4 ←
C4
C4
CB4
SC5 ←
C5
C5
CB5
SC6 ←
C6
C6
CB6
SC7 ←
—
C7
CB7
2584 tbl 21
Table 12. SC0-7 Outputs For Different Control Modes
11.6
14
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA CORRECTION
FUNCTIONAL EQUATIONS
The tables below indicate which data output bits are
corrected depending upon the syndromes and the CODE
ID1,0 position. The syndromes that determine data correction
are, in some cases, syndromes input externally via the CB
inputs and, in some cases, syndromes input externally by that
EDC (Si are the internal syndromes and are the same as the
value of the SCi output of that EDC if enabled).
The equations below describe the IDT49C460 output values as defined by the value of the inputs and internal states.
DEFINITIONS
PA = D0 ⊕ D1 ⊕ D2 ⊕ D4 ⊕ D6 ⊕ D8 ⊕ D10 ⊕ D12 ⊕ D16 ⊕ D17
⊕ D18 ⊕ D20 ⊕ D22 ⊕ D24 ⊕ D26 ⊕ D28
PB = D0 ⊕ D3 ⊕ D4 ⊕ D7 ⊕ D9 ⊕ D10 ⊕ D13 ⊕ D15 ⊕ D16 ⊕ D19
⊕ D20 ⊕ D23 ⊕ D25 ⊕ D26 ⊕ D29 ⊕ D31
PC = D0 ⊕ D1 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D16 ⊕ D17
⊕ D21 ⊕ D22 ⊕ D23 ⊕ D27 ⊕ D28 ⊕ D29
PD = D2 ⊕ D3 ⊕ D4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D14 ⊕ D15 ⊕ D18 ⊕ D19
⊕ D20 ⊕ D21 ⊕ D22 ⊕ D23 ⊕ D30 ⊕ D31
PE = D8 ⊕ D9 ⊕ D10 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D14 ⊕ D15 ⊕ D24
⊕ D25 ⊕ D26 ⊕ D27 ⊕ D28 ⊕ D29 ⊕ D30 ⊕ D31
PF = D0 ⊕ D1 ⊕ D2 ⊕ D3 ⊕ D4 ⊕ D5 ⊕ D6 ⊕ D7 ⊕ D24 ⊕ D25
⊕ D26 ⊕ D27 ⊕ D28 ⊕ D29 ⊕ D30 ⊕ D31
PG = D8 ⊕ D9 ⊕ D10 ⊕ D11 ⊕ D12 ⊕ D13 ⊕ D14 ⊕ D15 ⊕ D16
⊕ D17 ⊕ D18 ⊕ D19 ⊕ D20 ⊕ D21 ⊕ D22 ⊕ D23
PH0 = D0 ⊕ D4 ⊕ D6 ⊕ D7 ⊕ D8 ⊕ D9 ⊕ D11 ⊕ D14 ⊕ D17 ⊕ D18
⊕ D19 ⊕ D21 ⊕ D26 ⊕ D28 ⊕ D29 ⊕ D31
PH1 = D1 ⊕ D2 ⊕ D3 ⊕ D5 ⊕ D8 ⊕ D9 ⊕ D11 ⊕ D14 ⊕ D17 ⊕ D18
⊕ D19 ⊕ D21 ⊕ D24 ⊕ D25 ⊕ D27 ⊕ D30
PH2 = D0 ⊕ D4 ⊕ D6 ⊕ D7 ⊕ D10 ⊕ D12 ⊕ D13 ⊕ D15 ⊕ D16 ⊕
D20 ⊕ D22 ⊕ D23 ⊕ D26 ⊕ D28 ⊕ D29 ⊕ D31
11.6
15
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
Rating
Terminal Voltage
with Respect to
GND
CAPACITANCE (TA = + 25°C, f = 1.0MHz)
Com'l.
Mil.
Unit
–0.5 to
VCC + 0.5V
–0.5 to
VCC + 0.5V
V
VCC
Power Supply
Voltage
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
IOUT
DC Output Current
30
30
mA
Symbol
Parameter
(1)
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Typ.
Unit
VIN = 0V
5
pF
VOUT = 0V
7
NOTE:
1. This parameter is sampled and not 100% tested.
pF
2584 tbl 25
NOTE:
2584 tbl 24
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, V CC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Test Conditions (1)
Min.
Typ. (2)
Max.
Unit
Input HIGH Level
Guaranteed Logic HIGH Level (4)
2.0
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW
Level (4)
—
—
0.8
V
II H
Input HIGH Current
VCC = Max., VIN = VCC
VIH
Parameter
II L
Input LOW Current
VCC
VOH
Output HIGH Voltage
VCC = Min.
VOL
IOZ
Output LOW Voltage
Off State (High Impedance)
VCC = Min.
VCC = Max.
Output Current
IOS
Output Short Circuit Current
—
0.1
10.0
µA
—
–0.1
–10.0
µA
IOH = 300µA
VCC
—
—
V
IOH = –12mA Mil.
2.4
4.3
—
IOH = –15mA Com'l.
2.4
4.3
—
IOL = 300µA
—
—
GND
IOL = 12mA Mil.
—
0.3
0.5
= Max., VIN = GND
VCC = Max., VOUT =
0V (3)
IOL = 16mA Com'l.
—
0.3
0.5
VO = 0V
—
–0.1
–20.0
VO = VCC (Max.)
—
0.1
20.0
–30.0
—
—
NOTES:
1. For conditions shown as Max. or Min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
11.6
V
µA
mA
2584 tbl 26
16
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont’d.)
Commercial: TA = 0°C to +70°C, V CC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
ICCQ
Parameter
Test Conditions
Quiescent Power Supply Current
VCC = Max.; All Inputs
(CMOS Inputs)
VHC ≤ VIN, VIN ≤ VLC
Min.
Typ.
Max.
Unit
—
3.0
10
mA
—
0.3
0.75
fOP = 0; Outputs Disabled
ICCT
Quiescent Input Power Supply
Current (per Input @ TTL High)
ICCD
Dynamic Power Supply Current
VCC = Max., VIN = 3.4V, fOP = 0
(5)
mA/
Input
VCC = Max.
MIL.
—
6
10
mA/
VHC ≤ VIN, VIN ≤ VLC
COM'L.
—
6
7
MHz
VCC = Max., fOP = 10MHz
MIL.
—
60
110
mA
Outputs Open, OE = L
COM'L.
—
60
80
VCC = Max., fOP = 10MHz
MIL.
—
70
125
Outputs Open, OE = L
COM'L.
—
70
95
Outputs Open, OE = L
ICC
Total Power Supply Current (6)
50 % Duty cycle
VHC ≤ VIN, VIN ≤ VLC
50 % Duty cycle
VIH = 3.4V, VIL = 0.4V
NOTES:
2584 tbl 27
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCQ, then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
ICC = ICCQ + ICCT (NT x DH) + ICCD (fOP)
DH = Data duty cycle TTL high period (VIN = 3.4V).
NT = Number of dynamic inputs driven at TTL levels.
fOP = Operating frequency in Megahertz.
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into
account when applying high-speed CMOS products to the
automatic test environment. Large output currents are being
switched in very short periods and proper testing demands
that test set-ups have minimized inductance and guaranteed
zero voltage grounds. The techniques listed below will assist
the user in obtaining accurate testing results:
1) All input pins should be connected to a voltage potential
during testing. If left floating, the device may oscillate,
causing improper device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical.
Each physical set-up has different electrical
characteristics and it is recommended that various
decoupling capacitor sizes be experimented with.
Capacitors should be positioned using the minimum lead
lengths. They should also be distributed to decouple
power supply lines and be placed as close as possible to
the DUT power pins.
3) Device grounding is extremely critical for proper device
testing. The use of multi-layer performance boards with
radial decoupling between power and ground planes is
necessary. The ground plane must be sustained from the
performance board to the DUT interface board and wiring
unused interconnect pins to the ground plane is
recommended. Heavy gauge stranded wire should be
used for power wiring, with twisted pairs being
recommended for minimized inductance.
4) To guarantee data sheet compliance, the input thresholds
should be tested per input pin in a static environment. To
allow for testing and hardware-induced noise, IDT
recommends using VIL ≤ 0V and VIH ≥ 3V for AC tests.
11.6
17
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460E AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0°C to +70°C, VCC = 5.0V ± 5%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
SC 0–7
DATA 0–31
ERROR
MULT ERROR
Unit
11
14(2)
10
11
ns
CB0–7 (CODE ID1,0 = 00, 11)
9
12
7
9
ns
CB0–7 (CODE ID1,0 = 10)
9
10
—
—
ns
DATA0–31 (3)
u
d
LEOUT / GENERATE
9
—
CORRECT
Not Internal Control Mode
—
11
DIAG MODE
Not Internal Control Mode
11
18
13(6)
17
16
19
11(6)
17
11(6)
16
11
17(2)
LEDIAG
From latched to Transparent
LEDIAG (Internal Control Mode) From
latched to Transparent
DATA0–31 (Internal Control Mode)
Via Diagnostic Latch
u
u
u
7
—
d
u
8
8
8
14
ns
12
15
ns
13
16
ns
11
13
ns
11
13
ns
9
11
ns
2584 tbl 70
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID
10)(4, 6)
CORRECT(4, 6)
DIAG
MODE(4, 6)
CODE ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
NOTE: (15) above applies to correction path.
OUTPUT ENABLE/DISABLE TIMES(5)
From Input
OE Byte0–3
OESC
Enable
MINIMUM PULSE WIDTHS
LEIN, LEOUT/ GENERATE, LEDIAG ud
d
d
Unit
LEIN
3
3
ns
LEIN
2
3
ns
LEOUT/GENERATE
5(15)
0
ns
11
0
ns
6
0
ns
6
0
ns
13
0
ns
8
0
ns
LEOUT/GENERATE
14
0
ns
LEDIAG
3
3
IM
(4)
Hold Time
Min.
LEOUT/GENERATE
LEOUT/GENERATE
EL
CB0–7
Set-up Time
Min.
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
PR
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
To Input
(Latching Data)
ns
ns
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
ns
—
AR
LEIN
From latched to Transparent
7
IN
CODE ID1,0
Internal
Control
Mode
d
u
—
13
Y
From Input
Disable
u
u
ns
2584 tbl 71
Enable
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
7
0
6
ns
SC0–7
0
7
0
6
ns
2584 tbl 72
Min.
(Positive–going pulse)
5
ns
NOTES:
2584 tbl 73
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.
11.6
18
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460D AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0°C to +70°C, VCC = 5.0V ± 5%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
From Input
MULT ERROR
DATA0–31
14
18(2)
12
15
ns
CB0–7 (CODE ID1,0 = 00, 11)
11
16
10
12
ns
CB0–7 (CODE ID1,0 = 10)
12
12
—
—
ns
u
d
LEOUT/GENERATE
d
u
d
u
—
9
—
CORRECT
Not Internal Control Mode
—
12
—
—
ns
DIAG MODE
Not Internal Control Mode
12
20
10
15
ns
14(6)
18
13
16
ns
17
21
14
17
ns
12(6)
18
12
14
ns
12(6)
17
12
14
ns
12
19(2)
10
12
ns
LEIN
From latched to Transparent
LEDIAG
From latched to Transparent
LEDIAG (Internal Control Mode) From
latched to Transparent
DATA0–31 (Internal Control Mode)
Via Diagnostic Latch
u
u
u
7
Unit
14
CODE ID1,0
Internal
Control
Mode
ERROR
SC0–7
DATA0–31 (3)
7
8
ns
8
ns
2584 tbl 28
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
CB0–7
(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID 10)(4, 6)
CORRECT(4, 6)
DIAG MODE(4, 6)
CODE ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
LEIN
3
3
ns
LEIN
2
3
ns
LEOUT/GENERATE
5(15)
0
ns
11
0
ns
LEOUT/GENERATE
6
0
ns
6
0
ns
LEOUT/GENERATE
13
0
ns
8
0
ns
LEOUT/GENERATE
14
0
ns
LEDIAG
3
3
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
ns
NOTE: (15) above applies to correction path.
2584 tbl 29
OUTPUT ENABLE/DISABLE TIMES(5)
Enable
From Input
Enable
d
d
OE Byte0–3
OESC
Disable
u
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
8
0
10
ns
SC0–7
0
8
0
10
ns
2584 tbl 30
(6)
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG ud (Positive–going pulse)
Min.
5
ns
NOTES:
2584 tbl 31
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.
11.6
19
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460D AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: –55°C to +125°C, V CC = 5.0V ± 10%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
From Input
MULT ERROR
16
12
—
18
14
—
DATA0–31
17
13
13
—
15
22(2)
CORRECT
Not Internal Control Mode
—
13
—
—
ns
DIAG MODE
Not Internal Control Mode
14
22
12
17
ns
16(6)
20
15
18
ns
18
24
16
19
ns
14(6)
20
13
16
ns
14(6)
19
14
16
ns
11
14
ns
DATA0–3 (3)
CB0–7 (CODE ID1,0 = 00, 11)
CB0–7 (CODE ID1,0 = 10)
LEOUT/GENERATE
u
d
CODE ID1,0
LEIN
From latched to Transparent
u
u
u
LEDIAG
From latched to Transparent
Internal
Control
Mode
ERROR
SC0–7
LEDIAG
From latched to Transparent
DATA0–31
Via Diagnostic Latch
17
14
10
—
14
22
d
u
(2)
8
8
d
u
8
9
Unit
ns
ns
ns
ns
ns
2584 tbl 32
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
CB0–7(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID
10)(4, 6)
CORRECT(4, 6)
DIAG
MODE(4, 6)
CODE ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
LEIN
3
3
ns
LEIN
2
3
ns
LEOUT/GENERATE
6(15)
0
ns
12
0
ns
8
0
ns
7
0
ns
14
0
ns
9
0
ns
LEOUT/GENERATE
16
0
ns
LEDIAG
3
3
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
ns
NOTE: (15) above applies to correction path.
2584 tbl 33
OUTPUT ENABLE/DISABLE TIMES(5)
Enable
From Input
Enable
d
d
OE Byte0–3
OESC
Disable
u
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
10
0
12
ns
SC0–7
0
10
0
12
ns
2584 tbl 34
(6)
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG ud (Positive–going pulse)
Min.
5
ns
NOTES:
2584 tbl 35
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5F.
6. Not production tested, guaranteed by characterization.
11.6
20
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460C AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0°C to +70°C, VCC = 5.0V ± 5%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
SC0–7
DATA0–31
ERROR
MULT ERROR
Unit
DATA0–31 (3)
19
24(2)
16
20
ns
CB0–7 (CODE ID1,0 = 00, 11)
14
21
12
16
ns
14
16
—
12
From Input
CB0–7 (CODE ID1,0 = 10)
u
d
LEOUT/GENERATE
—
9
—
ns
11
ns
11
ns
18
—
—
16
—
—
ns
DIAG MODE
Not Internal Control Mode
16
26
11
20
ns
18(6)
23
17
21
ns
22
28(2)
19
22
ns
15(6)
24
15
19
ns
16(6)
22
15
18
ns
15
25(2)
13
16
ns
LEIN
From latched to Transparent
u
u
u
LEDIAG
From latched to Transparent
LEDIAG
From latched to Transparent
DATA0–31
Via Diagnostic Latch
9
d
u
CORRECT
Not Internal Control Mode
CODE ID1,0
Internal
Control
Mode
d
u
2584 tbl 36
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
CB0–7(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID 10)(4, 6)
CORRECT(4, 6)
DIAG MODE(4, 6)
CODE ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
LEIN
3
4
ns
LEIN
2
4
ns
LEOUT/GENERATE
6(16)
0
ns
14
0
ns
LEOUT/GENERATE
8
0
ns
8
0
ns
LEOUT/GENERATE
17
0
ns
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
10
0
ns
LEOUT/GENERATE
19
0
ns
LEDIAG
3
3
ns
NOTE: (16) above applies to correction path.
2584 tbl 37
OUTPUT ENABLE/DISABLE TIMES(5)
Enable
From Input
Enable
d
d
OE Byte0–3
OESC
Disable
u
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
10
0
12
ns
SC0–7
0
10
0
12
ns
2584 tbl 38
(6)
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG ud (Positive–going pulse)
Min.
6
ns
NOTES:
2584 tbl 39
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.
11.6
21
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460C AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: –55°C to +125°C, V CC = 5.0V ± 10%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
SC0–7
DATA0–31
ERROR
MULT ERROR
Unit
DATA0–31 (3)
22
29(2)
21
24
ns
CB0–7 (CODE ID1,0 = 00, 11)
17
23
16
18
ns
17
18
—
13
From Input
CB0–7 (CODE ID1,0 = 10)
u
d
LEOUT/GENERATE
—
10
—
ns
12
ns
12
ns
20
—
—
17
—
—
ns
DIAG MODE
Not Internal Control Mode
18
29
12
23
ns
21
LEIN
From latched to Transparent
(6)
24
u
u
u
LEDIAG
From latched to Transparent
LEDIAG
From latched to Transparent
DATA0–31
Via Diagnostic Latch
10
d
u
CORRECT
Not Internal Control Mode
CODE ID1,0
Internal
Control
Mode
d
u
26
20
24
ns
32
21
25
ns
18
(6)
27
17
21
ns
19
(6)
25
18
21
ns
29(2)
14
18
ns
18
2584 tbl 40
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
CB0–7(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID 10)(4, 6)
CORRECT(4, 6)
DIAG
MODE(4, 6)
CODE ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
3
4
ns
LEIN
LEIN
2
4
ns
LEOUT/GENERATE
7(19)
3
ns
16
0
ns
10
0
ns
9
0
ns
19
0
ns
12
0
ns
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
21
0
ns
LEDIAG
3
3
ns
Note: (19) above applies to correction path.
2584 tbl 41
(5)
OUTPUT ENABLE/DISABLE TIMES
Enable
From Input
OE Byte0–3
OESC
Enable
d
d
Disable
u
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
12
0
14
ns
SC0–7
0
12
0
14
ns
2584 tbl 42
MINIMUM PULSE WIDTHS(6)
LEIN, LEOUT/GENERATE, LEDIAG ud (Positive–going pulse)
Min.
6
ns
NOTES:
2584 tbl 43
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5F.
6. Not production tested, guaranteed by characterization.
11.6
22
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460B AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0°C to +70°C, VCC = 5.0V ± 5%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
SC0–7
DATA0–31
ERROR
MULT ERROR
Unit
DATA0–31 (3)
25
30(2)
25
27
ns
CB0–7 (CODE ID1,0 = 00, 11)
14
30
17
20
ns
CB0–7 (CODE ID1,0 = 10)
16
18
—
—
ns
From Input
u
d
LEOUT/GENERATE
—
CORRECT
Not Internal Control Mode
—
23
—
—
ns
DIAG MODE
Not Internal Control Mode
17
26
20
24
ns
18(6)
26
21
26
ns
30
3
ns
LEIN
From latched to Transparent
27
u
u
u
LEDIAG
From latched to Transparent
LEDIAG
From latched to Transparent
DATA0–31
Via Diagnostic Latch
38
(2)
23
d
u
12
CODE ID1,0
Internal
Control
Mode
d
u
—
21
23
23
ns
23
ns
15(6)
29
19
22
ns
16(6)
32
19
24
ns
20
25
ns
16
32
(2)
2584 tbl 44
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
CB0–7(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID
10)(4, 6)
CORRECT(4, 6)
DIAG
MODE(4, 6)
CODE ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
LEIN
4
4
ns
LEIN
4
4
ns
LEOUT/GENERATE
19
0
ns
15
0
ns
15
0
ns
11
0
ns
17
0
ns
17
0
ns
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
20
0
ns
LEDIAG
4
3
ns
2584 tbl 45
(5)
OUTPUT ENABLE/DISABLE TIMES
Enable
From Input
OE Byte0–3
OESC
Enable
d
d
Disable
u
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
12
0
14
ns
SC0–7
0
12
0
14
ns
2584 tbl 46
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG ud (Positive–going pulse)
Min.
9
ns
NOTES:
2584 tbl 47
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.
11.6
23
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460B AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: –55°C to +125°C, V CC = 5.0V ± 10%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
SC0–7
DATA0–31
ERROR
MULT ERROR
DATA0–31 (3)
28
33(2)
28
30
ns
CB0–7 (CODE ID1,0 = 00, 11)
17
33
20
23
ns
19
23
—
15
From Input
CB0–7 (CODE ID1,0 = 10)
u
d
LEOUT/GENERATE
—
26
—
ns
26
—
—
26
—
—
ns
DIAG MODE
Not Internal Control Mode
20
29
23
27
ns
CODE ID1,0
21
29
24
29
ns
LEIN
From latched to Transparent
30
41
33
36
ns
18
32
22
25
ns
19
35
22
27
ns
19
35(2)
23
28
ns
LEDIAG
From latched to Transparent
DATA0–31
Via Diagnostic Latch
26
ns
24
u
u
u
26
d
u
CORRECT
Not Internal Control Mode
LEDIAG
From latched to Transparent
Internal
Control
Mode
d
u
Unit
ns
2584 tbl 48
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
CB0–7
(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID 10)(4, 6)
CORRECT(4, 6)
DIAG MODE(4, 6)
CODE
ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
LEIN
4
4
ns
LEIN
4
4
ns
LEOUT/GENERATE
23
0
ns
18
0
ns
18
0
ns
14
0
ns
20
0
ns
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
20
0
ns
LEOUT/GENERATE
23
0
ns
LEDIAG
4
3
ns
2584 tbl 49
OUTPUT ENABLE/DISABLE TIMES(5)
Enable
From Input
OE Byte0–3
OESC
Enable
d
d
Disable
u
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
12
0
14
ns
SC0–7
0
12
0
14
ns
2584 tbl 50
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG ud (Positive–going pulse)
Min.
12
ns
NOTES:
2584 tbl 51
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.
11.6
24
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0°C to 70°C, VCC = 5.0V ± 5%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
SC0–7
DATA0–31
ERROR
MULT ERROR
Unit
DATA0–31 (3)
27
36(2)
30
33
ns
CB0–7 (CODE ID1,0 = 00, 11)
16
34
19
23
ns
CB0–7 (CODE ID1,0 = 10)
16
20
—
—
ns
From Input
u
d
LEOUT/GENERATE
—
CORRECT
Not Internal Control Mode
—
23
—
—
ns
DIAG MODE
Not Internal Control Mode
17
26
20
24
ns
CODE ID1,0
18
26
21
26
ns
LEIN
From latched to Transparent
27
38
30
33
ns
15
29
19
22
ns
16
32
29
24
ns
16
32(2)
20
25
ns
u
u
u
LEDIAG
From latched to Transparent
DATA0–31
Via Diagnostic Latch
25
d
u
12
LEDIAG
From latched to Transparent
Internal
Control
Mode
d
u
—
21
25
25
ns
25
ns
2584 tbl 52
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
CB0–7(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00,
11) (4, 6)
CB0–7 (CODE ID 10)(4, 6)
CORRECT(4, 6)
DIAG
MODE(4, 6)
CODE ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
5
4
ns
LEIN
5
4
ns
LEOUT/GENERATE
23
0
ns
15
0
ns
15
0
ns
11
0
ns
17
0
ns
17
0
ns
LEIN
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
25
0
ns
LEDIAG
5
3
ns
2584 tbl 53
(5)
OUTPUT ENABLE/DISABLE TIMES
Enable
From Input
OE Byte0–3
OESC
Enable
d
d
Disable
u
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
12
0
14
ns
SC0–7
0
12
0
14
ns
2584 tbl 54
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG ud (Positive–going pulse)
Min.
9
ns
NOTES:
2584 tbl 55
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.
11.6
25
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: –55°C to +125°C, V CC = 5.0V ± 10%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
SC0–7
DATA0–31
ERROR
MULT ERROR
Unit
DATA0–31 (3)
30
39(2)
33
36
ns
CB0–7 (CODE ID1,0 = 00, 11)
19
37
22
26
ns
19
23
—
15
From Input
CB0–7 (CODE ID1,0 = 10)
u
d
LEOUT/GENERATE
—
28
—
ns
28
ns
28
ns
24
—
—
26
—
—
ns
DIAG MODE
Not Internal Control Mode
20
29
23
27
ns
CODE ID1,0
21
29
24
29
ns
LEIN
From latched to Transparent
30
41
33
36
ns
18
32
22
25
ns
19
35
22
27
ns
19
35(2)
23
28
ns
u
u
u
LEDIAG
From latched to Transparent
DATA0–31
Via Diagnostic Latch
28
d
u
CORRECT
Not Internal Control Mode
LEDIAG
From latched to Transparent
Internal
Control
Mode
d
u
2584 tbl 56
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–3 (4)
CB0–7(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID
10)(4, 6)
CORRECT(4, 6)
DIAG
MODE(4, 6)
CODE ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
LEIN
5
4
ns
LEIN
5
4
ns
LEOUT/GENERATE
27
0
ns
18
0
ns
18
0
ns
14
0
ns
20
0
ns
20
0
ns
LEOUT/GENERATE
28
0
ns
LEDIAG
5
3
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
ns
2584 tbl 57
OUTPUT ENABLE/DISABLE TIMES(5)
Enable
From Input
OE Byte0–3
OESC
Enable
d
d
Disable
u
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
12
0
14
ns
SC0–7
0
12
0
14
ns
2584 tbl 58
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG ud (Positive–going pulse)
Min.
12
ns
NOTES:
2584 tbl 59
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.
11.6
26
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0°C to +70°C, VCC = 5.0V ± 5%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
SC0–7
DATA0–31
ERROR
MULT ERROR
Unit
DATA0–31 (3)
37
49(2)
40
45
ns
CB0–7 (CODE ID1,0 = 00, 11)
22
46
26
31
ns
CB0–7 (CODE ID1,0 = 10)
22
30
—
—
ns
From Input
u
d
LEOUT/GENERATE
—
CORRECT
Not Internal Control Mode
—
31
—
—
ns
DIAG MODE
Not Internal Control Mode
23
35
27
33
ns
CODE ID1,0
25
35
29
35
ns
LEIN
From latched to Transparent
37
51
41
45
ns
21
38
26
30
ns
22
42
26
33
ns
22
42(2)
27
34
ns
u
u
u
LEDIAG
From latched to Transparent
DATA0–31
Via Diagnostic Latch
30
d
u
17
LEDIAG
From latched to Transparent
Internal
Control
Mode
d
u
—
29
30
30
ns
30
ns
2584 tbl 60
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
CB0–7(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID
10)(4, 6)
CORRECT(4, 6)
DIAG
MODE(4, 6)
CODE ID1,0(4, 6)
LEIN
(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
LEIN
6
4
ns
LEIN
5
4
ns
LEOUT/GENERATE
30
0
ns
20
0
ns
20
0
ns
16
0
ns
23
0
ns
23
0
ns
LEOUT/GENERATE
31
0
ns
LEDIAG
6
3
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
ns
2584 tbl 61
OUTPUT ENABLE/DISABLE TIMES(5)
Enable
From Input
OE Byte0–3
OESC
Enable
d
d
Disable
u
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
15
0
17
ns
SC0–7
0
15
0
17
ns
2584 tbl 62
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG ud (Positive–going pulse)
Min.
12
ns
NOTES:
2584 tbl 63
1. CI = 50pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.
11.6
27
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: –55°C to +125°C, V CC = 5.0V ± 10%
The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output
SC0–7
DATA0–31
ERROR
MULT ERROR
Unit
DATA0–31 (3)
40
52(2)
44
48
ns
CB0–7 (CODE ID1,0 = 00, 11)
25
49
29
34
ns
CB0–7 (CODE ID1,0 = 10)
25
33
—
—
ns
—
20
From Input
u
d
LEOUT/GENERATE
33
33
ns
33
ns
32
—
—
34
—
—
ns
DIAG MODE
Not Internal Control Mode
26
38
30
36
ns
CODE ID1,0
28
38
32
38
ns
LEIN
From latched to Transparent
40
54
44
48
ns
24
42
29
33
ns
25
47(2)
29
36
ns
25
47
30
37
ns
u
u
u
LEDIAG
From latched to Transparent
DATA0–31
Via Diagnostic Latch
33
d
u
CORRECT
Not Internal Control Mode
LEDIAG
From latched to Transparent
Internal
Control
Mode
d
u
2584 tbl 64
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input
d
d
d
d
d
u d
d
d
u d
DATA0–31 (4)
CB0–7(4)
DATA0–31 (4, 6)
CB0–7 (CODE ID 00, 11) (4, 6)
CB0–7 (CODE ID 10)(4, 6)
CORRECT(4, 6)
DIAG MODE(4, 6)
CODE
ID1,0(4, 6)
LEIN(4, 6)
DATA0–31 (4, 6)
To Input
(Latching Data)
Set-up Time
Min.
Hold Time
Min.
Unit
LEIN
6
4
ns
LEIN
5
4
ns
LEOUT/GENERATE
36
0
ns
24
0
ns
24
0
ns
20
0
ns
28
0
ns
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
LEOUT/GENERATE
28
0
ns
LEOUT/GENERATE
37
0
ns
LEDIAG
6
3
ns
2584 tbl 65
OUTPUT ENABLE/DISABLE TIMES(5)
Enable
From Input
OE Byte0–3
OESC
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
Enable
d
d
Disable
u
Disable
To Output
Min.
Max.
Min.
Max.
Unit
DATA0–31
0
15
0
17
ns
SC0–7
0
15
0
17
ns
2584 tbl 66
Min.
(Positive–going pulse)
15
ns
NOTES:
2584 tbl 67
1. CI = 5pF.
2. These parameters are combinational propagation delay calculations, and are not tested in production.
3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms.
4. Set-up and Hold times relative to Latch Enables (Latching Data).
5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF.
6. Not production tested, guaranteed by characterization.
11.6
28
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETECT OR CORRECTION MODE (FROM GENERATE MODE)
OE byte
0
6
0
7
DATA bus
(Output)
Valid DATA IN
OUT
14
Propagation Delay
From
To
Min./Max.
OE byte = High to DATAOUT Disabled
OE byte = High to DATAOUT Disabled
OE byte = Low to DATAOUT Enabled
OE byte = Low to DATAOUT Enabled
Min.
Max.
Min.
Max.
(Corrected DATA if Correct Mode)
(DATAIN if Detect Mode)
DATAIN to DATAOUT
Max.
CORRECT = High to DATAOUT
Max.
CBIN to DATAOUT
CBIN to DATAOUT
*LEIN = High to DATAOUT
Max.
Max.
Max.
LEOUT/GEN = High to DATAOUT
LEOUT/GEN = High to MERROR = Low
LEOUT/GEN = High to ERROR = Low
DATAIN to ERROR = Low
CBIN to ERROR = Low
*LEIN = High to ERROR = Low*
Max.
Max.
Max.
Max.
Max.
Max.
(Low = Error)
DATAIN to MERROR = Low
CBIN to MERROR = Low
*LEIN = High to MERROR = Low*
Max.
Max.
Max.
(Low = Error)
DATAIN to SCOUT
CBIN to SCOUT
Max.
Max.
OESC = High to SCOUT Disabled
OESC = High to SCOUT Disabled
OESC = Low to SCOUT Enabled
OESC = Low to SCOUT Enabled
Min.
Max.
Min.
Max.
Valid Checkbits In
CBIN
11
CORRECT
CODE ID1,0 = 00, 11
CODE ID1,0 = 10
12
10
19*
LEIN.
LEOUT/GEN
9
8
7
10
7
13*
ERROR
11
9
16*
MERROR
11
9
OESC
0
6
0
7
SCOUT
Valid
NOTES:
1. BOLD indicates critical parameters.
2. This is "E" version timing spec. Check appropriate table for other speed versions.
* Assumes "CBIN" and/or "DATAIN" are valid at least 4ns before "LEIN" goes high.
11.6
(Syndrome Bits Come Out)
2584 drw 10
29
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
GENERATE MODE (FROM DETECT OR CORRECTION MODE)
OE byte
0
6
0
7
DATA Bus
(Output)
Valid DATA IN
CODE ID 1,0 = 10
CBIN
Propagation Delay
From
To
Min./Max.
OE byte = High to DATAOUT Disabled
OE byte = High to DATAOUT Disabled
OE byte = Low to DATAOUT Enabled
OE byte = Low to DATAOUT Enabled
Min.
Max.
Min.
Max.
CBIN to DATAOUT
Max.
OUT
10
Valid Checkbits In
LEIN
LEOUT/GEN
(Generate Mode)
7
13
ERR/MERR
(CODE ID 1,0 = 10)
DATAIN to SCOUT
*LEIN = High to SCOUT*
CBIN to SCOUT
(Forced High)
11
16*
9
OESC
OESC = High to SCOUT Disabled
OESC = High to SCOUT Disabled
OESC = Low to SCOUT Enabled
OESC = Low to SCOUT Enabled
0
6
0
7
SCOUT
LEOUT/GENERATE = Low to
ERROR = High
LEOUT/GENERATE = Low to SCOUT
Valid Checkbits
CORRECT
Max.
Max.
Max.
Max.
Max.
Min.
Max.
Min.
Max.
(Check Bits Exit)
(Don't Care)
2584 drw 09
NOTES:
1. BOLD indicates critical parameters.
2. Valiid "DATA" and valid CBIN" are shown to occur simultaneously, since both buses are latched and opened by the "LEIN" input.
3. This is "E" version timing spec. Check appropriate table for other speed versions.
* Assumes DATA bus becomes input 4ns before LEIN goes high.
11.6
30
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SET-UP AND HOLD TIMES AND MINIMUM PULSE WIDTHS
Set-up/Hold Time
With Respect To
Of
Min./Max.
Valid
CBIN
2
3
5
LEIN.
14*
3
3
CBIN Set-up to LEIN = Low
CBIN Hold to LEIN = Low
Min.
Min.
LEIN width
Min.
*LEIN = High to LEOUT/GEN = Low*
DATA Set-up to LEIN = Low
DATA Hold to LEIN = Low
Min.
Min.
Min.
CBIN Set-up to LEOUT/GEN = Low
CBIN Set-up to LEOUT/GEN = Low
DATA Set-up to LEOUT/GEN = Low
Min.
Min.
Min.
LEOUT/GENERATE Width
Min.
CORRECT Set-up to
LEOUT/GEN = Low
Min.
Valid
DATAIN
CODE ID1,0 = 00, 11
CODE ID1,0 = 10
11
6
6
LEOUT/GEN
5
6
CORRECT
NOTES:
2584 drw 11
1. BOLD indicates critical parameters.
2. This is "E" version timing spec. Check appropriate table for other speed versions.
* Enable to enable timing requirement to ensure that the last DATA word applied to "DATAIN" is made available as DATAOUT"; assumes that "DATAIN"
is valid at least 4ns before "LEIN" goes high.
INPUT/OUTPUT INTERFACE CIRCUIT
VCC
ESD
PROTECTION
IIH
IOH
INPUTS
OUTPUTS
IIL
IOL
2584 drw 12
2584 drw 13
Figure 5. Input Structure (All Inputs)
Figure 6. Out put Structure
11.6
31
IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST LOAD CIRCUIT
VCC
+ 7.0V
500Ω
VOUT
VIN
Pulse
Generator
D.U.T.
50pF
CL
RT
500Ω
2584 drw 14
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance
RL = Termination resistance: should be equal to ZOUT of the Pulse Generator
Figure 7.
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Test
Switch
Input Rise/Fall Times
1V/ns
Disable Low
Closed
Input Timing Reference Levels
1.5V
Enable Low
Output Reference Levels
1.5V
All other Tests
Output Load
Open
2584 tbl 68
See Figure 7
2584 tbl 69
ORDERING INFORMATION
IDT
49C460
Device Type
X
Speed
X
Package
X
Process/
Temperature
Range
BLANK
B
Commercial (0°C to + 70°C)
Military (– 55°C to + 125°C)
Compliant to MIL-STD-883, Class B
G
J
FF
Pin Grid Array
Plastic Leaded Chip Carrier
Fine Pitch Flatpack
Blank
A
B
C
D
E
Standard Speed
High-Speed
Very High-Speed
Super-High-Speed
Ultra-High Speed
Fastest Speed
49C460
32-Bit E. D. C.
2584 drw 15
11.6
32