TI CY74FCT162H501TSSOP 18-bit registered transceiver Datasheet

1CY74FCT162H501
T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
SCCS057 - August 1994 - Revised March 2000
18-Bit Registered Transceivers
Features
Functional Description
• FCT-E speed at 3.8 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6 mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
• VCC = 5V ± 10%
CY74FCT16501T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is latched
if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW,
the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA.
The output buffers are designed with a power-off disable
feature to allow live insertion of boards.
The CY74FCT16501T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
THE CY74FCT162501T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for minimal
undershoot
and
reduced
ground
bounce.
The
CY74FCT162501T is ideal for driving transmission lines.
CY74FCT162501T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
CY74FCT162H501T Features:
• Bus hold retains last active state
• Eliminates the need for external pull-up or pull-down
resistors
The CY74FCT162H501T is a 24-mA balanced output part, that
has “bus hold” on the data inputs. The device retains the input’s
last state whenever the input goes to high impedance. This
eliminates the need for pull-up/down resistors and prevents
floating inputs.
Pin Configuration
Functional Block Diagram
SSOP/TSSOP
Top View
OEAB
LEAB
A1
GND
A2
OEAB
A3
CLKBA
VCC
A4
A5
A6
LEBA
OEBA
CLKAB
LEAB
A1
C
C
D
D
B1
C
C
D
D
TO 17 OTHER CHANNELS
GND
A7
A8
A9
A 10
A 11
A 12
GND
A 13
A 14
A 15
VCC
FCT16501-1
A 16
A 17
GND
A 18
OEBA
LEBA
1
2
56
55
3
4
54
53
5
6
7
52
51
50
8
9
49
48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
46
45
44
43
42
41
40
39
38
37
36
35
34
24
25
26
27
28
33
32
31
30
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
FCT16501-2
Copyright
© 2000, Texas Instruments Incorporated
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Maximum Ratings[6, 7]
Pin Description
Name
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
DC Input Voltage................................................. −0.5V to +7.0V
CLKAB
A-to-B Clock Input
DC Output Voltage.............................................. −0.5V to +7.0V
CLKBA
B-to-A Clock Input
A
A-to-B Data Inputs or B-to-A Three-State
Outputs[1]
DC Output Current
(Maximum Sink Current/Pin)........................... −60 to +120 mA
B
B-to-A Data Inputs or A-to-B Three-State
Outputs[1]
Storage Temperature .................................... −55°C to +125°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Power Dissipation.......................................................... 1.0W
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Operating Range
Function Table[2, 3]
Inputs
Range
Outputs
OEAB
LEAB
CLKAB
A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
L
X
B[4]
H
L
H
X
B[5]
Industrial
Ambient
Temperature
VCC
−40°C to +85°C
5V ± 10%
Notes:
1. On the 74FCT162H501T these pins have bus hold.
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-impedance
= LOW-to-HIGH Transition
4. Output level before the indicated steady-state input conditions were established.
5. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
6. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
7. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
2
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Electrical Characteristics Over the Operating Range
Parameter
Description
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Test Conditions
Min.
Input Hysteresis
VIK
Input Clamp Diode Voltage
IIH
Input HIGH Current
100
−0.7
VCC=Min., IIN=−18 mA
Standard
Input LOW Current
Standard
VCC=Max., VI=VCC
V
mV
−1.2
V
±1
µA
±100
VCC=Max., VI=GND
Bus Hold
Input[10]
Unit
V
0.8
Bus Hold
IIL
Max.
2.0
[9]
VH
Typ.[8]
VCC=Min.,
±1
µA
±100
µA
VI=2.0V
−50
µA
VI=0.8V
+50
µA
IBBH
IBBL
Bus Hold Sustain Current on Bus Hold
IBHHO
IBHLO
Bus Hold Overdrive Current on Bus Hold Input[10]
VCC=Max., VI=1.5V
IOZH
High Impedance Output Current
(Three-State Output pins)
IOZL
IOS
TBD
mA
VCC=Max., VOUT=2.7V
±1
µA
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=0.5V
±1
µA
Short Circuit Current[11]
VCC=Max., VOUT=GND
−80
−200
mA
Current[11]
VCC=Max., VOUT=2.5V
−50
−180
mA
±1
µA
Max.
Unit
IO
Output Drive
IOFF
Power-Off Disable
−140
VCC=0V, VOUT≤4.5V[12]
Output Drive Characteristics for CY74FCT16501T
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Min.
Typ.[8]
VCC=Min., IOH=−3 mA
2.5
3.5
VCC=Min., IOH=−15 mA
2.4
3.5
VCC=Min., IOH=−32 mA
2.0
3.0
Test Conditions
VCC=Min., IOL=64 mA
V
0.2
0.55
V
Min.
Typ.[8]
Max.
Unit
Output Drive Characteristics for CY74FCT162501T, CY74FCT162H501T
Parameter
Description
Test Conditions
Output LOW
Current[11]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
60
115
150
mA
IODH
Output HIGH
Current[11]
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
−60
−115
−150
mA
VOH
Output HIGH Voltage
VCC=Min., IOH=−24 mA
2.4
3.3
VOL
Output LOW Voltage
VCC=Min., IOL=24 mA
IODL
0.3
V
0.55
V
Notes:
8. Typical values are at VCC= 5.0V, TA= +25˚C ambient.
9. This parameter is specified but not tested.
10. Pins with bus hold are described in Pin Description.
11. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
12. Tested at +25˚C.
3
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Capacitance[9] (TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Test Conditions
Typ.[8]
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6.0
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8.0
pF
Power Supply Characteristics
Sym.
Test Conditions[13]
Parameter
VIN<0.2V
VIN>VCC−0.2V
Min.
Typ.[8]
Max.
Unit
—
5
500
µA
—
0.5
1.5
mA
ICC
Quiescent Power Supply
Current
VCC=Max.
∆ICC
Quiescent Power Supply
Current TTL inputs HIGH
VCC= Max., VIN = 3.4V[14]
ICCD
Dynamic Power Supply
Current[15]
VCC=Max., Outputs Open
OEAB=OEBA=VCC or GND
One Input Toggling,
50% Duty Cycle
VIN=VCC or
VIN=GND
—
75
120
µA/
MHz
IC
Total Power Supply
Current[16]
VCC=Max., Outputs Open
f0 =10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB = GND, One Bit Toggling
f1 = 5MHz, 50% Duty Cycle
VIN=VCC or
VIN=GND
—
0.8
1.7
mA
VIN=3.4V or
VIN=GND
—
1.3
3.2
VIN=VCC or
VIN=GND
—
3.8
6.5[17]
VIN=3.4V or
VIN=GND
—
8.5
20.8[17]
VCC=Max., Outputs Open
f0 = 10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=VCC
LEAB=GND
Eighteen Bits Toggling
f1=2.5MHz, 50% Duty Cycle
Notes:
13. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
14. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
15. This parameter is not directly testable, but is derived for use in Total Power Supply.
16. IC= IQUIESCENT + IINPUTS + IDYNAMIC
IC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
= Duty Cycle for TTL inputs HIGH
DH
= Number of TTL inputs at DH
NT
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Input signal frequency
f1
= Number of inputs changing at f1
N1
All currents are in milliamps and all frequencies are in megahertz.
17. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
4
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Switching Characteristics Over the Operating Range[18]
CY74FCT16501AT
CY74FCT162501AT
Parameter
Description
CY74FCT162501CT
CY74FCT162H501CT
CY74FCT16501ET
CY74FCT162501ET
CY74FCT162H501ET
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Fig.
No.[19]
fMAX
CLKAB or CLKBA
frequency[20]
—
150
—
150
—
150
MHz
—
tPLH
tPHL
Propagation Delay
A to B or B to A
1.5
5.1
1.5
4.6
1.5
3.8
ns
1,3
tPLH
tPHL
Propagation Delay
LEBA to A, LEAB to B
1.5
5.6
1.5
5.3
1.5
4.2
ns
1,5
tPLH
tPHL
Propagation Delay
CLKBA to A,
CLKAB to B
1.5
5.6
1.5
5.3
1.5
4.2
ns
1,5
tPZH
tPZL
Output Enable Time
OEBA to A, OEAB to B
1.5
6.0
1.5
5.6
1.5
4.8
ns
1,7,8
tPHZ
tPLZ
Output Disable Time
OEBA to A, OEAB to B
1.5
5.6
1.5
5.2
1.5
5.2
ns
1,7,8
tSU
Set-Up Time,
HIGH or LOW
A to CLKAB,
B to CLKBA
3.0
—
3.0
—
2.4
—
ns
4
tH
Hold Time
HIGH or LOW
A to CLKAB,
B to CLKBA
0
—
0
—
0
—
ns
4
tSU
Set-Up Time, Clock
HIGH or LOW LOW
A to LEAB,
Clock
B to LEBA
HIGH
3.0
—
3.0
—
2.0
—
ns
4
1.5
—
1.5
—
1.5
—
ns
4
tH
Hold Time, HIGH or
LOW, A to LEAB,
B to LEBA
1.5
—
1.5
—
0.5
—
ns
4
tW
LEAB or LEBA Pulse
Width HIGH[20]
3.0
—
3.0
—
3.0
—
ns
5
tW
CLKAB or CLKBA
Pulse Width HIGH or
LOW[20]
3.0
—
3.0
—
3.0
—
ns
5
tSK(O)
Output Skew[21]
—
0.5
—
0.5
—
0.5
ns
—
Notes:
18. Minimum limits are specified, but not tested, on propagation delays.
19. See “Parameter Measurement Information” in the General Information section.
20. This parameter is guaranteed but not tested.
21. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
5
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Ordering Information CY74FCT16501T
Speed
(ns)
3.8
5.1
Ordering Code
Package
Name
Package Type
CY74FCT16501ETPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT16501ETPVC/PVCT
O56
56-Lead (300-Mil) SSOP
CY74FCT16501ATPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Operating
Range
Industrial
Industrial
Ordering Information CY74FCT162501T
Speed
(ns)
3.8
4.6
5.1
Ordering Code
Package
Name
Package Type
74FCT162501ETPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162501ETPVC
O56
56-Lead (300-Mil) SSOP
74FCT162501ETPVCT
O56
56-Lead (300-Mil) SSOP
74FCT162501CTPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162501CTPVC
O56
56-Lead (300-Mil) SSOP
74FCT162501CTPVCT
O56
56-Lead (300-Mil) SSOP
74FCT162501ATPACT
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162501ATPVC
O56
56-Lead (300-Mil) SSOP
74FCT162501ATPVCT
O56
56-Lead (300-Mil) SSOP
Operating
Range
Industrial
Industrial
Industrial
Ordering Information CY74FCT162H501T
Speed
(ns)
3.8
4.6
Ordering Code
Package
Name
Package Type
74FCT162H501ETPACT
Z56
56-Lead (240-Mil) TSSOP
74FCT162H501ETPVC/PVCT
O56
56-Lead (300-Mil) SSOP
74FCT162H501CTPACT
Z56
56-Lead (240-Mil) TSSOP
74FCT162H501CTPVC/PVCT
O56
56-Lead (300-Mil) SSOP
6
Operating
Range
Industrial
Industrial
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
7
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Copyright  2000, Texas Instruments Incorporated
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