ON NB3H60113G 3.3 v / 2.5 v programmable omniclock generator Datasheet

NB3H60113G
3.3 V / 2.5 V Programmable
OmniClock Generator
with Single Ended (LVCMOS/LVTTL) and
Differential (LVPECL/LVDS/ HCSL/CML)
Outputs
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The NB3H60113G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock
generator that supports any output frequency from 8 kHz to 200 MHz.
The device accepts fundamental mode parallel resonant crystal or a
single ended (LVCMOS/LVTTL) reference clock as input. It
generates either three single ended (LVCMOS/LVTTL) outputs, or
one single ended output and one differential
(LVPECL/LVDS/HCSL/CML) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Using the PLL bypass mode, it is possible to get a copy of the input
clock on any or all of the outputs. The device can be powered down
using the Power Down pin (PD#). It is possible to program the internal
input crystal load capacitance and the output drive current provided by
the device. The device also has automatic gain control (crystal power
limiting) circuitry which avoids the device overdriving the external
crystal.
WDFN8
CASE 511AT
MARKING DIAGRAM
1
H0MG
G
H0 = Specific Device Code
M = Date Code
G
= Pb−Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 21 of
this data sheet.
Features
• Member of the OmniClock Family of Programmable Clock
Generators
• Operating Power Supply: 3.3 V ± 10%, 2.5 V ± 10%
• I/O Standards
•
•
•
•
♦
•
•
•
•
•
•
Inputs: LVCMOS/LVTTL, Fundamental Mode
Crystal
♦ Outputs: LVCMOS/LVTTL
♦ Outputs: LVPECL, LVDS, CML and HCSL
3 Programmable Single Ended (LVCMOS/LVTTL)
Outputs from 8 kHz to 200 MHz
1 Programmable Differential Clock Output up to
200 MHz
Input Frequency Range
♦ Crystal: 3 MHz to 50 MHz
♦ Reference Clock: 3 MHz to 200 MHz
Configurable Spread Spectrum Frequency Modulation
Parameters (Type, Deviation, Rate)
Programmable Internal Crystal Load Capacitors
Programmable Output Drive Current for Single Ended
Outputs
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
•
•
•
Power Saving mode through Power Down Pin
Programmable PLL Bypass Mode
Programmable Output Inversion
Programming and Evaluation Kit for Field
Programming and Quick Evaluation
Temperature Range −40°C to 85°C
Packaged in 8−Pin WDFN
These are Pb−Free Devices
Typical Applications
• eBooks and Media Players
• Smart Wearables, Portable Medical and Industrial
•
1
Equipment
Set Top Boxes, Printers, Digital Cameras and
Camcorders
Publication Order Number:
NB3H60113G/D
NB3H60113G
BLOCK DIAGRAM
PD#
VDD
Crystal/Clock Control
Output control
Configuration
Memory
Frequency
and SS
XIN/CLKIN
Crystal
XOUT
Output
Divider
CMOS/
Diff
buffer
Output
Divider
CMOS /
Diff
buffer
CLK1
Output
Divider
CMOS
buffer
CLK2
PLL Block
Clock Buffer/
Crystal
Oscillator and
AGC
Phase
Detector
Charge
Pump
VCO
Feedback
Divider
CLK0
PLL Bypass Mode
GND
Notes:
1. CLK0 and CLK1 can be configured to be one of LVPECL, LVDS, HCSL or CML output, or two single−ended LVCMOS/ LVTTL outputs.
2. Dotted lines are the programmable control signals to internal IC blocks.
3. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
XIN/CLKIN
1
8
CLK2
XOUT
2
7
VDD
NB3H60113G
PD#
3
6
CLK1
GND
4
5
CLK0
Figure 2. Pin Connections (Top View) – WDFN8
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NB3H60113G
Table 1. PIN DESCRIPTION
Pin No.
Pin Name
Pin Type
1
XIN/CLKIN
Input
Description
2
XOUT
Output
3
PD#
Input
4
GND
Ground
Power supply ground
5
CLK0
SE/DIFF
output
Supports 8 kHz to 200 MHz Single−Ended (LVCMOS/LVTTL) signals or Differential
(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also be a
copy of the input clock. The single ended output will be LOW and differential outputs will
be complementary LOW/HIGH until the PLL has locked and the frequency has stabilized.
6
CLK1
SE/DIFF
output
Supports 8 kHz to 200 MHz Single−Ended (LVCMOS/LVTTL) signals or Differential
(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also be a
copy of the input clock. The single ended output will be LOW and differential outputs will
be complementary LOW/HIGH until the PLL has locked and the frequency has stabilized.
7
VDD
Power
3.3 V / 2.5 V power supply
8
CLK2
SE
output
Supports 8 kHz to 200 MHz Single−Ended (LVCMOS/LVTTL) signals. Using PLL Bypass
mode, the output can also be a copy of the input clock. The output will be LOW until the
PLL has locked and the frequency has stabilized.
3 MHz to 50 MHz crystal input connection or an external single−ended reference input
clock between 3 MHz and 200 MHz
Crystal output. Float this pin when external reference clock is connected at XIN
Asynchronous LVCMOS/ LVTTL input. Active Low Master Reset to disable the device and
set outputs Low. Internal pull−down resistor. This pin needs to be pulled High for normal
operation of the chip.
TYPICAL CRYSTAL PARAMETERS
Crystal: Fundamental Mode Parallel Resonant
Frequency: 3 MHz to 50 MHz
Table 2. POWER DOWN FUNCTION TABLE
PD#
Function
0
Device Powered Down
1
Device Powered Up
Table 3. MAX CRYSTAL LOAD CAPACITORS
RECOMMENDATION
Crystal Frequency Range
Max Cap Value
3 MHz – 30 MHz
20 pF
30 MHz – 50 MHz
10 pF
Shunt Capacitance (C0): 7 pF (Max)
Equivalent Series Resistance (ESR): 150 W (Max)
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3
NB3H60113G
FUNCTIONAL DESCRIPTION
The NB3H60113G is a 3.3 V / 2.5 V programmable, single
ended / differential clock generator, designed to meet the
clock requirements for consumer and portable markets. It
has a small package size and it requires low power during
operation and while in standby. This device provides the
ability to configure a number of parameters as detailed in the
following section. The One−Time Programmable memory
allows programming and storing of one configuration in the
memory space.
3.3V/2.5V
R (optional)
0.1 mF
0.01 mF
VDD
Crystal or
Reference
Clock input
XIN/CLKIN
XOUT
NB3H60113G
CLK2
PD#
GND
CLK1
CLK0
Single Ended Clock
Single Ended Clocks
OR
Differential Clock
LVPECL/LVDS/
HCSL/CML
Figure 3. Power Supply Noise Suppression
Power Supply
Clock Input
20.39 pF with a step size of 0.05 pF. Refer to Table 3 for
recommended maximum load capacitor values for stable
operation. There are three modes of loading the crystal –
with internal chip capacitors only, with external capacitors
only or with the both internal and external capacitors. Check
with the crystal vendor’s load capacitance specification for
setting of the internal load capacitors. The minimum value
of 4.36 pF internal load capacitor need to be considered
while selecting external capacitor value. These will be
bypassed when using an external reference clock.
Input Frequency
Automatic Gain Control (AGC)
The clock input block can be programmed to use a
fundamental mode crystal from 3 MHz to 50 MHz or a
single ended reference clock source from 3 MHz to
200 MHz. When using output frequency modulation for
EMI reduction, for optimal performance, it is recommended
to use crystals with frequency more than 6.75 MHz as input.
Crystals with ESR values of up to 150 W are supported.
When using a crystal input, it is important to set crystal load
capacitor values correctly to achieve good performance.
The Automatic Gain Control (AGC) feature adjusts the
gain to the input clock based on its signal strength to
maintain a good quality input clock signal level. This feature
takes care of low clock swings fed from external reference
clocks and ensures proper device operation. It also enables
maximum compatibility with crystals from different
manufacturers, processes, quality and performance. AGC
also takes care of the power dissipation in the crystal; avoids
over driving the crystal and thus extending the crystal life.
In order to calculate the AGC gain accurately and avoid
increasing the jitter on the output clocks, the user needs to
provide crystal load capacitance as well as other crystal
parameters like ESR and shunt capacitance (C0).
Device Supply
The NB3H60113G is designed to work with a 3.3 V/2.5 V
VDD power supply. For VDD operation of 1.8 V, refer to
NB3V60113G datasheet. In order to suppress power supply
noise it is recommended to connect decoupling capacitors of
0.1 mF and 0.01 mF close to the VDD pin as shown in
Figure 3.
Programmable Crystal Load Capacitors
The provision of internal programmable crystal load
capacitors eliminates the necessity of external load
capacitors for standard crystals. The internal load capacitor
can be programmed to any value between 4.36 pF and
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NB3H60113G
Programmable Clock Outputs
to 200 MHz with or without frequency modulation. It should
be noted that certain combinations of output frequencies and
spread spectrum configurations may not be recommended
for optimal and stable operation.
For differential clocking, CLK0 and CLK1 can be
configured as LVPECL, LVDS, HCSL or CML. Refer to the
Application Schematic in Figure 4.
Output Type and Frequency
The NB3H60113G provides three independent single
ended LVCMOS/LVTTL outputs, or one single ended
LVCMOS/LVTTL output and one LVPECL/LVDS/HCSL/
CML differential output. The device supports any single
ended output or differential output frequency from 8 kHz up
3 .3 V / 2 .5 V
0.1 mF
0.01 mF
VDD
Crystal or
Reference
Clock Input
XIN / CLKIN
CLK2
CLK1
XOUT
NB3H60113G
Single Ended Clock
Differential Clock
LVPECL/LVDS/HCSL/CML
CLK0
VDD
PD#
GND
Figure 4. Application Setup for Differential Output Configuration
Programmable Output Drive
Spread Spectrum Frequency Modulation
The drive strength or output current of each of the
LVCMOS clock outputs is programmable. For VDD of 3.3 V
and 2.5 V four distinct levels of LVCMOS output drive
strengths can be selected as mentioned in the DC Electrical
Characteristics. This feature provides further load drive and
signal conditioning as per the application requirement.
Spread spectrum is a technique using frequency
modulation to achieve lower peak electromagnetic
interference (EMI). It is an elegant solution compared to
techniques of filtering and shielding. The NB3H60113G
modulates the output of its PLL in order to “spread” the
bandwidth of the synthesized clock, decreasing the peak
amplitude at the center frequency and at the frequency’s
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most clock generators. Lowering EMI by
increasing a signal’s bandwidth is called ‘spread spectrum
modulation’.
PLL BYPASS Mode
PLL Bypass mode can be used to buffer the input clock on
any of the outputs or all of the outputs. Any of the clock
outputs can be programmed to generate a copy of the input
clock.
Output Inversion
All output clocks of the NB3H60113G can be
phase inverted relative to each other. This feature can also be
used in conjunction with the PLL Bypass mode.
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NB3H60113G
Figure 5. Frequency Modulation or Spread Spectrum Clock for EMI Reduction
For any input frequency selected, above limits must be
observed for a good spread spectrum profile.
For example, the minimum recommended reference
frequency for a modulation rate of 30 kHz would be 30 kHz
* 225 = 6.75 MHz. For 27 MHz, the maximum recommended
modulation rate would be 27 MHz / 225 = 120 kHz.
The outputs of the NB3H60113G can be programmed to
have either center spread from ±0.125% to ±3% or down
spread from −0.25% to −4%. The programmable step size
for spread spectrum deviation is 0.125% for center spread
and 0.25% for down spread respectively. Additionally, the
frequency modulation rate is also programmable.
Frequency modulation from 30 kHz to 130 kHz can be
selected. Spread spectrum, when on, applies to all the
outputs of the device but not to output clocks that use the
PLL bypass feature. There exists a tradeoff between the
input clock frequency and the desired spread spectrum
profile. For certain combinations of input frequency and
modulation rate, the device operation could be unstable and
should be avoided. For spread spectrum applications, the
following limits are recommended:
Fin (Min) = 6.75 MHz
Fmod (range) = 30 kHz to 130 kHz
Fmod (Max) = Fin / 225
Control Inputs
Power Down
Power saving mode can be activated through the power
down PD# input pin. This input is an LVCMOS/LVTTL
active Low Master Reset that disables the device and sets
outputs Low. By default it has an internal pull−down resistor.
The chip functions are disabled by default and when PD# pin
is pulled high the chip functions are activated.
Configuration Space
NB3H60113G has one Configuration. Table 4 shows an
example of device configuration.
Table 4. EXAMPLE CONFIGURATION
Input
Frequency
24 MHz
Output Frequency
VDD
SS%
SS Mod
Rate
CLK0 = 33 MHz
CLK1 = 12 MHz
CLK2 = 24 MHz
3.3 V
−0.5%
100 kHz
Output Drive
Output
Inversion
Output
Enable
PLL Bypass
Notes
CLK0 = 12 mA
CLK1 = 8 mA
CLK2 = 4 mA
CLK0 = N
CLK1 = N
CLK2 = Y
CLK0 = Y
CLK1 = Y
CLK2 = Y
CLK0 = N
CLK1 = N
CLK2 = Y
CLK2 Ref clk
Default Device State
website can be used along with the programming kit to
achieve this purpose. For mass production, parts can be
programmed with a customer qualified configuration and
sourced from ON Semiconductor as a dash part number (Eg.
NB3H60113G−01).
The NB3H60113G parts shipped from ON Semiconductor
are blank, with no inputs/outputs programmed. These need
to be programmed by the field sales or distribution or by the
user themselves before they can be used. Programmable
clock software downloadable from the ON Semiconductor
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NB3H60113G
Table 5. ATTRIBUTES
Characteristic
Value
ESD Protection Human Body Model
2 kV
Internal Input Default State Pull up/ down Resistor
50 kW
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
MSL1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
130 k
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 6. ABSOLUTE MAXIMUM RATING (Note 2)
Symbol
VDD
Parameter
Rating
Unit
−0.5 to +4.6
V
−0.5 to VDD + 0.5
V
Positive power supply with respect to Ground
VI
Input Voltage with respect to chip ground
TA
Operating Ambient Temperature Range (Industrial Grade)
−40 to +85
°C
TSTG
Storage temperature
−65 to +150
°C
TSOL
Max. Soldering Temperature (10 sec)
265
°C
129
84
°C/W
°C/W
35 to 40
°C/W
125
°C
qJA
Thermal Resistance (Junction−to−ambient)
(Note 3)
qJC
Thermal Resistance (Junction−to−case)
TJ
Junction temperature
0 lfpm
500 lfpm
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). ESD51.7 type board. Back side Copper heat spreader area 100 sq mm, 2 oz
(0.070 mm) copper thickness.
Table 7. RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
Condition
Min
Typ
Max
Unit
2.97
2.25
3.3
2.5
3.63
2.75
V
15
5
pF
pF
50
200
MHz
VDD
Core Power Supply Voltage
3.3 V operation
2.5 V operation
CL
Clock output load capacitance for
LVCMOS/ LVTTL clock
fout < 100 MHz
fout ≥ 100 MHz
fclkin
Crystal Input Frequency
Reference Clock Frequency
CX
XIN / XOUT pin stray Capacitance
CXL
Crystal Load Capacitance
ESR
Crystal ESR
Fundamental Crystal
Single ended clock Input
Note 4
3
3
4.5
pF
10
pF
150
W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. The XIN / XOUT pin stray capacitance needs to be subtracted from crystal load capacitance (along with PCB and trace capacitance) while
selecting appropriate load for the crystal in order to get minimum ppm error.
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NB3H60113G
Table 8. DC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ± 10%, 2.5 V ± 10%; GND = 0 V, TA = −40°C to 85°C, Notes 5, 17)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IDD_3.3 V
Power Supply current for core
Configuration Dependent.
VDD = 3.3 V, TA = 25°C,
XIN/CLKIN = 25 MHz
(XTAL), CLK[0:2] = 100 MHz, 16 mA
output drive
13
mA
IDD_2.5 V
Power Supply current for core
Configuration Dependent.
VDD = 2.5 V, TA = 25°C,
XIN/CLKIN = 25 MHz
(XTAL), CLK[0:2] = 100 MHz, 12 mA
output drive
13
mA
IPD
Power Down Supply Current
PD# is Low to make all outputs OFF
VIH
Input HIGH Voltage
Pin XIN
Pin PD#
20
mA
0.65 VDD
VDD
V
0.85 VDD
VDD
Pin XIN
0
0.35 VDD
Pin PD#
0
VIL
Input LOW Voltage
Zo
Nominal Output Impedance
Configuration Dependent. 12 mA
drive
22
W
Internal Pull up/ Pull down resistor
VDD = 3.3 V
50
kW
RPUP/PD
VDD = 2.5 V
Cprog
Programmable Internal Crystal Load
Capacitance
Input Capacitance
0.15 VDD
80
Configuration Dependent
4.36
Programmable Internal Crystal Load
Capacitance Resolution
Cin
V
20.39
0.05
Pin PD#
4
pF
pF
6
pF
LVCMOS / LVTTL OUTPUTS
VOH
VOL
IDD_LVCMOS
Output HIGH Voltage
0.75*VDD
VDD = 3.3 V
IOH = 16 mA
IOH = 12 mA
IOH = 8 mA
IOH= 4 mA
VDD = 2.5 V
IOH = 12 mA
IOH = 8 mA
IOH = 4 mA
IOH= 2 mA
VDD = 3.3 V
IOL = 16 mA
IOL = 12 mA
IOL = 8 mA
IOL= 4 mA
VDD = 2.5 V
IOL = 12 mA
IOL = 8 mA
IOL = 4 mA
IOL= 2 mA
V
Output LOW Voltage
LVCMOS Output Supply Current
0.25*VDD
Configuration Dependent. TA = 25°C,
CLK[0:2] = fout in PLL bypass mode
Measured on VDD = 3.3 V
fout = 33.33 MHz, CL = 5 pF
fout = 100 MHz, CL = 5 pF
fout = 200 MHz, CL = 5 pF
Measured on VDD = 2.5 V
fout = 33.33 MHz, CL = 5 pF
fout = 100 MHz, CL = 5 pF
fout = 200 MHz, CL = 5 pF
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8
V
mA
3
6.5
12
2.2
5
9.5
NB3H60113G
Table 8. DC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ± 10%, 2.5 V ± 10%; GND = 0 V, TA = −40°C to 85°C, Notes 5, 17)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
HCSL OUTPUTS (Note 6)
VOH_HCSL
Output HIGH Voltage (Note 7)
VOL_HCSL
Output Low Voltage (Note 7)
VDD = 3.3 V, 2.5 V
Crossing Point Voltage (Notes 8 and 9)
VDD = 3.3 V, 2.5 V
Change in Magnitude of Vcross for HCSL Output
(Notes 8 and 10)
VDD = 3.3 V, 2.5 V
VCROSS
Delta Vcross
IDD_HCSL
Measured on VDD = 2.5 V & 3.3 V with
VDD = 3.3 V, 2.5 V
700
mV
0
250
fout = 100 MHz, CL = 2 pF
fout = 200 MHz, CL = 2 pF
350
mV
450
mV
150
mV
22
mA
LVDS OUTPUTS (Notes 8 and 11)
VOD_LVDS
Differential Output Voltage
250
DeltaVOD_LVDS Change in Magnitude of VOD for Complementary Output States
VOS_LVDS
mV
25
mV
1200
Delta VOS_LVDS Change in Magnitude of VOS for Complementary Output States
VOH_LVDS
0
Offset Voltage
450
0
Output HIGH Voltage (Note 12)
1425
mV
25
mV
1600
mV
VDD = 2.5 V
VDD = 3.3 V
VOL_LVDS
Output LOW Voltage (Note 13)
900
1075
mV
14
mA
VDD = 2.5 V
VDD = 3.3 V
IDD_LVDS
fout = 100 MHz
fout = 200 MHz
LVPECL OUTPUTS (Notes 14 and 15)
VOH_LVPECL
VOL_LVPECL
Output HIGH Voltage
VDD−900
1600
2400
VDD−825
mV
VDD = 2.5 V
VDD = 3.3 V
VDD−1450
VDD−2000 VDD−1700 VDD−1500
800
1600
mV
VDD = 2.5 V
VDD = 3.3 V
Output LOW Voltage
VSWING
Peak−to−Peak output voltage swing
550
Vcross
Crossover point voltage (Note 15)
270
800
930
mV
380
VDD = 2.5 V
VDD = 3.3 V
IDD_LVPECL
25
mA
fout = 100 MHz
fout = 200 MHz
CML OUTPUTS (Notes 15 and 16)
VOH_CML
VOL_CML
VOD_CML
Output HIGH Voltage
VDD = 3.3 V
VDD = 2.5 V
VDD −60
3240
2440
VDD = 3.3 V
VDD = 2.5 V
VDD−1100
2200
1400
Output LOW Voltage
Differential Output Voltage Magnitude
640
VDD−10
3290
2490
VDD
3300
2500
VDD−800 VDD − 640
2500
2660
1700
1860
780
1000
mV
mV
mV
VDD = 3.3 V
VDD = 2.5 V
Vcross
Crossover point voltage (Note 15)
VDD−395
VDD = 3.3 V
VDD = 2.5 V
IDD_CML
5.0
mA
fout = 100 MHz
fout = 200 MHz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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NB3H60113G
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Measurement taken with single ended clock outputs terminated with test load capacitance of 5 pF and 15 pF and differential clock terminated
with test load of 2 pF. See Figures 7, 8 and 13. Specification for LVTTL are valid for the VDD 3.3 V only.
6. Measurement taken with outputs terminated with RS = 0 W, RL = 50 W, with test load capacitance of 2 pF. See Figure 8. Guaranteed by
characterization.
7. Measurement taken from single−ended waveform.
8. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx−.
9. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
10. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx−. This is maximum allowed variance in the VCROSS
for any particular system.
11. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 9.
12. VOHmax = VOSmax + 1/2 VODmax.
13. VOLmax = VOSmin − 1/2 VODmax.
14. LVPECL outputs loaded with 50 W to VDD − 2.0 V for proper operation.
15. Output parameters vary 1:1 with VDD.
16. CML outputs loaded with 50 W to VDD for proper operation.
17. Parameter guaranteed by design verification not tested in production.
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NB3H60113G
Table 9. AC ELECTRICAL CHARACTERISTICS
(VDD = 3.3 V ± 10%; 2.5 V ± 10%, GND = 0 V, TA = −40°C to 85°C, Notes 18, 19 and 22)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.008
200
MHz
fout
Single Ended Output Frequency
fMOD
Spread Spectrum Modulation Rate
fclkin ≥ 6.75 MHz
30
130
kHz
SS
Percent Spread Spectrum
(deviation from nominal frequency)
Down Spread
0
−4
%
Center Spread
0
±3
%
Percent Spread Spectrum change
step size
Down Spread step size
0.25
%
Center Spread step size
0.125
%
SSCRED
Spectral Reduction, 3rd harmonic
@SS=−0.5%, fout = 100 MHz, fclkin =
25 MHz crystal, RES BW at 30 kHz, All
Output Types
−10
dB
tPU
Stabilization time from Power−up
VDD = 3.3 V, 2.5 V with Frequency
Modulation
3.0
ms
tPD
Stabilization time from Power Down
Time from falling edge on PD# pin to
tri−stated outputs (Asynchronous)
3.0
ms
Synthesis Error
Configuration Dependent
0
ppm
ps
SSstep
Eppm
SINGLE ENDED OUTPUTS (VDD = 3.3 V ±10%, 2.5 V ±10%; TA = −40°C to 85°C, Notes 18, 19 and 22)
tJITTER−3.3 V
tJITTER−2.5 V
tr / tf 3.3 V
tr / tf 2.5 V
tDC
Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
input , fout = 100 MHz, SS off
(Notes 20, 22 and 24, see Figure 14)
100
Cycle−Cycle Peak Jitter
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off
(Notes 20, 22 and 24, see Figure 14)
100
Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off
(Notes 20, 22 and 24, see Figure 14)
100
Cycle−Cycle Peak Jitter
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off
(Notes 20, 22 and 24, see Figure 14)
100
Rise/Fall Time
Measured between 20% to 80% with
15 pF load, fout = 100 MHz,
VDD = VDDO = 3.3 V,
Max Drive
Min Drive
Rise/Fall Time
Output Clock Duty Cycle
ns
1
2
Measured between 20% to 80% with
15 pF load, fout = 100 MHz,
Max Drive
VDD = VDDO = 2.5 V,
Min Drive
VDD = 3.3 V, 2.5 V;
Duty Cycle of Ref clock is 50%
PLL Clock
Reference Clock
ps
ns
1
2
%
45
40
50
50
55
60
DIFFERENTIAL OUTPUT (CLK1, CLK0) (VDD = 3.3 V, ±10% 2.5 V ±10%; TA = −40°C to 85°C, Notes 18, 22 and 23)
tJITTER−3.3 V
tJITTER−2.5 V
Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off, CLK = OFF
(Notes 21, 22, and 24, see Figure 14)
100
ps
Cycle−Cycle Peak to Peak Jitter
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off, CLK2 = OFF
(Notes 21, 22, and 24, see Figure 14)
100
ps
Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off, CLK = OFF
(Notes 21, 22, and 24, see Figure 14)
100
ps
Cycle−Cycle Peak to Peak Jitter
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off, CLK2 = OFF
(Notes 21, 22, and 24, see Figure 14)
100
ps
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11
NB3H60113G
Table 9. AC ELECTRICAL CHARACTERISTICS
(VDD = 3.3 V ± 10%; 2.5 V ± 10%, GND = 0 V, TA = −40°C to 85°C, Notes 18, 19 and 22)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
175
700
ps
175
700
ps
175
700
ps
175
700
ps
DIFFERENTIAL OUTPUT (CLK1, CLK0) (VDD = 3.3 V, ±10% 2.5 V ±10%; TA = −40°C to 85°C, Notes 18, 22 and 23)
tr 3.3 V
Rise Time
Measured between 20% to 80%
VDD = 3.3 V
HCSL
LVDS
LVPECL
CML
tr 2.5 V
Rise Time
Measured between 20% to 80%
VDD = 2.5 V
HCSL
LVDS
LVPECL
CML
tf 3.3 V
Fall Time
Measured between 20% to 80%
VDD = 3.3 V
HCSL
LVDS
LVPECL
CML
tf 2.5 V
Fall Time
Measured between 20% to 80%
VDD = 2.5 V
HCSL
LVDS
LVPECL
CML
tDC
Output Clock Duty Cycle
VDD = 3.3 V, 2.5 V;
Duty Cycle of Ref clock is 50%
PLL Clock
Reference Clock
%
45
40
50
50
55
60
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
18. Parameter guaranteed by design verification not tested in production.
19. Measurement taken from single ended clock terminated with test load capacitance of 5 pF and 15 pF and differential clock terminated
with test load of 2 pF. See Figures 6, 7 and 12.
20. Measurement taken from single−ended waveform
21. Measurement taken from differential waveform
22. AC performance parameters like jitter change based on the output frequency, spread selection, power supply and loading conditions of
the output. For application specific AC performance parameters, please contact ON Semiconductor.
23. Measured at fout = 100 MHz, No Frequency Modulation, fclkin = 25 MHz fundamental mode crystal and output termination as described
in Parameter Measurement Test Circuits
24. Period jitter Sampled with 10000 cycles, Cycle−cycle jitter sampled with 1000 cycles. Jitter measurement may vary. Actual jitter is
dependent on Input jitter and edge rate, number of active outputs, inputs and output frequencies, supply voltage, temperature, and output
load.
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12
PD#
Reference
Clock
input
or Crystal
PD#
XOUT
XIN/CLKIN
GND
NB3H60113G
VDD
2.5V to 3.3V
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13
Optional
Optional
Optional
Optional
LVPECL
LVDS
HCSL
CML
Open
100
Open
Open
RD
Open
Open
Open
50
Open
RL
Open
RD
VTT=VCC-2.0V
RV
VCC (Receiver)
RV
RC
RC
VCC (Receiver)
Open
Open
2 pF
Open
CL
Open
Differential Clock Termination
CL
CL
Differential Clock
Single Ended Clock
Zo=50 W
RS
Optional
RL
RL
Zo=50 W
Signaling Type
LVCMOS
RS (optional)
RS (optional)
RS (optional)
Zo=50 W
50
Open
Open
Open
RC
Open
Receiver
25. Receiver VCC must be at same supply potential as VDD for differential clock outputs.
26. All resistor values are in ohms.
CLK0
CLK1
CLK2
VCC
Open
Open
Open
50
RV
Open
NB3H60113G
SCHEMATIC FOR OUTPUT TERMINATION
Figure 6. Typical Termination for Single−Ended and Differential Signaling Device Load
NB3H60113G
PARAMETER MEASUREMENT TEST CIRCUITS
CLKx
Hi−Z Probe
CL
LVCMOS/LVTTL
Clock
Measurement
Equipment
Figure 7. LVCMOS/LVTTL Parameter Measurement
CLK1
Hi−Z Probe
2 pF
HCSL
Clock
Measurement
Equipment
Hi−Z Probe
CLK0
2 pF
50 W
50 W
Figure 8. HCSL Parameter Measurement
CLK1
LVDS
Clock
Hi−Z Probe
Measurement
Equipment
100 W
Hi−Z Probe
CLK0
Figure 9. LVDS Parameter Measurement
CLK1
Hi−Z Probe
Measurement
Equipment
LVPECL
Clock
Hi−Z Probe
CLK0
50 W
50 W
VDD − 2 V
Figure 10. LVPECL Parameter Measurement
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14
NB3H60113G
CLK1
Hi−Z Probe
Measurement
Equipment
CML
Clock
Hi−Z Probe
CLK0
50 W
50 W
VDD
Figure 11. CML Parameter Measurement
TIMING MEASUREMENT DEFINITIONS
t2
tDC = 100 * t1 / t2
t1
80% of VDD
50% of VDD
20% of VDD
LVCMOS
Clock Output
GND
tf
tr
Figure 12. LVCMOS Measurement for AC Parameters
t2
tDC = 100 * t1/t2
tPeriod = t2
t1
80%
80%
Vcross = 50% of output swing
20%
tr
20%
tf
Figure 13. Differential Measurement for AC Parameters
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15
DVcross
NB3H60113G
tperiod−jitter
50% of CLK Swing
Clock
Output
tNcycle
t(N+1)cycle
50% of CLK Swing
Clock
Output
tCTC−jitter = t(N+1)cycle − tNcycle (over 1000 cycles)
Figure 14. Period and Cycle−Cycle Jitter Measurement
Tpower-up
Tpower-down
PD#
VIH
VIL
CLK Output
Figure 15. Output Enable/ Disable and Power Down Functions
APPLICATION GUIDELINES
Crystal Input Interface
Figure 16 shows the NB3H60113G device crystal
oscillator interface using a typical parallel resonant
fundamental mode crystal. A parallel crystal with loading
capacitance CL = 18 pF would use C1 = 32 pF and C2 =
32 pF as nominal values, assuming 4 pF of stray capacitance
per line.
C L + (C1 ) Cstray)ń2; C1 + C2
Figure 16. Crystal Interface Loading
The frequency accuracy and duty cycle skew can be
fine−tuned by adjusting the C1 and C2 values. For example,
increasing the C1 and C2 values will reduce the operational
frequency. Note R1 is optional and may be 0 W.
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16
NB3H60113G
Output Interface and Terminations
LVCMOS/ LVTTL Interface
The NB3H60113G consists of a unique Multi Standard
Output Driver to support LVCMOS/LVTTL, LVDS,
LVPECL, CML and HCSL standards. Termination
techniques required for each of these standards are different
to ensure proper functionality. The required termination
changes must be considered and taken care of by the system
designer.
LVCMOS/ LVTTL output swings rail−to−rail up to VDD
supply and can drive up to 15 pF load at higher drive
strengths. The output buffer’s drive is programmable up to
four steps, though the drive current will depend on the step
setting as well as the VDD supply voltage. (See Figure 17
and Table 10). Drive strength must be configured high for
driving higher loads. The slew rate of the clock signal
increases with higher output current drive for the same load.
The software lets the user choose the load drive current value
per LVCMOS/LVTTL output based on the VDD supply
selected.
Table 10. LVCMOS/ LVTTL DRIVE LEVEL SETTINGS
VDD Supply
Load Current Setting 3
Max Load Current
Load Current Setting 2
Load Current Setting 1
Load Current Setting 0
Min Load Current
3.3 V
16 mA
12 mA
8 mA
4 mA
2.5 V
12 mA
8 mA
4 mA
2 mA
the cap load posed by the receiver input pin. Cload = (CL +
Cpin+ Cin)
An optional series resistor Rs can be connected at the
output for impedance matching, to limit the overshoots and
ringings.
The load current consists of the static current component
(varies with drive) and dynamic current component. For any
supply voltage, the dynamic load current range per
LVCMOS output can be approximated by formula –
IDD + f out * C load * VDD
Cload includes the load capacitor connected to the output,
the pin capacitor posed by the output pin (typically 5 pF) and
VDD
Drive Strength
selection
CLKx
Drive Strength
selection
Figure 17. Simplified LVCMOS Output Structure
LVDS Interface
driver consists of a low swing differential with constant
current of 3.5 mA through the differential pair, and
generates switching output voltage across a 100 W
terminating resistor (externally connected or internal to the
receiver). Power dissipation in LVDS standard ((3.5 mA)2 x
100 W = 1.2 mW) is thus much lower than other differential
signalling standards.
Differential signaling like LVDS has inherent advantage
of common mode noise rejection and low noise emission,
and thus a popular choice clock distribution in systems.
TIA/EIA−644 or LVDS is a standard differential,
point−to−point bus topology that supports fast switching
speeds and has benefit of low power consumption. The
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17
NB3H60113G
VDD
A fan−out LVDS buffer (like ON Semiconductor’s
NB6N1xS and NB6L1xS) can be used as an extension to
provide clock signal to multiple LVDS receivers to drive
multiple point−to−point links to receiving node.
VCC (receiver)
R1
CLK1
R1
NB3H60113G
VDD
CLK0
R2
R2
Iss
Figure 20. LVPECL Thevenin Termination
CLK 1
+
RT
100 W
Vout
+
System Supply
Practical R2
(W)
Practical R1 (W)
2.5 V System
62(5%)
240(5%)
3.3 V system
82(5%)
130(5%)
_
CLK 0
Vin
_
Iss
VDD
Figure 18. Simplified LVDS Output Structure with
Termination
CLK1
LVPECL Interface
NB3H60113G
The LVPECL driver is designed to drive a 50 W
transmission line from a constant current differential and a
low impedance emitter follower. On the NB3H60113G, this
differential standard is supported for VDD supply voltage of
2.5 V and above. In the system, the clock receiver must be
referenced at the same supply voltage as VDD for reliable
functionality. The termination to VCC – 2 V (1.3 V for a
3.3 V VDD supply, and 0.5 V for a 2.5 V VDD supply) used
in evaluation boards, is rarely used in system boards as it
adds another power supply on the system board. Thus,
Thevenin’s equivalent circuit (Figure 20) for this
termination or a Y−type termination (Figure 21) is often
used in systems. Termination techniques for LVPECL are
detailed in the application note “Termination of ECL
Devices with EF (Emitter Follower) OUTPUT Structure −
AND8020”.
VDD
CLK0
50 W
RT
Figure 21. LVPECL Y−Termaination
Y−Termination
RT (W)
2.5 V System
50
3.3 V system
18
The termination should be placed as close to the receiver
as possible to avoid unterminated stubs that can cause signal
integrity issues.
VCC– 2V
CLK1
50 W
CML Interface
A CML driver consists of an NMOS open drain constant
current differential driving 16 mA current into a 50 W load
terminated to the supply voltage at the receiver. This
termination resistor can be external or internal to the
receiver and needs to be as close as possible to the receiver.
The termination techniques used for a CML driver are
detailed in application note “Termination and Interface of
ON Semiconductor ECL Devices With CML (Current
Mode Logic) OUTPUT Structure – AND8173”.
50W
50W
CLK0
Isc
Figure 19. Simplified LVPECL Output Structure with
Termination
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18
NB3H60113G
VCC (receiver )
50 W
50 W
CLK 1
CLK 0
Isc = 16mA
Figure 22. Simplified CML Output Structure with Termination
HCSL Termination
optionally used to achieve impedance matching by limiting
overshoot and ringing due to the rapid rise of current from
the output driver. The open source driver has high internal
impedance, thus a series resistor up to 33 W does not affect
the signal integrity. This resistor can be avoided for low VDD
supply of operation, unless impedance matching requires it.
HCSL is a differential signaling standard commonly used
in PCIe systems. The HCSL driver is typical 14.5 mA
switched current open source output that needs a 50 W
termination resistor to ground near the source, and generates
725 mV of signal swing. A series resistor (10 W to 33 W) is
14.5mA
2.6mA
CLK1
CLK0
50 W
50 W
Figure 23. Simplified HCSL Output Structure with Termination
Field Programming Kit and Software
and measurement techniques of Cycle−cycle jitter, period
jitter, TIE jitter and Phase Noise are explained in application
note AND8459/D.
In order to have a good clock signal integrity for minimum
data errors, it is necessary to reduce the signal reflections.
Reflection coefficient can be zero only when the source
impedance equals the load impedance. Reflections are based
on signal transition time (slew rate) and due to impedance
mismatch. Impedance matching with proper termination is
required to reduce the signal reflections. The amplitude of
overshoots is due to the difference in impedance and can be
minimized by adding a series resistor (Rs) near the output
The NB3H60113G can be programmed by the user using
the ‘Clock Cruiser Programmable Clock Kit’. This device
uses the 8L daughter card on the hardware kit. To design a
new clock, ‘Clock Cruiser Software’ is required to be
installed from the ON Semiconductor website. The user
manuals for the hardware kit Clock Cruiser Programmable
Clock Kit and Clock Cruiser Software can be found
following the link www.onsemi.com.
Recommendation for Clock Performance
Clock performance is specified in terms of Jitter in time
the domain and Phase noise in frequency domain. Details
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19
NB3H60113G
PCB Design Recommendation
pin. Greater the difference in impedance, greater is the
amplitude of the overshoots and subsequent ripples. The
ripple frequency is dependant on the signal travel time from
the receiver to the source. Shorter traces results in higher
ripple frequency, as the trace gets longer the travel time
increases, reducing the ripple frequency. The ripple
frequency is independent of signal frequency, and only
depends on the trace length and the propagation delay. For
eg. On an FR4 PCB with approximately 150 ps/ inch of
propagation rate, on a 2 inch trace, the ripple frequency = 1
/ (150 ps * 2 inch * 5) = 666.6 MHz; [5 = number of times
the signal travels, 1 trip to receiver plus 2 additional round
trips]
PCB traces should be terminated when trace length tr/f /
(2* tprate); tr/f = rise/ fall time of signal, tprate =
propagation rate of trace.
ÎÎÏ
For a clean clock signal waveform it is necessary to have
a clean power supply for the device. The device must be
isolated from system power supply noise. A 0.1 mF and a
2.2 mF decoupling capacitor should be mounted on the
component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin and the
ground via should be kept thicker and as short as possible.
All the VDD pins should have decoupling capacitors.
Stacked power and ground planes on the PCB should be
large. Signal traces should be on the top layer with minimum
vias and discontinuities and should not cross the reference
planes. The termination components must be placed near the
source or the receiver. In an optimum layout all components
are on the same side of the board, minimizing vias through
other signal layers.
Ringing
Overshoot
(Positive)
Device Applications
The NB3H60113G is targeted mainly for the Consumer
market segment and can be used as per the examples below.
Clock Generator
Overshoot
(Negative)
Consumer applications like a Set top Box, have multiple
sub−systems and standard interfaces and require multiple
reference clock sources at various locations in the system.
This part can function as a clock generating IC for such
applications generating a reference clock for interfaces like
USB, Ethernet, Audio/Video, ADSL, PCI etc.
ÎÎÏ
Figure 24. Signal Reflection Components
PD#
VDD
Crystal/Clock Control
Output control
Configuration
Memory
Frequency
and SS
XIN/CLKIN
Crystal
XOUT
Output
Divider
PLL Block
Clock Buffer/
Crystal
Oscillator and
AGC
CMOS/
Diff
buffer
CLK0
27MHz
Phase
Detector
Charge
Pump
VCO
Output
Divider
CMOS /
Diff
buffer
Video
CLK1
48MHz
USB
25MHz
Feedback
Divider
Output
Divider
CMOS
buffer
CLK2
25MHz
Ethernet
PLL Bypass Mode
GND
Figure 25. Application as Clock Generator
Buffer and Logic/Level Translator
The device can be simultaneously used as logic translator for
converting the LVCMOS input clock to HCSL, LVDS,
LVPECL, or CML.
For instance this device can be used in applications like an
LCD monitor, for converting the LVCMOS input clock to
LVDS output.
The NB3H60113G is useful as a simple CMOS Buffer in
PLL bypass mode. One or more outputs can use the PLL
Bypass mode to generate the buffered outputs. If the PLL is
configured to use spread spectrum, all outputs using PLL
Bypass feature will not be subjected to the spread spectrum.
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20
NB3H60113G
PD#
VDD
Crystal/Clock Control
Output control
Configuration
Memory
Frequency
and SS
LVCMOS/
LVTTL
Output
Divider
CMOS/
Diff
buffer
Output
Divider
CMOS /
Diff
buffer
CLK1
Output
Divider
CMOS
buffer
CLK2
PLL Block
XIN/CLKIN
Clock Buffer/
Crystal
Oscillator and
AGC
Crystal
XOUT
Phase
Detector
Charge
Pump
VCO
Feedback
Divider
CLK0
LVDS
PLL Bypass Mode
GND
NOTE:
Figure 26. Application as Level Translator
LVCMOS signal level cannot be translated to a higher level of LVCMOS voltage.
EMI Attenuator
clock outputs (not bypass outputs) even if they are at
different frequencies. In Figure 27, CLK0 uses the PLL and
hence is subjected to the spread spectrum modulation while
CLK1 and CLK2 use the PLL Bypass mode and hence are
not subjected to the spread spectrum modulation.
Spread spectrum through frequency modulation
technique enables the reduction of the EMI radiated from the
high frequency clock signals by spreading the spectral
energy to the nearby frequencies. While using frequency
modulation, the same selection is applied to all the PLL
PD#
VDD
Crystal/Clock Control
Output control
Configuration
Memory
Frequency
and SS
Output
Divider
PLL Block
XIN/CLKIN
Clock Buffer/
Crystal
Oscillator and
AGC
Crystal
XOUT
Phase
Detector
Charge
Pump
VCO
Output
Divider
CMOS/
Diff
buffer
CMOS /
Diff
buffer
CLK0
12MHz ± 0.375%
CPU
CLK1
12MHz
USB1
12MHz
Feedback
Divider
Output
Divider
CMOS
buffer
CLK2
12MHz
USB2
PLL Bypass Mode
GND
Figure 27. Application as EMI Attenuator
ORDERING INFORMATION
Device
Case
Package
Shipping†
NB3H60113G00MTR2G
511AT
DFN−8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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21
NB3H60113G
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT−01
ISSUE O
D
PIN ONE
REFERENCE
0.10 C
2X
2X
ALTERNATE TERMINAL
CONSTRUCTIONS
EXPOSED Cu
MOLD CMPD
DETAIL B
A
A1
A3
SIDE VIEW
DIM
A
A1
A3
b
D
E
e
L
L1
L2
ÉÉ
ÉÉ
TOP VIEW
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
DETAIL A
E
0.05 C
8X
L
L1
ÍÍÍ
ÍÍÍ
ÍÍÍ
0.10 C
L
A
B
ALTERNATE
CONSTRUCTIONS
C
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
7X
e/2
7X
1
PACKAGE
OUTLINE
0.78
DETAIL A
e
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
2.00 BSC
0.50 BSC
0.40
0.60
--0.15
0.50
0.70
L
4
L2
2.30
0.88
8
1
5
8X
BOTTOM VIEW
b
0.10 C A
0.05 C
0.50
PITCH
8X
0.30
B
DIMENSIONS: MILLIMETERS
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
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22
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB3H60113G/D