BELLING BL8083CKGTR Pmu with a synchronous 18v 2a buck and a cmos 6v 1.5a ldo Datasheet

BL8083
PMU with a Synchronous 18V 2A Buck and a CMOS 6V 1.5A LDO
DESCRIPTION
FEATURES
The BL8083 is a power management unit (PMU),
with 1 synchronous 18V Buck and 1 CMOS 6V lowdropout regulator that delivers a maximum
current of 2A for Buck’s output and a maximum
current of 1.5A for LDO’s output.
The synchronous buck is a high-efficiency, DC-to-DC
step-down switching regulator, capable of
delivering up to 2A of output current. It is a fully
integrated, high-efficiency synchronous rectified
step-down converter. It operates at high efficiency
over a wide output current load range. It offers
PWM switching control, which allows a high
efficiency over the wider range of the load.
The LDO is a low-dropout regulator that delivers a
maximum current of 1.5A output. Typical dropout
voltage at 1A load current is 0.3V. It has excellent
load and line transient response and good
temperature characteristics, which can assure the
stability of chip and power system. The output
accuracy is set within 2% by trimming.
Typical LDO output voltage: VOUT=3.3V. Other fixed
voltage can be provided in the range of 1.2V~5V
every 0.1V step. It also can be customized on
command. LDO can also work under a wide input
voltage ranging from 2V to 6V. They can provide
foldback short-circuit protection and output
current limit function.
BL8083 is available in lead (Pb)-free DFN2X3-8 (with
exposed pad for heat dissipation) package.
SW 3
LGND 4
9
8
FB
GSYW
LLLL
XX
BS 2
7
EN
6
VI
GND
5
VOUT
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DFN2x3-8
GS: Product Code
YW: Date code (Year & Week)
LLLL: Lot No.
XX: Output Voltage
e.g. 33=3.3V
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BUCK
High Efficiency : Up to 96%
Capable of Delivering 2A
500KHz Frequency Operation
No External Schottky Diode Needed
4.2V to 18V Input Voltage Range
0.8V Reference
Logic Control Shutdown (IQ<1uA)
Slope Compensated Current Mode Control for
Excellent Line and Load Transient Response
Integrated internal compensation
Stable with Low ESR Ceramic Output Capacitors
Over Current Protection with Hiccup-Mode
Thermal Shutdown
Inrush Current Limit and Soft Start
LDO
Max output current is 1.5A
Input voltage range: 2 – 6V
Output voltage range: 1.2V~5V (customized
on command every 0.1V step)
Low Quiescent Current: 100uA at 5V
High PSRR: 70dB range to 1KHz
Low Output Noise: 44uVRMS
Low Dropout: 300mV at 1A load
Low ESR Ceramic Capacitor Compatible
Low temperature coefficient: ±100ppm/C
Excellent line regulation: 0.05%/V
Highly accurate: ±2%
Output current limit
APPLICATIONS
PIN OUT & MARKING
VDD 1
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1
Distributed Power Systems
Digital Set Top Boxes
Flat Panel Television and Monitors
Wireless and DSL Modems
Power source for cellular phones and various
kind of PCSs
Battery Powered equipment
BL8083
TYPICAL APPLICATION
L1 4.7uH
C2 100nF
Vout
C3
BS
VDD
22uF
SW
VDD
VOUT
VOUT
VI
22uF
VI
BL8083
LC9208
C1
EN
R1
EN
C4
FB
GND
4.7uF
LGND
C5
4.7uF
R2
Note: C1 recommended using 22uF ceramic capacitors. If the electrolytic capacitor is used, it is recommended that the
ceramic capacitor in parallel with a capacitance value of 2.2uF or more.
ORDERING INFORMATION
PART No.
PACKAGE
Tape&Reel
BL8083CKGTR□□
DFN2x3-8
3000/Reel
ABSOLUTE MAXIMUM RATING
Parameter
Supply Voltage VDD
Supply Voltage VI
Switch Node Voltage VSW
Boost Voltage VBS
Enable Voltage VEN
All Other Pins
Package Thermal Resistance (jc)
Package Thermal Resistance (ja)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Value
-0.3V to 20V
-0.3V to 8V
-0.3V to (VDD+0.5V)
VSW-0.3V to VSW+5V
-0.3V to VDD
-0.3V to 6V
17C / W
75C / W
-40C to 85C
-65C to 150C
260C
DFN2x3-8
Warning: When the chip is working, VDD PIN can’t be shorted to the other PINs.
RECOMMENDED WORK CONDITIONS
Parameter
Value
Input Voltage Range (VDD)
Input Voltage Range (VI)
Operating Junction Temperature(Tj)
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Max. 18V
Max. 6V
Max. 125C
2
BL8083
ELECTRICAL CHARACTERISTICS
(VDD=12V, VOUT=3.3V, TA=25C, unless otherwise stated)
Parameter
Conditions
Min
Typ
Max
Unit
18
V
V
mA
uA
V
mΩ
mΩ
uA
A
KHz
%
ns
V
V
°C
BUCK
Input Voltage Range (VDD)
UVLO Threshold
Supply Current in Operation
Supply Current in Shutdown
Regulated Feedback Voltage
High-side Switch On Resistance
Low-side Switch On Resistance
High-side Switch Leakage Current
Upper Switch Current Limit
Oscillation Frequency
Maximum Duty Cycle
Minimum On Time
EN Input Voltage “H”
EN Input Voltage “L”
Thermal Shutdown
4.2
4
0.8
VEN = 2.0V, VFB = 1.1V
VEN = 0V or VEN = GND
4.2V≤VDD ≤18V
0.784
VEN = 0V, VSW = 0V
Minimum Duty Cycle
VFB = 0.7V
0.8
150
70
0
3.8
500
92
100
1.8
1
0.816
10
VDD
0.8
160
LDO
Input Voltage Range (VI)
VOUT>1.5
VOUT≤1.5
Output Voltage
1mA≤IOUT≤10mA
Maximum Output Current
Dropout Voltage
Line Regulation
VI-VOUT=1V
VOUT =3.3V, IOUT=1A
IOUT=10mA, 4V≤VI≤6V
VI=Set VOUT+1V
1mA≤IOUT≤1.5A
VI=Set VOUT+1V, VOUT Floating
F=100Hz, Ripple=0.5Vp-p,
VI=Set VOUT+1V
BW=10Hz~100KHz
Load Regulation
Supply Current
Ripple Rejection
Output Noise
VOUT
VOUT X0.98
VOUT -0.03
1.5
VOUT
6
VOUT X1.02
VOUT +0.03
V
V
300
0.05
500
0.2
A
mV
%/V
30
60
mV
100
150
uA
70
dB
44
uVrms
PIN DESCRIPTION
NAME
PIN #
DESCRIPTION
VDD
1
BS
2
SW
LGND
VOUT
VI
EN
3
4
5
6
7
FB
8
GND
9
Power supply Pin for BUCK
Boostrap. A capacitor connected between SW and BS pins is required to form a floating
supply across the high-side switch driver.
Switching Pin
LDO Ground
Output Voltage of LDO
Input Voltage of LDO
Enable Pin for BUCK
Adjustable version feedback input. Connect FB to the center point of the external resistor
divider.
GND (Thermal PAD)
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3
BL8083
BLOCK DIAGRAM
VDD
VI
4.7uF
22uF
EN
VI
VDD
BS
Ref
100nF
SW
VOUT
3.3V
Driver
Control
Logic
4.7uF
Vout
4.7uH
0~2A
R1
22uF
FB
R2
GND
LGND
ELECTRICAL PERFORMANCE
Tested under, L=4.7uH, TA=25C, unless otherwise specified
BUCK
Efficiency vs. Iout
Efficiency vs. Iout
(Vout=1.2V)
(Vout=3.3V)
90%
90%
80%
80%
70%
70%
Efficiency(%)
100%
Efficiency(%)
100%
60%
50%
40%
30%
60%
50%
40%
VDD=5V
VDD=6V
VDD=12V
VDD=18V
30%
20%
20%
VDD=5V
VDD=12V
10%
0%
0.0
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0.5
1.0
Iout (A)
1.5
10%
0%
2.0
0.0
4
0.5
1.0
Iout (A)
1.5
2.0
BL8083
Efficiency vs. Iout
Vout vs. Iout
(Vout=5.0V)
(Vout=1.2V)
100%
1.30
90%
1.25
80%
1.20
1.15
60%
Vout (V)
Efficiency(%)
70%
50%
40%
30%
1.10
1.05
1.00
VDD=6V
VDD=12V
VDD=18V
20%
10%
0%
0.0
0.5
1.0
Iout (A)
1.5
VDD=5V
VDD=12V
0.95
0.90
0.0
2.0
0.5
Vout vs. Iout
(Vout=3.3V)
3.40
3.30
Vout (V)
Vout (V)
3.35
3.25
3.20
3.15
VDD=5V
VDD=6V
VDD=12V
VDD=18V
3.10
3.05
3.00
1.0
2.0
(Vout=5.0V)
3.45
0.5
1.5
Vout vs. Iout
3.50
0.0
1.0
Iout (A)
1.5
2.0
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
VDD=6V
VDD=12V
VDD=18V
0.0
Iout (A)
0.5
1.0
1.5
Iout (A)
Load Transient
Load Transient
VDD=12V, Vout=3.3V, Iout=0.01~2A
Ch2—Vout, Ch4—IL
VDD=12V, Vout=3.3V, Iout=0.5~1A
Ch2—Vout, Ch4—IL
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5
2.0
BL8083
LDO
Load Regulation
Load Regulation
(VOUT=1.2V)
3.6
1.4
3.4
1.2
3.2
1.0
VOUT(V)
VOUT(V)
(VOUT=3.3V)
3.0
2.8
0.8
0.6
2.6
2.4
2.2
VI=5.0V
VI=3.0V
VI=2.0V
VI=1.8V
0.4
VI=5.0V
VI=4.3V
VI=4.0V
0.2
2.0
0.0
0.0
0.5
1.0
1.5
0.0
0.5
1.0
IOUT(A)
1.5
IOUT(A)
Iq
Line Regulation
3.5
250
3.0
200
Iq(uA)
VOUT(V)
2.5
2.0
1.5
150
100
1.0
50
0.5
VOUT=3.3V
VOUT=1.2V
VOUT=1.2V
0
0.0
0
1
2
3
VI(V)
4
5
VOUT=3.3V
0
6
2
3
VI(V)
4
5
6
VOUT vs. Temperature
Dropout Voltage
3.4
900
VOUT=3.3V
800
VOUT=1.2V
700
3.4
600
VOUT(V)
Dropout(mV)
1
500
400
3.3
300
3.3
200
100
0
0
0.5
1
3.2
1.5
(50)
IOUT(A)
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6
0
50
100
Temperature(℃)
150
BL8083
Load Transient Response (VI=5V,VOUT=3.3V)
C4=1uF,C5=1uf,IOUT=1mA-100mA
Line Transient Response(VOUT=3.3V)
C4=1uF,C5=1uf,IOUT=10mA,VI=4.3V-5.3V
DETAILED DESCRIPTION
higher than REF, REF regains control. The SS time is
internally fixed to 1ms.
Internal Regulator
The BL8083 is a current mode step down DC/DC
converter that provides excellent transient
response with no extra external compensation
components. This device contains an internal, low
resistance, high voltage power MOSFET, and
operates at a high 500K operating frequency to
ensure a compact, high efficiency design with
excellent AC and DC performance.
Over-Current-Protection
The BL8083 has over current limit when the output
current peak value exceeds the set current limit
threshold. Chip output short circuit to the ground,
will not be burned.
Startup and Shutdown
If VDD and EN are higher than their appropriate
thresholds, the chip starts. The reference block
starts first, generating stable reference voltage and
currents, and then the internal regulator is enabled.
The regulator provides stable supply for the
remaining circuitries. Three events can shut down
the chip: EN low, VDD low and thermal shutdown.
In the shutdown procedure, the signaling path is
first blocked to avoid any fault triggering. The
COMP voltage and the internal supply rail are then
pulled down. The floating driver is not subject to
this shutdown command.
Error Amplifier
The error amplifier compares the FB pin voltage
with the internal FB reference (VFB) and outputs a
current proportional to the difference between the
two. This output current is then used to charge or
discharge the internal compensation network to
form the COMP voltage, which is used to control
the power MOSFET current. The optimized internal
compensation network minimizes the external
component counts and simplifies the control loop
design.
Internal Soft-Start
APPLICATIONS INFORMATION
The soft-start is implemented to prevent the
converter output voltage from overshooting during
startup. When the chip starts, the internal circuitry
generates a soft-start voltage (SS) ramping up from
0V to 0.8V. When it is lower than the internal
reference (REF), SS overrides REF so the error
amplifier uses SS as the reference. When SS is
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Setting Buck Vout Voltages
The external resistor divider is used to set the Buck
Vout voltage (see Typical Application on page 1).
The feedback resistor R1 can also set the feedback
loop bandwidth with the internal compensation
capacitor. Choose R1 to be around 300KΩ for
optimal transient response. R2 is then given by:
7
BL8083
PC BOARD LAYOUT
PCB layout is very important to achieve stable
operation. For best results, use the following
guidelines and figures as reference.
Selecting the Inductor
A 4.7μH to 22μH inductor with a DC current rating
of at least 25% percent higher than the maximum
load current is recommended for most applications.
For highest efficiency, the inductor DC resistance
should be less than 15mΩ.
Selecting the Capacitor
The input and output capacitors are required to
maintain the DC output voltage. Ceramic, tantalum,
or low ESR electrolytic capacitors are recommended.
Low ESR capacitors are preferred to keep the
output voltage ripple low.
THERMAL CONSIDERATIONS
Thermal consideration has to be taken into account
to ensure proper function of the device. Power
dissipation of BL8083 can be calculated as:
PT: Total Power Dissipation, PL: LDO Power
Dissipation, PB: BUCK Power Dissipation
For proper function and safe operation of the
device, total power dissipation is recommended to
be limited within 2W. Due to the overall power
consumption and heat of the chip, the individual
pathway may not reach the maximum current due
to temperature protection.
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8
1) Keep the connection between the input
ground and GND pin as short and wide as
possible.
2) Keep the connection between the input
capacitor and VIN pin as short and wide as
possible.
3) Use short and direct feedback connections.
Place the feedback resistors and compensation
components as close to the chip as possible.
4) Route SW away from sensitive analog areas
such as FB and LGND.
BL8083
PACKAGE OUTLINE
Package
DFN2x3-8
Devices per reel
Package specification：
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9
3000
Unit
mm