IRF C3216X5R1E106M 6a highly intergrated suplrbuck Datasheet

PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
-1-
FEATURES
IR3898
DESCRIPTION
The IR3898 SupIRBuckTM is an easy-to-use, fully
integrated and highly efficient DC/DC regulator.
The onboard PWM controller and MOSFETs make
IR3898 a space-efficient solution, providing accurate
power delivery.
• Single 5V to 21V application
• Wide Input Voltage Range from 1.0V to 21V with
external Vcc
• Output Voltage Range: 0.5V to 0.86* Vin
• Enhanced Line/Load Regulation with Feed-Forward
IR3898 is a versatile regulator which offers
programmable switching frequency and the fixed
internal current limit while operates in wide input and
output voltage range.
• Programmable Switching Frequency up to 1.5MHz
• Internal Digital Soft-Start/Soft-Stop
• Enable input with Voltage Monitoring Capability
The switching frequency is programmable from 300kHz
to 1.5MHz for an optimum solution.
• Thermally Compensated Current Limit with robust
hiccup mode over current protection
• Smart Internal LDO to improve light load and full load
efficiency
It also features important protection functions, such as
Pre-Bias startup, thermally compensated current limit,
over voltage protection and thermal shutdown to give
required system level security in the event of fault
conditions.
• External Synchronization with Smooth Clocking
• Enhanced Pre-Bias Start-Up
• Precision Reference Voltage (0.5V+/-0.5%) with
margining capability
APPLICATIONS
• Vp for Tracking Applications (Source/Sink Capability
+/-6A)
• Netcom Applications
• Integrated MOSFET drivers and Bootstrap Diode
• Embedded Telecom Systems
• Thermal Shut Down
• Server Applications
• Programmable Power Good Output with tracking
capability
• Storage Applications
• Monotonic Start-Up
• Distributed Point of Load Power Architectures
o
o
• Operating temp: -40 C < Tj < 125 C
• Small Size: 4mm x 5mm PQFN
• Lead-free, Halogen-free and RoHS Compliant
BASIC APPLICATION
98
96
6.8V <Vin<21V
94
Vref S_Ctrl Vin PVin Boot
Vcc/
LDO_out
SW
Vo
PGood
90
88
86
84
PGood
Vp
Efficiency (%)
92
IR3898
Vp
Rt/Sync
Enable
Gnd
Vsns
*
*
Fb
82
12Vin,Internal bias,Frequency 600KHz
80
78
Comp
PGnd
0.6
1.2
1.8
2.4
3
3.6
4.2
Load Current (A)
* optional
Figure 1: IR3898 Basic Application Circuit
1
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
1.2Vout
3.3Vout
Figure 2:IR3898 Efficiency
4.8
5.4
6
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
-2-
ORDERING INFORMATION
IR3898 ―       
Package
M
Tape & Reel Qty
750
Part Number
IR3898MTR1PBF
M
4000
IR3898MTRPBF
PBF – Lead Free
TR/TR1 – Tape and Reel
M – Package Type
PIN DIAGRAM
4mm x 5mm POWER QFN
TOP VIEW
Fb
Vref Comp Gnd Rt/Sync S_Ctrl PGood
θ JA = 32o C / W
θ J - PCB = 2o C / W
2
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
IR3898
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
-3-
IR3898
BLOCK DIAGRAM
Vin
Vcc/ LDO_out
VLDO_Ref
LDO
Gnd
UVcc
UVcc
+
VCC
TSD
POR
FAULT
CONTROL
OV
DCM
Comp
POR
VREF
Vref
0.5V
Boot
THERMAL
SHUT DOWN
OC
PVin
FAULT
+
HDrv
+ E/A
+
-
Vp
0.15V
HDin
FB
Fb
GATE
DRIVE
LOGIC
Intl_SS
S_Ctrl
SOFT
START
Vin
FAULT
Rff
FAULT
SW
VCC
LDrv
LDin
SSOK
CONTROL
LOGIC
VREF
POR
Vp
Enable
UVEN
UVcc
OV
PGnd
DCM
UVEN
POR
POR
OC
VREF
OV
ZERO CROSSING
COMPARATOR
OVER CURRENT
PROTECTION
OVER VOLTAGE
PROTECTION
Vsns
Rt/Sync
PGood
Figure 3: IR3898 Simplified Block Diagram
3
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
-4-
IR3898
PIN DESCRIPTIONS
PIN #
PIN NAME
1
Fb
PIN DESCRIPTION
Inverting input to the error amplifier. This pin is connected to the output of the
regulator via resistor divider to set the output voltage and provide feedback to
the error amplifier.
2
Vref
Internal reference voltage, it can be used for margining operation also. In normal
and sequencing mode operation, Vref is left floating. A 1nF ceramic capacitor is
recommended between this pin and Gnd. In tracking mode operation, Vref
should be tied to Gnd.
3
Comp
Output of error amplifier. An external resistor and capacitor network is typically
connected from this pin to Fb to provide loop compensation.
4
Gnd
Signal ground for internal reference and control circuitry.
5
Rt/Sync
Multi-function pin to set switching frequency. Use an external resistor from this
pin to Gnd to set the free-running switching frequency. Or use an external clock
signal to connect to this pin through a diode, the device’s switching frequency is
synchronized with the external clock.
6
S_Ctrl
Soft start/stop control. A high logic input enables the device to go into the
internal soft start; a low logic input enables the output soft discharged. Pull this
pin high if this function is not used.
7
PGood
Power Good status pin. Output is open drain. Connect a pull up resistor (49.9K)
from this pin to the voltage lower than or equal to the Vcc.
8
Vsns
Sense pin for over-voltage protection and PGood. It is optional to tie this pin to
FB pin directly instead of using a resistor divider from Vout.
9
Vin
Input voltage for Internal LDO. A 1.0µF capacitor should be connected between
this pin and PGnd. If external supply is connected to Vcc/LDO_out pin, this pin
should be shorted to Vcc/LDO_out pin.
10
Vcc/LDO_Out
Input Bias for external Vcc Voltage/ output of internal LDO. Place a minimum
2.2µF cap from this pin to PGnd.
11
PGnd
Power Ground. This pin serves as a separated ground for the MOSFET drivers
and should be connected to the system’s power ground plane.
12
SW
Switch node. This pin is connected to the output inductor.
13
PVin
Input voltage for power stage.
14
Boot
Supply voltage for high side driver, a 100nF capacitor should be connected
between this pin and SW pin.
15
Enable
Enable pin to turn on and off the device, if this pin is connected to PVin pin
through a resistor divider, input voltage UVLO can be implemented.
16
Vp
Input to error amplifier for tracking purposes. In the normal operation, it is left
floating and no external capacitor is required. In the sequencing or the tracking
mode operation, an external signal can be applied as the reference.
17
Gnd
Signal ground for internal reference and control circuitry.
4
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
-5-
IR3898
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied.
PVin, Vin
-0.3V to 25V
Vcc/LDO_Out
-0.3V to 8V (Note 2)
Boot
-0.3V to 33V
SW
-0.3V to 25V (DC), -4V to 25V (AC, 100ns)
Boot to SW
-0.3V to VCC + 0.3V (Note 1)
S_Ctrl, PGood
-0.3V to VCC + 0.3V (Note 1)
Other Input/Output Pins
-0.3V to +3.9V
PGnd to Gnd
-0.3V to +0.3V
Storage Temperature Range
-55°C to 150°C
Junction Temperature Range
-40°C to 150°C (Note 2)
ESD Classification (HBM JESD22-A114)
2kV
Moisture Sensitivity Level
JEDEC Level 2@260°C
Note 1: Must not exceed 8V
Note 2: Vcc must not exceed 7.5V for Junction Temperature between -10°C and -40°C
5
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
-6-
IR3898
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
SYMBOL
MIN
UNITS
MAX
Input Voltage Range*
PVin
1.0
21
Input Voltage Range**
Vin
6.8
21
Supply Voltage Range***
VCC
4.5
7.5
Supply Voltage Range
Boot to SW
4.5
7.5
Output Voltage Range
VO
0.5
0.86xVin
Output Current Range
IO
0
±6
A
Switching Frequency
FS
300
1500
kHz
Operating Junction Temperature
TJ
-40
125
°C
V
*Maximum SW node voltage should not exceed 25V.
**For internally biased single rail operation.
***Vcc/LDO_Out can be connected to an external regulated supply. If so, the Vin pin should be connected to Vcc/LDO_Out pin.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specifications apply over, 6.8V < Vin = PVin < 21V, Vref = 0.5V in 0°C < TJ < 125°C.
Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
PLOSS
17.5
22.5
11.4
14.8
260
470
mV
1
µA
30
ns
100
µA
Power Stage
Top Switch
Rds(on)_Top
Vin = 12V, VO = 1.2V, IO = 6A,
Fs = 600kHz, L = 1uH,
Vcc = 6.4V, Note 4
VBoot-Vsw= 6.4V,IO= 6A,Tj=25°C
Bottom Switch
Rds(on)_Bot
Vcc = 6.4V, IO = 6A, Tj=25°C
Power Losses
Bootstrap Diode Forward Voltage
I(Boot) = 10mA
SW Leakage Current
ISW
Dead Band Time
Tdb
SW = 0V, Enable = 0V
SW = 0V, Enable = high,
Vp = 0V
Note 4
Iin(Standby)
EN = Low, No Switching
Iin(Dyn)
EN = High, Fs = 600kHz,
Vin = PVin = 21V
0.85
180
5
10
W
mΩ
Supply Current
VIN Supply Current (standby)
VIN Supply Current (dynamic)
11
15
mA
Vcc/ LDO_Out
Vcc
Output Voltage
LDO dropout Voltage
Vcc_drop
Short Circuit Current
Ishort
6
Vin(min) = 6.8V, Icc = 0-30mA,
Cload = 2.2uF, DCM = 0
6.0
6.4
6.7
Vin(min) = 6.8V, Icc = 0-30mA,
Cload = 2.2uF, DCM = 1
4.0
4.4
4.8
V
Icc=30mA,Cload=2.2uF
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
0.7
70
V
mA
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
-7PARAMETER
SYMBOL
CONDITIONS
Zero-crossing Comparator Delay
Tdly_zc
Note 4
Zero-crossing Comparator Offset
Vos_zc
Note 4
MIN
IR3898
TYP
MAX
256/Fs
-4
0
UNIT
s
4
mV
Oscillator
Rt Voltage
Vrt
Frequency Range
Fs
Ramp Amplitude
Vramp
1.0
V
Rt = 80.6K
270
300
330
Rt = 39.2K
540
600
660
Rt = 15.0K
1350
1500
1650
Vin = 7.0V, Vin slew rate max =
1V/µs, Note 4
1.05
Vin = 12V, Vin slew rate max =
1V/µs, Note 4
1.80
Vin = 16V, Vin slew rate max =
1V/µs, Note 4
2.39
Vin =Vcc=5V, For external Vcc
operation, Note 4
0.75
0.16
Ramp Offset
Ramp(os)
Note 4
Min Pulse Width
Tmin(ctrl)
Note 4
Max Duty Cycle
Dmax
Fixed Off Time
Toff
Fs = 300kHz, PVin = Vin = 12V
Vp-p
V
60
86
Note 4
Fsync
270
Sync Pulse Duration
Tsync
100
Sync Level Threshold
High
3
ns
%
200
Sync Frequency Range
kHz
250
ns
1650
kHz
200
Low
ns
0.6
V
Error Amplifier
Input Offset Voltage
Vos_Vref
Vos_Vp
VFb – Vref, Vref = 0.5V
-1.5
+1.5
VFb – Vp, Vp = 0.5V
-1.5
+1.5
%
Input Bias Current
IFb(E/A)
-1
+1
Input Bias Current
IVp(E/A)
0
+4
Sink Current
Isink(E/A)
0.4
0.85
1.2
mA
Isource(E/A)
4
7.5
11
mA
Source Current
Slew Rate
Gain-Bandwidth Product
DC Gain
µA
SR
Note 4
7
12
20
V/µs
GBWP
Note 4
20
30
40
MHz
Gain
Note 4
100
110
120
dB
1.7
2.0
2.3
V
100
mV
1.2
V
Maximum output Voltage
Vmax(E/A)
Minimum output Voltage
Vmin(E/A)
Common Mode input Voltage
0
Reference Voltage
Feedback Voltage
Accuracy
Vfb
Vref and Vp pin floating
0°C < Tj < +70°C
7
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
0.5
-0.5
V
+0.5
%
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
-8PARAMETER
SYMBOL
CONDITIONS
-40°C < Tj < +125°C
MIN
IR3898
TYP
MAX
UNIT
-1.0
+1.0
%
0.4
1.2
V
Vref Margining Voltage
Vref_marg
Sink Current
Isink_Vref
Vref = 0.6V
12.7
16.0
19.3
Source Current
Isrc_Vref
Vref = 0.4V
12.7
16.0
19.3
Vref Comparator Threshold
Vref_disable
Vref pin connected externally
0.15
Vref_enable
0.4
Soft Start Ramp Rate
Ramp(SS_start)
0.16
0.2
0.24
Soft Stop Ramp Rate
Ramp(SS_stop)
-0.24
-0.2
-0.16
High
2.4
µA
V
Soft Start/Stop
S_Ctrl Threshold
Low
0.6
mV/µs
V
Power Good
PGood Turn on Threshold
PGood Lower Turn off Threshold
VPG(on)
VPG(lower)
Vsns Rising, 0.4V < Vref < 1.2V
85
90
95
% Vref
Vsns Rising, Vref < 0.1V
85
90
95
% Vp
Vsns Falling, 0.4V < Vref < 1.2V
80
85
90
% Vref
Vsns Falling, Vref < 0.1V
80
85
90
% Vp
PGood Turn on Delay
VPG(on)_Dly
Vsns Rising,see VPG(on)
PGood Upper Turn off Threshold
VPG(upper)
Vsns Rising, 0.4V < Vref < 1.2V
115
120
125
% Vref
Vsns Rising, Vref < 0.1V
115
120
125
% Vp
1
2
3.5
µs
0.5
V
PGood Comparator Delay
VPG(comp)_
Dly
Vsns < VPG(lower) or
Vsns > VPG(upper)
PGood Voltage Low
PG(voltage)
IPgood = -5mA
1.28
Tracker Comparator Upper
Threshold
VPG(tracker_
upper)
Vp Rising, Vref < 0.1V
0.4
Tracker Comparator Lower
Threshold
VPG(tracker_
lower)
Vp Falling, Vref < 0.1V
0.3
Tracker Comparator Delay
Tdelay(tracker)
Vp Rising, Vref < 0.1V,see
VPG(tracker_upper)
1.28
ms
V
ms
Under-Voltage Lockout
Vcc-Start Threshold
VCC_UVLO_Start
Vcc Rising Trip Level
4.0
4.2
4.4
Vcc-Stop Threshold
VCC_UVLO_Stop
Vcc Falling Trip Level
3.7
3.9
4.1
V
Enable-Start-Threshold
Enable_UVLO_Start
Supply ramping up
1.14
1.2
1.26
Enable-Stop-Threshold
Enable_UVLO_Stop
Supply ramping down
0.95
1
1.05
Enable Leakage Current
Ien
Enable = 3.3V
V
1
µA
Over-Voltage Protection
OVP Trip Threshold
8
OVP_Vth
Vsns Rising, 0.45V < Vref < 1.2V
115
120
125
% Vref
Vsns Rising, Vref < 0.1V
115
120
125
% Vp
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
-9PARAMETER
SYMBOL
OVP Comparator Delay
OVP_Tdly
CONDITIONS
IR3898
MIN
TYP
MAX
UNIT
1
2
3.5
µs
7.5
9.0
10.5
A
Over-Current Protection
Current Limit
ILIMIT
Hiccup Blanking Time
Tj = 25°C, Vcc = 6.4V
Tblk_Hiccup
Note 4
20.48
Ttsd
Note 4
145
Ttsd_hys
Note 4
20
ms
Over-Temperature Protection
Thermal Shutdown Threshold
Hysteresis
Note 3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
Note 4: Guaranteed by design but not tested in production.
9
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
°C
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 10 -
IR3898
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, Vcc = Internal LDO (4.4V/6.4V), Io = 0A-6A, Fs = 600 kHz, Room Temperature, No Air Flow. Note that the
efficiency and power loss curves include the losses of IR3898, the inductor losses and the losses of the input and output
capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (µH)
0.82
SPM6550T-R82M (TDK)
P/N
DCR (mΩ)
4.2
1.2
1.0
SPM6550T-1R0M (TDK)
4.7
1.8
1.0
SPM6550T-1R0M (TDK)
4.7
3.3
2.2
7443340220(Wurth Elektronik)
4.4
5
2.2
7443340220(Wurth Elektronik)
4.4
98
96
94
Efficiency (%)
92
90
88
86
84
82
80
78
0.6
1.2
1.8
2.4
3
3.6
4.2
4.8
5.4
6
4.8
5.4
6
Load Current (A)
1.0V
1.2V
1.8V
3.3V
5.0V
1.5
Power Dissipation(W)
1.3
1.1
0.9
0.7
0.5
0.3
0.1
0.6
1.2
1.8
2.4
3
3.6
4.2
Load Current (A)
1.0V
10
1.2V
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
1.8V
3.3V
5.0V
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 11 -
IR3898
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, Vcc = External 5V, Io = 0A-6A, Fs = 600 kHz, Room Temperature, No Air Flow. Note that the efficiency and power
loss curves include the losses of IR3898, the inductor losses and the losses of the input and output capacitors. The table
below shows the inductors used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (µH)
0.82
SPM6550T-R82M (TDK)
P/N
DCR (mΩ)
4.2
1.2
1.0
SPM6550T-1R0M (TDK)
4.7
1.8
1.0
SPM6550T-1R0M (TDK)
4.7
3.3
2.2
7443340220(Wurth Elektronik)
4.4
5
2.2
7443340220(Wurth Elektronik)
4.4
97
95
Efficiency (%)
93
91
89
87
85
83
0.6
1.2
1.8
2.4
3
3.6
4.2
4.8
5.4
6
4.8
5.4
6
Load Current (A)
1.0V
1.2V
1.8V
3.3V
5.0V
1.7
1.5
Power Dissiation(W)
1.3
1.1
0.9
0.7
0.5
0.3
0.1
0.6
1.2
1.8
2.4
3
3.6
4.2
Load Current (A)
1.0V
11
1.2V
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
1.8V
3.3V
5.0V
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 12 -
IR3898
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 5.0V, Vcc = 5.0V, Io = 0A-6A, Fs = 600 kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss
curves include the losses of IR3898, the inductor losses and the losses of the input and output capacitors. The table below
shows the inductors used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (µH)
0.68
PCMB065T- R68MS (Cyntec)
P/N
DCR (mΩ)
3.9
1.2
0.82
SPM6550T-R82M(TDK)
4.2
1.8
0.82
SPM6550T-R82M(TDK)
4.7
3.3
1.0
SPM6550T-1R0M(TDK)
4.7
97
95
Efficiency (%)
93
91
89
87
85
83
0.6
1.2
1.8
2.4
3
3.6
4.2
4.8
5.4
6
4.8
5.4
6
Load Current (A)
1.0V
1.2V
1.8V
3
3.6
3.3V
1.4
Power Dissipation(W)
1.2
1
0.8
0.6
0.4
0.2
0
0.6
1.2
1.8
2.4
4.2
Load Current (A)
1.0V
12
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
1.2V
1.8V
3.3V
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 13 -
IR3898
THERMAL DERATING CURVES
Measurement is done on IRDC3898 Evaluation board, a 4-layer board with 2 oz Copper, FR4 material, size 2.23"x2"
PVin = 12V, Vout=1.2V, Vcc = Internal LDO (6.4V), Fs = 600 kHz
7.5
7.25
Iout(A)
7
6.75
6.5
6.25
Lout-1uH,4.7mΩ(TDK SPM6550T-1R0)
6
25
30
35
40
45
50
55
60
65
70
75
80
85
TAmb
0 LFM
200 LFM
PVin = 12V, Vout=3.3V, Vcc = Internal LDO (6.4V), Fs = 600 kHz
7.25
7
Iout(A)
6.75
6.5
6.25
6
5.75
Lout-1.5uH,6.7mΩ(Cyntec PCMB065T-1R5MS)
5.5
25
30
35
40
45
50
55
60
65
70
75
80
85
TAmb
0 LFM
200 LFM
Note: International Rectifier Corporation specifies current rating of SupIRBuck devices conservatively. The continuous current
load capability might be higher than the rating of the device if input voltage is 12V typical and switching frequency is below
750 kHz. The above derating curves are generated at 12V input, 600kHz with 0-200LFM air flow and ambient temperature up
to 85°C.Detailed thermal derating information can be found in the Application Note AN-1174 “Thermal Derating of DC DC
Convertors using IR3899/98/97”. However, the maximum current is limited by the internal current limit and designers need to
consider enough guard bands between load current and minimum current limit to guarantee that the device does not trip at
steady state condition.
13
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 14 -
RDSON OF MOSFETS OVER TEMPERATURE AT Vcc=6.4V
RDSON OF MOSFETS OVER TEMPERATURE AT Vcc=5.0V
14
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
IR3898
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 15 -
TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
15
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
IR3898
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 16 -
IR3898
TYPICAL OPERATING CHARACTERISTICS (-40°C to +125°C)
Note: See Over Current Protection section
16
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
Note: See Over Current Protection section
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 17 -
THEORY OF OPERATION
DESCRIPTION
The IR3898 uses a PWM voltage mode control scheme with
external compensation to provide good noise immunity
and maximum flexibility in selecting inductor values and
capacitor types.
The switching frequency is programmable from 300kHz
to 1.5MHz and provides the capability of optimizing the
design in terms of size and performance.
IR3898 provides precisely regulated output voltage
programmed via two external resistors from 0.5V to
0.86*Vin.
The IR3898 operates with an internal bias supply (LDO)
which is connected to the Vcc/LDO_out pin. This allows
operation with single supply. The bias voltage is variable
according to load condition. If the output load current is
less than half of the peak-to-peak inductor current, a lower
bias voltage, 4.4V, is used as the internal gate drive
voltage; otherwise, a higher voltage, 6.4V, is used.
This feature helps the converter to reduce power losses.
The device can also be operated with an external supply
from 4.5 to 7.5V, allowing an extended operating input
voltage (PVin) range from 1.0V to 16V. For using the
internal LDO supply, the Vin pin should be connected to
PVin pin. If an external supply is used, it should be
connected to Vcc/LDO_Out pin and the Vin pin should be
shorted to Vcc/LDO_Out pin.
The device utilizes the on-resistance of the low side
MOSFET (sync FET) for over current protection. This
method enhances the converter’s efficiency and reduces
cost by eliminating the need for external current sense
resistor.
IR3898
The POR (Power On Ready) signal is generated when all
these signals reach the valid logic level (see system block
diagram). When the POR is asserted the soft start
sequence starts (see soft start section).
ENABLE
The Enable features another level of flexibility for start up.
The Enable has precise threshold which is internally
monitored by Under-Voltage Lockout (UVLO) circuit.
Therefore, the IR3898 will turn on only when the voltage
at the Enable pin exceeds this threshold, typically, 1.2V.
If the input to the Enable pin is derived from the bus
voltage by a suitably programmed resistive divider, it can
be ensured that the IR3898 does not turn on until the bus
voltage reaches the desired level (Fig. 4). Only after the bus
voltage reaches or exceeds this level and voltage at the
Enable pin exceeds its threshold, IR3898 will be enabled.
Therefore, in addition to being a logic input pin to enable
the IR3898, the Enable feature, with its precise threshold,
also allows the user to implement an Under-Voltage
Lockout for the bus voltage (PVin). This is desirable
particularly for high output voltage applications, where we
might want the IR3898 to be disabled at least until PVIN
exceeds the desired output voltage level.
Pvin (12V)
10. 2 V
Vcc
Enable Threshold = 1.2V
Enable
Intl_SS
IR3898 includes two low Rds(on) MOSFETs using IR’s HEXFET
technology. These are specifically designed for high
efficiency applications.
UNDER-VOLTAGE LOCKOUT AND POR
The under-voltage lockout circuit monitors the voltage of
Vcc/LDO_Out pin and the Enable input. It assures that the
MOSFET driver outputs remain in the off state whenever
either of these two signals drop below the set thresholds.
Normal operation resumes once Vcc/LDO_Out and Enable
rise above their thresholds.
17
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
Figure 4: Normal Start up, device turns on
when the bus voltage reaches 10.2V
A resistor divider is used at EN pin from PVin to turn on the
device at 10.2V.
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 18 -
IR3898
Figure 5a shows the recommended start-up sequence for
the normal (non-tracking, non-sequencing) operation of
IR3898, when Enable is used as logic input. Figure 5b
shows the recommended startup sequence for sequenced
operation of IR3898 with Enable used as logic input. Figure
5c shows the recommended startup sequence for tracking
operation of IR3898 with Enable used as logic input.
Pvin(12V)
Vcc
Vp>1V
Enable >1.2V
Intl_SS
Figure 5a: Recommended startup for Normal operation
In normal and sequencing mode operation, Vref is left
floating. A 1nF ceramic capacitor is recommended
between this pin and Gnd. In tracking mode operation,
Vref should be tied to Gnd.
It is recommended to apply the Enable signal after the VCC
voltage has been established. If the Enable signal is present
before VCC, a 50kΩ resistor can be used in series with the
Enable pin to limit the current flowing into the Enable pin.
Pvin (12V)
PRE-BIAS STARTUP
IR3898 is able to start up into pre-charged output, which
prevents oscillation and disturbances of the output
voltage.
Vcc
Enable > 1. 2 V
Intl_SS
Vp
Figure 5b: Recommended startup for sequencing operation
(ratiometric or simultaneous)
The output starts in asynchronous fashion and keeps the
synchronous MOSFET (Sync FET) off until the first gate
signal for control MOSFET (Ctrl FET) is generated. Figure 6a
shows a typical Pre-Bias condition at start up. The sync FET
always starts with a narrow pulse width (12.5% of a
switching period) and gradually increases its duty cycle
with a step of 12.5% until it reaches the steady state value.
The number of these startup pulses for each step is 16 and
it’s internally programmed. Figure 6b shows the series of
16x8 startup pulses.
Pvin (12V)
[V]
Vo
Pre-Bias
Vcc
Voltage
[Time]
Figure 6a: Pre-Bias startup
Vref=0
Enable > 1. 2 V
Intl_SS
...
HDRv
12.5%
Vp
16
Figure 5c: Recommended startup for
memory tracking operation (Vtt-DDR)
18
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
...
25%
...
LDRv
...
...
...
16
...
87.5%
...
...
...
Figure 6b: Pre-Bias startup pulses
End of
PB
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 19 -
IR3898
TABLE 1: SWITCHING FREQUENCY (FS) VS. EXTERNAL RESISTOR (RT)
SOFT-START
IR3898 has an internal digital soft-start to control the
output voltage rise and to limit the current surge at the
start-up. To ensure correct start-up, the soft-start
sequence initiates when the Enable and Vcc rise above
their UVLO thresholds and generate the Power On Ready
(POR) signal. The internal soft-start (Intl_SS) signal linearly
rises with the rate of 0.2mV/µs from 0V to 1.5V. Figure 7
shows the waveforms during soft start (also refer to Fig.
20). The normal Vout start-up time is fixed, and is equal to:
=
Tstart
( 0.65V-0.15V
)
=
0.2mV/µ s
2.5ms
(1)
During the soft start the over-current protection (OCP) and
over-voltage protection (OVP) is enabled to protect the
device for any short circuit or over voltage condition.
POR
3.0V
1.5V
0.65V
0.15V
Intl_SS
Vout
t1 t 2
t3
Figure 7: Theoretical operation waveforms during
soft-start (non tracking / non sequencing)
OPERATING FREQUENCY
The switching frequency can be programmed between
300kHz – 1500kHz by connecting an external resistor from
Rt pin to Gnd. Table 1 tabulates the oscillator frequency
versus Rt.
SHUTDOWN
IR3898 can be shut down by pulling the Enable pin below
its 1.0V threshold. This will tri-state both the high side and
the low side driver.
19
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
Rt (KΩ)
80.6
60.4
48.7
39.2
34
29.4
26.1
23.2
21
19.1
17.4
16.2
15
Freq (KHz)
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
OVER CURRENT PROTECTION
The over current (OC) protection is performed by sensing
current through the RDS(on) of the Synchronous MOSFET.
This method enhances the converter’s efficiency, reduces
cost by eliminating a current sense resistor and any layout
related noise issues. The current limit is pre-set internally
and is compensated according to the IC temperature. So at
different ambient temperature, the over-current trip
threshold remains almost constant.
Over Current Protection circuit senses the inductor current
flowing through the Synchronous MOSFET closer to the
valley point. OCP circuit samples this current for 40nsec
typically after the rising edge of the PWM set pulse which
has a width of 12.5% of the switching period.The PWM
pulse starts at the falling edge of the PWM set pulse.This
makes valley current sense more robust as current is
sensed close to the bottom of the inductor downward
slope where transient and switching noise are lower and
helps to prevent false tripping due to noise and transient.
An OC condition is detected if the load current exceeds the
threshold, the converter enters into hiccup mode. PGood
will go low and the internal soft start signal will be pulled
low. The converter goes into hiccup mode with a 20.48ms
(typ.) delay as shown in Figure 8. The convertor stays in
this mode until the over load or short circuit is removed.
The actual DC output current limit point will be greater
than the valley point by an amount equal to approximately
half of peak to peak inductor ripple current.
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 20 ∆i
2
IOCP= DC current limit hiccup point
ILIMIT= Current limit Valley Point
Δi=Inductor ripple current
=
IOCP ILIMIT +
(2)
Current Limit
Hiccup
20.48ms
IR3898
the external clock frequency, no matter which one is
higher. On the contrary, when the external clock signal is
removed from Rt/Sync pin, the switching frequency is also
changed to free-running gradually. In order to minimize
the impact from these transitions to output voltage, a
diode is recommended to add between the external clock
and Rt/Sync pin as shown in Figure 9a. Figure 9b shows the
timing diagram of these transitions.
IL
IR3898
0
HDrv
Rt/Sync
...
Gnd
0
LDrv
...
0
PGood
0
Figure 8: Timing Diagram for Current Limit and Hiccup
Figure 9a: Configuration of External Synchronization
THERMAL SHUTDOWN
Temperature sensing is provided inside IR3898. The trip
threshold is typically set to 145oC. When trip threshold is
exceeded, thermal shutdown turns off both MOSFETs and
resets the internal soft start.
Automatic restart is initiated when the sensed
temperature drops within the operating range. There is
a 20oC hysteresis in the thermal shutdown threshold.
EXTERNAL SYNCHRONIZATION
IR3898 incorporates an internal phase lock loop (PLL)
circuit which enables synchronization of the internal
oscillator to an external clock. This function is important to
avoid sub-harmonic oscillations due to beat frequency for
embedded systems when multiple point-of-load (POL)
regulators are used. A multi-function pin, Rt/Sync, is used
to connect the external clock. If the external clock is
present before the converter turns on, Rt/Sync pin can be
connected to the external clock signal solely and no other
resistor is needed. If the external clock is applied after the
converter turns on, or the converter switching frequency
needs to toggle between the external clock frequency and
the internal free-running frequency, an external resistor
from Rt/Sync pin to Gnd is required to set the free-running
frequency.
When an external clock is applied to Rt/Sync pin after the
converter runs in steady state with its free-running
frequency, a transition from the free-running frequency to
the external clock frequency will happen. This transition is
to gradually make the actual switching frequency equal to
20
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
Synchronize to the
external clock
Free Running
Frequency
Return to freerunning freq
...
SW
Gradually change
Gradually change
...
Fs1
SYNC
Fs1
Fs2
Figure 9b: Timing Diagram for Synchronization
to the external clock (Fs1>Fs2 or Fs1<Fs2)
An internal circuit is used to change the PWM ramp slope
according to the clock frequency applied on Rt/Sync pin.
Even though the frequency of the external synchronization
clock can vary in a wide range, the PLL circuit will make
sure that the ramp amplitude is kept constant, requiring no
adjustment of the loop compensation. Vin variation also
affects the ramp amplitude, which will be discussed
separately in Feed-Forward section.
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 21 FEEDFORWARD
Feed-Forward (F.F.) is an important feature, because it can
keep the converter stable and preserve its load transient
performance when Vin varies in a large range. In IR3898,
F.F. function is enabled when Vin pin is connected to PVin
pin. In this case, the internal low dropout (LDO) regulator is
used. The PWM ramp amplitude (Vramp) is proportionally
changed with Vin to maintain Vin/Vramp almost constant
throughout Vin variation range (as shown in Fig. 10). Thus,
the control loop bandwidth and phase margin can be
maintained constant. Feed-forward function can also
minimize impact on output voltage from fast Vin change.
The maximum Vin slew rate is within 1V/µs.
If an external bias voltage is used as Vcc, Vin pin should be
connected to Vcc/LDO_Out pin instead of PVin pin. Then
the F.F. function is disabled. A re-calculation of control
loop parameters is needed for re-compensation.
21V
12V
12V
IR3898
chattering. Figure 11a shows the timing diagram.
Whenever device turns on, LDO always starts with 6.4V,
then goes to 4.4V/6.4V depending upon the load
condition. For internally biased single rail operation, Vin
pin should be connected to PVin pin, as shown in Figure
11b. If external bias voltage is used, Vin pin should be
connected to Vcc/LDO_Out pin, as shown in Figure 11c.
...
IL
...
...
0
...
256/Fs
Vcc/
LDO
6.4V
6.4V
4.4V
0
Figure 11a: Time Diagram for Smart LDO
6.8V
Vin
PWM Ramp
Amplitude = 0.15xVin
0
Vin
PWM Ramp
Amplitude = 3.15V
PWM Ramp
PWM Ramp
Amplitude = 1.8V
Vin
PWM Ramp
Amplitude = 1.02V
PVin
IR3898
VCC/
LDO_OUT
Ramp Offset
0
PGnd
Figure 10: Timing Diagram for Feed-Forward (F.F.) Function
SMART LOW DROPOUT REGULATOR (LDO)
IR3898 has an integrated low dropout (LDO) regulator
which can provide gate drive voltage for both drivers.
In order to improve overall efficiency over the entire load
range, LDO voltage is set to 6.4V (typ.) at mid- or heavy
load condition to reduce Rds(on) and thus MOSFET
conduction loss; and it is reduced to 4.4 (typ.) at light load
condition to reduce gate drive loss.
The smart LDO can select its output voltage according to
the load condition by sensing switch node (SW) voltage. At
light load condition when part of the inductor current
flows in the reverse direction (DCM=1), VSW > 0 on LDrv
falling edge in a switching cycle. If this case happens for
consecutive 256 switching cycles, the smart LDO reduces
its output to 4.4. If in any one of the 256 cycles, Vsw < 0 on
LDrv falling edge, the counter is reset and LDO voltage
doesn’t change. On the other hand, if Vsw < 0 on LDrv
falling edge (DCM=0), LDO output is increased to 6.4V. A
hysteresis band is added to Vsw comparison to avoid
21
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
Figure 11b: Internally Biased Single Rail Operation
Ext
VCC
Vin
Vin
PVin
IR3898
VCC/
LDO_OUT
PGnd
Figure 11c: Use External Bias Voltage
OUTPUT VOLTAGE TRACKING AND SEQUENCING
IR3898 can accommodate user programmable tracking
and/or sequencing options using Vp, Vref, Enable, and
Power Good pins. In the block diagram presented on page
3, the error-amplifier (E/A) has been depicted with three
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 22 positive inputs. Ideally, the input with the lowest voltage
is used for regulating the output voltage and the other
two inputs are ignored. In practice the voltage of the other
two inputs should be about 200mV greater than the
low-voltage input so that their effects can completely
be ignored. Vp is internally biased to 3.3V via a high
impedance path. For normal operation, Vp and Vref is
left floating (Vref should have a bypass capacitor).
Therefore, in normal operating condition, after Enable
goes high, the internal soft-start (Intl_SS) ramps up the
output voltage until Vfb (voltage of feedback/Fb pin)
reaches about 0.5V. Then Vref takes over and the output
voltage is regulated.
Tracking-mode operation is achieved by connecting Vref to
GND. Then, while Vp=0, Enable is taken above its threshold
so that the soft-start circuit generates Intl_SS signal. After
the Intl_SS signal reaches the final value (refer to Fig. 5c),
ramping up the Vp input will ramp up the output voltage.
In tracking mode, Vfb always follows Vp which means Vout
is always proportional to Vp voltage (typical for DDR/Vtt
rail applications). The effective Vp variation range is
0V~1.2V.
In sequencing mode of operation (simultaneous or
ratiometric), Vref is left floating and Vp is kept to ground
level until Intl_SS signal reaches the final value. Then Vp is
ramped up and Vfb follows Vp. When Vp>0.5V the erroramplifier switches to Vref and the output voltage is
regulated with Vref.The final Vp voltage after sequencing
startup should between 0.7V ~ 3.3V.
6.8 V <Vin<16V
IR3898
6.8 V < Vin < 16 V
Vref
S_Ctrl EN
Vin PVin Boot
Vcc/LDO
Vo1
(master)
RE
PGood
RF
Vo2
(Salve)
SW
PGood
Vsns
Vp
RC
Rt/
Sync
Fb
Gnd
PGnd
Comp
RD
Figure 12: Application Circuit for Simultaneous
and Ratiometric Sequencing
Tracking and sequencing operations can be implemented
to be simultaneous or ratiometric (refer to Fig. 13 and 14).
Figure 12 shows typical circuit configuration for sequencing
operation. With this power-up configuration, the voltage
at the Vp pin of the slave reaches 0.5V before the Fb pin of
the master. If RE/RF =RC/RD, simultaneous startup is
achieved. That is, the output voltage of the slave follows
that of the master until the voltage at the Vp pin of the
slave reaches 0.5 V. After the voltage at the Vp pin of the
slave exceeds 0.5V, the internal 0.5V reference of the
slave dictates its output voltage. In reality the regulation
gradually shifts from Vp to internal Vref. The circuit shown
in Fig. 12 can also be used for simultaneous or ratiometric
tracking operation if Vref of the slave is connected to GND.
Table 2 summarizes the required conditions to achieve
simultaneous/ratiometric tracking or sequencing
operations.
Vcc
Vref
S_Ctrl EN
Vref=0.5V
Vin PVin Boot
Vcc/LDO
Vo1
(master)
Enable (slave)
SW
1.2V
PGood
Soft Start (slave)
PGood
Vsns
Vp
Rt/
Sync
RA
Vo1 (master)
Fb
Gnd
PGnd
Comp
RB
(a)
Vo2 (slave)
Vo1 (master)
(b)
Vo2 (slave)
Figure 13: Typical waveforms for sequencing mode of operation:
(a) simultaneous, (b) ratiometric
22
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 23 -
POWER GOOD OUTPUT (TRACKING,
SEQUENCING, VREF MARGINING)
Vcc
Vref=0V (slave)
Enable (slave)
1.2V
Soft Start (slave)
Vo1 (master)
Vo2 (slave)
(a)
Vo1 (master)
(b)
Vo2 (slave)
Figure 14: Typical waveforms in tracking mode of operation:
(a) simultaneous, (b) ratiometric
TABLE 2: REQUIRED CONDITIONS FOR SIMULTANEOUS/RATIOMETRIC
TRACKING AND SEQUENCING (FIG. 12)
Operating
Mode
Normal
(Non-sequencing,
Non-tracking)
Simultaneous
Sequencing
Ratiometric
Sequencing
Simultaneous
Tracking
Ratiometric
Tracking
Vref
(Slave)
0.5V
(Floating)
0.5V
0.5V
0V
0V
IR3898
Vp
Required
Condition
Floating
―
IR3898 continually monitors the output voltage via the
sense pin (Vsns) voltage. The Vsns voltage is an input to
the window comparator with upper and lower threshold of
0.6V and 0.45V respectively. PGood signal is high
whenever Vsns voltage is within the PGood comparator
window thresholds. The PGood pin is open drain and it
needs to be externally pulled high. High state indicates that
output is in regulation.
The threshold is set differently at different operating
modes and the results of the comparison sets the PGood
signal. Figures 15, 16, and 17 show the timing diagram of
the PGood signal at different operating modes. Vsns signal
is also used by OVP comparator for detecting output over
voltage condition.
Vref
0.5 V
0
1.2*Vref
Vsns
Ramp up
from 0V
Ramp up
from 0V
Ramp up
from 0V
Ramp up
from 0V
RA/RB>RE/
RF=RC/RD
RA/RB>RE/
RF>RC/RD
RE/RF
=RC/RD
RE/RF
>RC/RD
0.85*Vp
0
0.9*Vp
OVP
Latch
PGood
0
1.28ms
1.28ms
Figure 15: Non-sequence, Non-tracking Startup
and Vref Margin (Vp pin floating)
VREF
This pin reflects the internal reference voltage which is
used by the error amplifier to set the output voltage. In
most operating conditions this pin is only connected to an
external bypass capacitor and it is left floating. A 1nF
ceramic capacitor is recommended for the bypass
capacitor. To keep stand by current to minimum, Vref is
not allowed to come up until EN starts going high. In
tracking mode this pin should be pulled to GND. For
margining applications, an external voltage source is
connected to Vref pin and overrides the internal reference
voltage. The external voltage source should have a low
internal resistance (<100Ω) and be able to source and sink
more than 25µA.
0.4V
0.3V
Vp
0
1.2*Vp
Vsns
0.9*Vp
0
PGood
0
1.28ms
Figure 16: Vp Tracking (Vref =0V)
23
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 24 SOFT-STOP (S_CTRL)
Internal
SS
Soft-stop function can make output voltage discharge
gradually. To enable this function, S_Ctrl is kept low first
when EN goes high. Then S_Ctrl is pulled high to cross the
logic level threshold (typ. 2V), the internal soft-start ramp
is initiated. So Vo follows Intl_SS to ramp up until it
reaches its steady state. In soft-stop process, S_Ctrl needs
to be pulled low before EN goes low. After S_Ctrl goes
below its threshold, a decreasing ramp is generated at
Intl_SS with the same slope as in soft-start ramp. Vo
follows this ramp to discharge softly until shutdown
completely. Figure 19 shows the timing diagram of S_Ctrl
controlled soft-start and soft-stop.
0
Vref
0.5V
0
IR3898
(0.7V<Vp<3.3V)
0.5V
Vp
0
1.2*Vref
Vsns
0.9*Vref
0
PGood
0
1.28ms
Figure 17: Vp Sequence and Vref Margin
OVER-VOLTAGE PROTECTION (OVP)
Over-voltage protection in IR3898 is achieved by
comparing sense pin voltage Vsns to a pre-set threshold.
In non-tracking mode, OVP threshold can be set at
1.2*Vref; in tracking mode, it can be at 1.2*Vp. When Vsns
exceeds the over voltage threshold, an over voltage trip
signal asserts after 2us(typ.) delay. Then the high side drive
signal HDrv is turned off immediately, PGood flags low. The
low side drive signal is kept on until the Vsns voltage drops
below the threshold. After that, HDrv is latched off until a
reset performed by cycling either Vcc or Enable.
Vsns voltage is set by the voltage divider connected to the
output and it can be programmed externally. Figure 18
shows the timing diagram for OVP in non-tracking mode.
If the falling edge of Enable signal asserts before S_Ctrl
falling edge, the converter is still turned off by Enable.
Both gate drivers are turned off immediately and Vo
discharges to zero. Figure 20 shows the timing diagram
of Enable controlled soft-start and soft-stop. Soft stop
feature ensures that Vout discharges and also regulates
the current precisely to zero with no undershoot.
Enable
0
S_Ctrl
0
0.15V
0.15V
0
Vout
0
Figure 19: Timing Diagram for S_Ctrl controlled
Soft Start/Soft Stop
1.2*Vref
Vsns
0.65V
0.65V
Intl
_SS
1.15*Vref
S_Ctrl
0
0
HDrv
Enable
0
1.2V
1.0V
0
LDrv
0.65V
Intl
_SS
0
0.15V
0
PGood
Vout
0
0
Figure 18: Timing Diagram for OVP in non-tracking mode
24
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
Figure 20: Timing Diagram for Enable controlled
Soft Start/Shutdown
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 25 -
IR3898
MINIMUM ON TIME CONSIDERATIONS
MAXIMUM DUTY RATIO
The minimum ON time is the shortest amount of time for
Ctrl FET to be reliably turned on. This is very critical
parameter for low duty cycle, high frequency applications.
Conventional approach limits the pulse width to prevent
noise, jitter and pulse skipping. This results to lower closed
loop bandwidth.
A certain off-time is specified for IR3898. This provides
an upper limit on the operating duty ratio at any given
switching frequency. The off-time remains at a relatively
fixed ratio to switching period in low and mid frequency
range, while in high frequency range this ratio increases,
thus the lower the maximum duty ratio at which IR3898
can operate. Figure 21 shows a plot of the maximum duty
ratio vs. the switching frequency with built in input voltage
feed forward mechanism.
IR has developed a proprietary scheme to improve and
enhance minimum pulse width which utilizes the benefits
of voltage mode control scheme with higher switching
frequency, wider conversion ratio and higher closed loop
bandwidth, the latter results in reduction of output
capacitors. Any design or application using IR3898 must
ensure operation with a pulse width that is higher than this
minimum on-time and preferably higher than 60 ns.
This is necessary for the circuit to operate without jitter
and pulse-skipping, which can cause high inductor current
ripple and high output voltage ripple.
=
ton
Vout
Vin × Fs
D
=
Fs
(3)
In any application that uses IR3898, the following condition
must be satisfied:
ton (min) ≤ ton
∴ ton (min)
(4)
V
≤ out
Vin × Fs
∴Vin × Fs ≤
Vout
ton (min)
(5)
(6)
The minimum output voltage is limited by the reference
voltage and hence Vout(min) = 0.5 V. Therefore, for
Vout(min) = 0.5 V,
∴ Vin × Fs ≤
Vout (min)
∴ Vin × Fs ≤
ton (min)
0.5 V
= 8.33 V/uS
60 ns
Therefore, at the maximum recommended input voltage
21V and minimum output voltage, the converter should be
designed at a switching frequency that does not exceed
396 kHz. Conversely, for operation at the maximum
recommended operating frequency (1.65 MHz) and
minimum output voltage (0.5V). The input voltage (PVin)
should not exceed 5.05V, otherwise pulse skipping will
happen.
25
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
Figure 21: Maximum duty cycle vs. switching frequency.
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 26 -
DESIGN EXAMPLE
IR3898
Output Voltage Programming
The following example is a typical application for
IR3898. The application circuit is shown in Fig.28.
Vin =12 V ( ± 10%)
Vo =1.2 V
Io = 6 A
Ripple Voltage= ± 1% *Vo
ΔVo = ± 5% *Vo( for 50% load transient )
Output voltage is programmed by reference voltage and
external voltage divider. The Fb pin is the inverting input of
the error amplifier, which is internally referenced to 0.5V.
The divider ratio is set to provide 0.5V at the Fb pin when the
output is at its desired value. The output voltage is defined by
using the following equation:
 R 
V
=
Vref ∗ 1 + 5 
o
 R6 
(9)
When an external resistor divider is connected to the output
as shown in Fig. 23.
Fs =600 kHz
Enabling the IR3898
As explained earlier, the precise threshold of the Enable
lends itself well to implementation of a UVLO for the
Bus Voltage as shown in Fig. 22.



(10)
For the calculated values of R5 and R6, see feedback
compensation section.
Vin
IR3898
 Vref
R=
R5 ∗ 
6
 V −V
 o ref
R1
Vout
Enable
R2
IR3898
R5
Fb
R6
Figure 22: Using Enable pin for UVLO implementation
For a typical Enable threshold of VEN = 1.2 V
R2
Vin (min) *
= VEN= 1.2
R1 + R2
VEN
=
R2 R1
Vin( min ) − VEN
(7)
Figure 23: Typical application of the IR3898
for programming the output voltage
Bootstrap Capacitor Selection
(8)
For Vin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a good
choice.
Programming the frequency
For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1.
To drive the Control FET, it is necessary to supply a gate
voltage at least 4V greater than the voltage at the SW pin,
which is connected to the source of the Control FET.
This is achieved by using a bootstrap configuration, which
comprises the internal bootstrap diode and an external
bootstrap capacitor (C1). The operation of the circuit is as
follows: When the sync FET is turned on, the capacitor node
connected to SW is pulled down to ground. The capacitor
charges towards Vcc through the internal bootstrap diode
(Fig.24), which has a forward voltage drop VD. The voltage Vc
across the bootstrap capacitor C1 is approximately given as:
Vc ≅ Vcc − VD
26
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
(11)
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 27 When the control FET turns on in the next cycle, the
capacitor node connected to SW rises to the bus voltage
Vin. However, if the value of C1 is appropriately chosen,
the voltage Vc across C1 remains approximately
unchanged and the voltage at the Boot pin becomes:
VBoot ≅ Vin + Vcc − VD
(12)
+ VD -
Boot
Vcc
C1
SW
+
Vc
L
IR3898
PGnd
Figure 24: Bootstrap circuit to generate Vc voltage
A bootstrap capacitor of value 0.1uF is suitable for most
applications.
Input Capacitor Selection
The ripple current generated during the on time of the
control FET should be provided by the input capacitor.
The RMS value of this ripple is expressed by:
I RMS= I o ∗ D ∗ (1 − D )
D
=
Vo
Vin
(13)
(14)
Where:
D is the Duty Cycle
IRMS is the RMS value of the input capacitor current.
Io is the output current.
For Io=6A and D = 0.1, the IRMS = 1.8A.
27
Ceramic capacitors are recommended due to their peak
current capabilities. They also feature low ESR and ESL at
higher frequency which enables better efficiency.
For this application, it is advisable to have 3x10uF, 25V
ceramic capacitors, C3216X5R1E106M from TDK. In addition
to these, although not mandatory, a 1x330uF, 25V SMD
capacitor EEV-FK1E331P from Panasonic may also be used as
a bulk capacitor and is recommended if the input power
supply is not located close to the converter.
Inductor Selection
VIN
Cvin
IR3898
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
The inductor is selected based on output power, operating
frequency and efficiency requirements. A low inductor value
causes large ripple current, resulting in the smaller size, faster
response to a load transient but poor efficiency and high
output noise. Generally, the selection of the inductor value
can be reduced to the desired maximum ripple current in the
inductor (Δi). The optimum point is usually found between
20% and 50% ripple of the output current.
For the buck converter, the inductor value for the desired
operating ripple current can be determined using the
following relation:
Vin − Vo = L ∗
∆i
1
; ∆t = D ∗
∆t
Fs
L = (Vin − Vo ) ∗
Vo
Vin ∗ ∆i * Fs
(15)
Where:
Vin = Maximum input voltage
V0 = Output Voltage
Δi = Inductor Peak-to-Peak Ripple Current
Fs = Switching Frequency
Δt = On time
D = Duty Cycle
If Δi ≈ 30%*Io, then the output inductor is calculated to be
1.0μH. Select L=1.0μH, SPM6550T-1R0M, from TDK which
provides a compact, low profile inductor suitable for this
application.
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 28 -
IR3898
Output Capacitor Selection
Feedback Compensation
The voltage ripple and transient requirements
determine the output capacitors type and values.
The criteria is normally based on the value of the
Effective Series Resistance (ESR). However the actual
capacitance value and the Equivalent Series Inductance
(ESL) are other contributing components.
These components can be described as:
The IR3898 is a voltage mode controller. The control loop
is a single voltage feedback path including an error amplifier
and a comparator. To achieve fast transient response
and accurate output regulation, a compensation circuit is
necessary. The goal of the compensation network is to close
the control loop at high crossover frequency with phase
o
margin greater than 45 .
∆Vo = ∆Vo ( ESR ) + ∆Vo ( ESL ) + ∆Vo (C )
The output LC filter introduces a double pole, -40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180o. The resonant frequency of the LC filter is
expressed as follows:
∆Vo ( ESR ) =
∆I L * ESR
 Vin − Vo 
∆Vo ( ESL ) =

 * ESL
 L 
∆I
∆Vo (C ) = L
8* Co * Fs
FLC
=
(16)
Where:
ΔV0 = Output Voltage Ripple
ΔIL = Inductor Ripple Current
Since the output capacitor has a major role in the
overall performance of the converter and determines
the result of transient response, selection of the
capacitor is critical. The IR3898 can perform well with
all types of capacitors.
As a rule, the capacitor must have low enough ESR to
meet output ripple and load transient requirements.
The goal for this design is to meet the voltage ripple
requirement in the smallest possible capacitor size.
Therefore it is advisable to select ceramic capacitors
due to their low ESR and ESL and small size. Four of TDK
C2012X5R0J226M (22uF/0805/X5R/6.3V) capacitors is
a good choice.
It is also recommended to use a 0.1µF ceramic capacitor
at the output for high frequency filtering.
28
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
1
2 ∗ π Lo ∗ Co
(17)
Figure 25 shows gain and phase of the LC filter. Since we
already have 180o phase shift from the output filter alone,
the system runs the risk of being unstable.
Phase
Gain
0dB
00
-40dB/Decade
-900
-1800
FLC
Frequency
FLC
Frequency
Figure 25: Gain and Phase of LC filter
The IR3898 uses a voltage-type error amplifier with high-gain
(110dB) and high-bandwidth (30MHz). The output of the
amplifier is available for DC gain control and AC phase
compensation.
The error amplifier can be compensated either in type II or
type III compensation. Type II compensation is shown in Fig.
26. This method requires that the output capacitors have
enough ESR to satisfy stability requirements. If the output
capacitor’s ESR generates a zero at 5kHz to 50kHz, the zero
generates acceptable phase margin and the Type II
compensator can be used.
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 29 Use the following equation to calculate R3:
The ESR zero of the output capacitor is expressed as
follows:
1
=
FESR
2π* ESR* Co
=
R3
(18)
VOUT
Z IN
C3
R5
Zf
Fb
E/A
R6
Comp
Ve
VREF
Gain(dB)
Vosc * Fo * FESR * R5
2
Vin * FLC
(23)
Where:
Vin = Maximum Input Voltage
Vosc = Amplitude of the oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 = Feedback Resistor
C POLE
R3
IR3898
To cancel one of the LC filter poles, place the zero before the
LC filter resonant frequency pole:
Fz = 75 % *FLC
H(s) dB
=
Fz 0.75*
F
FZ
Use equations (20), (21) and (22) to calculate C3.
Figure 26: Type II compensation network
and its asymptotic gain plot
One more capacitor is sometimes added in parallel with C3
and R3. This introduces one more pole which is mainly used
to suppress the switching noise.
The transfer function (Ve/Vout) is given by:
Zf
Ve
1 + sR 3C3
= H (s) = −
= −
Vout
Z IN
sR 5C3
The additional pole is given by:
(19)
=
FP
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a
gain and zero, expressed by:
R3
R5
1
Fz
=
2π * R 3 * C3
1
C *C
2π * R3 * 3 POLE
C3 + CPOLE
(25)
The pole sets to one half of the switching frequency which
results in the capacitor CPOLE:
(20)
=
CPOLE
(21)
First select the desired zero-crossover frequency (Fo):
Fo > FESR and Fo ≤ (1/5~1/10 ) * Fs
29
(24)
Frequency
POLE
H ( s )=
1
2π Lo * Co
(22)
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
1
π * R 3 * Fs −
1
C3
≅
1
π * R 3 * Fs
(26)
For a general solution for unconditional stability for any type
of output capacitors, and a wide range of ESR values, a type III
compensation network can be used, as shown in Fig. 27.
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 30 VOUT
ZIN
R4
1
2π * R3 * C3
(31)
1
1
FZ 2
=
≅
2π * C4 *( R4 + R5 ) 2π * C4 * R5
Zf
(32)
FZ 1
=
C2
C4
R3
C3
R5
Fb
R6
E/ A
Ve
Comp
Crossover frequency is expressed as:
Fo = R3 * C4 *
VREF
|H(s)| dB
FZ1
FZ 2
FP2
FP3
Frequency
Figure 27: Type III Compensation network
and its asymptotic gain plot
Again, the transfer function is given by:
Zf
Ve
= H (s) = −
Vout
Z IN
By replacing Zin and Zf, according to Fig. 27, the transfer
function can be expressed as:
H (s) =
(1 + sR3C3 ) 1 + sC4 ( R4 + R5 ) 

 C * C3
sR5 (C2 + C3 ) 1 + sR3  2
 C2 + C3


  (1 + sR4C4 )

(27)
The compensation network has three poles and two
zeros and they are expressed as follows:
FP1 = 0
FP 2
=
FP 3
=
(28)
1
2π * R4 * C4
1
1
≅
 C2 * C3  2π * R3 * C2
2π * R3 

 C2 + C3 
30
Vin
1
*
Vosc 2π * Lo * Co
(33)
Based on the frequency of the zero generated by the output
capacitor and its ESR, relative to crossover frequency, the
compensation type can be different. Table 3 shows the
compensation types for relative locations of the crossover
frequency.
Gain (dB)
−
IR3898
(29)
(30)
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
TABLE 3: DIFFERENT TYPES OF COMPENSATORS
Compensator
Type
FESR vs FO
Typical Output
Capacitor
Type II
Type III
FLC < FESR < FO < FS/2
FLC < FO < FESR
Electrolytic
SP Cap, Ceramic
The higher the crossover frequency is, the potentially faster
the load transient response will be. However, the crossover
frequency should be low enough to attenuate the switching
noise. Typically, the control loop bandwidth or crossover
frequency (Fo) is selected such that:
Fo ≤ (1/5 ~ 1/10 )* Fs
The DC gain should be large enough to provide high
DC-regulation accuracy. The phase margin should be greater
than 45o for overall stability.
For this design we have:
Vin=12V
Vo=1.2V
Vosc=1.8V (This is a function of Vin, see feedforward
section)
Vref=0.5V
Lo=1.0uH
Co=4x22uF, ESR≈3mΩ each
It must be noted here that the value of the capacitance used
in the compensator design must be the small signal value.
For instance, the small signal capacitance of the 22uF
capacitor used in this design is 10uF at 1.2 V DC bias and
600 kHz frequency. It is this value that must be used for all
computations related to the compensation. The small signal
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 31 -
IR3898
Calculate R4, R5 and R6:
value may be obtained from the manufacturer’s
datasheets, design tools or SPICE models. Alternatively,
they may also be inferred from measuring the power
1
; R4 106
Ω,
Select:
100
=
R4 =
=
R4 Ω
stage transfer function of the converter and measuring
2π * C4 * FP 2
the double pole frequency FLC and using equation (17)
to compute the small signal Co.
1
- R4 ; R5 Ω,
3.41 k
=
R5 =
2π * C4 * FZ 2
These result in:
FLC=25.2 kHz
Select R5 = 3.32 kΩ:
FESR=5.3 MHz
Fs/2=300 kHz
Select crossover frequency F0=120 kHz
=
R6
Since FLC<F0<Fs/2<FESR, Type III is selected to place the
pole and zeros.
Detailed calculation of compensation Type III:
Desired Phase Boost Θ = 70°
1 − sin Θ
21.2 kHz
=
FZ 2 F=
o
1 + sin Θ
1 + sin Θ
680.6 kHz
=
FP 2 F=
o
1 − sin Θ
Vref
* R5 ; R6 Ω2.37
Select:
k
2.37
=
=
R6 kΩ
Vo - Vref
Setting the Power Good Threshold
In this design IR3898 is used in normal (non-tracking,
non-sequencing) mode, therefore the PGood thresholds are
internally set at 90% and 120% of Vref. At startup as soon as
Vsns voltage reaches 0.9*0.5V=0.45V (Fig. 15), after 1.28ms
delay, PGood signal is asserted. As long as the Vsns voltage
is between the threshold range, Enable is high, and no fault
happens, the PGood remains high.
The following formula can be used to set the threshold.
VoutPGood_Th can be taken as 90% of Vout. Choose R7=3.32KΩ:
R8 =
Select:
=
FZ 1 0.5*
=
FZ 2
10.6 kHz and
=
FP 3 0.5*
=
Fs 300 kHz
Select C4 = 2.2nF.
Calculate R3, C3 and C2:
R3
2π * Fo * Lo * Co *Vosc
=
; R3 2.1
Ω k
C4 *Vin
Select R3 = 2.0 kΩ:
(34)
=
R8 2.37 K Ω
The PGood is an open drain output. Hence, it is necessary to
use a pull up resistor, RPG, from PGood pin to Vcc. The value
of the pull-up resistor must be chosen such as to limit the
current flowing into the PGood pin to less than 5mA when
the output voltage is not in regulation. A typical value used
is 49.9kΩ.
OVP comparator also uses Vsns signal for over Voltage
dectection.With above values for R7 and R8, OVP trip point
(Vout_OVP) is
Vout=
_ OVP Vref *1.2 * ( R 7 + R8)=
/ R8 1.44V
1
; C3 7.5 =
nF, Select: C3 10 nF
=
C3 =
2π *FZ 1 * R 3
1
; C2 265=
pF, Select: C2 180 pF
=
C2 =
2π * FP 3 * R3
31
Vref *0.9* R 7
Vout PGood _ Th − Vref *0.9
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
(35)
Vref Bypass Capacitor
A 1nF bypass capacitor is recommended to be placed
between Vref and Gnd pins.This capacitor should be placed as
close as possible to Vref pin.
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 32 -
IR3898
APPLICATION DIAGRAM
C6
0.1uF Cin = 3 X 10uF
Vin=12 V
R1
49.9K
Cvin
1.0uF
R2
7.5K
U1
Enable
S_Ctrl
Vin PVin
Boot
C1
0. 1 uF
2.2uF
Lo
1 uH
Vcc/LDO_out
CVcc
Vo=1.2V
SW
RPG
49.9K
PGood
PGood
IR3898
Vp
R7
3.32k
R8
2.37K
Vsns
R4
100
Co=4X22uF
Fb
Rt/Sync
Rt
C3
10nF
39.2
. K
Vref Gnd
C5
0.1uF
C4
2.2nF
R5
3.32k
R6
2.37K
R3
2.0K
Comp
PGnd
C2
180pF
100pF
Cref
Figure 28a: Application Circuit for a 12V to 1.2V, 6A Point of Load Converter Using the internal LDO
Suggested bill of materials for the application circuit 12V to 1.2V
Part Reference
Cin
Qty
3
C1 C5 C6
3
Cref
Value
Manufacturer
10uF
Description
1206, 16V, X5R, 20%
Part Number
TDK
C3216X5R1E106M
0.1uF
0603, 25V, X7R, 10%
Murata
GRM188R71E104KA01B
1
1nF
0603,50V,X7R, 10%
Murata
GRM188R71H102KA01B
C4
1
2200pF
C2
1
180pF
0603,50V,X7R
0603, 50V, NP0, 5%
Murata
Murata
GRM188R71H222KA01B
GRM1885C1H181JA01D
Co
4
22uF
0805, 6.3V, X5R, 20%
TDK
C2012X5R0J226M
CVcc
1
2.2uF
0603, 16V, X5R, 20%
TDK
C1608X5R1C225M
C3
1
10nF
0603, 25V, X7R, 10%
Murata
GRM188R71E103KA01J
Cvin
1
1.0uF
0603, 25V, X5R, 10%
Murata
GRM188R61E105KA12D
Lo
1
1uH
TDK
SPM6550T-1R0
R3
1
2.0K
SMD 7.1x6.5x5 mm ,4.7mΩ
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF2001V
R5 R7
2
3.32K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF3321V
R6 R8
2
2.37K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF2371V
R4
1
100
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF1000V
Panasonic
ERJ-3EKF3922V
Rt
1
39.2K
Thick Film, 0603,1/10W,1%
R1 Rpg
2
49.9K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF4992V
R2
1
7.5K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF7551V
U1
1
IR3898
PQFN 4x5mm
IR
IR3898MPBF
32
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 33 -
Vin=12 V
IR3898
C6
0.1uF Cin = 3 X10uF
R1
49.9K
R2
7.5K
U1
Vin
S_Ctrl
External VCC=5V
Enable PVin
Boot
C1
0. 1 uF
2.2uF
CVcc
Lo
1 uH
Vcc/LDO_out
Vo=1.2V
SW
RPG
49.9K
PGood
IR3898
Vsns
Vp
R7
3.32k
R8
2.37K
R4
64.9
Co=4X22uF
Fb
Rt/Sync
Rt
C3
33nF
39.2
. K
Vref Gnd
C5
0.1uF
C4
2.2nF
R5
3.32k
R3
1k
R6
2.37K
Comp
PGnd
100pF
Cref
C2
390pF
Figure 28b: Application Circuit for a 12V to 1.2V, 6A Point of Load Converter Using External 5V VCC
33
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 34 Vin= 5 V
IR3898
C6
0.1uF Cin = 4 X10uF
Enable
U1
Enable PVin
Vin
S_Ctrl
Boot
C1
0. 1 uF
2.2uF
CVcc
Lo
0.68uH
Vcc/LDO_out
Vo=1V
SW
RPG
49.9K
PGood
PGood
IR3898
Vsns
Vp
R7
3.32k
R8
3.32k
R4
100
Co=4X22uF
Fb
Rt/Sync
Rt
C3
10nF
39.2
. K
Vref Gnd
C5
0.1uF
C4
2.2nF
R5
3.32k
R6
3.32k
R3
2.0k
Comp
PGnd
C2
220pF
100pF
Cref
Figure 29: Application Circuit for a 5V to 1V, 6A Point of Load Converter
Suggested bill of materials for the application circuit 5V to 1V
Part Reference
Cin
Qty
3
C1 C5 C6
3
Cref
Value
Manufacturer
10uF
Description
1206, 16V, X5R, 20%
Part Number
TDK
C3216X5R1E106M
0.1uF
0603, 25V, X7R, 10%
Murata
GRM188R71E104KA01B
1
1nF
0603,50V,X7R
Murata
GRM188R71H102KA01B
C4
1
2200pF
C2
1
220pF
0603,50V,X7R, 10%
0603,50V,X7R, 10%
Murata
Murata
GRM188R71H222KA01B
GRM188R71H221KA01D
Co
4
22uF
0805, 6.3V, X5R, 20%
TDK
C2012X5R0J226M
CVcc
1
2.2uF
0603, 16V, X5R, 20%
TDK
C1608X5R1C225M
C3
1
10nF
0603, 25V, X7R, 10%
Murata
GRM188R71E103KA01J
Lo
1
0.68uH
PCMB065T-R68MS
1
2.0K
SMD 7.05x6.6x4.8 mm, 3.9mΩ
Thick Film, 0603,1/10W,1%
Cyntec
R3
Panasonic
ERJ-3EKF2001V
R5 R6 R7 R8
4
3.32K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF3321V
Panasonic
ERJ-3EKF1000V
R4
1
100
Thick Film, 0603,1/10W,1%
Rt
1
39.2K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF3922V
Rpg
1
49.9K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF4992V
U1
1
IR3898
PQFN 4x5mm
IR
IR3898MPBF
34
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 35 -
IR3898
C6
0.1uF Cin = 3 X 10uF
Vin=12 V
R1
49.9k
Cvin
1.0uF
R2
7.5k
U1
Enable
S_Ctrl
Vin PVin
C1
0. 1 uF
Boot
2.2uF
Lo
Vcc/LDO_out
CVcc
SW
RPG
49.9k
PGood
VDDQ=1.2V
PGood
R6
R7
6.65k
IR3898
Vsns
N/S
(optional)
Vp
1.5k
C7
10nF
R8
1.5k
Vo=0.6V
680nH
R5
6.65k
C5
0.1uF
C4
2.2nF
R4
215
Co=6X22uF
Fb
Rt/Sync
C3
15nF
Rt
Comp
Vref Gnd
39.2 K
R3
2k
PGnd
C2
270pF
Figure 30: Application Circuit for a 12V input, 0.6V output, VTT Rail
Vin=1.2V
C6
0.1uF Cin = 3 X 22uF
Enable
U1
Vin Enable
S_Ctrl
Ext VCC
PVin
Boot
C1
0. 1 uF
2.2uF
CVcc
Lo
Vcc/LDO_out
SW
RPG
49.9k
PGood
PGood
Vin=1.2V
R6
R7
4.99k
IR3898
Vsns
N/S
(optional)
Vp
1.5k
1.5k
R8
C7
10nF
Fb
R5
4.99k
C5
0.1uF
C4
2.2nF
R4
158
Co=6X22uF
Rt/Sync
C3
3.9nF
Rt
39.2 K
Vo=0.6V
0.35uH
Vref Gnd
R3
5.76k
Comp
PGnd
C2
91pF
Figure 31: Application Circuit for a 1.2V input, 0.6V output, VTT Rail
35
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 36 -
IR3898
TYPICAL OPERATING WAVEFORMS
Vin = 12V, Vo = 1.2V, Iout = 0-6A Room Temperature, No Air Flow
Figure 32: Start up at 6A Load,
Ch1:Vin, Ch2:Vo, Ch3:PGood, Ch4:Enable
Figure 34: Start up with 1V pre bias
0A Load
Ch2:Vo
Figure 36: Inductor node at 6A Load, Ch3:LX
36
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
Figure 33: Start up at 6A Load,
Ch1:Vin, Ch2:Vo, Ch3:Vcc, Ch4:PGood
Figure 35: Output Voltage Ripple
6A Load
Ch2:Vo
Figure 37: Short circuit Recovery
Ch2:Vout,Ch4:Iout(2A/Div)
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 37 -
IR3898
TYPICAL OPERATING WAVEFORMS
Vin = 12V, Vo = 1.2V, Iout = 0-6A Room Temperature, No Air Flow
Figure 38: Turn on at no load showing Vcc level
Ch1:Vin, Ch2:Vo, Ch3:Vcc, Ch4:Inductor current
Figure 39: Turn on at full load showing Vcc level
Ch1:Vin, Ch2:Vo, Ch3:Vcc, Ch4:Inductor current
Figure 40: Transient Response, 3 to 6A step at 2.5A/uSec slew rate
Ch2:Vo, Ch4:Iout(2A/Div)
37
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 38 -
IR3898
TYPICAL OPERATING WAVEFORMS
Vin = 12V, Vo = 1.2V, Iout = 0-6A Room Temperature, No Air Flow
Figure 41: Bode Plot at 6A load shows a bandwidth of 110.8KHz and phase margin of 50.6 degrees
Figure 42: Thermal Image of the Board at 6A Load,
Test Point 1 is IR3898,
Test Point 2 is inductor
38
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 39 -
IR3898
TYPICAL OPERATING WAVEFORMS
Vin = 12V, Vo = 1.2V, Iout = 0-6A Room Temperature, No Air Flow
Figure 43: Feed Forward for Vin change from 7-16-7V
Ch2-Vo,Ch4:Vin
Figure 45: External frequency synchronization to
800KHz from free running 600KHz, Ch2:Vo, Ch3:LX, Ch4:Rt/Sync Voltage
Figure 47: Voltage Margining using Vref pin
Ch2:Vo, Ch3:PGood, Ch4:Vref
39
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
Figure 44: Start/Stop using S-ctrl pin
Ch1-PGood,Ch2:Vout;Ch3-EN.Ch4-S-Ctrl
Figure 46: Over Voltage protection
Ch2-Vo,Ch43-PGood
Figure 48: Voltage tracking using Vp Pin
Ch1:Vo, Ch3:PGood, Ch4:Vp
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 40 LAYOUT RECOMMENDATIONS
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with less
than expected results.
Make the connections for the power components in the
top layer with wide, copper filled areas or polygons. In
general, it is desirable to make proper use of power planes
and polygons for power distribution and heat dissipation.
The inductor, output capacitors and the IR3898 should be
as close to each other as possible. This helps to reduce the
EMI radiated by the power traces due to the high switching
currents through them. Place the input capacitor directly
at the PVin pin of IR3898.
The feedback part of the system should be kept away from
the inductor and other noise sources.
IR3898
The critical bypass components such as capacitors for Vin,
Vcc and Vref should be close to their respective pins. It is
important to place the feedback components including
feedback resistors and compensation components close to
Fb and Comp pins.
In a multilayer PCB use one layer as a power ground plane
and have a control circuit ground (analog ground), to which
all signals are referenced. The goal is to localize the high
current path to a separate loop that does not interfere
with the more sensitive analog control function. These two
grounds must be connected together on the PC board
layout at a single point. It is recommended to place all
the compensation parts over the analog ground plane in
top layer.
The Power QFN is a thermally enhanced package. Based on
thermal performance it is recommended to use at least a
4-layers PCB. To effectively remove heat from the device
the exposed pad should be connected to the ground plane
using vias. Figures 46a-d illustrates the implementation of
the layout guidelines outlined above, on the IRDC3898 4layer demo board.
Enough copper &
minimum ground
length
path between Input
and Output
All bypass caps
should be placed
as close as possible
to their connecting
pins
Compensation parts
should be placed
as close as possible
to the Comp pin
SW node copper is
kept only at the top
layer to minimize
the switching noise
Resistor Rt and Vref
decoupling cap should
be placed as close as
possible to their pins
Figure 49a: IRDC3898 Demo board Layout Considerations – Top Layer
40
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 41 -
Single point connection
between AGND & PGND,
should be close to the
SupIRBuck kept away from
noise sources
IR3898
Feedback and Vsns trace
routing should be kept away
from noise sources
Figure 49b: IRDC3898 Demo board Layout Considerations – Bottom Layer
Analog Ground plane
Power Ground plane
Figure 49c: IRDC3898 Demo board Layout Considerations – Mid Layer 1
Figure 49d: IRDC3898 Demo board Layout Considerations – Mid Layer 2
41
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 42 PCB METAL AND COMPONENT PLACEMENT
Evaluations have shown that the best overall
performance is achieved using the substrate/PCB layout
as shown in following figures. PQFN devices should be
placed to an accuracy of 0.050mm on both X and Y axes.
Self-centering behavior is highly dependent on solders
and processes, and experiments should be run to confirm
the limits of self-centering on specific processes.
For further information, please refer to “SupIRBuck™
Multi-Chip Module (MCM) Power Quad Flat No-Lead
(PQFN) Board Mounting Application Note.” (AN1132)
Figure 50: PCB Metal Pad Spacing (all dimensions in mm)
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
42
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
IR3898
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 43 -
IR3898
SOLDER RESIST
• IR recommends that the larger Power or Land
Area pads are Solder Mask Defined (SMD.)
This allows the underlying Copper traces to be as
large as possible, which helps in terms of current
carrying capability and device cooling capability.
• When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on each
edge) than the Solder Mask window, in order to
accommodate any layer to layer misalignment.
(i.e. 0.1mm in X & Y.)
• However, for the smaller Signal type leads around
the edge of the device, IR recommends that these
are Non Solder Mask Defined or Copper Defined.
• When using NSMD pads, the Solder Resist
Window should be larger than the Copper Pad
by at least 0.025mm on each edge, (i.e. 0.05mm
in X&Y,) in order to accommodate any layer to
layer misalignment.
• Ensure that the solder resist in-between the
smaller signal lead areas are at least 0.15mm
wide, due to the high x/y aspect ratio of the
solder mask strip.
Figure 51: Solder resist
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
43
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 44 -
IR3898
STENCIL DESIGN
• Stencils for PQFN can be used with thicknesses
of 0.100-0.250mm (0.004-0.010"). Stencils thinner
than 0.100mm are unsuitable because they
deposit insufficient solder paste to make good
solder joints with the ground pad; high reductions
sometimes create similar problems. Stencils in
the range of 0.125mm-0.200mm (0.005-0.008"),
with suitable reductions, give the best results.
• Evaluations have shown that the best overall
performance is achieved using the stencil design
shown in following figure. This design is for
a stencil thickness of 0.127mm (0.005").
The reduction should be adjusted for stencils
of other thicknesses.
Figure 52: Stencil Pad Spacing (all dimensions in mm)
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
44
AUGUST 08, 2012 | DATA SHEET | Rev 3.3
PD-97662
6A Highly Integrated SupIRBuckTM
Single-Input Voltage,
Synchronous Buck Regulator
- 45 -
IR3898
MARKING INFORMATION
Figure 53: Marking Information
PACKAGE INFORMATION
Figure 54: Package Dimensions
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial market
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice 12/11.
45
AUGUST 08, 2012 | DATA SHEET | Rev 3.3