AMD AM79C978

Am79C978
PCnet™- Home
Single-Chip 1/10 Mbps PCI Home Networking Controller
DISTINCTIVE CHARACTERISTICS
n Fully integrated 1 Mbps HomePNA Physical
Layer (PHY) as defined by Home Phoneline
Networking Alliance (HomePNA) specification
1.1
— Supports both PCI 5.0-V and 3.3-V signaling
environments
— Plug and Play compatible
— Supports an unlimited PCI burst length
— Optimized for home networking applications
over ordinary telephone wire
— Big endian and little endian byte alignments
supported
— In-band control features:
— Implements optional PCI power management
event (PME) pin
Adjustable power and speed levels
n Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 Ethernet standard
32 bits of reserved in-band messaging piggybacked on Ethernet packet
— Register programmable features:
n Media Independent Interface (MII) for
connecting external 10/100 Mbps transceivers
Power control
Performance registers
— IEEE 802.3u compliant MII
Speed control
— Intelligent Auto-Poll™ external PHY status
monitor and interrupt
Major frame timing parameters programmable: ISBI, AID ISBI, pulse width, inter-symbol
time
— Supports both auto-negotiable and nonauto-negotiable external PHYs
— Supports 10BASE-T, 100BASETX/FX,
100BASET4, and 100BASET2 IEEE 802.3
compliant MII PHYs at full-duplex or halfduplex
n Fully integrated 10 Mbps PHY interface
— Comprehensive Auto-Negotiation
implementation
— Full-duplex capability
n Full-duplex operation supported on the MII port
with independent Transmit (TX) and Receive
(RX) channels
— Optimized for 10BASE-T applications
n Integrated Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) bus
n Supports PC98 and Net PC specifications
— 32-bit glueless PCI host interface
— Supports PCI clock frequency from DC to
33 MHz independent of network clock
— Implements full OnNow features including
pattern matching and link status wake-up
events
— Supports network operation with PCI clock
from 15 MHz to 33 MHz
— Implements Magic Packet™ mode
— Magic Packet mode and the physical address
loaded from EEPROM at power up without
requiring PCI clock
— High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
— Supports PCI Bus Power Management
Interface specification revision 1.1
— PCI draft specification revision 2.2 compliant
— Supports Advanced Configuration and
Power Interface (ACPI) specification version
1.0
— Supports PCI Subsystem/Subvendor ID/
Vendor ID programming through the
EEPROM interface
— Supports Network Device Class Power
Management specification version 1.0a
Publication# 22206 Rev: D Amendment/0
Issue Date: November 1999
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n Independent internal TX and RX FIFOs
— Programmable FIFO watermarks for both TX
and RX operations
by allowing protocol analysis to begin before
the end of a receive frame
— RX frame queuing for high latency PCI bus
host operation
n Includes Programmable Inter Packet Gap (IPG)
to address less network aggressive MAC
controllers
— Programmable allocation of buffer space
between RX and TX queues
n Offers the Modified Back-Off algorithm to
address the Ethernet Capture Effect
n Extensive programmable internal/external
loopback capabilities
n EEPROM interface supports jumperless design
and provides through-chip programming
— Supports full programmability of half-/fullduplex operation through EEPROM mapping
— Programmable PHY reset output pin capable
of resetting external PHY without the need
for buffering
n Extensive programmable LED status support
n Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
n IEEE 1149.1-compliant JTAG Boundary Scan
test access port interface and NAND tree test
mode for board-level production connectivity
test
n Software compatible with AMD’s PCnet™
Family and LANCE/C-LANCE register and
descriptor architecture
n Very low power consumption
n +3.3 V power supply along with 5 V tolerant I/Os
enable broad system compatibility
n Available in 144-pin TQFP and 160-pin PQFP
packages
GENERAL DESCRIPTION
The Am79C978 controller is the first in a series of home
networking products from AMD. The Am79C978 controller is fabricated in an advanced low power 3.3 V
CMOS process to provide low operating current for
power sensitive applications.
The Am79C978 controller contains an Ethernet Controller based on the Am79C971 Fast Ethernet controller, a physical layer device for supporting the 802.3
standard for 10BASE-T, and a physical layer device for
data networking at speeds up to 1 Mbps over ordinary
residential telephone wiring.
The integrated PCI Ethernet controller is a highly integrated 32-bit full-duplex, 10/100 Mbps Ethernet controller solution designed to address high-performance
system application requirements. It is a flexible busmastering device that can be used in any application,
including network ready PCs. The bus master architecture provides high data throughput and low CPU and
system bus utilization.
system. The device has built-in support for both little
and big endian byte alignment. The integrated home
networking controller’s advanced CMOS design allows
the bus interface to be connected to either a +5.0 V or
a +3.3 V signaling environment. A compliant IEEE
1149.1 JTAG test interface for board level testing is
also provided, as well as a NAND tree test structure for
those systems that do not support the JTAG interface.
The integrated Am79C978 home networking controller
is also compliant with the PC98 and Net PC specifications. It includes the full implementation of the Microsoft OnNow and ACPI specifications, which are
backward compatible with Magic Packet technology. It
is also compliant with the PCI Bus Power Management
Interface specification by supporting the four power
management states (D0, D1, D2, and D3), the optional
PME pin, and the necessary configuration and data
registers.
The integrated HomePNA transceiver is a physical
layer device that enables data networking at speeds up
to 1 Mbps over common residential phone wiring regardless of topology and without disrupting telephone
(POTS) service.
The integrated Am79C978 home networking controller
is a complete Ethernet or home network node integrated into a single VLSI device. It contains a bus interface unit, a Direct Memory Access (DMA) Buffer
Management Unit, an ISO/IEC 88023 (IEEE 802.3)
compliant Media Access Controller (MAC), a Transmit
FIFO and a large Receive FIFO, and an IEEE 802.3u
compliant MII. Both IEEE 802.3 compliant full-duplex
and half-duplex operations are supported on the MII interface. 10/100 Mbps operation is supported through
the MII interface.
The 32-bit multiplexed bus interface unit provides a direct interface to the PCI local bus, simplifying the design of an Ethernet or home network node in a PC
The integrated Am79C978 home networking controller
is register compatible with the LANCE (Am7990) and
C-LANCE (Am79C90) Ethernet controllers and all
The integrated Ethernet transceiver is a physical layer
device supporting the IEEE 802.3 standards for
10BASE-T. It provides all of the PHY layer functions required to support 10 Mbps data transfer speeds.
2
Am79C978
Ethernet controllers in the PCnet Family (except
ILACC™ (Am79C900)), including PCnet-ISA
(Am79C960), PCnet-ISA+ (Am79C961), PCnet-ISA II
(Am79C961A), PCnet-32 (Am79C965A), PCnet-PCI
(Am79C970), PCnet-PCI II (Am79C970A), PCnetFAST (Am79C971), and PCnet-FAST+ (Am79C972).
The Buffer Management Unit supports the LANCE and
PCnet descriptor software models.
While consuming minimal network resources, AMD’s
innovative any1Home™ Link Detection Packet for
HomePNA networks provides a means to indicate to
the MAC and thus the upper layers of the system protocol that a valid network (as defined by Home Networking Alliance) has been detected. The Link
Detection Packet is also capable of detecting a network
failure and allows the upper layer protocol to take cor-
rective action. Thus, the Link Detection Packet ensure
strict compliance to the Microsoft PC97, PC98, and
Home PNA requirements.
The integrated Am79C978 controller supports autoconfiguration in the PCI configuration space. Additional
integrated controller configuration parameters, including the unique IEEE physical address, can be read
from an external non-volatile memory (EEPROM) immediately following system reset.
In addition, the Am79C978 controller provides programmable on-chip LED drivers for transmit, receive,
collision, link integrity, Magic Packet status, speed, activity, power output, address match, full-duplex, or 100
Mbps status.
Am79C978
3
MDC
MDIO
RXD(3:0)/TXD(3:0)
XTAL2
Clock
Reference
XTAL1
BLOCK DIAGRAM
1Mbps HomePNA PHY
Transmit
State
Machine
MII
Interface
CLK
RST
AD[31:0]
C/BE[3:0]
PAR
FRAME
TRDY
IRDY
STOP
IDSEL
DEVSEL
REQ
GNT
PERR
SERR
INTA
HRTXRXP/N
Receive
State
Machine
MII
Management
PHY
Control
Bus
Rcv
FIFO
PCI Bus
Interface
Unit
MAC
Rcv
FIFO
Analog
Front
End
Link
Monitor
10 Mbps PHY
802.3
MAC
Core
MII
Interface
12K
SRAM
Transmit
State
Machine
TX±
10 BASE-T
Bus
Xmt
FIFO
MAC
Xmt
FIFO
FIFO
Control
Network
Port
Manager
MDC
MDIO
MII
Management
RX±
Receive
State
Machine
Link
Monitor
Buffer
Management
Unit
Auto
Negotiation
PHY Control
LED
Control
TCK
TMS
TDI
TDO
Drive
Control
OnNow
Power
Management
Unit
JTAG
Port
Control
93C46
EEPROM
Interface
LED0
LED1
LED2
LED3
LED4
EECS
EESK
EEDI
EEDO
PME
PG
22206B-1
4
Am79C978
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
RELATED AMD PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CONNECTION DIAGRAM (144 TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
CONNECTION DIAGRAM (160 PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PIN DESIGNATIONS (PQL144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Magic Packet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Ethernet Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
HomePNA PHY Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
BASIC FUNCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
MII Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
MII Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Network Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MII Management Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Auto-Poll External PHY Status Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Network Port Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
10BASE-T PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PCI and JTAG Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Slave Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Slave I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Disconnect When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Disconnect Of Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Basic Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Basic Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Basic Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Basic Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Am79C978
5
Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Master Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Preemption During Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Advanced Parity Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Non-Burst FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Burst FIFO DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Re-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Transmit Descriptor Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Receive Descriptor Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Receive Frame Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
10/100 Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Destination Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Media Access Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Medium Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Collision Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Automatic Pad Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Loss of Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Late Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
SQE Test Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Receive Function Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Address Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Miscellaneous Loopback Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Full-Duplex Link Status LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
PHY/MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
1 Mbps HomePNA PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
HomePNA PHY Medium Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
HomePNA Symbol Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Time Interval Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
ACCESS ID Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Symbol 0 (SYNC interval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SYNC Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
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SYNC Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
AID Symbols 1 through 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AID Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AID Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Collisions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
JAM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ACCESS ID Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Silence Interval (AID symbol 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Data Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Symbol RLL25 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Management Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Header AID Remote Control Word Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PHY Control and Management Block (PCM Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Register Administration for 10BASE-T PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Description of the Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Low Latency Receive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Direct SRAM Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Automatic EEPROM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EEPROM Auto-Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Direct Access to the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EEPROM-Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EEPROM MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
OnNow Wake-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Link Change Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
OnNow Pattern Match Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Pattern Match RAM (PMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Magic Packet Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TAP Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Instruction Register and Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Other Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
NAND Tree Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
H_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
S_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Power on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Address PROM Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Word I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Double Word I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10BASE-T Physical Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Twisted Pair Transmit Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Reverse Polarity Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Soft Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
PCI Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
PCI Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
PCI Programming Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
PCI Sub-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
PCI Base-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI Latency Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI Header Type Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
PCI Memory Mapped I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PCI Subsystem Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PCI Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI Capabilities Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI MIN_GNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Capability Identifier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Power Management Capabilities Register (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
PCI Power Management Control/Status Register (PMCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
PCI PMCSR Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
RAP: Register Address Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Control and Status Registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
CSR0: Controller Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
CSR1: Initialization Block Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
CSR2: Initialization Block Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
CSR5: Extended Control and Interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
CSR6: RX/TX Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
CSR7: Extended Control and Interrupt 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
CSR8: Logical Address Filter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
CSR9: Logical Address Filter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
CSR10: Logical Address Filter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
CSR11: Logical Address Filter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
CSR12: Physical Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
CSR13: Physical Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
CSR14: Physical Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
CSR15: Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR18: Current Receive Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR19: Current Receive Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
CSR20: Current Transmit Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR21: Current Transmit Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR22: Next Receive Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR23: Next Receive Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
8
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CSR25: Base Address of Receive Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR26: Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
CSR27: Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR28: Current Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR29: Current Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR30: Base Address of Transmit Ring Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR31: Base Address of Transmit Ring Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR32: Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR33: Next Transmit Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
CSR34: Current Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR35: Current Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR36: Next Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR37: Next Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR38: Next Next Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR39: Next Next Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR40: Current Receive Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
CSR41: Current Receive Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR42: Current Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR43: Current Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR44: Next Receive Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR45: Next Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR46: Transmit Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
CSR47: Transmit Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR48: Receive Poll Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR49: Receive Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
CSR58: Software Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
CSR60: Previous Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR61: Previous Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR62: Previous Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR63: Previous Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR64: Next Transmit Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR65: Next Transmit Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR66: Next Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
CSR67: Next Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR72: Receive Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
CSR80: DMA Transfer Counter and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
CSR82: Transmit Descriptor Address Pointer Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR84: DMA Address Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR85: DMA Address Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
CSR88: Chip ID Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
CSR89: Chip ID Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
CSR92: Ring Length Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
CSR100: Bus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR116: OnNow Power Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
CSR122: Advanced Feature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
CSR124: Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
CSR125: MAC Enhanced Configuration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Bus Configuration Registers (BCRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
BCR0: Master Mode Read Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
BCR1: Master Mode Write Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
BCR2: Miscellaneous Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
BCR4: LED0 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
BCR5: LED1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
BCR6: LED2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Am79C978
9
BCR7: LED3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
BCR9: Full-Duplex Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
BCR16: I/O Base Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
BCR17: I/O Base Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
BCR18: Burst and Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
BCR19: EEPROM Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
BCR20: Software Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
BCR22: PCI Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
BCR23: PCI Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
BCR24: PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
BCR25: SRAM Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
BCR26: SRAM Boundary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
BCR27: SRAM Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
BCR28: Expansion Bus Port Address Lower (Used for Flash/EPROM and SRAM Accesses) . . . .166
BCR29: Expansion Port Address Upper (Used for Flash/EPROM Accesses). . . . . . . . . . . . . . . . .167
BCR30: Expansion Bus Data Port Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
BCR31: Software Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
BCR32: PHY Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
BCR33: PHY Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
BCR34: PHY Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
BCR35: PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
BCR36: PCI Power Management Capabilities (PMC) Alias Register . . . . . . . . . . . . . . . . . . . . . . .172
BCR37: PCI DATA Register 0 (DATA0) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
BCR38: PCI DATA Register 1 (DATA1) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
BCR39: PCI DATA Register 2 (DATA2) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
BCR40: PCI DATA Register 3 (DATA3) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
BCR41: PCI DATA Register 4 (DATA4) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
BCR42: PCI DATA Register 5 (DATA5) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
BCR43: PCI DATA Register 6 (DATA6) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
BCR44: PCI DATA Register 7 (DATA7) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
BCR45: OnNow Pattern Matching Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
BCR46: OnNow Pattern Matching Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
BCR47: OnNow Pattern Matching Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
BCR48: LED4 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
BCR49: PHY Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
BCR50-BCR55: Reserved Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
1 Mbps HomePNA PHY Internal Registers 179
HPR0: HomePNA PHY MII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
HPR1: HomePNA PHY MII Status (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
HPR2 and HPR3: HomePNA PHY MII PHY ID (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . .181
HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7). . . . . . . . . . . . . . . . . . . . . . . . . .181
Reserved Registers: HPR8 - HPR15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
HPR16: HomePNA PHY Control (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
HPR17: HomePNA Status Control (Register 17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19) . . . . . . . . . . . . . . . . . . . . .183
HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21) . . . . . . . . . . . . . . . . . . . . 184
HPR22: HomePNA PHY AID (Register 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
HPR23: HomePNA PHY Noise Control (Register 23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
HPR24: HomePNA PHY Noise Control 2 (Register 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
HPR25: HomePNA PHY Noise Statistics (Register 25). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
HPR26: HomePNA PHY Event Status (Register 26). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
HPR27: HomePNA PHY Event Status (Register 27). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
HPR28: HomePNA PHY ISBI Control (Register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
HPR29: HomePNA PHY TX Control (Register 29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
HPR30: 1 Mbps HomePNA PHY Drive Level Control Test Register (Register 30) . . . . . . . . . . . . .187
HPR31: 1 Mbps HomePNA PHY Analog Control Register (Register 31) . . . . . . . . . . . . . . . . . . . .187
10BASE-T PHY Management Registers (TBRs) 188
TBR0: 10BASE-T PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
TBR1: 10BASE-T Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
TBR2 and TBR3: 10BASE-T PHY Identifier (Registers 2 and 3). . . . . . . . . . . . . . . . . . . . . . . . . . 191
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TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . .192
TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . . . . . . . .193
TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . . . . . . . . 194
TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7) . . . . . . . . . . . . . . . . . . . . . . .194
Reserved Registers (Registers 8-15, 18, 20-23, and 25-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16). . . . . . . . . . . . . . . . . 195
TBR17: 10BASE-T PHY Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . 196
TBR19: 10BASE-T PHY Management Extension Register (Register 19) . . . . . . . . . . . . . . . . . . . 197
Reserved Register: 10BASE-T Configuration Register (Register 22) . . . . . . . . . . . . . . . . . . . . . . .197
Reserved Register: 10BASE-T Carrier Status Register (Register 23). . . . . . . . . . . . . . . . . . . . . . .197
TBR24: 10BASE-T Summary Status Register (Register 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
RDRA and TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
LADRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
PADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
RMD0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
RMD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
RMD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
RMD3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
TMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
TMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
TMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
TMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
10BASE-T PHY Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
1 Mbps HomePNA PHY Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
REGISTER PROGRAMMING SUMMARY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
Am79C978 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE
SPECIFIED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
10BASE-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
External Clock (XTAL) Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
External Clock (Oscillator) Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
PECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
10BASE-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . .228
SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
PQL144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
PQR160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
APPENDIX A: ALTERNATIVE METHOD FOR INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
APPENDIX B: LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT . . . . . . . . . . . . . . . . . . . B-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDEX-1
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LIST OF FIGURES
Figure 1. Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 2. Frame Format at the MII Interface Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 3. Slave Configuration Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 4. Slave Configuration Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 5. Slave Read Using I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 6. Slave Write Using Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7. Expansion ROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 8. Disconnect of Slave Cycle When Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 9. Disconnect of Slave Burst Transfer - No Host Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 10. Disconnect of Slave Burst Transfer - Host Inserts Wait States. . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Address Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Slave Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 14. Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 15. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 17. Burst Write Transfer (EXTREQ = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 18. Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 19. Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 20. Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 21. Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 22. Preemption During Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23. Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 24. Master Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 25. Initialization Block Read In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 26. Initialization Block Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 27. Descriptor Ring Read In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 28. Descriptor Ring Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 29. Descriptor Ring Write In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 30. Descriptor Ring Write In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 31. FIFO Burst Write at Start of Unaligned Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 32. FIFO Burst Write at End of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 33. 16-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 34. 32-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 35. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 36. IEEE 802.3 Frame and Length Field Transmission Order . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 37. HomePNA PHY Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 38. AID Symbol Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 39. AID Symbol Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 40. Transmit Data Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 41. Receive Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 42. RLL 25 Coding Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 43. Block Diagram No SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 44. Block Diagram Low Latency Receive Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 45. LED Control Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 46. OnNow Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 47. Pattern Match RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 48. NAND Tree Circuitry (160 PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 49. NAND Tree Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 50. 10BASE-T Transmit and Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 51. Address Match Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 52. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 53. PMD Interface Timing (PECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Figure 54. 10 Mbps Transmit (TX±) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
Figure 55. 10 Mbps Receive (RX±) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
Figure 56. Normal and Tri-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 57. CLK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 58. CLK Waveform for 3.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
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Figure 59. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 60. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 61. Output Tri-State Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 62. EEPROM Read Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 63. Automatic PREAD EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 64. JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 65. JTAG (IEEE 1149.1) Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 66. Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 67. Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 68. MDC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 69. Management Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 70. Management Data Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure B-1. LAPP Timeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Figure B-2. LAPP 3 Buffer Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Figure B-3. LAPP Timeline for Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
Figure B-4. LAPP 3 Buffer Grouping for Two-interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
LIST OF TABLES
Table 1. Interrupt Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 2. External Clock/Crystal Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 3. PCI Device ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 4. PCI Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5. Slave Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 6. Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7. Master Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8. Descriptor Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 9. Descriptor Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 10. Receive Address Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 11. HomePNA PHY Pulse Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 12. Access ID Symbol Pulse Positions and Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 13. Blanking Interval Speed Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 14. Master Station Control Word Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 15. MII Control Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 16. EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 17. LED Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 18. IEEE 1149.1 Supported Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 19. BSR Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 20. Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 21. NAND Tree Pin Sequence (160 PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 22. NAND Tree Pin Sequence (144 TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 24. PCI Configuration Space Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 25. I/O Map in Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 26. Legal I/O Accesses in Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 27. I/O Map in DWord I/O Mode (DWIO = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 28. Legal I/O Accesses in Double Word I/O Mode (DWIO =1). . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 29. Auto-Negotiation Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 30. Loopback Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 31. Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 32. Receive Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 33. Transmit Start Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 34. Transmit Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 35. BCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 36. ROMTNG Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 37. PHY Select Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 38. EEDET Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 39. Interface Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 40. Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 41. SRAM_BND Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 42. EBCS Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 43. CLK_FAC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Am79C978
13
Table 44. FMDC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 45. APDW Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 46. HPR0: HomePNA PHY MII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 47. HPR1: HomePNA PHY MII Status (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 48. HPR2 and HPR3: HomePNA PHY MII ID (Registers 2 and 3). . . . . . . . . . . . . . . . . . . . . .
Table 49. HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7) . . . . . . . . . . . . . . . . . . .
Table 50. HPR16: HomePNA PHY Control (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 51. HPR17: HomePNA Status Control (Register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 52. HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19). . . . . . . . . . . . . . .
Table 53. HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21) . . . . . . . . . . . . . .
Table 54. HPR22: HomePNA PHY AID (Register 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 55. HPR23: HomePNA PHY Noise Control (Register 23) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 56. HPR24: HomePNA PHY Noise Control 2 (Register 24). . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 57. HPR25: HomePNA PHY Noise Statistics (Register 25) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 58. HPR26: HomePNA PHY Event Status (Register 26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 59. HPR27: HomePNA PHY Event Status (Register 27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 60. HPR8: HomePNA PHY ISBI Control (Register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 61. HPR29: HomePNA PHY TX Control (Register 29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 62. HPR30: HomePNA PHY Drive Level Control Test Register (Register 30) . . . . . . . . . . . . .
Table 63. HPR31: HomePNA PHY Analog Control Register (Register 31) . . . . . . . . . . . . . . . . . . . .
Table 64. Am79C978 10BASE-T PHY Management Register Set . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 65. TBR0: 10BASE-T PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 66. TBR1: 10BASE-T PHY Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 67. TBR2: 10BASE-T PHY Identifier (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 68. TBR3: 10BASE-T PHY Identifier (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 69. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . .
Table 70. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page
Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 71. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Next Page
Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 72. TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . .
Table 73. TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7) . . . . . . . . . . . . . . . .
Table 74. TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16) . . . . . . . . . . .
Table 75. TBR17: 10BASE-T PHY Control/Status Register (Register 17). . . . . . . . . . . . . . . . . . . . .
Table 76. TBR19: 10BASE-T PHY Management Extension Register (Register 19) . . . . . . . . . . . . .
Table 77. TBR24: 10BASE-T Summary Status Register (Register 24) . . . . . . . . . . . . . . . . . . . . . . .
Table 78. Initialization Block (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 79. Initialization Block (SSIZE32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 80. R/TLEN Decoding (SSIZE32 = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 81. R/TLEN Decoding (SSIZE32 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 82. Receive Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 83. Receive Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 84. Receive Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 85. Transmit Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 86. Transmit Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 87. Transmit Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 88. PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 89. Control and Status Registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 90. Bus Configuration Registers (BCRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 91. 10BASE-T PHY Management Registers (TBRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 92. 1 Mbps HomePNA PHY Management Registers (HPRs) . . . . . . . . . . . . . . . . . . . . . . . . .
Table 93. Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 94. Bus Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table A-1. Registers for Alternative Initialization Method (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Am79C978
169
169
179
180
181
181
182
183
183
184
184
184
185
185
186
186
186
187
187
187
188
189
190
191
191
192
193
193
194
194
195
196
197
197
198
198
199
199
200
200
200
203
203
203
207
208
212
213
214
215
217
A-1
RELATED AMD PRODUCTS
Part No.
Description
Controllers
Am79C90
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Integrated Controllers
Am79C930
PCnet™-Mobile Single Chip Wireless LAN Media Access Controller
Am79C940B
Media Access Controller for Ethernet (MACE™)
Am79C961A
PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus
Am79C965A
PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses
Am79C970A
PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus
Am79C971
PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
Am79C972
PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
Manchester Encoder/Decoder
Am7992B
Serial Interface Adapter (SIA)
Physical Layer Devices (Single-Port)
Am7996
IEEE 802.3/Ethernet/Cheapernet Transceiver (TAP)
Am79761
Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD)
Am79C98
Twisted Pair Ethernet Transceiver (TPEX)
Am79C100
Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am79C873
10/100 Mbps Ethernet Physical Layer Transceiver (NetPHY™-1)
Physical Layer Devices (Multi-Port)
Am79C871
Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™)
Am79C988B
Quad Integrated Ethernet Transceiver (QuIET™)
Am79C989
Quad Ethernet Switching Transceiver (QuEST™)
Integrated Repeater/Hub Devices
Am79C981
Integrated Multiport Repeater Plus (IMR+)
Am79C982
Basic Integrated Multiport Repeater (bIMR)
Am79C983A
Integrated Multiport Repeater 2 (IMR2™)
Am79C984A
Enhanced Integrated Multiport Repeater (eIMR™)
Am79C985
Enhanced Integrated Multiport Repeater Plus (eIMR+™)
Am79C987
Hardware Implemented Management Information Base (HIMIB™)
Am79C978
15
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
C/BE3
AD24
AD25
VSSB
AD26
VDD_PCI
AD27
AD28
AD29
AD30
VSS
VSSB
AD31
VDD_PCI
REQ
GNT
PCI_CLK
RST
INTA
PG
VDD
TDI
VSSB
TDO
VDDB
TMS
TCK
PME
VSS
EECS
VSSB
EESK/LED1
LED2
VDDB
EEDI/LED0
EEDO/LED3
CONNECTION DIAGRAM (144 TQFP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Am79C978
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
RXDVDDRX
RX+
DVSSX
TXDVDDTX
TX+
DVDDD
IREF
DVSSD
DVSSA
DVDDA
PHY_RST
DVDDA_HR
VSSB
VDDB
HRTRXP
VDDHR
HRTRXN
VSSHR
VDDCO
XTAL1
XTAL2
VSS
VDD
XCLK/XTAL
LED4
MDIO
VSSB
MDC
RXD3
RXD2
VDDB
RXD1
RXD0
VSS
AD11
VDD_PCI
AD10
AD9
AD8
C/BE0
VSSB
AD7
VDD_PCI
AD6
AD5
VDD
AD4
AD3
VSSB
AD2
VDD_PCI
AD1
AD0
VSS
VDD
CRS
VSSB
COL
TXD3
TXD2
TXD1
VDD
VDDB
TXD0
TX_EN
TX_CLK
VSSB
RX_ER
RX_CLK
RX_DV
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IDSEL
AD23
VSSB
AD22
VDD_PCI
AD21
AD20
VDD
AD19
AD18
VSSB
AD17
VDD_PCI
AD16
C/BE2
VSS
FRAME
IRDY
VSSB
TRDY
VDD_PCI
DEVSEL
STOP
VDD
PERR
SERR
VSSB
PAR
VDD_PCI
C/BE1
AD15
VSS
AD14
AD13
VSSB
AD12
22206B-2
16
Am79C978
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
NC
NC
C/BE3
AD24
AD25
VSSB
AD26
VDD_PCI
AD27
AD28
AD29
AD30
VSS
VSSB
AD31
VDD_PCI
REQ
GNT
PCI_CLK
RST
INTA
PG
VDD
TDI
VSSB
TDO
VDDB
TMS
TCK
PME
VSS
EECS
VSSB
EESK/LED1
LED2
VDDB
EEDI/LED0
EEDO/LED3
NC
NC
CONNECTION DIAGRAM (160 PQFP)
Am79C978
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
RXDVDDRX
RX+
DVSSX
TXDVDDTX
TX+
DVDDD
IREF
DVSSD
DVSSA
DVDDA
PHY_RST
DVDDA_HR
VSSB
VDDB
HRTRXP
VDDHR
HRTRXN
VSSHR
VDDCO
XTAL1
XTAL2
VSS
VDD
XCLK/XTAL
LED4
MDIO
VSSB
MDC
RXD3
RXD2
VDDB
RXD1
RXD0
VSS
NC
NC
NC
NC
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
AD11
VDD_PCI
AD10
AD9
AD8
C/BE0
VSSB
AD7
VDD_PCI
AD6
AD5
VDD
AD4
AD3
VSSB
AD2
VDD_PCI
AD1
AD0
VSS
VDD
CRS
VSSB
COL
TXD3
TXD2
TXD1
VDD
VDDB
TXD0
TX_EN
TX_CLK
VSSB
RX_ER
RX_CLK
RX_DV
NC
NC
NC
NC
IDSEL
AD23
VSSB
AD22
VDD_PCI
AD21
AD20
VDD
AD19
AD18
VSSB
AD17
VDD_PCI
AD16
C/BE2
VSS
FRAME
IRDY
VSSB
TRDY
VDD_PCI
DEVSEL
STOP
VDD
PERR
SERR
VSSB
PAR
VDD_PCI
C/BE1
AD15
VSS
AD14
AD13
VSSB
AD12
NC
NC
22206B-3
Am79C978
17
PIN DESIGNATIONS (PQL144)
Listed By Pin Number
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
1
2
IDSEL
AD23
37
38
AD11
VDD_PCI
73
74
VSS
RXD0
109
110
EEDO/LED3
EEDI/LED0
3
4
VSSB
AD22
39
40
AD10
AD9
75
76
RXD1
VDDB
111
112
VDDB
LED2
5
6
VDD_PCI
AD21
41
42
AD8
C/BE0
77
78
RXD2
RXD3
113
114
EESK/LED1
VSSB
7
8
AD20
VDD
43
44
VSSB
AD7
79
80
MDC
VSSB
115
116
EECS
VSS
9
10
AD19
AD18
45
46
VDD_PCI
AD6
81
82
MDIO
LED4
117
118
PME
TCK
11
12
VSSB
AD17
47
48
AD5
VDD
83
84
XCLK/XTAL
VDD
119
120
TMS
VDDB
13
14
VDD_PCI
AD16
49
50
AD4
AD3
85
86
VSS
XTAL2
121
122
TDO
VSSB
15
16
C/BE2
VSS
51
52
VSSB
AD2
87
88
XTAL1
VDDCO
123
124
TDI
VDD
17
18
FRAME
IRDY
53
54
VDD_PCI
AD1
89
90
VSSHR
HRTRXN
125
126
PG
INTA
19
20
VSSB
TRDY
55
56
AD0
VSS
91
92
VDDHR
HRTRXP
127
128
RST
PCI_CLK
21
VDD_PCI
57
VDD
93
VDDB
129
GNT
22
23
DEVSEL
STOP
58
59
CRS
VSSB
94
95
VSSB
DVDDA_HR
130
131
REQ
VDD_PCI
24
25
VDD
PERR
60
61
COL
TXD3
96
97
PHY_RST
DVDDA
132
133
AD31
VSSB
26
27
SERR
VSSB
62
63
TXD2
TXD1
98
99
DVSSA
DVSSD
134
135
VSS
AD30
28
29
PAR
VDD_PCI
64
65
VDD
VDDB
100
101
IREF
DVDDD
136
137
AD29
AD28
30
31
C/BE1
AD15
66
67
TXD0
TX_EN
102
103
TX+
DVDDTX
138
139
AD27
VDD_PCI
32
33
VSS
AD14
68
69
TX_CLK
VSSB
104
105
TXDVSSX
140
141
AD26
VSSB
34
35
AD13
VSSB
70
71
RX_ER
RX_CLK
106
107
RX+
DVDDRX
142
143
AD25
AD24
36
AD12
72
RX_DV
108
RX-
144
C/BE3
18
Am79C978
PIN DESIGNATIONS (PQR160)
Listed By Pin Number
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
1
2
NC
NC
41
42
NC
NC
81
82
NC
NC
121
122
NC
NC
3
4
IDSEL
AD23
43
44
AD11
VDD_PCI
83
84
NC
NC
123
124
EEDO/LED3
EEDI/LED0
5
6
VSSB
AD22
45
46
AD10
AD9
85
86
VSS
RXD0
125
126
VDDB
LED2
7
8
VDD_PCI
AD21
47
48
AD8
C/BE0
87
88
RXD1
VDDB
127
128
EESK/LED1
VSSB
9
10
AD20
VDD
49
50
VSSB
AD7
89
90
RXD2
RXD3
129
130
EECS
VSS
11
12
AD19
AD18
51
52
VDD_PCI
AD6
91
92
MDC
VSSB
131
132
PME
TCK
13
14
VSSB
AD17
53
54
AD5
VDD
93
94
MDIO
LED4
133
134
TMS
VDDB
15
16
VDD_PCI
AD16
55
56
AD4
AD3
95
96
XCLK/XTAL
VDD
135
136
TDO
VSSB
17
18
C/BE2
VSS
57
58
VSSB
AD2
97
98
VSS
XTAL2
137
138
TDI
VDD
19
20
FRAME
IRDY
59
60
VDD_PCI
AD1
99
100
XTAL1
VDDCO
139
140
PG
INTA
21
VSSB
61
AD0
101
VSSHR
141
RST
22
23
TRDY
VDD_PCI
62
63
VSS
VDD
102
103
HRTRXN
VDDHR
142
143
PCI_CLK
GNT
24
25
DEVSEL
STOP
64
65
CRS
VSSB
104
105
HRTRXP
VDDB
144
145
REQ
VDD_PCI
26
27
VDD
PERR
66
67
COL
TXD3
106
107
VSSB
DVDDA_HR
146
147
AD31
VSSB
28
29
SERR
VSSB
68
69
TXD2
TXD1
108
109
PHY_RST
DVDDA
148
149
VSS
AD30
30
31
PAR
VDD_PCI
70
71
VDD
VDDB
110
111
DVSSA
DVSSD
150
151
AD29
AD28
32
33
C/BE1
AD15
72
73
TXD0
TX_EN
112
113
IREF
DVDDD
152
153
AD27
VDD_PCI
34
35
VSS
AD14
74
75
TX_CLK
VSSB
114
115
TX+
DVDDTX
154
155
AD26
VSSB
36
37
AD13
VSSB
76
77
RX_ER
RX_CLK
116
117
TXDVSSX
156
157
AD25
AD24
38
39
AD12
NC
78
79
RX_DV
NC
118
119
RX+
DVDDRX
158
159
C/BE3
NC
40
NC
80
NC
120
RX-
160
NC
Am79C978
19
PIN DESIGNATIONS (PQL144)
Listed By Group
Pin Name
Pin Function
Type
Voltage
Driver
No. of
Pins
HomePNA PHY Network Ports
HRTXRXP/N
Receive/Transmit Data
I/O
3.3
NA
2
XTAL1
Crystal Input (20 MHz XTAL/60 MHz CLK)
I
3.3
-
1
XTAL2
Crystal Output (20 MHz XTAL)
O
3.3
XTAL
1
XCLK/XTAL
Oscillator/Crystal Select
I
3.3
-
1
10BASE-T Network Ports
TX±
Serial Transmit Data
O
3.3
NA
2
RX±
Serial Receive Data
I
3.3
-
2
IREF
Tied to GND via a 12 kΩ 1% resistor
I
3.3
-
1
PHY_RST
Buffered PCI RST signal
O
3.3
OMII1
1
TX_CLK
MII Transmit Clock
I
3.3
-
1
TXD[3:0]
MII Transmit Data
O
3.3
OMII1
4
TX_EN
MII Transmit Enable
O
3.3
OMII1
1
RX_CLK
MII Receive Clock
I
3.3
-
1
RXD[3:0]
MII Receive Data
I
3.3
-
4
RX_ER
MII Receive Error
I
3.3
-
1
RX_DV
MII Receive Data Valid
I
3.3
-
1
MDC
MII Management Data Clock
O
3.3
OMII2
1
MDIO
MII Management Data I/O
I/O
3.3
TSMII
1
CRS
Carrier Sense
I
3.3
-
1
COL
Collision
I
3.3
-
1
PME
Power Management Event
O
3.3
OD6
1
PG
Power Good
I
3.3
-
1
PCI_CLK
CPU Clock
I
3.3/5
-
1
C/BE[3:0]
Bus Command Byte Enable
I/O
3.3/5
TS3
4
AD[31:0]
Address/Data
I/O
3.3/5
TS3
32
DEVSEL
Device Select
I/O
3.3/5
STS6
1
FRAME
Cycle Frame
I/O
3.3/5
STS6
1
GNT
Bus Grant
I
3.3/5
-
1
IDSEL
Initialization Device Select
I
3.3/5
-
1
INTA
Interrupt
O
3.3/5
OD6
1
IRDY
Initiator Ready
I/O
3.3/5
STS6
1
PAR
Parity
I/O
3.3/5
STS6
1
PERR
Parity Error
I/O
3.3/5
STS6
1
REQ
Bus Request
O
3.3/5
TS3
1
RST
Reset
I
3.3/5
-
1
SERR
System Error
I/O
3.3/5
OD6
1
MII
Magic Packet
Host CPU Interface
20
Am79C978
Pin Name
Pin Function
Type
Voltage
Driver
No. of
Pins
STOP
Stop
I/O
3.3/5
STS6
1
TRDY
Target Ready
I/O
3.3/5
STS6
1
EEPROM/LED Interface
EECS
Chip Select
O
3.3
O6
1
EEDI/LED0
Data In/LED0
I/O
3.3
LED
1
EESK/LED1
Serial Clock/LED1
O
3.3
LED
1
LED2
LED2
O
3.3
LED
1
EEDO/LED3
Data Out/LED3
O
3.3
LED
1
LED4
LED4
O
3.3
LED
1
Test Access Port Interface (JTAG)
TCLK
Test Clock
I
3.3
-
1
TMS
Test Mode Select
I
3.3
-
1
TDI
Test Data In
I
3.3
-
1
TDO
Test Data Out
O
3.3
TS6
1
DVDDTX
Transceiver Digital Power
P
3.3
-
1
DVDDRX
Transceiver Digital Power
P
3.3
-
1
VDD_PCI
Digital power for the PCI bus
P
3.3
-
9
VDDB
Digital power for the PCI bus
P
3.3
-
5
VDD
Digital power
P
3.3
-
7
VDDHR
Digital power for HomePNA PHY
P
3.3
-
1
DVDDA
Transceiver Analog Power
P
3.3
-
1
DVDDD
Transceiver Digital Power
P
3.3
-
1
VDDCO
Crystal Oscillator Power
P
3.3
-
1
DVDDA_HR
Transceiver Analog Power
P
3.3
-
1
DVSSD
Transceiver Digital Ground
G
0
-
1
DVSSA
Transceiver Analog Ground
G
0
-
1
DVSSX
Transceiver Ground
G
0
-
1
VSSB
Digital I/O Ground
G
0
-
15
VSS
Digital Ground
G
0
-
7
VSSHR
HomePNA PHY Analog Ground
G
0
-
1
Power/Ground
Am79C978
21
PIN DESIGNATIONS (PQR160)
Listed By Group
Pin Name
Pin Function
Type
Voltage
Driver
No. of
Pins
HomePNA PHY Network Ports
HRTXRXP/N
Receive/Transmit Data
I/O
3.3
NA
2
XTAL1
Crystal Input (20 MHz XTAL/60 MHz CLK)
I
3.3
-
1
XTAL2
Crystal Output (20 MHz XTAL)
O
3.3
XTAL
1
XCLK/XTAL
Oscillator/Crystal Select
I
3.3
-
1
10BASE-T Network Ports
TX±
Serial Transmit Data
O
3.3
NA
2
RX±
Serial Receive Data
I
3.3
-
2
IREF
Tied to GND via a 12 kΩ 1% resistor
I
3.3
-
1
PHY_RST
Buffered PCI RST signal
O
3.3
OMII1
1
TX_CLK
MII Transmit Clock
I
3.3
-
1
TXD[3:0]
MII Transmit Data
O
3.3
OMII1
4
TX_EN
MII Transmit Enable
O
3.3
OMII1
1
RX_CLK
MII Receive Clock
I
3.3
-
1
RXD[3:0]
MII Receive Data
I
3.3
-
4
RX_ER
MII Receive Error
I
3.3
-
1
RX_DV
MII Receive Data Valid
I
3.3
-
1
MDC
MII Management Data Clock
O
3.3
OMII2
1
MDIO
MII Management Data I/O
I/O
3.3
TSMII
1
CRS
Carrier Sense
I
3.3
-
1
COL
Collision
I
3.3
-
1
PME
Power Management Event
O
3.3
OD6
1
PG
Power Good
I
3.3
-
1
PCI_CLK
CPU Clock
I
3.3/5
-
1
C/BE[3:0]
Bus Command Byte Enable
I/O
3.3/5
TS3
4
AD[31:0]
Address/Data
I/O
3.3/5
TS3
32
DEVSEL
Device Select
I/O
3.3/5
STS6
1
FRAME
Cycle Frame
I/O
3.3/5
STS6
1
GNT
Bus Grant
I
3.3/5
-
1
IDSEL
Initialization Device Select
I
3.3/5
-
1
INTA
Interrupt
O
3.3/5
OD6
1
IRDY
Initiator Ready
I/O
3.3/5
STS6
1
PAR
Parity
I/O
3.3/5
STS6
1
PERR
Parity Error
I/O
3.3/5
STS6
1
REQ
Bus Request
O
3.3/5
TS3
1
RST
Reset
I
3.3/5
-
1
SERR
System Error
I/O
3.3/5
OD6
1
MII
Magic Packet
Host CPU Interface
22
Am79C978
Pin Name
Pin Function
Type
Voltage
Driver
No. of
Pins
STOP
Stop
I/O
3.3/5
STS6
1
TRDY
Target Ready
I/O
3.3/5
STS6
1
EEPROM/LED Interface
EECS
Chip Select
O
3.3
O6
1
EEDI/LED0
Data In/LED0
I/O
3.3
LED
1
EESK/LED1
Serial Clock/LED1
O
3.3
LED
1
LED2
LED2
O
3.3
LED
1
EEDO/LED3
Data Out/LED3
O
3.3
LED
1
LED4
LED4
O
3.3
LED
1
Test Access Port Interface (JTAG)
TCLK
Test Clock
I
3.3
-
1
TMS
Test Mode Select
I
3.3
-
1
TDI
Test Data In
I
3.3
-
1
TDO
Test Data Out
O
3.3
TS6
1
DVDDTX
Transceiver Digital Power
P
3.3
-
1
DVDDRX
Transceiver Digital Power
P
3.3
-
1
VDD_PCI
Digital power for the PCI bus
P
3.3
-
9
VDDB
Digital power for the PCI bus
P
3.3
-
5
VDD
Digital power
P
3.3
-
7
VDDHR
Digital power for HomePNA PHY
P
3.3
-
1
DVDDA
Transceiver Analog Power
P
3.3
-
1
DVDDD
Transceiver Digital Power
P
3.3
-
1
VDDCO
Crystal Oscillator Power
P
3.3
-
1
DVDDA_HR
Transceiver Analog Power
P
3.3
-
1
DVSSD
Transceiver Digital Ground
G
0
-
1
DVSSA
Transceiver Analog Ground
G
0
-
1
DVSSX
Transceiver Ground
G
0
-
1
VSSB
Digital I/O Ground
G
0
-
15
VSS
Digital Ground
G
0
-
7
VSSHR
HomePNA PHY Analog Ground
G
0
-
1
Power/Ground
Am79C978
23
PIN DESIGNATIONS
Listed By Driver Type
The following table describes the various types of output drivers used in the Am79C978 controller. All IOL and
IOH values shown in the table apply to 3.3 V signaling.
Driver Name
A sustained tri-state signal is a low active signal that is
driven high for one clock period before it is left floating.
TX is a differential output driver. Its characteristics and
those of XTAL2 output are described in the DC CHARACTERISTICS section.
Type
IOL (mA)
IOH (mA)
Load (pF)
LED
LED
12
0.4
50
O6
Totem Pole
6
0.4
50
OD6
Open Drain
6
NA
50
TS3
Tri-State
3
2
50
TS6
Tri-State
6
2
50
STS6
Sustained Tri-State
6
2
50
OMII1
Tri-State
4
4
50
OMII2
Tri-State
4
4
390
TSMII
Tri-State
4
4
470
For typical 5 V DC characteristics, please refer to DC
Characteristics Over Commercial Operating Ranges
section.
24
Am79C978
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am79C978
K\V
C
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and formed in a tray
TEMPERATURE RANGE
C = Commercial (0° C to +70° C)
PACKAGE TYPE
K = Plastic Quad Flat Pack (PQR160)
V = Thin Quad Flat Pack (PQL144)
SPEED OPTION
Not applicable
DEVICE NUMBER/DESCRIPTION
Am79C978
PCnet-Home
Single-Chip 1/10 Mbps PCI Home Networking Controller
Valid Combinations
Am79C978
KC\W
VC\W
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid
combinations and to check on newly released
combinations.
Am79C978
25
PIN DESCRIPTIONS
PCI Interface
AD[31:0]
Address and Data
support a clock frequency of 0 MHz after certain precautions are taken to ensure data integrity. This clock
or a derivation is not used to drive any network functions.
Input/Output
Address and data are multiplexed on the same bus interface pins. During the first clock of a transaction,
AD[31:0] contain a physical address (32 bits). During
the subsequent clocks, AD[31:0] contain data. Byte ordering is little endian by default. AD[7:0] are defined as
the least significant byte (LSB) and AD[31:24] are defined as the most significant byte (MSB). For FIFO data
transfers, the Am79C978 controller can be programmed for big endian byte ordering. See CSR3, bit 2
(BSWP) for more details.
During the address phase of the transaction, when the
Am79C978 controller is a bus master, AD[31:2] will add r e s s t h e a c t i v e D o u bl e Wo r d ( D Wo r d ) . T h e
Am79C978 controller always drives AD[1:0] to ’00’ during the address phase indicating linear burst order.
When the Am79C978 controller is not a bus master, the
AD[31:0] lines are continuously monitored to determine
if an address match exists for slave transfers.
During the data phase of the transaction, AD[31:0] are
driven by the Am79C978 controller when performing
bus master write and slave read operations. Data on
AD[31:0] is latched by the Am79C978 controller when
performing bus master read and slave write operations.
When RST is active, AD[31:0] are inputs for NAND tree
testing.
C/BE[3:0]
Bus Command and Byte Enables
Input/Output
When RST is active, C/BE[3:0] are inputs for NAND
tree testing.
PCI_CLK
Input
This clock is used to drive the system bus interface and
the internal buffer management unit. All bus signals are
sampled on the rising edge of PCI_CLK and all parameters are defined with respect to this edge. The
Am79C978 controller normally operates over a frequency range of 10 to 33 MHz on the PCI bus due to
networking demands. The Am79C978 controller will
26
DEVSEL
Device Select
Input/Output
The Am79C978 controller drives DEVSEL LOW when
it detects a transaction that selects the device as a target. The device samples DEVSEL to detect if a target
claims a transaction that the Am79C978 controller has
initiated.
When RST is active, DEVSEL is an input for NAND tree
testing.
FRAME
Cycle Frame
Input/Output
FRAME is driven by the Am79C978 controller when it
is the bus master to indicate the beginning and duration
of a transaction. FRAME is asserted to indicate a bus
transaction is beginning. FRAME is asserted while data
transfers continue. FRAME is deasserted before the
final data phase of a transaction. When the Am79C978
controller is in slave mode, it samples FRAME to determine the address phase of a transaction.
When RST is active, FRAME is an input for NAND tree
testing.
GNT
Bus Grant
Bus command and byte enables are multiplexed on the
same bus interface pins. During the address phase of
the transaction, C/BE[3:0] define the bus command.
During the data phase, C/BE[3:0] are used as byte enables. The byte enables define which physical byte
lanes carry meaningful data. C/BE0 applies to byte 0
(AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The
function of the byte enables is independent of the byte
ordering mode (BSWP, CSR3, bit 2).
Clock
When RST is active, PCI_CLK is an input for NAND
tree testing.
Input
This signal indicates that the access to the bus has
been granted to the Am79C978 controller.
The Am79C978 controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts GNT
without an active REQ from the Am79C978 controller,
the device will drive the AD[31:0], C/BE[3:0], and PAR
lines.
When RST is active, GNT is an input for NAND tree
testing.
IDSEL
Initialization Device Select
Input
This signal is used as a chip select for the Am79C978
controller during configuration read and write transactions.
When RST is active, IDSEL is an input for NAND tree
testing.
Am79C978
INTA
IRDY
Interrupt Request
Output
An attention signal which indicates that one or more of
the following status flags is set: EXDINT, IDON, MERR,
MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT,
TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MREINT, and STINT. Each status flag has either a mask or
an enable bit which allows for suppression of INTA assertion. Table 1 shows the flag descriptions. By default
INTA is an open-drain output. For applications that
need a high-active edge-sensitive interrupt signal, the
INTA pin can be configured for this mode by setting INTLEVEL (BCR2, bit 7) to Table 1.
When RST is active, INTA is the output for NAND tree
testing.
Table 1. Interrupt Flags
Initiator Ready
Input/Output
IRDY indicates the ability of the initiator of the transaction to complete the current data phase. IRDY is used
in conjunction with TRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the Am79C978 controller is a bus master, it asserts IRDY during all write data phases to indicate that
valid data is present on AD[31:0]. During all read data
phases, the device asserts IRDY to indicate that it is
ready to accept the data.
When the Am79C978 controller is the target of a transaction, it checks IRDY during all write data phases to
determine if valid data is present on AD[31:0]. During
all read data phases, the device checks IRDY to determine if the initiator is ready to accept the data.
Name
Description
Mask Bit
Interrupt Bit
EXDINT
Excessive
Deferral
CSR5, bit 6
CSR5, bit 7
IDON
Initialization
Done
CSR3, bit 8
CSR0, bit 8
MERR
Memory Error
CSR3, bit 11
CSR0, bit 11
MISS
Missed Frame CSR3, bit 12
CSR0, bit 12
MFCO
Missed Frame
Count OverCSR4, bit 8
flow
CSR4, bit 9
MPINT
Magic Packet
Interrupt
CSR5, bit 3
CSR5, bit 4
RCVCCO
Receive
Collision Count CSR4, bit 4
Overflow
CSR4, bit 5
Parity is even parity across AD[31:0] and C/BE[3:0].
When the Am79C978 controller is a bus master, it generates parity during the address and write data phases.
It checks parity during read data phases. When the
Am79C978 controller operates in slave mode, it checks
parity during every address phase. When it is the target
of a cycle, it checks parity during write data phases and
it generates parity during read data phases.
RINT
Receive
Interrupt
CSR3, bit 10
CSR0, bit 10
When RST is active, PAR is an input for NAND tree
testing.
SINT
System Error
CSR5, bit 10
CSR5, bit 11
PERR
TINT
Transmit
Interrupt
CSR3, bit 9
CSR0, bit 9
Parity Error
TXSTRT
Transmit Start CSR4, bit 2
CSR4, bit 3
UINT
User Interrupt
CSR4, bit 7
CSR4, bit 6
MCCINT
MII
Management
Command
Complete
Interrupt
CSR7, bit 4
CSR7, bit 5
MPDTINT
MII PHY Detect
CSR7, bit 0
Transition
Interrupt
CSR7, bit 1
MAPINT
MII Auto-Poll
Interrupt
CSR7, bit 7
MREINT
MII
Management
CSR7, bit 8
Frame Read
Error Interrupt
CSR7, bit 9
STINT
Software Timer
CSR7, bit 10
Interrupt
CSR7, bit 11
CSR7, bit 6
When RST is active, IRDY is an input for NAND tree
testing.
PAR
Parity
Input/Output
Input/Output
During any slave write transaction and any master read
transaction, the Am79C978 controller asserts PERR
when it detects a data parity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to 1. During any master write transaction,
the Am79C978 controller monitors PERR to see if the
target reports a data parity error.
When RST is active, PERR is an input for NAND tree
testing.
REQ
Bus Request
Input/Output
The Am79C978 controller asserts REQ pin as a signal
that it wishes to become a bus master. REQ is driven
high when the Am79C978 controller does not request
the bus. In Power Management mode, the REQ pin will
not be driven.
Am79C978
27
When RST is active, REQ is an input for NAND tree
testing.
RST
Reset
Input
When RST is asserted LOW and the PG pin is HIGH,
then the Am79C978 controller performs an internal
system reset of the type H_RESET
(HARDWARE_RESET, see section on RESET). RST
must be held for a minimum of 30 clock periods. While
in the H_RESET state, the Am79C978 controller will
disable or deassert all outputs. RST may be asynchronous to clock when asserted or deasserted.
When the PG pin is LOW, RST disables all of the PCI
pins except the PME pin.
When RST is LOW and PG is HIGH, NAND tree testing
is enabled.
When RST is active, TRDY is an input for NAND tree
testing.
Magic Packet Interface
PME
Power Management Event
Output, Open Drain
PME is an output that can be used to indicate that a
power management event (a Magic Packet, an OnNow
pattern match, or a change in link state) has been detected. The PME pin is asserted when either
1. PME_STATUS and PME_EN are both 1,
2. PME_EN_OVR and MPMAT are both 1, or
SERR
System Error
When the Am79C978 controller is the target of a transaction, it asserts TRDY during all read data phases to
indicate that valid data is present on AD[31:0]. During
all write data phases, the device asserts TRDY to indicate that it is ready to accept the data.
3. PME_EN_OVR and LCDET are both 1.
Output
During any slave transaction, the Am79C978 controller
asserts SERR when it detects an address parity error,
and reporting of the error is enabled by setting PERREN (PCI Command register, bit 6) and SERREN (PCI
Command register, bit 8) to 1.
The PME signal is asynchronous with respect to the
PCI clock. See the Power Saving Mode section for detailed description.
PG
Power Good
Input
By default SERR is an open-drain output. For component test, it can be programmed to be an active-high
totem-pole output.
The PG pin has two functions: (1) it puts the device into
Magic Packet mode, and (2) it blocks any resets when
the PCI bus power is off.
When RST is active, SERR is an input for NAND tree
testing.
When PG is LOW and either MPPEN or MPMODE is
set to 1, the device enters Magic Packet mode.
STOP
When PG is LOW, a LOW assertion of the PCI RST pin
will only cause the PCI interface pins (except for PME)
to be put in the high impedance state. The internal logic
will ignore the assertion of RST.
Stop
Input/Output
In slave mode, the Am79C978 controller drives the
STOP signal to inform the bus master to stop the current transaction. In bus master mode, the Am79C978
controller checks STOP to determine if the target wants
to disconnect the current transaction.
When PG is HIGH, assertion of the PCI RST pin
causes the controller logic to be reset and the configuration information to be loaded from the EEPROM.
When RST is active, STOP is an input for NAND tree
testing.
Note: PG input should be kept high during NAND tree
testing.
TRDY
Board Interface
Target Ready
Input/Output
TRDY indicates the ability of the target of the transaction to complete the current data phase. Wait states are
inserted until both IRDY and TRDY are asserted simultaneously. A data phase is completed on any clock
when both IRDY and TRDY are asserted.
When the Am79C978 controller is a bus master, it
checks TRDY during all read data phases to determine
if valid data is present on AD[31:0]. During all write data
phases, the device checks TRDY to determine if the
target is ready to accept the data.
28
Note: Before programming the LED pins, see the
description of LEDPE in BCR2, bit 12.
LED0
LED0
Output
This output is designed to directly drive an LED. By default, LED0 indicates an active link connection. This pin
can also be programmed to indicate other network status (see BCR4). The LED0 pin polarity is programmable, but by default it is active LOW. When the LED0 pin
polarity is programmed to active LOW, the output is an
open drain driver. When the LED0 pin polarity is pro-
Am79C978
grammed to active HIGH, the output is a totem pole
driver.
larity is programmed to active HIGH, the output is a
totem pole driver.
Note: The LED0 pin is multiplexed with the EEDI pin.
Special attention must be given to the external circuitry
attached to this pin. When this pin is used to drive an
LED while an EEPROM is used in the system, then
buffering may be required between the LED3 pin and
the LED circuit. If an LED circuit were directly attached
to this pin, it may create an IOL requirement that could
not be met by the serial EEPROM attached to this pin.
If no EEPROM is included in the system design or low
current LEDs are used, then the LED3 signal may be
directly connected to an LED without buffering. For
more details regarding LED connection, see the section on LED Support.
LED1
LED1
Output
This output is designed to directly drive an LED. By default, LED1 indicates receive activity on the network.
This pin can also be programmed to indicate other network status (see BCR5). The LED1 pin polarity is programmable, but by default, it is active LOW. When the
LED1 pin polarity is programmed to active LOW, the
output is an open drain driver. When the LED1 pin polarity is programmed to active HIGH, the output is a
totem pole driver.
Note: The LED1 pin is multiplexed with the EESK pin.
The LED1 pin is also used during EEPROM AutoDetection to determine whether or not an EEPROM is
present at the Am79C978 controller interface. At the
last rising edge of CLK while RST is active LOW, LED1
is sampled to determine the value of the EEDET bit in
BCR19. It is important to maintain adequate hold time
around the rising edge of the CLK at this time to ensure
a correctly sampled value. A sampled HIGH value
means that an EEPROM is present, and EEDET will be
set to 1. A sampled LOW value means that an EEPROM is not present, and EEDET will be set to 0. See
the EEPROM Auto-Detection section for more details.
If no LED circuit is to be attached to this pin, then a pullup or pull-down resistor must be attached in order to
select the EEDET setting.
WARNING: The input signal level of LED1 must be insured for correct EEPROM detection before the deassertion of RST.
LED2
LED2
Output
This output is designed to directly drive an LED. This
pin can be programmed to indicate various network
status (see BCR6). The LED2 pin polarity is programmable, but by default it is active LOW. When the LED2
pin polarity is programmed to active LOW, the output is
an open drain driver. When the LED2 pin polarity is programmed to active HIGH, the output is a totem pole
driver.
LED3
LED3
Output
This output is designed to directly drive an LED. By default, LED3 indicates transmit activity on the network.
This pin can also be programmed to indicate other network status (see BCR7). The LED3 pin polarity is programmable, but by default it is active LOW. When the
LED3 pin polarity is programmed to active LOW, the
output is an open drain driver. When the LED3 pin po-
Note: The LED3 pin is multiplexed with the EEDO pin.
LED4
LED4
Output
This output is designed to directly drive an LED. This
pin can be programmed to indicate various network
status (see BCR48). The LED4 pin polarity is programmable, but by default it is active LOW. When the LED4
pin polarity is programmed to active LOW, the output is
an open drain driver. When the LED4 pin polarity is programmed to active HIGH, the output is a totem pole
driver.
EEPROM Interface
EECS
EEPROM Chip Select
Output
This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EECS is connected to the EEPROM’s chip select
pin. It is controlled by either the Am79C978 controller
during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to
BCR19, bit 2.
EEDI
EEPROM Data In
Output
This pin is designed to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface protocol. EEDI is connected to the EEPROM’s data input
pin. It is controlled by either the Am79C978 controller
during command portions of a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 0.
Note: The EEDI pin is multiplexed with the LED0 pin.
EEDO
EEPROM Data Out
Input
This pin is designed to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface protocol. EEDO is connected to the EEPROM’s data output pin. It is controlled by either the Am79C978
Am79C978
29
controller during command portions of a read of the entire EEPROM, or indirectly by the host system by reading from BCR19, bit 0.
Note: The EEDO pin is multiplexed with the LED3 pin.
EESK
EEPROM Serial Clock
Output
This pin is designed to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface protocol. EESK is connected to the EEPROM’s clock pin.
It is controlled by either the Am79C978 controller directly during a read of the entire EEPROM, or indirectly
by the host system by writing to BCR19, bit 1.
Note: The EESK pin is multiplexed with the LED1 pin.
The EESK pin is also used during EEPROM AutoDetection to determine whether or not an EEPROM is
present at the Am79C978 controller interface. At the
rising edge of the last CLK edge while RST is asserted,
EESK is sampled to determine the value of the EEDET
bit in BCR19. A sampled HIGH value means that an
EEPROM is present, and EEDET will be set to 1. A
sampled LOW value means that an EEPROM is not
present, and EEDET will be set to 0. See the EEPROM
Auto-Detection section for more details.
If no LED circuit is to be attached to this pin, then a pullup or pull-down resistor must be attached instead to resolve the EEDET setting.
WARNING: The input signal level of EESK must be
valid for correct EEPROM detection before the deassertion of RST.
MII Interface
RX_CLK
Receive Clock
Input
RX_CLK is a clock input that provides the timing reference for the transfer of the RX_DV, RXD[3:0], and
RX_ER signals into the Am79C978 device. RX_CLK
must provide a nibble rate clock (25% of the network
data rate). Hence, when the Am79C978 device is operating at 10 Mbps, it provides an RX_CLK frequency of
2.5 MHz, and at 100 Mbps it provides an RX_CLK frequency of 25 MHz.
RXD[3:0]
Receive Data
Input
RXD[3:0] is the nibble-wide MII-compatible receive
data bus. Data on RXD[3:0] is sampled on every rising
edge of RX_CLK while RX_DV is asserted. RXD[3:0] is
ignored while RX_DV is de-asserted.
RX_DV
Receive Data Valid
Input
RX_CLK is synchronous to the receive data. In order
for a frame to be fully received by the Am79C978 device, RX_DV must be asserted prior to the RX_CLK rising edge, when the first nibble of the Start of Frame
Delimiter is driven on RXD[3:0], and must remain asserted until after the rising edge of RX_CLK, when the
last nibble of the CRC is driven on RXD[3:0]. RX_DV
must then be deasserted prior to the RX_CLK rising
edge which follows this final nibble. RX_DV transitions
are synchronous to RX_CLK rising edges.
CRS
Receive Carrier Sense
CRS is an input that indicates that a non-idle medium,
due either to transmit or receive activity, has been detected.
COL
Collision
Input
COL is an input that indicates that a collision has been
detected on the network medium.
RX_ER
Receive Error
Input
RX_ER is an input that indicates that the MII transceiver device has detected a coding error in the receive
data frame currently being transferred on the RXD[3:0]
pins. If RX_ER is asserted while RX_DV is asserted, a
CRC error will be indicated in the receive descriptor for
the incoming receive frame. RX_ER is ignored while
RX_DV is deasserted. Special code groups generated
on RXD while RX_DV is deasserted are ignored (e.g.,
bad SSD in TX and idle in T4). RX_ER transitions are
synchronous to RX_CLK.
TX_CLK
Transmit Clock
Input
TX_CLK is a clock input that provides the timing reference for the transfer of the TXD[3:0] and TX_ER signals into the Am79C978 device. TX_CLK must provide
a nibble rate clock (25% of the network data rate).
Hence, when the Am79C978 device is operating at 10
Mbps, it provides an TX_CLK frequency of 2.5 MHz,
and at 100 Mbps it provides an RX_CLK frequency of
25 MHz.
TXD[3:0]
Transmit Data
Output
TXD[3:0] is the nibble-wide MII-compatible transmit
data bus. Valid data is generated on TXD[3:0] on every
rising edge of TX_CLK while TX_EN is asserted. While
TX_EN is deasserted, TXD[3:0] values are driven to 0.
TXD[3:0] transitions are synchronous to rising edges of
TX_CLK.
RX_DV is an input used to indicate that valid received
data is being presented on the RXD[3:0] pins and
30
Input
Am79C978
TX_EN
Transmit Enable
TDO
Output
Test Data Out
Output
TX_EN indicates when the Am79C978 device is presenting valid transmit nibbles on the MII TXD[3:0] bus.
While TX_EN is asserted, the Am79C978 device generates TXD[3:0] and TX_ER on TX_CLK rising edges.
TX_EN is asserted with the first nibble of preamble and
remains asserted throughout the duration of the packet
until it is deasserted prior to the first TX_CLK following
the final nibble of the frame. TX_EN transitions are synchronous to TX_CLK.
TDO is the test data output path from the Am79C978
controller. The pin is tri-stated when the JTAG port is inactive.
MDC
Ethernet Network Interfaces
TX±
Management Data Clock
Output
MDC is the non-continuous clock output that provides
a timing reference for bits on the MDIO pin. During MII
management port operations, MDC runs at a nominal
frequency of 2.5 MHz. When no management operations are in progress, MDC is driven LOW.
If the MII port is not selected, the MDC pin may be left
floating.
MDIO
Management Data Input/Output
Output
Input/
MDIO is a bidirectional MII management port data pin.
MDIO is an output during the header portion of the
management frame transfers and during the data portion of write operations. MDIO is an input during the
data portion of read operations.
If a PHY is attached to the MII port via a MII physical
connector then the MDIO pin should be externally
pulled down to Vss with a 10 kΩ ±5% resistor. If a PHY
is directly attached to the MII pins then the MDIO pin
should be externally pulled up to Vcc with a 10 kΩ ±5%
resistor.
IEEE 1149.1 (1990) Test Access Port
Interface
TCK
Test Clock
TMS
Test Mode Select
Input
A serial input bit stream on the TMS pin is used to define the specific boundary scan test to be executed.
The pin has an internal pull-up resistor.
Serial Transmit Data
Output
These pins carry the transmit output data and are connected to the transmit side of the magnetics module.
RX±
Serial Receive Data
Input
These pins accept the receive input data from the magnetics module.
IREF
Internal Current Reference
Input
This pin serves as a current reference for the integrated 1/10 PHY. It must be connected to VSS through
a 12100-Ω resistor (1%).
PHY_RST
PHY Reset
Output
This output is used to reset the external PHY. This output eliminates the need for a fanout buffer on the PCI
reset (RST) signal, provided polarity control for the
specific PHY used, and prevents the resetting of the
PHY when the PG input is LOW. The output polarity is
determined by the RST_POL (CRS116, bit0).
HomePNA PHY Network Interface
HRTXRXP/HRTXRXN
Input
Serial Receive Data
Input/Output
TCK is the clock input for the boundary scan test mode
operation. It can operate at a frequency of up to 10
MHz. TCK has an internal pull-up resistor.
These pins accept the receive input data from the magnetics module and carry the transmit output data. A
102-Ω resistor should be placed between these pins.
TDI
Clock Interface
XCLK/XTAL
Test Data In
Input
TDI is the test data input path to the Am79C978 controller. The pin has an internal pull-up resistor.
External Clock/Crystal Select
Input
When HIGH, an external 60-MHz clock source is selected bypassing the crystal circuit and clock trippler.
When LOW, a 20-MHz crystal is used instead. The following table illustrates how this pin works.
Am79C978
31
DVDDD
Table 2. External Clock/Crystal Select
10BASE-T PDX Block Power
Input Pin
Output
Pin
XCLK/XTAL
Clock Source
XTAL1
XTAL2
0
20-MHz Crystal
XTAL1
Don’t Care
1
60-MHz Oscillator/
External CLK
Source
Crystal Oscillator In
Input
The internal clock generator utilizes either a 20-MHz
crystal that is attached to pins XTAL1 and XTAL2 or a
60-MHz clock source connected to XTAL1. This pin is
not 5 V tolerant, and the 60 MHz clock source must be
from a 3.3 V source.
XTAL2
Crystal Oscillator Out
This pin supplies power to the 10 Mbps Transceiver
block. It must be connected to a +3.3 V ±300 mV
source. This pin requires careful decoupling to ensure
proper device performance.
DVDDRX, DVDDTX
10BASE-T I/O Buffer Power
XTAL1
Output
The internal clock generator utilizesd a 20-MHz crystal
that is attached to pins XTAL1 and XTAL2.
+3.3 V Power
+3.3 V Power
These pins supply power to the 10BASE-T input/output
buffers. They must be connected to a +3.3 V ±300 mV
source. These pins require careful decoupling to ensure proper device performance.
DVDDA
Analog PLL Power
+3.3 V Power
This pin supplies power to the IREF current reference
circuit and the 10BASE-T analog PLL. They must be
connected to a +3.3 V ±300 mV source. These pins require careful decoupling to ensure proper device performance.
Power Supply
VDDB
DVSSX, DVSSA
I/O Buffer Power (5 Pins)
These pins are the ground connection for the analog
section within the Physical Data Transceiver (PDX)
block.
10BASE-T PDX Analog Ground
+3.3 V Power
These pins are the power supply pins that are used by
the input/output buffer drivers. All VDDB pins must be
connected to a +3.3 V supply.
VDD_PCI
PCI I/O Buffer Power (9 Pins)
+3.3 V Power
Ground
These pins are the ground pins that are used by the
input/output buffer drivers.
VDD
+3.3 V Power
These pins are the power supply pins that are used by
the internal digital circuitry. All VDD pins must be connected to a +3.3 V supply.
VSS
Digital Ground (7 Pins)
Ground
There are seven ground pins that are used by the internal digital circuitry.
32
Ground
This pin is the ground connection for the digital logic
within the PDX block.
VDDCO
Crystal
+3.3 V Power
This pin supplies power to the crystal circuit.
VSSB
Digital Power (7 Pins)
DVSSD
10BASE-T PDX Digital Ground
These pins are the power supply pins that are used by
the PCI input/output buffer drivers (except PME driver).
All VDD_PCI pins must be connected to a +3.3 V supply.
I/O Buffer Ground (15 Pins)
Ground
VDDHR
HomePNA Digital Power
+3.3 V Power
These pins are the digital power supply pins that are
used by the internal digital circuitry for the HomePNA
block. They must be connected to a +3.3 V source.
VSSHR
HomePNA Analog Ground
Ground
This pin is the ground connection for the analog section
within the HomePNA block.
DVDDA_HR
HomePNA Analog Power
+3.3 V Power
This pin supplies power to the analog section of the
HomePNA block. It must be connected to a +3.3 V
±300 mV source. This pin requires careful decoupling
to ensure proper device performance.
Am79C978
BASIC FUNCTIONS
System Bus Interface
The Am79C978 controller is designed to operate as a
bus master during normal operations. Some slave I/O
accesses to the Am79C978 controller are required in
normal operations as well. Initialization of the
Am79C978 controller is achieved through a combination of PCI Configuration Space accesses, bus slave
accesses, bus master accesses, and an optional read
of a serial EEPROM that is performed by the
Am79C978 controller. The EEPROM read operation is
performed through the 93C46 EEPROM interface. The
ISO 8802-3 (IEEE/ANSI 802.3) Ethernet Address may
reside within the serial EEPROM. Some controller configuration registers may also be programmed by the
EEPROM read operation.
The Address PROM, on-chip board-configuration registers, and the Ethernet controller registers occupy 32
bytes of address space. I/O and memory mapped I/O
accesses are supported. Base Address registers in the
PCI configuration space allow locating the address
space on a wide variety of starting addresses.
Software Interface
The software interface to the Am79C978 controller is
divided into three parts. One part is the PCI configuration registers used to identify the Am79C978 controller
and to setup the configuration of the device. The setup
information includes the I/O or memory mapped I/O
base address, mapping of the Expansion ROM, and
the routing of the Am79C978 controller interrupt channel. This allows for a jumperless implementation.
The second portion of the software interface is the direct access to the I/O resources of the Am79C978 controller. The Am79C978 controller occupies 32 bytes of
address space that must begin on a 32-byte block
boundary. The address space can be mapped into I/O
or memory space (memory mapped I/O). The I/O Base
Address Register in the PCI Configuration Space controls the start address of the address space if it is
mapped to I/O space. The Memory Mapped I/O Base
Address Register controls the start address of the address space if it is mapped to memory space. The 32byte address space is used by the software to program
the Am79C978 controller operating mode, to enable
and disable various features, to monitor operating status, and to request particular functions to be executed
by the Am79C978 controller.
The third portion of the software interface is the descriptor and buffer areas that are shared between the
software and the Am79C978 controller during normal
network operations. The descriptor area boundaries
are set by the software and do not change during nor-
mal network operations. There is one descriptor area
for receive activity, and there is a separate area for
transmit activity. The descriptor space contains relocatable pointers to the network frame data, and it is used
to transfer frame status from the Am79C978 controller
to the software. The buffer areas are locations that hold
frame data for transmission or that accept frame data
that has been received.
Network Interfaces
The Am79C978 controller provides all of the PHY layer
functions for 10 Mbps (10BASE-T) or 1 Mbps. The
Am79C978 controller supports both half-duplex and
full-duplex operation on the network MII interface.
Media Independent Interface
The Am79C978 controller fully supports the MII according to the IEEE 802.3u standard. This Reconciliation Sublayer interface allows a variety of PHYs
(100BASE-TX, 100BASE-FX, 100BASE-T4,
100BASE-T2, 10BASE-T, etc.) to be attached to the
Am79C978 device without future upgrade problems.
The MII interface is a 4-bit (nibble) wide data path interface that runs at 25 MHz for 100-Mbps networks or 2.5
MHz for 10-Mbps networks. The interface consists of
two independent data paths, receive (RXD(3:0)) and
transmit (TXD(3:0)), control signals for each data path
(RX_ER, RX_DV, TX_EN), network status signals
(COL, CRS), clocks (RX_CLK, TX_CLK) for each data
path, and a two-wire management interface (MDC and
MDIO). See Figure 2.
MII Transmit Interface
The MII transmit clock is generated by the external
PHY and is sent to the Am79C978 controller on the
TX_CLK input pin. The clock can run at 25 MHz or 2.5
MHz, depending on the speed of the network to which
the external PHY is attached. The data is a nibble-wide
(4 bits) data path, TXD(3:0), from the Am79C978 controller to the external PHY and is synchronous to the
rising edge of TX_CLK. The transmit process starts
when the Am79C978 controller asserts the TX_EN,
which indicates to the external PHY that the data on
TXD(3:0) is valid.
Normally, unrecoverable errors are signaled through
the MII to the external PHY with the TX_ER output pin.
The external PHY will respond to this error by generating a TX coding error on the current transmitted frame.
The Am79C978 controller does not use this method of
signaling errors on the transmit side. The Am79C978
controller will invert the FCS on the last byte generating
an invalid FCS. The TX_ER pin should be tied to GND.
Am79C978
33
4
RXD(3:0)
RX_DV
Receive Signals
RX_ER
Am79C978
MII Interface
RX_CLK
CRS
COL
Network Status Signals
4
TXD(3:0)
TX_EN
Transmit Signals
TX_CLK
MDC
Management Port Signals
MDIO
22206B-4
Figure 1.
Media Independent Interface
MII Receive Interface
MII Network Status Interface
The MII receive clock is also generated by the external
PHY and is sent to the Am79C978 controller on the
RX_CLK input pin. The clock will be the same frequency as the TX_CLK but will be out of phase and can
run at 25 MHz or 2.5 MHz, depending on the speed of
the network to which the external PHY is attached.
The MII also provides signals that are consistent and
necessary for IEEE 802.3 and IEEE 802.3u operation.
These signals are CRS (Carrier Sense) and COL (Collision Sense). Carrier Sense is used to detect non-idle
activity on the network. Collision Sense is used to indicate that simultaneous transmission has occurred in a
half-duplex network.
The RX_CLK is a continuous clock during the reception
of the frame, but can be stopped for up to two RX_CLK
periods at the beginning and the end of frames, so that
the external PHY can sync up to the network data traffic
necessary to recover the receive clock. During this
time, the external PHY may switch to the TX_CLK to
maintain a stable clock on the receive interface. The
Am79C978 controller will handle this situation with no
loss of data. The data is a nibble-wide (4 bits) data
path, RXD(3:0), from the external PHY to the
Am79C978 controller and is synchronous to the rising
edge of RX_CLK.
The receive process starts when RX_DV is asserted.
RX_DV will remain asserted until the end of the receive
frame. The Am79C978 controller requires CRS (Carrier Sense) to toggle in between frames in order to receive them properly. Errors in the currently received
frame are signaled across the MII by the RX_ER pin.
RX_ER can be used to signal special conditions out of
band when RX_DV is not asserted. Two defined out-ofband conditions for this are the 100BASE-TX signaling
of bad Start of Frame Delimiter and the 100BASE-T4
indication of illegal code group before the receiver has
synched to the incoming data. The Am79C978 controller will not respond to these conditions. All out of band
conditions are currently treated as NULL events.
34
MII Management Interface
The MII provides a two-wire management interface so
that the Am79C978 controller can control and receive
status from external PHY devices.
The Network Port Manager copies the PHYAD after the
Am79C978 controller reads the EEPROM and uses it
to communicate with the external PHY. (Refer also to
the BCR49 description). The PHY address must be
programmed into the EEPROM prior to starting the
Am79C978 controller. This is necessary so that the internal management controller can work autonomously
from the software driver and can always know where to
access the external PHY. The Am79C978 controller is
unique by offering direct hardware support of the external PHY device without software support. The PHY address of 1Fh is reserved and should not be used. To
access the internal or external PHYs, the software
driver must have knowledge of the PHY’s address before attempting to address it.
The MII Management Interface uses the MII Control,
Address, and Data registers (BCR32, 33, 34) to control
an d c om mu ni c at e to th e e x te r na l PH Y s. Th e
Am79C978 controller generates MII management
frames to the external PHY through the MDIO pin synchronous to the rising edge of the Management Data
Clock (MDC) based on a combination of writes and
reads to these registers.
Am79C978
MII Management Frames
MII management frames are automatically generated
by the Am79C978 controller and conform to the MII
clause in the IEEE 802.3u standard.
The start of the frame may be a preamble of 32 ones
(unless bit 6 of register equals 1) and guarantees that
all of the external PHYs are synchronized on the same
interface. See Figure 2. Loss of synchronization is pos-
Preamble
1111....1111
32
Bits
sible due to the hot-plugging capability of the exposed
MII.
The IEEE 802.3 specification allows you to drop the
preamble, if after reading the MII Status Register from
the external PHY you can determine that the external
PHY will support Preamble Suppression (BCR34, bit
6). After having a valid MII Status Register read, the
Am79C978 controller will then drop the creation of the
preamble stream until a reset occurs, receives a read
error, or the external PHY is disconnected.
ST
01
OP
10 Rd
01 Wr
PHY
Address
Register
Address
TA
Z0 Rd
10 Wr
Data
Idle
Z
2
Bits
2
Bits
5
Bits
5
Bits
2
Bits
16
Bits
1
Bit
22206B-5
Figure 2.
Frame Format at the MII Interface Connection
This is followed by a start field (ST) and an operation
field (OP). The operation field (OP) indicates whether
the Am79C978 controller is initiating a read or write operation. This is followed by the external PHY address
(PHYAD) and the register address (REGAD) programmed in BCR33. The PHY address of 1D,1E, and
1F are reserved and should not be used. The external
PHY may have a larger address space starting at 10h
- 1Fh. This is the address range set aside by the IEEE
as vendor usable address space and will vary from
vendor to vendor. This field is followed by a bus turnaround field. During a read operation, the bus turnaround field is used to determine if the external PHY is
responding correctly to the read request or not. The
Am79C978 controller will tri-state the MDIO for both
MDC cycles.
During the second cycle, if the external PHY is synchronized to the Am79C978 controller, the external
PHY will drive a 0. If the external PHY does not drive a
0, the Am79C978 controller will signal a MREINT
(CSR7, bit 9) interrupt, if MREINTE (CSR7, bit 8) is set
to a 1, indicating the Am79C978 controller had an MII
management frame read error and that the data in
BCR34 is not valid. The data field to/from the external
PHY is read or written into the BCR34 register. The last
field is an IDLE field that is necessary to give ample
time for drivers to turn off before the next access. The
Am79C978 controller will drive the MDC to 0 and tristate the MDIO anytime the MII Management Port is
not active.
To help to speed up the reading and of writing the MII
management frames to the external PHY, the MDC can
be sped up to 5 MHz by setting the FMDC bits in
BCR32. The IEEE 802.3 specification requires use of
the 2.5-MHz clock rate, but 5 MHz is also available for
the user. The 5-MHz clock rate can be used for an exposed MII with one external PHY attached. The 2.5MHz clock rate is intended to be used when multiple
external PHYs are connected to the MII Management
Port or if compliance to the IEEE 802.3u standard is required.
Auto-Poll External PHY Status Polling
As defined in the IEEE 802.3 standard, the external
PHY attached to the Am79C978 controller’s MII has no
way of communicating important timely status information back to Am79C978 controller. The Am79C978
controller has no way of knowing that an external PHY
has undergone a change in status without polling the
MII status register. To prevent problems from occurring
with i nadequate host or software polling, the
Am79C978 controller will Auto-Poll when APEP
(BCR32, bit 11) is set to 1 to insure that the most current information is available. See 10BASE-T PHY Management Registers for the bit descriptions of the MII
Status Register. The contents of the latest read from
the external PHY will be stored in a shadow register in
the Auto-Poll block. The first read of the MII Status
Register will just be stored, but subsequent reads will
be compared to the contents already stored in the
shadow register. If there has been a change in the contents of the MII Status Register, a MAPINT (CSR7, bit
5) interrupt will be generated on INTA if the MAPINTE
(CSR7, bit 4) is set to 1. The Auto-Poll features can be
disabled if software driver polling is required.
Am79C978
35
The Auto-Poll’s frequency of generating MII management frames can be adjusted by setting of the APDW
bits (BCR32, bits 10-8). The delay can be adjusted
from 0 MDC periods to 2048 MDC periods. Auto-Poll
by default will only read the MII Status register of the
currently active PHY.
Network Port Manager
If the PHY is active, the Network Port Manager will request status from the selected PHY by generating MII
management frames. These frames will be sent
roughly every 900 ms. These frames are necessary so
that the Network Port Manager can monitor the current
active link and can notify the software if the current link
goes down.
Slave Bus Interface Unit
The slave Bus Interface Unit (BIU) controls all accesses to the PCI configuration space, the Control and
Status Registers (CSR), the Bus Configuration Registers (BCR), and the Address PROM (APROM) locations. Table 5 shows the response of the Am79C978
controller to each of the PCI commands in slave mode.
Table 5. Slave Commands
C[3:0]
10BASE-T PHY
The 10BASE-T transceiver incorporates the physical
layer function, including both clock recovery (ENDEC)
and transceiver function. Data transmission over the
10BASE-T medium requires an integrated 10BASE-T
MAU. The transceiver will meet the electrical requirements for 10BASE-T as specified in IEEE 802.3i. The
transmit signal is filtered on the transceiver to reduce
harmonic content per IEEE 802.3i. Since filtering is
performed in silicon, external filtering modules are not
needed. The 10BASE-T PHY transceiver receives 10
Mbps data from the MAC across the internal MII at 2.5
million nibbles per second (parallel), or 10 million bits
per second (serial) for 10BASE-T. It then Manchester
encodes the data before transmission to the network.
The RX+ pins are differential twisted-pair receivers.
When properly terminated, each receiver will meet the
electrical requirements for 10BASE-T as specified in
IEEE 802.3i. Each receiver has internal filtering and
does not r equir e external fil ter modules. The
10BASE-T PHY transceiver receives a Manchester
coded 10BASE-T data stream from the medium. It then
recovers the clock and decodes the data. The data
stream is presented at the internal MII interface in parallel format.
Table 3. PCI Device ID
Vendor ID
Device ID
Rev ID (offset 0x08)
1022
2001
51
Table 4. PCI Software Configuration
36
CSR89
CSR88
JTAG
00001262h
00006003h
1262 6003h
Use
0000
Interrupt
Acknowledge
Not used
0001
Special Cycle
Not used
0010
I/O Read
Read of CSR, BCR, APROM,
and Reset registers
0011
I/O Write
Write to CSR, BCR, and
APROM
0100
Reserved
0101
Reserved
0110
Memory Read
Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers. Read of the
Expansion Bus
0111
Memory Write
Memory mapped I/O write of
CSR, BCR, and APROM
1000
Reserved
1001
Reserved
1010
Configuration
Read
Read of the Configuration
Space
1011
Configuration
Write
Write to the Configuration
Space
1100
Memory Read
Multiple
Aliased to Memory Read
1101
Dual Address
Cycle
Not used
1110
Memory Read
Line
Aliased to Memory Read
1111
Memory Write
Invalidate
Aliased to Memory Write
PCI and JTAG Configuration Information
The PCI device ID and software configuration information is as follows in Table 3 and Table 4.
Command
Slave Configuration Transfers
The host can access the PCI configuration space with
a c on f i g u r a t i o n r e a d o r w r i t e c o m m a n d . T h e
Am79C978 controller will assert DEVSEL during the
address phase when IDSEL is asserted, AD[1:0] are
both 0, and the access is a configuration cycle. AD[7:2]
select the DWord location in the configuration space.
The Am79C978 controller ignores AD[10:8], because it
Am79C978
is a single function device. AD[31:11] are “don't cares.”
See Table 6.
Table 6. Slave Configuration Transfers
AD31
AD11
AD10
AD8
AD7
AD2
Don’t care
Don’t care
DWord
Index
AD1
AD0
0
0
The active bytes within a DWord are determined by the
byte enable signals. Eight-bit, 16-bit, and 32-bit transfers are supported. DEVSEL is asserted two clock cyc le s a fte r t he ho s t ha s as s e r te d F RA ME. A ll
c onf ig ur at io n c y cl es a re of fi xe d l en gth . Th e
Am79C978 controller will assert TRDY on the third
clock of the data phase.
The Am79C978 controller does not support burst transfers for access to configuration space. When the host
keeps FRAME asserted for a second data phase, the
Am79C978 controller will disconnect the transfer.
When the host tries to access the PCI configuration
space while the automatic read of the EEPROM after
H_RESET (see section on RESET) is on-going, the
Am79C978 controller will terminate the access on the
PCI bus with a disconnect/retry response.
The Am79C978 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit
7), which is hardwired to 1. The Am79C978 controller
is capable of detecting a configuration cycle even when
its address phase immediately follows the data phase
of a transaction to a different target without any idle
state in-between. There will be no contention on the
DEVSEL, TRDY, and STOP signals, since the
Am79C978 controller asserts DEVSEL on the second
clock after FRAME is asserted (medium timing).
Slave I/O Transfers
After the Am79C978 controller is configured as an I/O
device by setting IOEN (for regular I/O mode) or
MEMEN (for memory mapped I/O mode) in the PCI
Command register, it starts monitoring the PCI bus for
access to its CSR, BCR, or EEPROM locations. If configured for regular I/O mode, the Am79C978 controller
will look for an address that falls within its 32 bytes of I/
O address space (starting from the I/O base address).
The Am79C978 controller asserts DEVSEL if it detects
an address match and the access is an I/O cycle. If
configured for memory mapped I/O mode, the
Am79C978 controller will look for an address that falls
within its 32 bytes of memory address space (starting
from the memory mapped I/O base address). The
Am79C978 controller asserts DEVSEL if it detects an
address match and the access is a memory cycle.
DEVSEL is asserted two clock cycles after the host has
asserted FRAME. See Figure 3 and Figure 4.
The Am79C978 controller will not assert DEVSEL if it
detects an address match and the PCI command is not
of the correct type. In memory mapped I/O mode, the
Am79C978 controller aliases all accesses to the I/O resources of the command types Memory Read Multiple
and Memory Read Line to the basic Memory Read command. All accesses of the type Memory Write and Invalidate are aliased to the basic Memory Write
command. Eight-bit, 16-bit, and 32-bit non-burst transactions are supported. The Am79C978 controller decodes all 32 address lines to determine which I/O
resource is accessed.
The typical number of wait states added to a slave I/O
or memory mapped I/O read or write access on the part
of the Am79C978 controller is six to seven clock cycles,
depending upon the relative phases of the internal Buffer Management Unit clock and the CLK signal, since
the internal Buffer Management Unit clock is a divideby-two version of the CLK signal.
The Am79C978 controller does not support burst transfers for access to its I/O resources. When the host keeps
FRAME asserted for a second data phase, the
Am79C978 controller will disconnect the transfer.
The Am79C978 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit
7), which is hardwired to 1. The Am79C978 controller
is capable of detecting an I/O or a memory-mapped I/
O cycle even when its address phase immediately follows the data phase of a transaction to a different target,
without any idle state in-between. There will be no contention on the DEVSEL, TRDY, and STOP signals, since
the Am79C978 controller asserts DEVSEL on the second clock after FRAME is asserted (medium timing).
See Figure 5 and Figure 6.
Am79C978
37
CLK
CLK
1
2
3
4
5
7
6
1
FRAME
3
4
5
6
FRAME
AD
ADDR
C/BE
1010
PAR
2
DATA
AD
ADDR
C/BE
1011
BE
PAR
DATA
BE
PAR
PAR
PAR
PAR
IRDY
IRDY
TRDY
TRDY
DEVSEL
DEVSEL
STOP
STOP
IDSEL
IDSEL
DEVSEL is sampled
22206B-6
22206B-7
Figure 3. Slave Configuration Read
Figure 4.
Slave Configuration Write
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
ADDR
C/BE
0010
PAR
DATA
BE
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
22206B-8
Figure 5.
38
Slave Read Using I/O Command
Am79C978
7
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
ADDR
DATA
C/BE
0111
BE
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
22206B-9
Figure 6.
Slave Write Using Memory Command
Expansion ROM Transfers
pansion ROM is present when it reads the ROM signature 55H (byte 0) and AAH (byte 1).
Since the Am79C978 device does not have expansion
ROM capabilities, PCI configuration offset must be set
to 30H = 0.
Slave Cycle Termination
There are three scenarios besides normal completion
of a transaction where the Am79C978 controller is the
target of a slave cycle and it will terminate the access.
During the boot procedure, the system will try to find an
Expansion ROM. A PCI system assumes that an Ex-
CLK
1
2
3
4
5
48
49
50
51
FRAME
AD
ADDR
C/BE
CMD
PAR
DATA
BE
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
22206B-10
DEVSEL is sampled
Figure 7. Expansion ROM Read
Am79C978
39
Disconnect When Busy
The Am79C978 controller cannot service any slave access while it is reading the contents of the EEPROM.
Simultaneous access is not allowed in order to avoid
conflicts, since the EEPROM is used to initialize some
of the PCI configuration space locations and most of
the BCRs and CSR116. The EEPROM read operation
will always happen automatically after the deassertion
of the RST pin. In addition, the host can start the read
operation by setting the PREAD bit (BCR19, bit 14).
While the EEPROM read is on-going, the Am79C978
controller will disconnect any slave access where it is
the target by asserting STOP together with DEVSEL,
while driving TRDY high. STOP will stay asserted until
the end of the cycle.
CLK
1
2
3
4
5
FRAME
AD
ADDR
DATA
C/BE
CMD
BE
PAR
PAR
PAR
IRDY
A second situation where the Am79C978 controller will
generate a PCI disconnect/retry cycle is when the host
tries to access any of the I/O resources right after having read the Reset register. Since the access generates an internal reset pulse of about 1 ms in length, all
further slave accesses will be deferred until the internal
reset operation is completed. See Figure 8.
TRDY
DEVSEL
STOP
Disconnect Of Burst Transfer
The Am79C978 controller does not support burst access to the configuration space, the I/O resources, or
to the Expansion Bus. The host indicates a burst transaction by keeping FRAME asserted during the data
phase. When the Am79C978 controller sees FRAME
and IRDY asserted in the clock cycle before it wants to
assert TRDY, it also asserts STOP at the same time.
The transfer of the first data phase is still successful,
since IRDY and TRDY are both asserted. See Figure 9.
22206B-11
Figure 8.
Disconnect of Slave Cycle When Busy
CLK
1
2
3
4
5
FRAME
If the host is not yet ready when the Am79C978 controller asserts TRDY, the device will wait for the host to assert IRDY. When the host asserts IRDY and FRAME is
still asserted, the Am79C978 controller will finish the
first data phase by deasserting TRDY one clock later.
At the same time, it will assert STOP to signal a disconnect to the host. STOP will stay asserted until the host
removes FRAME. See Figure 10.
AD
C/BE
PAR
1st DATA
BE
DATA
BE
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
22206B-12
Figure 9. Disconnect of Slave Burst Transfer - No
Host Wait States
40
Am79C978
CLK
1
2
3
4
5
CLK
6
1
2
3
4
5
FRAME
FRAME
AD
C/BE
PAR
1st DATA
BE
DATA
AD
ADDR
1st DATA
C/BE
CMD
BE
BE
PAR
PAR
PAR
PAR
PAR
IRDY
SERR
TRDY
DEVSEL
DEVSEL
22206B-14
STOP
Figure 11. Address Parity Error Response
22206B-13
Figure 10.
Disconnect of Slave Burst Transfer Host Inserts Wait States
Parity Error Response
When the Am79C978 controller is not the current bus
master, it samples the AD[31:0], C/BE[3:0], and the
PAR lines during the address phase of any PCI command for a parity error. When it detects an address parity error, the Am79C978 controller sets PERR (PCI
Status register, bit 15) to 1. When reporting of that error
is enabled by setting SERREN (PCI Command register, bit 8) and PERREN (PCI Command register, bit 6)
to 1, the Am79C978 controller also drives the SERR
signal low for one clock cycle and sets SERR (PCI Status register, bit 14) to 1. The assertion of SERR follows
th e a d dr e s s p h a s e b y t w o c l o c k c y c l e s . T h e
Am79C978 controller will not assert DEVSEL for a PCI
transaction that has an address parity error when PERREN and SERREN are set to 1. See Figure 11.
During the data phase of an I/O write, memory-mapped
I/O write, or configuration write command that selects
the Am79C978 controller as target, the device samples
the AD[31:0] and C/BE[3:0] lines for parity on the clock
edge, and data is transferred as indicated by the assertion of IRDY and TRDY. PAR is sampled in the following clock cycle. If a parity error is detected and
reporting of that error is enabled by setting PERREN
(PCI Command register, bit 6) to 1, PERR is asserted
one clock later. The parity error will always set PERR
(PCI Status register, bit 15) to 1 even when PERREN
is cleared to 0. The Am79C978 controller will finish a
transaction that has a data parity error in the normal
way by asserting TRDY. The corrupted data will be written to the addressed location.
Figure 12 shows a transaction that suffered a parity
error at the time data was transferred (clock 7, IRDY
and TRDY are both asserted). PERR is driven high at
the beginning of the data phase and then drops low due
to the parity error on clock 9, two clock cycles after the
data was transferred. After PERR is driven low, the
Am79C978 controller drives PERR high for one clock
cycle, since PERR is a sustained tri-state signal.
Am79C978
41
CLK
1
2
3
4
5
6
7
8
9
10
FRAME
AD
ADDR
DATA
C/BE
CMD
BE
PAR
PAR
PAR
PERR
IRDY
TRDY
DEVSEL
22206B-15
Figure 12.
Slave Cycle Data Parity Error Response
Master Bus Interface Unit
Table 7.
The master Bus Interface Unit (BIU) controls the acquisition of the PCI bus and all accesses to the initialization block, descriptor rings, and the receive and
transmit buffer memory. Table 7 shows the usage of
PCI commands by the Am79C978 controller in master
mode.
Table 7.
C[3:0]
Master Commands
Command
Use
0000
Interrupt
Acknowledge
Not used
0001
Special Cycle
Not used
0010
I/O Read
Not used
0011
I/O Write
Not used
0100
Reserved
0101
Reserved
1010
Configuration Read Not used
1011
Configuration Write
Not used
1100
Memory Read
Multiple
Read of the transmit
buffer in burst mode
1101
Dual Address Cycle Not used
1110
Memory Read Line
Read of the transmit
buffer in burst mode
1111
Memory Write
Invalidate
Not used
Bus Acquisition
0110
Memory Read
Read of the initialization
block and descriptor
rings
Read of the transmit
buffer in non-burst mode
0111
Memory Write
Write to the descriptor
rings and to the receive
buffer
1000
Reserved
1001
Reserved
42
Master Commands (Continued)
The microcode will determine when a DMA transfer
should be initiated. The first step in any bus master
transfer is to acquire ownership of the bus. This task is
handled by synchronous logic within the BIU. Bus ownership is requested with the REQ signal and ownership
is granted by the arbiter through the GNT signal.
Figure 13 shows the Am79C978 controller bus acquisition. REQ is asserted and the arbiter returns GNT while
ano ther bu s m ast er is tra ns fer ri ng d ata. Th e
Am79C978 controller waits until the bus is idle
(FRAME and IRDY deasserted) before it starts driving
AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted
at clock 5 indicating a valid address and command on
AD[31:0] and C/BE[3:0]. The Am79C978 controller
does not use address stepping which is reflected by
Am79C978
ADSTEP (bit 7) in the PCI Command register being
hardwired to 0.
The Am79C978 controller typically performs more than
one non-burst read transaction within a single bus
mastership period. FRAME is dropped between consecutive non-burst read cycles. REQ stays asserted
until FRAME is asserted for the last transaction. The
Am79C978 controller supports zero wait state read cycles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
Figure 14 shows two non-burst read transactions. The
first transaction has zero wait states. In the second
transaction, the target extends the cycle by asserting
TRDY one clock later.
CLK
1
2
3
4
5
FRAME
AD
ADDR
C/BE
CMD
Am79C978 controller will internally discard unneeded
bytes.
Basic Burst Read Transfer
IRDY
REQ
GNT
22206B-16
Figure 13. Bus Acquisition
In burst mode, the deassertion of REQ depends on the
setting of EXTREQ (BCR18, bit 8). If EXTREQ is
cleared to 0, REQ is deasserted at the same time as
FRAME is asserted. (The Am79C978 controller never
performs more than one burst transaction within a single bus mastership period.) If EXTREQ is set to 1, the
Am79C978 controller does not deassert REQ until it
starts the last data phase of the transaction.
Once asserted, REQ remains active until GNT has become active and independent of subsequent setting of
STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The assertion of H_RESET or S_RESET, however, will cause
REQ to go inactive immediately.
Bus Master DMA Transfers
There are four primary types of DMA transfers. The
Am79C978 controller uses non-burst as well as burst
cycles for read and write access to the main memory.
Basic Non-Burst Read Transfer
By default, the Am79C978 controller uses non-burst
cycles in all bus master read operations. All controller
non-burst read accesses are of the PCI command type
Memory Read (type 6). Note that during a non-burst
read operation, all byte lanes will always be active. The
The Am79C978 controller supports burst mode for all
bus master read operations. The burst mode must be
enabled by setting BREADE (BCR18, bit 6). To allow
burst transfers in descriptor read operations, the
Am79C978 controller must also be programmed to use
SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses
to the initialization block and descriptor ring are of the
PCI command type Memory Read (type 6). Burst read
accesses to the transmit buffer typically are longer than
two data phases. When MEMCMD (BCR18, bit 9) is
cleared to 0, all burst read accesses to the transmit
buffer are of the PCI command type Memory Read Line
(type 14). When MEMCMD (BCR18, bit 9) is set to 1,
all burst read accesses to the transmit buffer are of the
PCI command type Memory Read Multiple (type 12).
AD[1:0] will both be 0 during the address phase indicating a linear burst order. Note that during a burst read
operation, all byte lanes will always be active. The
Am79C978 controller will internally discard unneeded
bytes.
The Am79C978 controller will always perform only a
single burst read transaction per bus mastership period, where transaction is defined as one address
ph as e a nd one or m ul ti pl e d ata ph as es . Th e
Am79C978 controller supports zero wait state read cycles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
Figure 15 shows a typical burst read access. The
Am79C978 controller arbitrates for the bus, is granted
access, reads three 32-bit words (DWord) from the system memory, and then releases the bus. In the example, the memory system extends the data phase of
each access by one wait state. The example assumes
that EXTREQ (BCR18, bit 8) is cleared to 0, therefore,
REQ is deasserted in the same cycle as FRAME is asserted.
Am79C978
43
CLK
1
2
3
4
5
6
7
8
9
11
10
FRAME
DATA
ADDR
AD
0110
C/BE
0000
0110
0000
PAR
PAR
PAR
DATA
ADDR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-17
DEVSEL is sampled
Figure 14. Non-Burst Read Transfer
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
C/BE
DATA
ADDR
1110
PAR
DATA
DATA
0000
PAR
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-18
DEVSEL is sampled
Figure 15. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)
44
Am79C978
Basic Non-Burst Write Transfer
Basic Burst Write Transfer
By default, the Am79C978 controller uses non-burst
cycles in all bus master write operations. All controller
non-burst write accesses are of the PCI command type
Memory Write (type 7). The byte enable signals indicate the byte lanes that have valid data. The
Am79C978 controller typically performs more than one
non-burst write transaction within a single bus mastership period. FRAME is dropped between consecutive
non-burst write cycles. REQ stays asserted until
FRAME is asserted for the last transaction. The
Am79C978 controller supports zero wait state write cycles except with descriptor write transfers. (See the
section Descriptor DMA Transfers for the only exception.) It asserts IRDY immediately after the address
phase.
The Am79C978 controller supports burst mode for all
bus master write operations. The burst mode must be
enabled by setting BWRITE (BCR18, bit 5). To allow
burst transfers in descriptor write operations, the
Am79C978 controller must also be programmed to use
SWSTYLE 3 (BCR20, bits 7-0). All controller burst
write transfers are of the PCI command type Memory
Write (type 7). AD[1:0] will both be 0 during the address
phase indicating a linear burst order. The byte enable
signals indicate the byte lanes that have valid data.
The Am79C978 controller will always perform a single
burst write transaction per bus mastership period,
where transaction is defined as one address phase and
one or multiple data phases. The Am79C978 controller
supports zero wait state write cycles except with the
case of descriptor write transfers. (See the section Descriptor DMA Transfers for the only exception.) The device asserts IRDY immediately after the address phase
and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
Figure 16 shows two non-burst write transactions. The
first transaction has two wait states. The target inserts
one wait state by asserting DEVSEL one clock late and
another wait state by also asserting TRDY one clock
late. The second transaction shows a zero wait state
write cycle. The target asserts DEVSEL and TRDY in
the same cycle as the Am79C978 controller asserts
IRDY.
CLK
1
2
3
4
5
6
7
8
9
10
FRAME
AD
C/BE
ADDR
DATA
ADDR
DATA
0111
BE
0111
BE
PAR
PAR
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-19
DEVSEL is sampled
Figure 16.
Non-Burst Write Transfer
Figure 17 shows a typical burst write access. The
Am79C978 controller arbitrates for the bus, is granted
access, and writes four 32-bit words (DWords) to the
system memory and then releases the bus. In this ex-
Am79C978
45
ample, the memory system extends the data phase of
the first access by one wait state. The following three
data phases take one clock cycle each, which is determined by the timing of TRDY. The example assumes
that EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ
is not deasserted until the next to last data phase is finished.
Disconnect With Data Transfer
Figure 18 shows a disconnection in which one last data
transfer occurs after the target asserted STOP. STOP
is asserted on clock 4 to start the termination sequence. Data is still transferred during this cycle, since
both IRDY and TRDY are asserted. The Am79C978
controller terminates the current transfer with the deassertion of FRAME on clock 5 and of IRDY one clock
later. It finally releases the bus on clock 7. If it wants to
transfer more data, the Am79C978 controller will again
request the bus after two clock cycles. The starting address of the new transfer will be the address of the next
non-transferred data.
Target Initiated Termination
When the Am79C978 controller is a bus master, the cycles it produces on the PCI bus may be terminated by
the target in one of three different ways: disconnect
with data transfer, disconnect without data transfer, and
target abort.
CLK
1
2
3
4
5
6
7
8
DATA
DATA
DATA
PAR
PAR
9
FRAME
AD
C/BE
ADDR
DATA
0111
BE
PAR
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-20
DEVSEL is sampled
Figure 17. Burst Write Transfer (EXTREQ = 1)
46
Am79C978
CLK
1
2
3
4
5
DATA
DATA
6
7
8
9
10
11
FRAME
ADDRi
AD
0111
C/BE
0000
PAR
PAR
ADDRi+8
0111
PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
22206B-21
DEVSEL is sampled
Figure 18.
Disconnect With Data Transfer
Disconnect Without Data Transfer
Figure 19 shows a target disconnect sequence during
which no data is transferred. STOP is asserted on clock
4 without TRDY being asserted at the same time. The
Am79C978 controller terminates the access with the
deassertion of FRAME on clock 5 and of IRDY one
clock cycle later. It finally releases the bus on clock 7.
The Am79C978 controller will again request the bus
after two clock cycles to retry the last transfer. The
starting address of the new transfer will be the address
of the last non-transferred data.
Target Abort
Figure 20 shows a target abort sequence. The target
asserts DEVSEL for one clock. It then deasserts
DEVSEL and asserts STOP on clock 4. A target can
use the target abort sequence to indicate that it cannot service the data transfer and that it does not want
the transaction to be retried. Additionally, the
Am79C978 controller cannot make any assumption
about the success of the previous data transfers in the
current transaction. The Am79C978 controller terminates the current transfer with the deassertion of
FRAME on clock 5 and of IRDY one clock cycle later.
It finally releases the bus on clock 6.
Since data integrity is not guaranteed, the Am79C978
controller cannot recover from a target abort event.
TheAm79C978 controller will reset all CSR locations to
their STOP_RESET values. The BCR and PCI configuration registers will not be cleared. Any on-going network transmission is terminated in an orderly
sequence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
immediately, generating a runt packet. If 512 bits or
more have been transmitted, the message will have the
current FCS inverted and appended at the next byte
boundary to guarantee an FCS error is detected at the
receiving station.
Am79C978
47
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
C/BE
ADDRi
DATA
ADDRi
0111
0000
0111
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
REQ
GNT
22206B-22
DEVSEL is sampled
Figure 19.
Disconnect Without Data Transfer
RTABORT (PCI Status register, bit 12) will be set to
indicate that the Am79C978 controller has received a
target abort. In addition, SINT (CSR5, bit 11) will be set
to 1. When SINT is set, INTA is asserted if the enable
bit SINTE (CSR5, bit 10) is set to 1. This mechanism
can be used to inform the driver of the system error. The
host can read the PCI Status register to determine the
exact cause of the interrupt.
Master Initiated Termination
There are three scenarios besides normal completion
of a transaction where the Am79C978 controller will
terminate the cycles it produces on the PCI bus.
Preemption During Non-Burst Transaction
When the Am79C978 controller performs multiple nonburst transactions, it keeps REQ asserted until the assertion of FRAME for the last transaction. When GNT
is removed, the Am79C978 controller will finish the current transaction and then release the bus. If it is not the
48
last transaction, REQ will remain asserted to regain
bus ownership as soon as possible. See Figure 21.
Preemption During Burst Transaction
When the Am79C978 controller operates in burst
mode, it only performs a single transaction per bus
mastership period, where transaction is defined as one
address phase and one or multiple data phases. The
central arbiter can remove GNT at any time during the
transaction. TheAm79C978 controller will ignore the
deassertion of GNT and continue with data transfers,
as long as the PCI Latency Timer is not expired. When
the Latency Timer is 0 and GNT is deasserted, the
Am79C978 controller will finish the current data phase,
deassert FRAME, finish the last data phase, and release the bus. If EXTREQ (BCR18, bit 8) is cleared to
0, it will immediately assert REQ to regain bus ownership as soon as possible. If EXTREQ is set to 1, REQ
will stay asserted.
Am79C978
CLK
1
2
3
4
5
6
7
FRAME
AD
C/BE
ADDR
DATA
0111
0000
PAR
PAR
TheAm79C978 controller will reset all CSR locations to
their STOP_RESET values. The BCR and PCI configuration registers will not be cleared. Any on-going network transmission is terminated in an orderly
sequence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
immediately, generating a runt packet. If 512 bits or
more have been transmitted, the message will have the
current FCS inverted and appended at the next byte
boundary to guarantee an FCS error is detected at the
receiving station.
RMABORT (in the PCI Status register, bit 13) will be set
to indicate that the Am79C978 controller has terminated its transaction with a master abort. In addition,
SINT (CSR5, bit 11) will be set to 1. When SINT is set,
INTA is asserted if the enable bit SINTE (CSR5, bit 10)
is set to 1. This mechanism can be used to inform the
driver of the system error. The host can read the PCI
Status register to determine the exact cause of the interrupt. See Figure 23.
PAR
IRDY
TRDY
DEVSEL
Parity Error Response
STOP
REQ
GNT
DEVSEL is sampled
22206B-23
Figure 20. Target Abort
During every data phase of a DMA read operation,
when the target indicates that the data is valid by asserting TRDY, the Am79C978 controller samples the
AD[31:0], C/BE[3:0], and the PAR lines for a data parity
error. When it detects a data parity error, the
Am79C978 controller sets PERR (PCI Status register,
bit 15) to 1. When reporting of that error is enabled by
setting PERREN (PCI Command register, bit 6) to 1,
the Am79C978 controller also drives the PERR signal
low and sets DATAPERR (PCI Status register, bit 8) to
1. The assertion of PERR follows the corrupted data/
byte enables by two clock cycles and PAR by one clock
cycle.
When the preemption occurs after the counter has
counted down to 0, the Am79C978 controller will finish
the current data phase, deassert FRAME, finish the
last data phase, and release the bus. Note that it is important for the host to program the PCI Latency Timer
according to the bus bandwidth requirement of the
Am79C978 controller. The host can determine this bus
bandwidth requirement by reading the PCI MAX_LAT
and MIN_GNT registers.
Figure 24 shows a transaction that has a parity error in
the data phase. TheAm79C978 controller asserts
PERR on clock 8, two clock cycles after data is valid.
The data on clock 5 is not checked for parity, because
on a read access, PAR is only required to be valid one
c l o c k a f t e r t h e t a r g e t h a s a s s e r t e d T R D Y.
TheAm79C978 controller then drives PERR high for
one clock cycle, since PERR is a sustained tri-state
signal.
Figure 22 assumes that the PCI Latency Timer has
counted down to 0 on clock 7.
During every data phase of a DMA write operation, the
Am79C978 controller checks the PERR input to see if
the target reports a parity error. When it sees the PERR
input asserted, the Am79C978 controller sets PERR
(PCI Status register, bit 15) to 1. When PERREN (PCI
Command register, bit 6) is set to 1, the Am79C978
controller also sets DATAPERR (PCI Status register, bit
8) to 1.
Master Abort
TheAm79C978 controller will terminate its cycle with a
Master Abort sequence if DEVSEL is not asserted
within 4 clocks after FRAME is asserted. Master Abort
is treated as a fatal error by the Am79C978 controller.
Am79C978
49
CLK
1
2
3
4
5
6
7
FRAME
AD
C/BE
ADDR
DATA
0111
BE
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-24
DEVSEL is sampled
Figure 21.
Preemption During Non-Burst Transaction
CLK
1
2
3
4
5
6
7
8
ADDR
DATA
DATA
DATA
DATA
DATA
PAR
PAR
9
FRAME
AD
0111
C/BE
BE
PAR
PAR
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
Figure 22.
50
22206B-25
Preemption During Burst Transaction
Am79C978
CLK
1
2
3
4
5
7
6
8
9
FRAME
AD
C/BE
ADDR
DATA
0111
0000
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
22206B-26
Figure 23. Master Abort
CLK
1
2
3
4
5
6
7
8
9
FRAME
AD
C/BE
DATA
ADDR
0111
BE
PAR
PAR
PAR
PERR
IRDY
TRDY
DEVSEL
DEVSEL is sampled
22206B-27
Figure 24. Master Cycle Data Parity Error Response
Am79C978
51
Whenever the Am79C978 controller is the current bus
master and a data parity error occurs, SINT (CSR5, bit
11) will be set to 1. When SINT is set, INTA is asserted
if the enable bit SINTE (CSR5, bit 10) is set to 1. This
mechanism can be used to inform the driver of the system error. The host can read the PCI Status register to
determine the exact cause of the interrupt. The setting
of SINT due to a data parity error is not dependent on
the setting of PERREN (PCI Command register, bit 6).
By default, a data parity error does not affect the state
of the MAC engine. TheAm79C978 controller treats the
data in all bus master transfers that have a parity error
as if nothing has happened. All network activity continues.
Advanced Parity Error Handling
For all DMA cycles, the Am79C978 controller provides
a second, more advanced level of parity error handling.
This mode is enabled by setting APERREN (BCR20, bit
10) to 1. When APERREN is set to 1, the BPE bits
(RMD1 and TMD1, bit 23) are used to indicate parity
error in data transfers to the receive and transmit buffers. Note that since the advanced parity error handling
uses an additional bit in the descriptor, SWSTYLE
(BCR20, bits 7-0) must be set to 2 or 3 to program the
Am79C978 controller to use 32-bit software structures.
TheAm79C978 controller will react in the following way
when a data parity error occurs:
n Initialization block read: STOP (CSR0, bit 2) is set
to 1 and causes a STOP_RESET of the device.
n Descriptor ring read: Any on-going network activity
is terminated in an orderly sequence and then STOP
(CSR0, bit 2) is set to 1 to cause a STOP_RESET
of the device.
n Descriptor ring write: Any on-going network activity
is terminated in an orderly sequence and then STOP
(CSR0, bit 2) is set to 1 to cause a STOP_RESET
of the device.
n Transmit buffer read: BPE (TMD1, bit 23) is set in
the current transmit descriptor. Any on-going network transmission is terminated in an orderly sequence.
n Receive buffer write: BPE (RMD1, bit 23) is set in
the last receive descriptor associated with the frame.
Terminating on-going network transmission in an orderly sequence means that if less than 512 bits have
been transmitted onto the network, the transmission
52
will be terminated immediately, generating a runt
packet.
If 512 bits or more have been transmitted, the message
will have the current FCS inverted and appended at the
next byte boundary to guarantee an FCS error is detected at the receiving station.
APERREN does not affect the reporting of address
parity errors or data parity errors that occur when the
Am79C978 controller is the target of the transfer.
Initialization Block DMA Transfers
During execution of the Am79C978 controller bus master initialization procedure, the microcode will repeatedly request DMA transfers from the BIU. During each
of these initialization block DMA transfers, the BIU will
perform two data transfer cycles reading one DWord
per transfer and then it will relinquish the bus. When
SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the initialization
block is organized as 32-bit software structures), there
are seven DWords to transfer during the bus master initialization procedure, so four bus mastership periods
are needed in order to complete the initialization sequence. Note that the last DWord transfer of the last
bus mastership period of the initialization sequence accesses an unneeded location. Data from this transfer is
discarded internally. When SSIZE32 is cleared to 0
(i.e., the initialization block is organized as 16-bit software structures), then three bus mastership periods
are needed to complete the initialization sequence.
The Am79C978 device supports two transfer modes
for reading the initialization block: non-burst and burst
mode, with burst mode being the preferred mode when
the Am79C978 controller is used in a PCI bus application. See Figure 25 and Figure 26.
When BREADE is cleared to 0 (BCR18, bit 6), all initialization block read transfers will be executed in nonburst mode. There is a new address phase for every
data phase. FRAME will be dropped between the two
transfers. The two phases within a bus mastership period will have addresses of ascending contiguous order.
When BREADE is set to 1 (BCR18, bit 6), all initialization block read transfers will be executed in burst
mode. AD[1:0] will be 0 during the address phase indicating a linear burst order.
Am79C978
CLK
1
2
3
4
5
6
7
8
9
10
FRAME
AD
0110
C/BE
0000
PAR
0110
0000
PAR
PAR
PAR
DATA
IADDi+4
DATA
IADDi
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-28
DEVSEL is sampled
Figure 25. Initialization Block Read In Non-Burst Mode
CLK
1
2
3
4
5
6
7
FRAME
AD
IADDi
DATA
C/BE
0110
0000
PAR
PAR
DATA
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
22206B-29
Figure 26. Initialization Block Read In Burst Mode
Am79C978
53
Descriptor DMA Transfers
The Am79C978 microcode will determine when a descriptor access is required. A descriptor DMA read will
consist of two data transfers. A descriptor DMA write
will consist of one or two data transfers. The descriptor
DMA transfers within a single bus mastership period
will always be of the same type (either all read or all
write).
During descriptor read accesses, the byte enable signals will indicate that all byte lanes are active. Should
some of the bytes not be needed, then the Am79C978
controller will internally discard the extraneous information that was gathered during such a read.
The settings of SWSTYLE (BCR20, bits 7-0) and
BREADE (BCR18, bit 6) affect the way the Am79C978
controller performs descriptor read operations.
When SWSTYLE is set to 0 or 2, all descriptor read operations are performed in non-burst mode. The setting
of BREADE has no effect in this configuration. See Figure 27.
When SWSTYLE is set to 3, the descriptor entries are
ordered to allow burst transfers. TheAm79C978 controller will perform all descriptor read operations in
burst mode, if BREADE is set to 1. See Figure 28.
of BWRITE has no effect in this configuration. See Figure 29.
When SWSTYLE is set to 3, the descriptor entries are
ordered to allow burst transfers. TheAm79C978 controller will perform all descriptor write operations in
burst mode, if BWRITE is set to 1. See Figure 30 and
Table 9 for the descriptor write sequence.
A write transaction to the descriptor ring entries is the
only case where the Am79C978 controller inserts a
wait state when being the bus master. Every data
phase in non-burst and burst mode is extended by one
clock cycle, during which IRDY is deasserted.
Note that Figure 28 assumes that the Am79C978 controller is programmed to use 32-bit software structures
(SWSTYLE = 2 or 3). The byte enable signals for the
second data transfer would be 0111b, if the device was
programmed to use 16-bit software structures (SWSTYLE = 0).
Table 8.
SWSTYLE
BCR20[7:0]
Descriptor Read Sequence
BREADE
BCR18[6]
Address = XXXX XX00h
Turn around cycle
Table 8 shows the descriptor read sequence.
Data = MD1[31:24], MD0[23:0]
During descriptor write accesses, only the byte lanes
which need to be written are enabled.
If buffer chaining is used, accesses to the descriptors
of all intermediate buffers consist of only one data
transfer to return ownership of the buffer to the system.
When SWSTYLE (BCR20, bits 7-0) is cleared to 0 (i.e.,
the descriptor entries are organized as 16-bit software
structures), the descriptor access will write a single
byte. When SWSTYLE (BCR20, bits 7-0) is set to 2 or
3 (i.e., the descriptor entries are organized as 32-bit
software structures), the descriptor access will write a
single word. On all single buffer transmit or receive descriptors, as well as on the last buffer in chain, writes to
the descriptor consist of two data transfers.
The first data transfer writes a DWord containing status
information. The second data transfer writes a byte
(SWSTYLE cleared to 0), or otherwise a word containing additional status and the ownership bit (i.e.,
MD1[31]).
0
X
When SWSTYLE is set to 0 or 2, all descriptor write operations are performed in non-burst mode. The setting
Am79C978
Idle
Address = XXXX XX04h
Turn around cycle
Data = MD2[15:0], MD1[15:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
2
X
Idle
Address = XXXX XX00h
Turn around cycle
Data = MD0[31:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
3
0
Idle
Address = XXXX XX08h
Turn around cycle
Data = MD0[31:0]
The settings of SWSTYLE (BCR20, bits 7-0) and
BWRITE (BCR18, bit 5) affect the way the Am79C978
controller performs descriptor write operations.
54
AD Bus Sequence
Address = XXXX XX04h
3
1
Turn around cycle
Data = MD1[31:0]
Data = MD0[31:0]
CLK
1
2
3
4
5
6
7
8
9
10
FRAME
AD
MD1
C/BE
0110
DATA
0000
0110
0000
PAR
PAR
PAR
PAR
DATA
MD0
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-30
DEVSEL is sampled
Figure 27. Descriptor Ring Read In Non-Burst Mode
CLK
1
2
3
4
5
6
DATA
7
FRAME
AD
MD1
DATA
C/BE
0110
0000
PAR
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
DEVSEL is sampled
22206B-31
Figure 28. Descriptor Ring Read In Burst Mode
Am79C978
55
CLK
1
2
3
4
5
6
7
8
9
10
FRAME
AD
MD2
C/BE
0111
0000
PAR
DATA
MD1
DATA
0111
PAR
0011
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-32
DEVSEL is sampled
Figure 29.
Descriptor Ring Write In Non-Burst Mode
CLK
1
2
3
5
4
6
7
8
FRAME
AD
MD2
C/BE
0110
0000
PAR
PAR
DATA
DATA
0011
PAR
PAR
IRDY
TRDY
DEVSEL
REQ
GNT
22206B-33
DEVSEL is sampled
Figure 30.
56
Descriptor Ring Write In Burst Mode
Am79C978
Table 9.
SWSTYLE
BCR20[7:0]
Descriptor Write Sequence
BWRITE
BCR18[5]
mastership period is dependent on all of the following
variables: the settings of the FIFO watermarks, the
conditions of the FIFOs, the latency of the system bus
to the Am79C978 controller’s bus request, the speed of
bus operation and bus preemption events. The TRDY
response time of the memory device will also affect the
number of transfers, since the speed of the accesses
will affect the state of the FIFO. During accesses, the
FIFO may be filling or emptying on the network end.
For example, on a receive operation, a slower TRDY
response will allow additional data to accumulate inside of the FIFO. If the accesses are slow enough, a
complete DWord may become available before the end
of the bus mastership period and, thereby, increase the
number of transfers in that period. The general rule is
that the longer the Bus Grant latency, the slower the
bus transfer operations; the slower the clock speed, the
higher the transmit watermark; or the higher the receive watermark, the longer the bus mastership period
will be.
AD Bus Sequence
Address = XXXX XX04h
Data = MD2[15:0],
MD1[15:0]
0
X
Idle
Address = XXXX XX00h
Data = MD1[31:24]
Address = XXXX XX08h
Data = MD2[31:0]
2
X
Idle
Address = XXXX XX04h
Data = MD1[31:16]
Address = XXXX XX00h
Data = MD2[31:0]
3
0
Idle
Note: The PCI Latency Timer is not significant during
non-burst transfers.
Address = XXXX XX04h
Data = MD1[31:16]
Burst FIFO DMA Transfers
Address = XXXX XX00h
3
1
Bursting is only performed by the Am79C978 controller
if the BREADE and/or BWRITE bits of BCR18 are set.
These bits individually enable/disable the ability of the
Am79C978 controller to perform burst accesses during
master read operations and master write operations,
respectively.
Data = MD2[31:0]
Data = MD1[31:16]
FIFO DMA Transfers
The Am79C978 microcode will determine when a FIFO
DMA transfer is required. This transfer mode will be
used for transfers of data to and from the FIFOs. Once
the BIU has been granted bus mastership, it will perform a series of consecutive transfer cycles before relinquishing the bus. All transfers within the master cycle
will be either read or write cycles, and all transfers will
be to contiguous, ascending addresses. Both nonburst and burst cycles are used, with burst mode being
the preferred mode when the device is used in a PCI
bus application.
A burst transaction will start with an address phase, followed by one or more data phases. AD[1:0] will always
be 0 during the address phase indicating a linear burst
order.
Non-Burst FIFO DMA Transfers
Figure 31 shows the beginning of a FIFO DMA write
with the beginning of the buffer not aligned to a DWord
boundary. TheAm79C978 controller starts off by writing
only three bytes during the first data phase. This operation aligns the address for all other data transfers to a
32-bit boundary so that the Am79C978 controller can
continue bursting full DWords.
In the default mode, the Am79C978 controller uses
non-burst transfers to read and write data when accessing the FIFOs. Each non-burst transfer will be performed sequentially with the issue of an address and
the transfer of the corresponding data with appropriate
output signals to indicate selection of the active data
bytes during the transfer.
FRAME will be deasserted after every address phase.
Several factors will affect the length of the bus mastership period. The possibilities are as follows:
Bus cycles will continue until the transmit FIFO is filled
to its high threshold (read transfers) or the receive
FIFO is emptied to its low threshold (write transfers).
The exact number of total transfer cycles in the bus
During FIFO DMA read operations, all byte lanes will
always be active. TheAm79C978 controller will internally discard unused bytes. During the first and the last
data phases of a FIFO DMA burst write operation, one
or more of the byte enable signals may be inactive. All
other data phases will always write a complete DWord.
If a receive buffer does not end on a DWord boundary,
the Am79C978 controller will perform a non-DWord
write on the last transfer to the buffer. Figure 32 shows
the final three FIFO DMA transfers to a receive buffer.
Since there were only nine bytes of space left in the receive buffer, the Am79C978 controller bursts three
data phases. The first two data phases write a full
DWord, the last one only writes a single byte.
Am79C978
57
Note that the Am79C978 controller will always perform
a DWord transfer as long as it owns the buffer space,
even when there are less than four bytes to write. For
example, if there is only one byte left for the current receive frame, the Am79C978 controller will write a full
DWord, containing the last byte of the receive frame in
the least significant byte position (BSWP is cleared to
0, CSR3, bit 2). The content of the other three bytes is
undefined. The message byte count in the receive descriptor always reflects the exact length of the received
frame.
CLK
1
2
3
4
5
6
7
FRAME
AD
ADD
C/BE
0111
PAR
DATA
PAR
DATA
DATA
0000
1110
PAR
PAR
PAR
IRDY
CLK
1
2
3
4
5
6
TRDY
FRAME
AD
ADD
DATA
C/BE
0111
0001
DATA
DEVSEL
DATA
REQ
0000
GNT
PAR
PAR
PAR
PAR
DEVSEL is sampled
IRDY
22206B-35
Figure 32.
TRDY
FIFO Burst Write at End of Unaligned
Buffer
DEVSEL
REQ
GNT
DEVSEL is sampled
22206B-34
Figure 31.
FIFO Burst Write at Start of Unaligned
Buffer
TheAm79C978 controller will continue transferring
FIFO data until the transmit FIFO is filled to its high
threshold (read transfers) or the receive FIFO is emptied to its low threshold (write transfers), or the
Am79C978 controller is preempted and the PCI Latency Timer is expired. The host should use the values
in the PCI MIN_GNT and MAX_LAT registers to determine the value for the PCI Latency Timer.
58
The exact number of total transfer cycles in the bus
mastership period is dependent on all of the following
variables: the settings of the FIFO watermarks, the
conditions of the FIFOs, the latency of the system bus
to the Am79C978 controller’s bus request, and the
speed of bus operation. The TRDY response time of
the memory device will also affect the number of transfers, since the speed of the accesses will affect the
state of the FIFO. During accesses, the FIFO may be
filling or emptying on the network end. For example, on
a receive operation, a slower TRDY response will allow
additional data to accumulate inside of the FIFO. If the
accesses are slow enough, a complete DWord may become available before the end of the bus mastership
period and, thereby, increase the number of transfers
in that period. The general rule is that the longer the
Bus Grant latency, the slower the bus transfer operations; the slower the clock speed, the higher the transmit watermark; or the lower the receive watermark, the
longer the total burst length will be.
When a FIFO DMA burst operation is preempted, the
Am79C978 controller will not relinquish bus ownership
until the PCI Latency Timer expires.
Am79C978
Buffer Management Unit
The Buffer Management Unit (BMU) is a microcoded
state machine which implements the initialization procedure and manages the descriptors and buffers. The
buffer management unit operates at half the speed of
the CLK input.
Initialization
Initialization includes the reading of the initialization
block in memory to obtain the operating parameters.
The initialization block can be organized in two ways.
When SSIZE32 (BCR20, bit 8) is at its default value of
0, all initialization block entries are logically 16-bits
wide to be backwards compatible with the Am79C90
C-LANCE and Am79C96x PCnet-ISA family. When
SSIZE32 (BCR20, bit 8) is set to 1, all initialization
block entries are logically 32-bits wide. Note that the
Am79C978 controller always performs 32-bit bus
transfers to read the initialization block entries. The initialization block is read when the INIT bit in CSR0 is
set. The INIT bit should be set before or concurrent with
the STRT bit to insure correct operation. Once the initialization block has been completely read in and internal registers have been updated, IDON will be set in
CSR0, generating an interrupt (if IENA is set).
The Am79C978 controller obtains the start address of
the initialization block from the contents of CSR1 (least
significant 16 bits of address) and CSR2 (most significant 16 bits of address). The host must write CSR1 and
CSR2 before setting the INIT bit. The initialization block
contains the user defined conditions for operation, together with the base addresses and length information
of the transmit and receive descriptor rings.
There is an alternate method to initialize the
Am79C978 controller. Instead of initialization via the
initialization block in memory, data can be written directly into the appropriate registers. Either method or a
combination of the two may be used at the discretion of
the programmer. Please refer to Appendix A, Alternative Method for Initialization for details on this alternate
method.
Re-Initialization
Th e tr an s m i tt e r a n d r e c ei v e r s ec t i on s of t h e
Am79C978 controller can be turned on via the initialization block (DTX, DRX, CSR15, bits 1-0). The states
of the transmitter and receiver are monitored by the
ho st throu gh CS R0 (RX O N, TX ON bi ts ). Th e
Am79C978 controller should be re-initialized if the
transmitter and/or the receiver were not turned on during the original initialization and it was subsequently required to activate them, or if either section was shut off
due to the detection of an error condition (MERR,
UFLO, TX BUFF error).
Re-initialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same
in the Am79C978 controller as in the C-LANCE device.
In particular, upon restart, the Am79C978 controller reloads the transmit and receive descriptor pointers with
their respective base addresses. This means that the
software must clear the descriptor OWN bits and reset
its descriptor ring pointers before restarting the
Am79C978 controller. The reload of descriptor base
addresses is performed in the C-LANCE device only
after initialization, so that a restart of the C-LANCE
without initialization leaves the C-LANCE pointing at
the same descriptor locations as before the restart.
Suspend
The Am79C978 controller offers two suspend modes
that allow easy updating of the CSR registers without
going through a full re-initialization of the device. The
suspend modes also allow stopping the device with orderly termination of all network activity.
The host requests the Am79C978 controller to enter
the suspend mode by setting SPND (CSR5, bit 0) to 1.
The host must poll SPND until it reads back 1 to determine that the Am79C978 controller has entered the
suspend mode. When the host sets SPND to 1, the procedure taken by the Am79C978 controller to enter the
suspend mode depends on the setting of the fast suspend enable bit (FASTSPND, CSR7, bit 15).
When a fast suspend is requested (FASTSPND is set
to 1), the Am79C978 controller performs a quick entry
into the suspend mode. At the time the SPND bit is set,
the Am79C978 controller will continue the DMA process of any transmit and/or receive packets that have
already begun DMA activity until the network activity
has been completed. In addition, any transmit packet
that had started transmission will be fully transmitted
and any receive packet that had begun reception will
be fully received. However, no additional packets will
be transmitted or received and no additional transmit or
receive DMA activity will begin after network activity
has ceased. Hence, the Am79C978 controller may
enter the suspend mode with transmit and/or receive
packets still in the FIFOs or the SRAM. This offers a
worst case suspend time of a maximum length packet
over the possibility of completely emptying the SRAM.
Care must be exercised in this mode, because the entire memory subsystem of the Am79C978 controller is
suspended. Any changes to either the descriptor rings
or the SRAM can cause the Am79C978 controller to
start up in an unknown condition and could cause data
corruption.
When FASTSPNDE is 0 and the SPND bit is set, the
Am79C978 controller may take longer before entering
the suspend mode. At the time the SPND bit is set, the
Am79C978 controller will complete the DMA process of
a transmit packet if it had already begun, and the
Am79C978
59
Am79C978 controller will completely receive a receive
packet if it had already begun. TheAm79C978 controller will not receive any new packets after the completion of the current reception. Additionally, all transmit
packets stored in the transmit FIFOs and the transmit
buffer area in the SRAM (if one is present) will be transmitted, and all receive packets stored in the receive
FIFOs and the receive buffer area in the SRAM (if selected) will be transferred into system memory. Since
the FIFO and the SRAM contents are flushed, it may
take much longer before the Am79C978 controller enters the suspend mode. The amount of time that it
takes depends on many factors including the size of
the SRAM, bus latency, and network traffic level.
Upon completion of the described operations, the
Am79C978 controller sets the read-version of SPND to
1 and enters the suspend mode. In suspend mode, all
of the CSR and BCR registers are accessible. As long
as the Am79C978 controller is not reset while in suspend mode (by H_RESET, S_RESET, or by setting the
STOP bit), no re-initialization of the device is required
after the device comes out of suspend mode. When
SPND is set to 0, the Am79C978 controller will leave
the suspend mode and will continue at the transmit and
receive descriptor ring locations where it was when it
entered the suspend mode.
See the section on Magic Packet technology for details
on how that affects suspension of the integrated Ethernet controller.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in memory. There are two descriptor rings, one for transmit and
one for receive. Each descriptor describes a single
buffer. A frame may occupy one or more buffers. If multiple buffers are used, this is referred to as buffer chaining.
Descriptor Rings
Each descriptor ring must occupy a contiguous area of
memory. During initialization, the user-defined base
address for the transmit and receive descriptor rings,
as well as the number of entries contained in the descriptor rings are set up. The programming of the software style (SWSTYLE, BCR20, bits 7-0) affects the
way the descriptor rings and their entries are arranged.
When SWSTYLE is at its default value of 0, the descriptor rings are backwards compatible with the
Am79C90 C-LANCE and the Am79C96x PCnet-ISA
family. The descriptor ring base addresses must be
aligned to an 8-byte boundary and a maximum of 128
ring entries is allowed when the ring length is set
through the TLEN and RLEN fields of the initialization
block. Each ring entry contains a subset of the three
60
32-bit transmit or receive message descriptors (TMD,
RMD) that are organized as four 16-bit structures
(SSIZE32 (BCR20, bit 8) is set to 0). Note that even
though the Am79C978 controller treats the descriptor
entries as 16-bit structures, it will always perform 32-bit
bus transfers to access the descriptor entries. The
value of CSR2, bits 15-8, is used as the upper 8-bits for
all memory addresses during bus master transfers.
When SWSTYLE is set to 2 or 3, the descriptor ring
base addresses must be aligned to a 16-byte boundary, and a maximum of 512 ring entries is allowed when
the ring length is set through the TLEN and RLEN fields
of the initialization block. Each ring entry is organized
as three 32-bit message descriptors (SSIZE32
(BCR20, bit 8) is set to 1). The fourth DWord is reserved. When SWSTYLE is set to 3, the order of the
message descriptors is optimized to allow read and
write access in burst mode.
For any software style, the ring lengths can be set beyond this range (up to 65535) by writing the transmit
and receive ring length registers (CSR76, CSR78) directly.
Each ring entry contains the following information:
n The address of the actual message data buffer in
user or host memory
n The length of the message buffer
n Status information indicating the condition of the
buffer
To permit the queuing and de-queuing of message
buffers, ownership of each buffer is allocated to either
the Am79C978 controller or the host. The OWN bit
within the descriptor status information, either TMD or
RMD, is used for this purpose.
When OWN is set to 1, it signifies that the Am79C978
controller currently has ownership of this ring descriptor and its associated buffer. Only the owner is permitted to relinquish ownership or to write to any field in the
descriptor entry. A device that is not the current owner
of a descriptor entry cannot assume ownership or
change any field in the entry. A device may, however,
read from a descriptor that it does not currently own.
Software should always read descriptor entries in sequential order. When software finds that the current descriptor is owned by the Am79C978 controller, then the
software must not read ahead to the next descriptor.
The software should wait at a descriptor it does not own
until the Am79C978 controller sets OWN to 0 to release ownership to the software. When LAPPEN
(CSR3, bit 5) is set to 1, this rule is modified. See the
LAPPEN description. At initialization, the Am79C978
controller reads the base address of both the transmit
and receive descriptor rings into CSRs for use by the
Am79C978 controller during subsequent operations.
Am79C978
Figure 33 illustrates the relationship between the initialization base address, the initialization block, the receive and transmit descriptor ring base addresses, the
receive and transmit descriptors, and the receive and
transmit data buffers, when SSIZE32 is cleared to 0.
Figure 34 illustrates when SSIZE32 is set to 1, the relationship between the initialization base address, the
initialization block, the receive and transmit descriptor
ring base addresses, the receive and transmit descriptors, and the receive and transmit data buffers.
Note that the value of CSR2, bits 15-8, is used as the
upper 8-bits for all memory addresses during bus master transfers.
N
N
N
N
•
•
•
Rcv Descriptor
Ring
CSR2
IADR[31:16]
1st desc.
start
CSR1
2nd
desc.
IADR[15:0]
RMD
RMD
RMD
RMD0
RMD
Initialization
Block
RLE
TLE
MOD
PADR[15:0]
PADR[31:16]
PADR[47:32]
LADRF[15:0]
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
RDRA[15:0]
RES RDRA[23:16]
TDRA[15:0]
RES TDRA[23:16]
Data
Buffer
1
Rcv
Buffers
Data
Buffer
2
M
M
Data
Buffer
N
M
M
•
•
Xmt Descriptor
Ring
2nd
desc.
1st desc.
start
TMD
Xmt
Buffers
•
TMD
TMD
Data
Buffer
1
TMD
Data
Buffer
2
TMD
Data
Buffer
M
22206B-36
Figure 33. 16-Bit Software Model
Am79C978
61
.
N
N
N
N
•
•
•
CSR2
CSR1
IADR[31:16]
IADR[15:0]
Rcv Descriptor
Ring
1st
desc.
start
RMD
2nd
desc.
start
RMD
RMD
RMD
RMD
Initialization
Block
TLE RES RLE RES
MODE
PADR[31:0]
PADR[47:32]
RES
LADRF[31:0]
LADRF[63:32]
RDRA[31:0]
TDRA[31:0]
Data
Buffer
1
Rcv
Buffers
Data
Buffer
2
M
M
Data
Buffer
N
M
M
•
•
•
1st
desc.
start
TMD0
Xmt
Buffers
Xmt Descriptor
Ring
2nd
desc.
start
TMD0
TMD1 TMD2 TMD3
Data
Buffer
1
Data
Buffer
2
Data
Buffer
M
22206B-37
Figure 34. 32-Bit Software Model
Polling
If there is no network channel activity and there is no
pre- or post-receive or pre- or post-transmit activity
being performed by the Am79C978 controller, then the
Am79C978 controller will periodically poll the current
receive and transmit descriptor entries in order to ascertain their ownership. If the DPOLL bit in CSR4 is set,
then the transmit polling function is disabled.
A typical polling operation consists of the following sequence. TheAm79C978 controller will use the current
receive descriptor address stored internally to vector to
the appropriate Receive Descriptor Table Entry
(RDTE). It will then use the current transmit descriptor
address (stored internally) to vector to the appropriate
Transmit Descriptor Table Entry (TDTE). The accesses
will be made in the following order: RMD1, then RMD0
of the current RDTE during one bus arbitration, and
after that, TMD1, then TMD0 of the current TDTE during a second bus arbitration. All information collected
during polling activity will be stored internally in the appropriate CSRs, if the OWN bit is set (i.e., CSR18,
62
CSR19, CSR20, CSR21, CSR40, CSR42, CSR50,
CSR52).
A typical receive poll is the product of the following conditions:
1. The controller does not own the current RDTE and
the poll time has elapsed and RXON = 1 (CSR0,
bit 5), or
2. The controller does not own the next RDTE and
there is more than one receive descriptor in the ring
and the poll time has elapsed and RXON = 1.
If RXON is cleared to 0, the Am79C978 controller will
never poll RDTE locations.
In order to avoid missing frames, the system should
have at least one RDTE available. To minimize poll activity, two RDTEs should be available. In this case, the
poll operation will only consist of the check of the status
of the current TDTE.
A typical transmit poll is the product of the following
conditions:
Am79C978
1. The controller does not own the current TDTE and
TXDPOLL = 0 (CSR4, bit 12) and TXON = 1 (CSR0,
bit 4) and the poll time has elapsed, or
2. The controller does not own the current TDTE and
TXDPOLL = 0 and TXON = 1 and a frame has just
been received, or
3. The controller does not own the current TDTE and
TXDPOLL = 0 and TXON = 1 and a frame has just
been transmitted.
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immediately perform a polling operation. If RDTE ownership
has not been previously established, then an RDTE
poll will be performed ahead of the TDTE poll. If the microcode is not executing the poll counting code when
the TDMD bit is set, then the demanded poll of the
TDTE will be delayed until the microcode returns to the
poll counting code.
The user may change the poll time value from the default of 65,536 clock periods by modifying the value in
the Polling Interval register (CSR47).
Transmit Descriptor Table Entry
If, after a Transmit Descriptor Table Entry (TDTE) access, the Am79C978 controller finds that the OWN bit
of that TDTE is not set, the Am79C978 controller resumes the poll time count and re-examines the same
TDTE at the next expiration of the poll time count.
If the OWN bit of the TDTE is set, but the Start of
Packet (STP) bit is not set, the Am79C978 controller
will immediately request the bus in order to clear the
OWN bit of this descriptor. (This condition would normally be found following a late collision (LCOL) or retry
(RTRY) error that occurred in the middle of a transmit
frame chain of buffers.) After resetting the OWN bit of
this descriptor, the Am79C978 controller will again immediately request the bus in order to access the next
TDTE location in the ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be cleared. In the C-LANCE device, the buffer
length of 0 is interpreted as a 4096-byte buffer. A zero
length buffer is acceptable as long as it is not the last
buffer in a chain (STP = 0 and ENP = 1).
If the OWN bit and STP are set, then microcode control
proceeds to a routine that will enable transmit data
transfers to the FIFO. TheAm79C978 controller will
look ahead to the next transmit descriptor after it has
performed at least one transmit data transfer from the
first buffer.
If the Am79C978 controller does not own the next
TDTE (i.e., the second TDTE for this frame), it will complete transmission of the current buffer and update the
status of the current (first) TDTE with the BUFF and
UFLO bits being set. If DXSUFLO (CSR3, bit 6) is
cleared to 0, the underflow error will cause the transmitter to be disabled (CSR0,
TXON = 0).
TheAm79C978 controller will have to be re-initialized to
restore the transmit function. Setting DXSUFLO to 1
enables the Am79C978 controller to gracefully recover
from an underflow error. The device will scan the transmit descriptor ring until it finds either the start of a new
frame or a TDTE it does not own. To avoid an underflow
situation in a chained buffer transmission, the system
should always set the transmit chain descriptor own
bits in reverse order.
If the Am79C978 controller does own the second TDTE
in a chain, it will gradually empty the contents of the first
buffer (as the bytes are needed by the transmit operation), perform a single-cycle DMA transfer to update
the status of the first descriptor (clear the OWN bit in
TMD1), and then it may perform one data DMA access
on the second buffer in the chain before executing another lookahead operation. (i.e., a lookahead to the
third descriptor.)
It is imperative that the host system never reads the
TDTE OWN bits out of order. TheAm79C978 controller
normally clears OWN bits in strict FIFO order. However, the Am79C978 controller can queue up to two
frames in the transmit FIFO. When the second frame
uses buffer chaining, the Am79C978 controller might
return ownership out of normal FIFO order. The OWN
bit for the last (and maybe only) buffer of the first frame
is not cleared until transmission is completed. During
the transmission the Am79C978 controller will read in
buffers for the next frame and clear their OWN bits for
all but the last one. The first and all intermediate buffers
of the second frame can have their OWN bits cleared
before the Am79C978 controller returns ownership for
the last buffer of the first frame.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred,
transmit status of the current buffer will be immediately
updated. If the buffer does not contain the end of
packet, the Am79C978 controller will skip over the rest
of the frame which experienced the error. This is done
by returning to the polling microcode where the
Am79C978 controller will clear the OWN bit for all descriptors with OWN = 1 and STP = 0 and continue in
like manner until a descriptor with OWN = 0 (no more
transmit frames in the ring) or OWN = 1 and STP = 1
(the first buffer of a new frame) is reached.
At the end of any transmit operation, whether successful or with errors, immediately following the completion
of the descriptor updates, the Am79C978 controller will
always perform another polling operation. As described
earlier, this polling operation will begin with a check of
the current RDTE, unless the Am79C978 controller already owns that descriptor. Then the Am79C978 controller will poll the next TDTE. If the transmit descriptor
OWN bit has a 0 value, the Am79C978 controller will
Am79C978
63
resume incrementing the poll time counter. If the transmit descriptor OWN bit has a value of 1, the Am79C978
controller will begin filling the FIFO with transmit data
and initiate a transmission. This end-of-operation poll
coupled with the TDTE lookahead operation allows the
Am79C978 controller to avoid inserting poll time counts
between successive transmit frames.
By default, whenever the Am79C978 controller completes a transmit frame (either with or without error)
and writes the status information to the current descriptor, then the TINT bit of CSR0 is set to indicate the completion of a transmission. This causes an interrupt
signal if the IENA bit of CSR0 has been set and the
TINTM bit of CSR3 is cleared. TheAm79C978 controller provides two modes to reduce the number of transmit interrupts. The interrupt of a successfully
transmitted frame can be suppressed by setting TINTOKD (CSR5, bit 15) to 1. Another mode, which is enabled by setting LTINTEN (CSR5, bit 14) to 1, allows
suppression of interrupts for successful transmissions
for all but the last frame in a sequence.
Receive Descriptor Table Entry
If the Am79C978 controller does not own both the current and the next Receive Descriptor Table Entry
(RDTE), then the Am79C978 controller will continue to
poll according to the polling sequence described
above. If the receive descriptor ring length is one, then
there is no next descriptor to be polled.
If a poll operation has revealed that the current and the
next RDTE belong to the Am79C978 controller, then
additional poll accesses are not necessary. Future poll
operations will not include RDTE accesses as long as
the Am79C978 controller retains ownership of the current and the next RDTE.
When receive activity is present on the channel, the
Am79C978 controller waits for the complete address of
the message to arrive. It then decides whether to accept or reject the frame based on all active addressing
schemes. If the frame is accepted, the Am79C978 controller checks the current receive buffer status register
CRST (CSR41) to determine the ownership of the current buffer.
If ownership is lacking, the Am79C978 controller will
immediately perform a final poll of the current RDTE. If
ownership is still denied, the Am79C978 controller has
no buffer in which to store the incoming message. The
MISS bit will be set in CSR0 and the Missed Frame
Counter (CSR112) will be incremented. Another poll of
the current RDTE will not occur until the frame has finished.
If the Am79C978 controller sees that the last poll (either a normal poll, or the final effort described in the
above paragraph) of the current RDTE shows valid
ownership, it proceeds to a poll of the next RDTE. Fol-
64
lowing this poll, and regardless of the outcome of this
poll, transfers of receive data from the FIFO may begin.
Regardless of ownership of the second receive descriptor, the Am79C978 controller will continue to perform receive data DMA transfers to the first buffer. If the
frame length exceeds the length of the first buffer, and
the Am79C978 controller does not own the second
buffer, ownership of the current descriptor will be
passed back to the system by writing a 0 to the OWN
bit of RMD1. Status will be written indicating buffer
(BUFF = 1) and possibly overflow (OFLO = 1) errors.
If the frame length exceeds the length of the first (current) buffer, and the Am79C978 controller does own
the second (next) buffer, ownership will be passed
back to the system by writing a 0 to the OWN bit of
RMD1 when the first buffer is full. The OWN bit is the
only bit modified in the descriptor. Receive data transfers to the second buffer may occur before the
Am79C978 controller proceeds to look ahead to the
ownership of the third buffer. Such action will depend
upon the state of the FIFO when the OWN bit has been
updated in the first descriptor. In any case, lookahead
will be performed to the third buffer and the information
gathered will be stored in the chip, regardless of the
state of the ownership bit.
This activity continues until the Am79C978 controller
recognizes the completion of the frame (the last byte of
this receive message has been removed from the
FIFO). TheAm79C978 controller will subsequently update the current RDTE status with the end of frame
(ENP) indication set, write the message byte count
(MCNT) for the entire frame into RMD2, and overwrite
the “current” entries in the CSRs with the “next” entries.
Receive Frame Queuing
TheAm79C978 controller supports the lack of RDTEs
when SRAM (SRAM SIZE in BCR 25, bits 7-0) is enabled through the Receive Frame Queuing mechanism. When the SRAM SIZE = 0, then the Am79C978
controller reverts back to the PCnet-PCI II mode of operation. This operation is automatic and does not require any programming by the host. When SRAM is
enabled, the Receive Frame Queuing mechanism allows a slow protocol to manage more frames without
the high frame loss rate normally attributed to FIFObased network controllers.
TheAm79C978 controller will store the incoming
frames in the extended FIFOs until polling takes place,
if enabled and it discovers it owns an RDTE. The stored
frames are not altered in any way until written out into
system buffers. When the receive FIFO overflows, further incoming receive frames will be missed during that
time. As soon as the network receive FIFO is empty, incoming frames are processed as normal. Status on a
per frame basis is not kept during the overflow process.
Am79C978
Statistic counters are maintained and accurate during
that time.
During the time that the Receive Frame Queuing
mechanism is in operation, the Am79C978 controller
relies on the Receive Poll Time Counter (CSR 48) to
control the worst case access to the RDTE. The Receive Poll Time Counter is programmed through the
Receive Polling Interval (CSR49) register. The Received Polling Interval defaults to approximately 2 ms.
TheAm79C978 controller will also try to access the
RDTE during normal descriptor accesses whether they
are transmit or receive accesses. The host can force
the Am79C978 controller to immediately access the
RDTE by setting the RDMD (CSR 7, bit 13) to 1. Its operation is similar to the transmit one. The polling process can be disabled by setting the RXDPOLL (CSR7,
bit 12) bit. This will stop the automatic polling process
and the host must set the RDMD bit to initiate the receive process into host memory. Receive frames are
still stored even when the receive polling process is
disabled.
Software Interrupt Timer
TheAm79C978 controller is equipped with a software
programmable free-running interrupt timer. The timer is
constantly running and will generate an interrupt STINT
(CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to
1. After generating the interrupt, the software timer will
load the value stored in STVAL and restart. The timer
value STVAL (BCR31, bits 15-0) is interpreted as an
unsigned number with a resolution of 256 Time Base
Clock periods. For instance, a value of 122 ms would
be programmed with a value of 9531 (253Bh), if the
Time Base Clock is running at 20 MHz. The default
value of STVAL is FFFFh which yields the approximate
maximum 838 ms timer duration. A write to STVAL restarts the timer with the new contents of STVAL.
10/100 Media Access Controller
The Media Access Controller (MAC) engine incorporates the essential protocol requirements for operation
of an Ethernet/IEEE 802.3-compliant node and provides the interface between the FIFO subsystem and
the internal PHY.
This section describes operation of the MAC engine
when operating in half-duplex mode. When operating
in half-duplex mode, the MAC engine is fully compliant
to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard
1990 Second Edition) and ANSI/IEEE 802.3 (1985).
When operating in full-duplex mode, the MAC engine
behavior changes as described in the section FullDuplex Operation.
The MAC engine provides programmable enhanced
features designed to minimize host supervision, bus
utilization, and pre- or post-message processing.
These features include the ability to disable retries after
a collision, dynamic FCS generation on a frame-byframe basis, automatic pad field insertion and deletion
to enforce minimum frame size attributes, automatic retransmission without reloading the FIFO, and automatic deletion of collision fragments.
The two primary attributes of the MAC engine are:
n Transmit and receive message data encapsulation
— Framing (frame boundary delimitation, frame
synchronization)
— Addressing (source and destination address
handling)
— Error detection (physical medium transmission
errors)
n Media access management
— Medium allocation (collision avoidance, except
in full-duplex operation)
— Contention resolution (collision handling, except
in full-duplex operation)
Transmit and Receive Message Data
Encapsulation
The MAC engine provides minimum frame size enforcement for transmit and receive frames. When
APAD_XMT (CSR, bit 11) is set to 1, transmit messages will be padded with sufficient bytes (containing
00h) to ensure that the receiving station will observe an
information field (destination address, source address,
length/type, data, and FCS) of 64 bytes. When
ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will
automatically strip pad bytes from the received message by observing the value in the length field and by
stripping excess bytes if this value is below the minimum data size (46 bytes). Both features can be independently over-ridden to allow illegally short (less than
64 bytes of frame data) messages to be transmitted
and/or received. The use of this feature reduces bus
utilization because the pad bytes are not transferred
into or out of main memory.
Framing
The MAC engine will autonomously handle the construction of the transmit frame. Once the transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80) and access to the channel is currently permitted, the MAC engine will commence the 7byte preamble sequence (10101010b, where first bit
transmitted is a 1). The MAC engine will subsequently
append the Star t Frame Delimiter (SFD) byte
(10101011b) followed by the serialized data from the
transmit FIFO. Once the data has been completed, the
MAC engine will append the FCS (most significant bit
first), which was computed on the entire data portion of
the frame. The data portion of the frame consists of
destination address, source address, length/type, and
frame data. The user is responsible for the correct or-
Am79C978
65
dering and content in each of these fields in the frame.
The MAC does not use the content in the length/type
field unless APAD_XMT (CSR4, bit 11) is set and the
data portion of the frame is shorter than 60 bytes.
The MAC engine will detect the incoming preamble sequence when the RX_DV signal is activated by the internal PHY. The MAC will discard the preamble and
begin searching for the SFD. Once the SFD is detected, all subsequent nibbles are treated as part of the
frame. The MAC engine will inspect the length field to
ensure minimum frame size, strip unnecessary pad
characters (if enabled), and pass the remaining bytes
through the receive FIFO to the host. If pad stripping is
performed, the MAC engine will also strip the received
FCS bytes, although normal FCS computation and
checking will occur. Note that apart from pad stripping,
the frame will be passed unmodified to the host. If the
length field has a value of 46 or greater, all frame bytes
including FCS will be passed unmodified to the receive
buffer, regardless of the actual frame length.
If the frame terminates or suffers a collision before 64
bytes of information (after SFD) have been received,
the MAC engine will automatically delete the frame
from the receive FIFO, without host intervention.
TheAm79C978 controller has the ability to accept runt
packets for diagnostic purposes and proprietary networks.
Destination Address Handling
The first 6 bytes of information after SFD will be interpreted as the destination address field. The MAC engine provides facilities for physical (unicast), logical
(multicast), and broadcast address reception.
Error Detection
The MAC engine provides several facilities which report and recover from errors on the medium. In addition, it protects the network from gross errors due to
inability of the host to keep pace with the MAC engine
activity.
On completion of transmission, the following transmit
status is available in the appropriate Transmit Message
Descriptor (TMD) and Control and Status Register
(CSR) areas:
n The number of transmission retry attempts (ONE,
MORE, RTRY, and TRC).
dicate a potentially faulty transceiver or network
connection.
n Late Collision (LCOL) indicates that the transmission suffered a collision after the slot time. This is indicative of a badly configured network. Late
collisions should not occur in a normal operating
network.
n Collision Error (CERR) indicates that the transceiver did not respond with an SQE Test message
within the first 4 ms after a transmission was completed. This may be due to a failed transceiver, disconnected or faulty transceiver drop cable, or
because the transceiver does not support this feature (or it is disabled). SQE Test is only valid for 10Mbps networks.
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails
to keep the transmit FIFO filled sufficiently, causing an
underflow, the MAC engine will guarantee the message
is either sent as a runt packet (which will be deleted by
the receiving station) or as an invalid FCS (which will
also cause the receiver to reject the message).
The status of each receive message is available in the
appropriate Receive Message Descriptor (RMD) and
CSR areas. All received frames are passed to the host
regardless of any error. The FRAM error will only be reported if an FCS error is detected and there is a nonintegral number of bytes in the message.
During the reception, the FCS is generated on every
nibble (including the dribbling bits) coming from the cable, although the internally saved FCS value is only updated on the eighth bit (on each byte boundary). The
MAC engine will ignore up to 7 additional bits at the end
of a message (dribbling bits), which can occur under
normal network operating conditions. The framing error
is reported to the user as follows:
n If the number of dribbling bits are 1 to 7 and there is
no FCS error, then there is no Framing error
(FRAM = 0).
n If the number of dribbling bits are 1 to 7 and there is
a FCS error, then there is also a Framing error
(FRAM = 1).
n Whether the MAC engine had to Defer (DEF) due to
channel activity.
n If the number of dribbling bits is 0, then there is no
Framing error. There may or may not be a FCS error.
n Excessive deferral (EXDEF), indicating that the
transmitter experienced Excessive Deferral on this
transmit frame, where Excessive Deferral is defined
in the ISO 8802-3 (IEEE/ANSI 802.3) standard.
n If the number of dribbling bits is 8, then there is no
Framing error. FCS error will be reported, and the
receive message count will indicate one extra byte.
n Loss of Carrier (LCAR), indicating that there was an
interruption in the ability of the MAC engine to monitor its own transmission. Repeated LCAR errors in-
Counters are provided to report the Receive Collision
Count and Runt Packet Count for network statistics
and utilization calculations.
66
Am79C978
Media Access Management
The basic requirement for all stations on the network is
to provide fairness of channel allocation. The IEEE
802.3/Ethernet protocols define a media access mechanism which permits all stations to access the channel
with equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter
Packet Gap) after the last activity, before transmitting
on the media. The channel is a multidrop communications media (with various topological configurations
permitted), which allows a single station to transmit and
all other stations to receive. If two nodes simultaneously contend for the channel, their signals will interact causing loss of data, defined as a collision. It is the
responsibility of the MAC to attempt to avoid and
recover from a collision and to guarantee data integrity
for the end-to-end transmission to the receiving station.
Medium Allocation
The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990)
requires that the CSMA/CD MAC monitor the medium
for traffic by watching for carrier activity. When carrier
is detected, the media is considered busy, and the
MAC should defer to the existing message.
The ISO 8802-3 (IEEE/ANSI 802.3) standard also
allows optionally a two-part deferral after a receive
message.
See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:
Note: “It is possible for the PLS carrier sense indication to fail to be asserted during a collision on the media. If the deference process simply times the interframe gap based on this indication, it is possible for a
short interframe gap to be generated, leading to a potential reception failure of a subsequent frame. To enhance system robustness, the following optional
measures (as specified in 4.2.8) are recommended
when InterFrameSpacingPart1 is other than 0:
1. Upon completing a transmission, start timing the interrupted gap as soon as transmitting and carrier
sense are both false.
2. When timing an inter-frame gap following reception,
reset the inter-frame gap timing if carrier sense becomes true during the first 2/3 of the inter-frame gap
timing interval. During the final 1/3 of the interval,
the timer shall not be reset to ensure fair access to
the medium. An initial period shorter than 2/3 of the
interval is permissible including 0.”
rier is deasserted. During the first part deferral
(InterFrameSpacingPart1 - IFS1), the Am79C978 controller will defer any pending transmit frame and respond to the receive message. The IPG counter will be
cleared to 0 continuously until the carrier deasserts, at
which point the IPG counter will resume the 9.6 ms
count once again. Once the IFS1 period of 6.0 ms has
elapsed, the Am79C978 controller will begin timing the
second part deferral (InterFrameSpacingPart2 - IFS2)
of 3.4 ms. Once IFS1 has completed and IFS2 has
commenced, the Am79C978 controller will not defer to
a receive frame if a transmit frame is pending. This
means that the Am79C978 controller will not attempt to
receive the receive frame, since it will start to transmit
and generate a collision at 9.6 ms. TheAm79C978 controller will complete the preamble (64-bit) and jam (32bit) sequence before ceasing transmission and invoking the random backoff algorithm.
TheAm79C978 controller allows the user to program
the
IPG
and
the
first-part
deferral
(InterFrameSpacingPart1 - IFS1) through CSR125. By
changing the IPG default value of 96 bit times (60h),
the user can adjust the fairness or aggressiveness of
the MAC on the network. By programming a lower
number of bit times than the ISO/IEC 8802-3 standard
requires, the MAC engine will become more aggressive on the network. This aggressive nature will give
rise to the Am79C978 controller possibly capturing the
network at times by forcing other less aggressive compliant nodes to defer. By programming a larger number
of bit times, the MAC will become less aggressive on
the network and may defer more often than normal.
The performance of the Am79C978 controller may decrease as the IPG value is increased from the default
value, but the resulting behavior may improve network
performance by reducing collisions. TheAm79C978
controller uses the same IPG for back-to-back transmits and receive-to-transmit accesses. Changing IFS1
will alter the period for which the MAC engine will defer
to incoming receive frames.
CAUTION: Care must be exercised when altering
these parameters. Adverse network activity could
result!
The MAC engine implements the optional receive twopart deferral algorithm, with an InterFrameSpacingPart1 time of 6.0 ms. The InterFrameSpacingPart 2 interval is, therefore, 3.4 ms.
This transmit two-part deferral algorithm is implemented as an option which can be disabled using the
DXMT2PD bit in CSR3. The IFS1 programming will
have no effect when DXMT2PD is set to 1, but the IPG
programming value is still valid. Two part deferral after
transmission is useful for ensuring that severe IPG
shrinkage cannot occur in specific circumstances,
causing a transmit message to follow a receive message so closely as to make them indistinguishable.
TheAm79C978 controller will perform the two-part deferral algorithm as specified in the Process Deference
section. The Inter Packet Gap (IPG) timer will start timing the 9.6 ms InterFrameSpacing after the receive car-
During the time period immediately after a transmission
has been completed, the external transceiver should
generate the SQE Test message within 0.6 to 1.6 ms
after the transmission ceases. During the time period in
Am79C978
67
which the SQE Test message is expected, the
Am79C978 controller will not respond to receive carrier
sense.
first collision. In this case, only the RTRY bit will be set,
and the transmit message will be flushed from the
FIFO.
See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC engine will abort the transmission, append the
jam sequence, and set the LCOL bit. No retry attempt
will be scheduled on detection of a late collision, and
the transmit message will be flushed from the FIFO.
“At the conclusion of the output function, the DTE
opens a time window during which it expects to see
the signal_quality_error signal asserted on the
Control In circuit. The time window begins when
the
CARRIER_STATUS
becomes
CARRIER_OFF. If execution of the output function
does not cause CARRIER_ON to occur, no SQE
test occurs in the DTE. The duration of the window
shall be at least 4.0 µs but no more than 8.0 µs.
During the time window the Carrier Sense Function
is inhibited.”
TheAm79C978 controller implements a carrier sense
“blinding” period of 4.0 µs length starting from the deassertion of carrier sense after transmission. This effectively means that when transmit two-part deferral is
enabled (DXMT2PD is cleared), the IFS1 time is from
4 ms to 6 ms after a transmission. However, since IPG
shrinkage below 4 ms will rarely be encountered on a
correctly configured network, and since the fragment
size will be larger than the 4 ms blinding window, the
IPG counter will be reset by a worst case IPG shrinkage/fragment scenario and the Am79C978 controller
will defer its transmission. If carrier is detected within
the 4.0 to 6.0 ms IFS1 period, the Am79C978 controller
will not restart the “blinding” period, but only restart
IFS1.
Collision Handling
Collision detection is performed and reported to the
MAC engine via the COL input pin.
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the preamble/SFD has been completed, but prior to 512 bits
being transmitted, the MAC engine will abort the transmission and append the jam sequence immediately.
The jam sequence is a 32-bit all zeros pattern.
The MAC engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of collision will cause the transmission to be rescheduled to a
time determined by the random backoff algorithm. If a
single retry was required, the 1 bit will be set in the
transmit frame status. If more than one retry was required, the MORE bit will be set. If all 16 attempts experienced collisions, the RTRY bit will be set (1 and
MORE will be clear), and the transmit message will be
flushed from the FIFO. If retries have been disabled by
setting the DRTY bit in CSR15, the MAC engine will
abandon transmission of the frame on detection of the
68
The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires
use of a “truncated binary exponential backoff” algorithm, which provides a controlled pseudo random
mechanism to enforce the collision backoff interval,
before retransmission is attempted.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming), the
CSMA/CD sublayer delays before attempting to retransmit the frame. The delay is an integer multiple
of slot time. The number of slot times to delay before the nth retransmission attempt is chosen as a
uniformly distributed random integer r in the range:
0 ≤ r < 2k Where k = Min (N,10).”
TheAm79C978 controller provides an alternative algorithm, which suspends the counting of the slot time/IPG
during the time that receive carrier sense is detected.
This aids in networks where large numbers of nodes
are present, and numerous nodes can be in collision. It
effectively accelerates the increase in the backoff time
in busy networks and allows nodes not involved in the
collision to access the channel, while the colliding
nodes await a reduction in channel activity. Once channel activity is reduced, the nodes resolving the collision
time-out their slot time counters as normal.
This modified backoff algorithm is enabled when EMBA
(CSR3, bit 3) is set to 1.
Transmit Operation
The transmit operation and features of the Am79C978
controller are controlled by programmable options.
TheAm79C978 controller offers a large transmit FIFO
to provide frame buffering for increased system latency, automatic retransmission with no FIFO reload,
and automatic transmit padding.
Transmit Function Programming
Automatic transmit features such as retry on collision,
FCS generation/transmission, and pad field insertion
can all be programmed to provide flexibility in the (re-)
transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the initialization block.
Am79C978
Automatic pad field insertion is controlled by the
APAD_XMT bit in CSR4.
APAD_XMT is 0, which will disable automatic pad generation after H_RESET.
The disable FCS generation/transmission feature can
be programmed as a static feature or dynamically on a
frame-by-frame basis.
It is the responsibility of upper layer software to correctly define the actual length field contained in the
message to correspond to the total number of LLC data
bytes encapsulated in the frame (length field as defined
in the ISO 8802-3 (IEEE/ANSI 802.3) standard). The
length value contained in the message is not used by
the Am79C978 controller to compute the actual number of pad bytes to be inserted. TheAm79C978 controller will append pad bytes dependent on the actual
number of bits transmitted onto the network. Once the
last data byte of the frame has completed, prior to appending the FCS, the Am79C978 controller will check
to ensure that 544 bits have been transmitted. If not,
pad bytes are added to extend the frame size to this
value, and the FCS is then added. See Figure 35.
Transmit FIFO Watermark (XMTFW) in CSR80 sets
the point at which the BMU requests more data from
the transmit buffers for the FIFO. A minimum of
XMTFW empty spaces must be available in the transmit FIFO before the BMU will request the system bus in
order to transfer transmit frame data into the transmit
FIFO.
Transmit Start Point (XMTSP) in CSR80 sets the point
when the transmitter actually attempts to transmit a
frame onto the media. A minimum of XMTSP bytes
must be written to the transmit FIFO for the current
frame before transmission of the current frame will begin. (When automatically padded packets are being
sent, it is conceivable that the XMTSP is not reached
when all of the data has been transferred to the FIFO.
In this case, the transmission will begin when all of the
frame data has been placed into the transmit FIFO.)
The default value of XMTSP is 01b, meaning there has
to be 64 bytes in the transmit FIFO to start a transmission.
The 544 bit count is derived from the following:
Minimum frame size (excluding preamble/SFD,
including FCS)
64 bytes
512 bits
Preamble/SFD size 8 bytes
64 bits
FCS size
32 bits
4 bytes
The 544 bit count is derived from the following:
Minimum frame size (excluding preamble/SFD,
including FCS)
64 bytes
512 bits
Automatic Pad Generation
Transmit frames can be automatically padded to extend them to 64 data bytes (excluding preamble). This
allows the minimum frame size of 64 bytes (512 bits)
for IEEE 802.3/Ethernet to be guaranteed with no software intervention from the host/controlling process.
Setting the APAD_XMT bit in CSR4 enables the automatic padding feature. The pad is placed between the
LLC data field and FCS field in the IEEE 802.3 frame.
FCS is always added if the frame is padded, regardless
of the state of DXMTFCS (CSR15, bit 3) or ADD_FCS
(TMD1, bit 29). The transmit frame will be padded by
bytes with the value of 00h. The default value of
Preamble/SFD size 8 bytes
64 bits
FCS size
32 bits
4 bytes
At the point that FCS is to be appended, the transmitted
frame should contain:
Preamble/SFD + (Min Frame Size - FCS)
64 + (512-32) = 544 bits
A minimum length transmit frame from theAm79C978
controller, therefore, will be 576 bits after the FCS is appended.
.
Preamble
1010....1010
SFD
10101011
Destination
Address
Source
Address
Length
56
Bits
8
Bits
6
Bytes
6
Bytes
2
Bytes
LLC
Data
Pad
4
Bytes
46 – 1500
Bytes
Figure 35.
FCS
22206B-38
ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
Am79C978
69
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS
(CSR15, bit 3). If DXMTFCS is cleared to 0, the transmitter will generate and append the FCS to the transmitted frame. If the automatic padding feature is
invoked (APAD_XMT is set in CSR4), the FCS will be
appended by theAm79C978 controller regardless of
the state of DXMTFCS or ADD_FCS (TMD1, bit 29).
Note that the calculated FCS is transmitted most significant bit first. The default value of DXMTFCS is 0 after
H_RESET.
ADD_FCS (TMD1, bit 29) allows the automatic generation and transmission of FCS on a frame-by-frame
basis. DXMTFCS should be cleared to 0 in this mode.
To generate FCS for a frame, ADD_FCS must be set in
all descriptors of a frame (STP is set to 1). Note that bit
29 of TMD1 has the function of ADD_FCS if SWSTYLE
(BCR20, bits 7-0) is programmed to 0, 2, or 3.
Transmit Exception Conditions
Exception conditions for frame transmission fall into
two distinct categories: those conditions which are the
result of normal network operation, and those which
occur due to abnormal network and/or host related
events.
Normal events which may occur and which are handled
autonomously by theAm79C978 controller include collisions within the slot time with automatic retry.
TheAm79C978 controller will ensure that collisions
which occur within 512 bit times from the start of transmission (including preamble) will be automatically retried with no host intervention. The transmit FIFO
ensures this by guaranteeing that data contained within
the FIFO will not be overwritten until at least 64 bytes
(512 bits) of preamble plus address, length, and data
fields have been transmitted onto the network without
encountering a collision. Note that if DRTY (CSR15, bit
5) is set to 1 or if the network interface is operating in
full-duplex mode, no collision handling is required, and
any byte of frame data in the FIFO can be overwritten
as soon as it is transmitted.
If 16 total attempts (initial attempt plus 15 retries) fail,
theAm79C978 controller sets the RTRY bit in the current transmit TDTE in host memory (TMD2), gives up
ownership (resets the OWN bit to 0) for this frame, and
processes the next frame in the transmit ring for transmission.
Abnormal network conditions include:
n Loss of carrier
n Late collision
n SQE Test Error (does not apply to 100 Mbps networks.)
70
These conditions should not occur on a correctly configured IEEE 802.3 network operating in half-duplex
mode. If they do, they will be reported. None of these
conditions will occur on a network operating in fullduplex mode. (See the section Full-Duplex Operation
for more detail.)
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be cleared until the STP (the next
frame) is found.
Loss of Carrier
LCAR will be reported for every frame transmitted if
theAm79C978 controller detects a loss of carrier.
Late Collision
A late collision will be reported if a collision condition
occurs after one slot time (512 bit times) after the transmit process was initiated (first bit of preamble commenced). TheAm79C978 controller will abandon the
transmit process for that frame, set Late Collision
(LCOL) in the associated TMD2, and process the next
transmit frame in the ring. Frames experiencing a late
collision will not be retried. Recovery from this condition must be performed by upper layer software.
SQE Test Error
If the network port is in Link Fail state, CERR will be
asserted in the 10BASE-T mode after transmit. CERR
will never cause INTA to be activated. It will, however,
set the ERR bit CSR0.
Receive Operation
The receive operation and features of theAm79C978
controller are controlled by programmable options.
TheAm79C978 controller offers a large receive FIFO to
provide frame buffering for increased system latency,
automatic flushing of collision fragments (runt packets),
automatic receive pad stripping, and a variety of address match options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. This can provide flexibility in
the reception of messages using the IEEE 802.3 frame
format.
All receive frames can be accepted by setting the
PROM bit in CSR15. Acceptance of unicast and broadcast frames can be individually turned off by setting the
DRCVPA or DRCVBC bits in CSR15. The Physical Address register (CSR12 to CSR14) stores the address
that theAm79C978 controller compares to the destination address of the incoming frame for a unicast address match. The Logical Address Filter register
(CSR8 to CSR11) serves as a hash filter for multicast
address match.
Am79C978
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established
during H_RESET is 01b, which sets the watermark flag
at 64 bytes filled.
For test purposes, theAm79C978 controller can be programmed to accept runt packets by setting RPA in
CSR124.
Address Matching
TheAm79C978 controller supports three types of address matching: unicast, multicast, and broadcast. The
normal address matching procedure can be modified
by programming three bits in CSR15, the mode register
(PROM, DRCVPA, and DRCVBC).
If the first bit received after the SFD (the least significant bit of the first byte of the destination address field)
is 0, the frame is unicast, which indicates that the frame
is meant to be received by a single node. If the first bit
received is 1, the frame is multicast, which indicates
that the frame is meant to be received by a group of
nodes. If the destination address field contains all 1s,
the frame is broadcast, which is a special type of multicast. Frames with the broadcast address in the destination address field are meant to be received by all
nodes on the local area network.
When a unicast frame arrives at theAm79C978 controller, the Am79C978 controller will accept the frame if the
destination address field of the incoming frame exactly
matches the 6-byte station address stored in the Physical Address registers (PADR, CSR12 to CSR14). The
byte ordering is such that the first byte received from
the network (after the SFD) must match the least significant byte of CSR12 (PADR[7:0]), and the sixth byte received must match the most significant byte of CSR14
(PADR[47:40]).
When DRCVPA (CSR15, bit 13) is set to 1,the
Am79C978 controller will not accept unicast frames.
If the incoming frame is multicast, the Am79C978 controller performs a calculation on the contents of the
destination address field to determine whether or not to
accept the frame. This calculation is explained in the
Logical Address Filter (LADRF) bits description.
When all bits of the LADRF registers are 0, no multicast
frames are accepted, except for broadcast frames.
Although broadcast frames are classified as special
multicast frames, they are treated differently by the
Am79C978 controller hardware. Broadcast frames are
always accepted, except when DRCVBC (CSR15, bit
14) is set and there is no Logical Address match.
miscuous mode. In the promiscuous mode, all properly
formed packets are received, regardless of the contents of their destination address fields. The promiscuous mode overrides the Disable Receive Broadcast bit
(DRCVBC bit l4 in the MODE register) and the Disable
Receive Physical Address bit (DRCVPA, CSR15, bit
13).
TheAm79C978 controller operates in promiscuous
mode when PROM (CSR15, bit 15) is set.
The receive descriptor entry RMD1 contains three bits
that indicate which method of address matching
caused the Am79C978 controller to accept the frame.
Note that these indicator bits are only available when
the Am79C978 controller is programmed to use 32-bit
structures for the descriptor entries (BCR20, bit 7-0,
SWSTYLE is set to 2 or 3).
Physical Address Match (PAM) (RMD1, bit 22) is set by
the Am79C978 controller when it accepts the received
frame due to a match of the frame’s destination address with the content of the physical address register.
Logical Address Filter Match (LAFM) (RMD1, bit 21) is
set by the Am79C978 controller when it accepts the received frame based on the value in the logical address
filter register.
Broadcast Address Match (BAM) (RMD1, bit 20) is set
by the Am79C978 controller when it accepts the received frame because the frame’s destination address
is of the type 'Broadcast.’
If DRCVBC (CSR15, bit 14) is cleared to 0, only BAM,
but not LAFM will be set when a Broadcast frame is received, even if the Logical Address Filter is programmed in such a way that a Broadcast frame would
pass the hash filter. If DRCVBC is set to 1 and the Logical Address Filter is programmed in such a way that a
Broadcast frame would pass the hash filter, LAFM will
be set on the reception of a Broadcast frame.
When the Am79C978 controller operates in promiscuous mode and none of the three match bits is set, it is
an indication that the Am79C978 controller has only
accepted the frame because it was in promiscuous
mode.
When the Am79C978 controller is not programmed to
be in promiscuous mode, then when none of the three
match bits is set, it is an indication that the Am79C978
controller only accepted the frame because it was not
rejected. See Table 10 for receive address matches.
None of the address filtering described above applies
when the Am79C978 controller is operating in the pro-
Am79C978
71
Table 10. Receive Address Match
PAM
LAFM
BAM
DRCVBC
Comment
802.3 Length field is not compliant with either standard
and may cause problems if pad stripping is enabled.
0
0
0
X
Frame accepted
due to PROM = 1
1
0
0
X
Physical address
match
0
Logical address
filter match;
frame is not of
type broadcast
1
Logical address
filter match;
frame can be of
type broadcast
0
0
0
1
1
0
0
0
1
0
Broadcast frame
Automatic Pad Stripping
During reception of an IEEE 802.3 frame, the pad field
can be stripped automatically. Setting ASTRP_RCV
(CSR4, bit 0) to 1 enables the automatic pad stripping
feature. The pad field will be stripped before the frame
is passed to the FIFO, thus preserving FIFO space for
additional frames. The FCS field will also be stripped,
since it is computed at the transmitting station based
on the data and pad field characters, and will be invalid
for a receive frame that has had the pad characters
stripped.
The number of bytes to be stripped is calculated from
the embedded length field (as defined in the ISO 88023 (IEEE/ANSI 802.3) definition) contained in the frame.
The length indicates the actual number of LLC data
bytes contained in the message. Any received frame
which contains a length field less than 46 bytes will have
the pad field stripped (if ASTRP_RCV is set). Receive
frames which have a length field of 46 bytes or greater
will be passed to the host unmodified.
Receive FCS Checking
Reception and checking of the received FCS is performed automatically by the Am79C978 controller.
Note that if the Automatic Pad Stripping feature is enabled, the FCS for padded frames will be verified
against the value computed for the incoming bit stream
including pad characters, but the FCS value for a padded frame will not be passed to the host. If an FCS
error is detected in any frame, the error will be reported
in the CRC bit in RMD1.
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories, i.e., those conditions which are the
result of normal network operation, and those which
occur due to abnormal network and/or host related
events.
Normal events which may occur and which are handled
autonomously by the Am79C978 controller are basically collisions within the slot time and automatic runt
packet rejection. The Am79C978 controller will ensure
that collisions that occur within 512 bit times from the
start of reception (excluding preamble) will be automatically deleted from the receive FIFO with no host intervention.
The receive FIFO will delete any frame that is composed of fewer than 64 bytes provided that the Runt
Packet Accept (RPA bit in CSR124) feature has not
been enabled and the network interface is operating in
half-duplex mode, or the full-duplex Runt Packet Accept Disable bit (FDRPAD, BCR9, bit 2) is set. This criterion will be met regardless of whether the receive
frame was the first (or only) frame in the FIFO or if the
receive frame was queued behind a previously received message.
Figure 36 shows the byte/bit ordering of the received
length field for an IEEE 802.3-compatible frame format.
Abnormal network conditions include:
Since any valid Ethernet Type field value will always be
greater than a normal IEEE 802.3 Length field (≥46),
the Am79C978 controller will not attempt to strip valid
Ethernet frames. Note that for some network protocols,
the value passed in the Ethernet Type and/or IEEE
n Late collision
72
n FCS errors
Host related receive exception conditions include
MISS, BUFF, and OFLO. These are described in the
Buffer Management Unit section.
Am79C978
46 – 1500
Bytes
56
Bits
8
Bits
6
Bytes
6
Bytes
2
Bytes
Preamble
1010....1010
SFD
10101011
Destination
Address
Source
Address
Length
4
Bytes
LLC
Data
Pad
1 – 1500
Bytes
45 – 0
Bytes
FCS
Start of Frame
at Time = 0
Bit
0
Bit
7
Bit
0
Bit
7
Increasing Time
Most
Significant
Byte
Least
Significant
Byte
22206B-39
Figure 36. IEEE 802.3 Frame and Length Field Transmission Order
Loopback Operation
Loopback is a mode of operation intended for system
diagnostics. In this mode, the transmitter and receiver
are both operating at the same time so that the
Am79C978 controller receives its own transmissions.
The Am79C978 controller provides two basic types of
loopback. In internal loopback mode, the transmitted
data is looped back to the receiver inside the
Am79C978 controller without actually transmitting any
data to the external network. The receiver will move the
received data to the next receive buffer, where it can be
examined by software. Alternatively, in external loopback mode, data can be transmitted to and received
from the PHY.
Refer to Table 30 for various bit settings required for
Loopback modes.
The external loopback requires a two-step operation.
The internal PHY must be placed into a loopback mode
by writing to the PHY Control Register (BCR33,
BCR34). Then, the Am79C978 controller must be
placed into an external loopback mode by setting the
Loop bits.
Miscellaneous Loopback Features
All transmit and receive function programming, such as
automatic transmit padding and receive pad stripping,
operates identically in loopback as in normal operation.
voked. This is to be backwards compatible to the
C-LANCE (Am79C90) software.
Since the Am79C978 controller has two FCS generators, there are no more restrictions on FCS generation
or checking, or on testing multicast address detection
as they exist in the half-duplex PCnet family devices
and in the C-LANCE. On receive, the Am79C978 controller now provides true FCS status. The descriptor for
a frame with an FCS error will have the FCS bit (RMD1,
bit 27) set to 1. The FCS generator on the transmit side
can still be disabled by setting DXMTFCS (CSR15, bit
3) to 1.
In internal loopback operation, the Am79C978 controller provides a special mode to test the collision logic.
When FCOLL (CSR15, bit 4) is set to 1, a collision is
forced during every transmission attempt. This will result in a Retry error.
Full-Duplex Operation
TheAm79C978 controller supports full-duplex operation on the 10BASE-T and MII interfaces. Full-duplex
operation allows simultaneous transmit and receive activity. Full-duplex operation is enabled by the FDEN bit
located in BCR9. Full-duplex operation is also enabled
through Auto-Negotiation when DANAS (BCR 32, bit 7)
is not enabled and the ASEL bit is set, and its link partner
is capable of Auto-Negotiation and full-duplex operation.
Runt Packet Accept is internally enabled (RPA bit in
CSR124 is not affected) when any loopback mode is in-
Am79C978
73
When operating in full-duplex mode, the following
changes to the device operation are made:
Bus Interface/Buffer Management Unit changes:
n The first 64 bytes of every transmit frame are not
preserved in the Transmit FIFO during transmission
of the first 512 bits as described in the Transmit Exception Conditions section. Instead, when full-duplex mode is active and a frame is being transmitted,
the XMTFW bits (CSR80, bits 9-8) always govern
when transmit DMA is requested.
n Successful reception of the first 64 bytes of every
receive frame is not a requirement for Receive DMA
to begin as described in the Receive Exception Conditions section. Instead, receive DMA will be requested as soon as either the RCVFW threshold
(CSR80, bits 12-13) is reached or a complete valid
receive frame is detected, regardless of length. This
Receive FIFO operation is identical to when the RPA
bit (CSR124, bit 3) is set during half-duplex mode
operation.
packet ends, instead of when transmit and carrier activity ends.
n The 4.0 µs carrier sense blinding period after a
transmission during which the SQE test normally
occurs is disabled.
n The collision indication input to the MAC engine is
ignored.
The internal PHY changes for full-duplex operation are
as follows:
n The collision detect (COL) pin is disabled.
n The SQE test function is disabled.
n Loss of Carrier (LCAR) reporting is disabled.
n PHY Control Register (TBR0) bit 8 is set to 1 if AutoNegotiation is disabled.
Full-Duplex Link Status LED Support
The MAC engine changes for full-duplex operation are
as follows:
TheAm79C978 controller provides bits in each of the
LED Status registers (BCR4, BCR5, BCR6, BCR7, and
BCR48) to display the Full-Duplex Link Status. If the
FDLSE bit (bit 8) is set, a value of 1 will be sent to the
associated LEDOUT bit when in Full-Duplex.
n Changes to the transmit deferral mechanism:
PHY/MAC Interface
— Transmission is not deferred while receive is
active.
— The IPG counter which governs transmit deferral
during the IPG between back-to-back transmits
is started when transmit activity for the first
74
The internal MII-compatible interface provides the data
path connection between the 10BASE-T PHY, the 1
Mbps HomePNA PHY, and the 10/100 Media Access
Controller (MAC). The interface is compatible with
Clause 22 of the IEEE 802.3 standard specification.
Am79C978
DETAILED FUNCTIONS
1 Mbps HomePNA PHY
The integrated HomePNA transceiver is a physical
layer device supporting the HomePNA specification 1.0
for home phone line networking. It provides all of the
PHY layer functions required to support 1 Mbps data
transfer speeds over common residential phone wiring.
All data bits are encoded into the relative time position
of a pulse with respect to the previous one, the waveform on the wire consists of a 7.5 MHz carrier sinusoid
enclosed within an exponential (bell shaped) envelope.
The waveform is produced by generating four 7.5 MHz
square wave cycles and passing them through a bandpass filter.
The HomePNA PHY frame consists of a HomePNA
header that replaces the normal Ethernet 64-bit preamble and delimiter and is prepended to a standard Ethernet packet starting with the destination address and
ending with the CRC.
Only the PHY layer and its parameters are modified
from that of the standard Ethernet implementation. The
HomePNA PHY layer is designed to operate with the
internal Ethernet MAC layer controller implementing all
the CSMA/CD protocol features.
The frame begins with a characteristic SYNC interval
that delineates the beginning of a HomePNA frame followed by an Access ID (AID) which encodes 8 bits of
Access ID and 4 bits of control word. The Access ID is
used to detect collisions and is dynamically assigned,
while the control word carries speed and power information.
The AID is followed by a silence interval, then 32 bits of
data reserved for PHY layer communication. These
bits are accessible via HPR20 and HPR21 and are for
future use.
The data encoding consists of two symbol types: an
AID symbol and a data symbol. The AID symbol is always transmitted at the same speed and encodes two
bits that determine the pulse position (one of four) relative to the previous pulse. The access symbol interval
is fixed.
The data symbol interval is variable. The arriving bit
stream is blocked into from 3 to 6 bit blocks according
to a proprietary (RLL25™) algorithm. The bits in each
block are then used to encode a data symbol. Each
symbol consists of a Data Inter Symbol Blanking Interval (DISBI) and then a pulse at one of twenty-five possible positions. The bits in the data block determine the
pulse position. Immediately after the pulse a new symbol interval begins. During the DISBI the receiver ignores all incoming pulses to allow network reflections
to die out.
Any station may be programmed to assume the role of
a PHY master and remotely command, via the control
word, the rest of the units on the network to change
their transmit speed or power level.
Many of the framing parameters are programmable in
the HomePNA PHY and will allow future modifications
to both transmission speed as well as noise and reflection rejection algorithms.
Two default speeds are provided, low at 0.7 Mbps and
high at 1 Mbps. The center frequency is also programmable for future use.
HomePNA PHY Medium Interface
Framing
The HomePNA frame on the phone wire network consists of a header generated in the PHY prepended to
an IEEE 802.3 Ethernet data packet received from the
MAC layer. See Figure 37.
When transmitting on the phone wire pair, the
HomePNA PHY first receives an Ethernet MAC frame
from the MAC. The 8 octets of preamble and delimiter
are stripped off and replaced with the HomePNA PHY
header described below, then transmitted LSB first on
the phone wire network.
During a receive operation, the reverse process is executed. When a HomePNA frame is received by the
PHY, the header is stripped off and replaced with the
four octets of preamble and delimiter of the IEEE 802.3
Ethernet MAC frame specification and then passed on
to the MAC layer.
Am79C978
75
Ethernet Packet
HomePNA Header
SYNC
interval
Access ID
AID
blanking
interval
Fixed
14.93 µs
AID
blanking
interval
01
Silence
AID
blanking
interval
11
AID
blanking
interval
10
AID
blanking
interval
00
01
Destination Source Length
6
6
2
PCOM
4 bytes
AID
blanking
interval
ETHERNET MAC and DATA
max 1500
Silence
interval
00
32 bits
PCOM
60 tics
20 tics
66 tics
potential
pulse position
pulse
129 tics
129 tics
129 tics
129 tics
129 tics
129 tics
129 tics
129 tics
SYNC
Symbol 0
ACCESS
ID Symbol
1
ACCESS
ID Symbol
2
ACCESS
ID Symbol
3
ACCESS
ID Symbol
4
ACCESS
ID Symbol
5
ACCESS
ID Symbol
6
ACCESS
ID Symbol
7
ACCESS ID interval
Fixed 119.44 µs
CRC
4
Ethernet Packet
Data
symbols
30.75 µs
@ 1 Mbps
Example Access ID of 01110100 and control word 0100
HomePNA PHY Header
150.19 µs @ 1 Mbps
1 Tic = 116.6667 ns
= receiver blanking interval
22206B-41
Figure 37.
HomePNA PHY Framing
HomePNA Symbol Waveform
These symbols are described in the following sections.
All HomePNA symbols are composed at the transmitter
of a silence interval, and a pulse formed of an integer
number of cycles (TX_PULSE_CYCLES_P/N in
HPR29) of a square wave of frequency
(CENTER_FREQUENCY TX_PULSE_WIDTH in
HPR29) that has been filtered with a bandpass filter.
Data is encoded in the time interval from the preceding
pulse.
Symbol 0 (SYNC interval)
Table 11. HomePNA PHY Pulse Parameters
Parameter
Value
Tolerance
Unit
CENTER_FREQUENCY
7.5
500 PPM
MHz
CYCLES_PER_PULSE
4
--
Cycles
Time Interval Unit
HomePNA PHY time intervals are expressed in Time
Interval Clock (TIC) units. One TIC is defined as
1/60E6 seconds or approximately 116.7 ns.
ACCESS ID Intervals
A HomePNA frame begins with an Access ID (AID) interval which is composed of eight equally spaced subintervals termed AID symbols 0 through 7 as shown in
Figure 37.
An AID symbol is 129 TICs long. Transmit timing is
shown in Figure 38; receive timing in Figure 39. Timing
starts at the beginning of each AID symbol at TIC = 0
and ends at TIC = 129.
76
SYNC Transmit Timing
The SYNC interval (AID symbol 0) delineates the beginning of a HomePNA frame and is composed of a
SYNC_START pulse, followed by a SYNC_END pulse,
after a fixed silence interval as shown in Figure 38.
Timing for this (AID symbol 0) starts (TIC = 0) at the beginning of the SYNC_START pulse. The SYNC_END
pulse starts at TIC = 126.
At TIC = 129, this AID symbol 0 ends and the next AID
symbol begins, with the symbol timing reference reset
to TIC = 0. No information bits are coded in the SYNC
(AID symbol 0 interval).
SYNC Receive Timing
As soon as the SYNC_START pulse is detected the receiver disables (blanks) further detection until time
TIC = 61, after which detection is re-enabled for the
next received pulse. The receiver allows for jitter by establishing a window around each legal pulse position.
This window is -2 +1 TICS wide on either side of the position.
A SYNC_END pulse that arrives outside the window of
the legal TIC = 126 is considered a noise event which
is used in setting the adaptive squelch level, aborts the
packet, and sets the receiver in search of a new
SYNC_START pulse and SYNC interval. If it is a transmitting station, the COLLISION event is asserted as
described in the Collisions section.
Am79C978
Transmitter
AID Symbol 0
AID Symbol 1
pulse 0
AID Symbol 2
pulse 2
shown in position 1
pulse 1
TIC=129
and
TIC=0
SYNC_START
TIC=0
TIC=129
and
TIC=0
AID_Position_0
TIC=66
SYNC_END
TIC=126
AID_Position_1
TIC=86
AID_Position_2
TIC=106
AID_Position_3
TIC=126
22206B-42
Figure 38. AID Symbol Transmit Timing
Receiver
AID slice threshold
AID Symbol 1
AID Symbol 0
pulse 0
pulse 1
Detected envelope
AID Symbol 2
pulse 2
shown in position 1
END_RCV_BLANK
TIC=128
and
TIC=0
SYNC_START
TIC=0
AID_Position_0
TIC=66
AID_Position_1
TIC=86
TIC=12
8 and
TIC=0
AID_GUARD_INTERVAL
AID_Position_2
TIC=106
SYNC_END
TIC=126
AID_Position_3
TIC=126
22206B-43
Figure 39. AID Symbol Receive Timing
AID Symbols 1 through 6
AID symbols 1 through 4 are used to identify individual
stations to enable reliable collision detection as described in the Collisions section. Symbols 5 and 6 are
used to transmit remote control management commands across the network. Coding and timing details
are as follows.
The SYNC interval is followed by six AID symbols
(symbols 1 through 6). Transmit timing is shown in Figure 38; receive timing in Figure 39. Data is encoded in
the relative position of each pulse with respect to the
previous one. A pulse may occur at one, and only one,
of the four possible positions within an AID symbol
yielding two bits of data coded per AID symbol.
The decoded bits from the AID symbols 1 to 4 produce
eight bits of Access ID which is used to identify individual HomePNA stations and to detect collisions. The
MSB is encoded in AID Symbol 1 and is the leftmost bit
in Table 12.
Am79C978
77
Table 12.
Access ID Symbol Pulse Positions and
Encoding
The following criteria must be met to guarantee reliable
collision detection:
Pulse
Position
TICs from Beginning of AID
Symbol
Bit Encoding
At least one HomePNA station of a colliding group
must always detect a collision when the delay between
the beginning of its transmitted packet and the beginning of the received colliding packet is between -1.5 µs
and +1.5 µs.
1
66
00
2
86
01
3
106
10
4
126
11
The next two AID symbols (5 and 6) encode four bits of
control word information. The MSB is encoded in AID
Symbol 5. Control word messages are described further in the Management Interfaces section.
AID Transmit Timing
The transmitter encodes the Access ID in a pulse position in each 128 TIC interval. Each AID symbol interval
must have only one pulse. Pulse transmission must
start in only one of the four possible positions (measured from the beginning of the Access ID symbol) defined in Table 12.
AID Receive Timing
The receiver allows for jitter by establishing a window
around each legal pulse position. This window is -2 +1
TICS wide on either side of the position. A pulse that arrives outside of the legal AID positions is considered a
COLLISION event.
Collisions
A Collision is detected only during Access ID and silent
intervals (AID symbols 0 through 7). In general during
a collision, a transmitting station will read back an AID
value that does not match its own and recognizes the
event as a collision and alerts other stations with a JAM
signal. Non-transmitting stations may also detect some
collisions by interpreting received non-conforming AID
pulses as collisions.
With two transmitters colliding, each transmitter normally blanks its receive input immediately after transmitting (and simultaneously receiving) a pulse.
Therefore, only when a transmitting station receives
pulses in a position earlier than the position it transmitted will it recognize it as a pulse transmitted by another
station and signal a collision.
For this reason, guaranteed collision detection is possible only as long as the spacing between successive
possible pulse positions in an AID symbol (20 TICs or
2.3 µs) is greater than the round trip delay between the
colliding nodes. At approximately 1.5 ns propagation
delay per foot, the maximum distance between two
HomePNA units must not be greater than 500 feet for
collision detection purposes (1.5 µs round trip delay
plus margin).
78
In general, any received pulse at a HomePNA station
that does not conform to the pulse position requirements of AID symbols 0 through 7 shall indicate a collision on the wire. When a transmitting station senses a
collision, it emits a JAM signal to alert all other stations
to the collision. The following conditions signify a COLLISION event:
1. A HomePNA station receives an AID that does not
match the one being sent.
2. A HomePNA station receives a pulse outside the
AID_GUARD INTERVAL in AID intervals 0 to 7.
3. A HomePNA station receives a pulse inside the
SILENT_INTERVAL (AID symbol 7).
As in all cases, pulses received during a blanking interval are ignored.
Passive stations (stations not actively transmitting during the collision) cannot reliably detect collisions.
Therefore, once a collision is detected by a transmitting
station, the station must inform the rest of the stations
of the collision with a JAM pattern described below.
Only a transmitting station emits a JAM signal.
Once a collision is detected, the COLLISION signal to
the MAC interface is asserted and is not reset until the
MAC deactivates the TXEN signal.
JAM Signal
A JAM pattern consists of 1 pulse every 32 TICs and
continues until at least the end of the AID intervals.
After the AID interval, the JAM pattern will continue
until TXEN from the MAC is deactivated.
ACCESS ID Values
The access ID values for slave stations are picked by
each individual station randomly from the set of AID
slave numbers described in the management section.
During operation, each HomePNA station monitors
HomePNA frames received on the wire. If it detects another HomePNA station using the same AID, it will select a new random AID.
Silence Interval (AID symbol 7)
The Access ID symbols are followed by a fixed silence
interval of 129 TICs. The receive blanking interval is
the same as that of the AID symbols (1 through 6).
Any pulses detected in the silence interval are considered a COLLISION event for transmitting stations and
are handled as described in the Collisions section.
Am79C978
PULSE_POSITION_0 occurs at a value defined in
Table 13 which determines the transmission speed.
When a pulse begins transmission, the previous symbol interval ends and a new one begins immediately.
Data Symbols
Data symbols encode data for a much higher transmission rate, and they do not allow collision detection.
Data Transmit Timing
Table 13.
A data symbol interval begins with the beginning of
transmission of a pulse as shown in Figure 40. Transmit Symbol timing (in TICS) is measured from this point
(TIC = 0).
Depending on the data code, the next pulse may begin
at any PULSE_POSITION_N where N = 0 to 24. Each
position is separated from the previous one by one TIC.
Blanking Interval Speed Settings
Speed Setting
Nominal Data
Rate
PULSE_POSITION_0
Value
(in TICs)
LOW_SPEED
0.7 Mbps
44
HIGH_SPEED
1.0 Mbps
28
Transmitter
Symbol 1
Pulse 0
START_TX_PULSE
TIC=0
Symbol 2
Data Blanking interval (DISBI)
END_TX_PULSE
time
Pulse 1
PULSE_POSITION_0
time
Position 1
1 TIC
Position n1
n=0-24
Position 0
Position 1
Pulse 2
Position n2
22206B-44
Figure 40. Transmit Data Symbol Timing
Data Receive Timing
The incoming waveform is formed from the transmitted
pulse. The receiver detects the point at which the envelope of the received waveform crosses a set threshold.
See Figure 41.
Immediately after the threshold crossing, the receiver
disables any further detection for a period ISBI-3 TICs
(HPR28 ISBI_SLOW or ISBI_FAST) starting with the
detection of the pulse peak.
The receiver is then re-enabled for pulse detection.
Upon reception of the next pulse, the receiver measures the elapsed time from the previous pulse. This
value is then placed in the nearest pulse position bin
(one of 25) where pulse position 0 is at
PULSE_POSITION_0 and each subsequent position is
spaced one TIC from the previous one as defined in the
Data Transmit Timing section. Data symbol intervals
are therefore variable and depend on the encoded
data.
Receiver
Symbol 1
Data slice
threshold
Symbol 2
Pulse 0
Pulse 1
Pulse 2
Detected Envelope
END_DATA_BLANK
Begin of receive
Blanking interval
Position 0
Position 1
Position n1
Position 0
Position 1
Position n2
22206B-45
Figure 41. Receive Symbol Timing
Am79C978
79
3. If bit A is a zero, bit B is a zero, and bit C is a one,
the next three bits (D, E, and F) select which one of
the eight positions 17-24 is transmitted. The encoding process then continues at the root node.
Data Symbol RLL25 Encoding
The RLL25 code is the version of TM32 that was developed for the HomePNA PHY. It produces both the highest bit rate for a given value of ISBI and TIC size. In a
manner similar to run length limited disk coding, RLL25
encodes data bits in groups of varying sizes, specifically: 3, 4, 5, and 6 bits. Pulse positions are assigned
to the encoded bit groups in a manner, which causes
more data bits to be encoded in positions that are farther apart. This keeps both the average and minimum
bit rates higher.
4. Finally, if bits A, B, and C are all zeros, position 0 is
transmitted. The encoding process then continues
at the root node.
As a result, Symbol 0 encodes the 3-bit data pattern
000, positions 1-8 encode the 4-bit data pattern 1BCD,
positions 9-16 encode the 5-bit data pattern 01CDE,
and positions 17-24 encode the 6-bit data pattern
001DEF. If the data encoded is random, 50% of the positions used will be for 4-bit patterns, 25% will be for 5bit patterns, 12.5% will be for 6-bit patterns, and 12.5%
will be for 3-bit patterns.
Data symbol RLL25 codes data by traversing a tree as
illustrated in Figure 42. Assuming that successive data
bits to be encoded are labeled A, B, C, D,…, etc. The
encoding process begins at the root node and proceeds as follows:
Management Interfaces
1. If the first bit (bit A) is a one, the next three bits (B,
C, and D) select which one of the eight positions 18 is transmitted. The encoding process then continues at the root node.
The HomePNA PHY may be managed from either of
two interfaces (the managed parameters vary depending on the interface):
1. Remote Control-Word management commands
embedded in the HomePNA AID header on the wire
network.
2. If bit A is a zero and bit B is a one, the next three bits
(C, D, and E) select which one of the eight positions
9-16 is transmitted. The encoding process then
continues at the root node.
2. Management messages from a local management
entity.
Data stream from MAC controller
Start: Examine the next
bits to be encoded
A
Encoded and
A=?
1
Send symbol 1-8
B=?
D
E
F
B
C
D
These select position 1 - 8
1
Send symbol 9-16
0
0
C=?
C
Awaiting coding and transmission
1
0
B
1
C
D
E
These select position 9 - 16
1
Send symbol 17-24
1
Send symbol 0
0
0
0
1
D
E
F
These select position 17- 24
0
0
0
22206B-46
Figure 42. RLL 25 Coding Tree
80
Am79C978
Header AID Remote Control Word Commands
Table 14. Master Station Control Word Functions
Stations may be configured either as master stations or
as slave stations. Only one master may exist on a given
HomePNA segment.
Aid No.
2. A slave is identified with an AID of 00h to EFh.
3. AID values of F0h to FEh are reserved for future
use.
Once a command has been transmitted, the master
station will revert to a slave AID, so that subsequent
control words are not interpreted as new commands.
Master mode is entered by writing to the PHY control
register (HPR16) and is exited upon the completion of
the command sequence.
A valid master remote command consists of three
HomePNA frames with an AID of FFh. Since the
HomePNA header is prepended to packets received
from the MAC as well as Any1Home packets. Packets
from the master station may be separated by intervals
during which other (slave) stations may transmit their
frames.
A remote master Control Word command must be recognized and executed by a HomePNA PHY when it receives three consecutive valid HomePNA frames with
an AID of FFh.
If HPR16, bit 15 is not set to 0, valid commands are as
follows:
1. SET_POWER: Commands slave stations to set
their transmit level to a prescribed level.
2. SET_SPEED: Commands slave stations to set their
transmit speed to a prescribed value.
The control word bit encoding and possible values are
described in Table 14.
MSB
Set to:
5
The master station may send commands embedded in
the HomePNA header control word to remotely set various parameters of the remote slave stations. Stations
are identified via the AID as follows:
1. The master station is identified on the HomePNA
wire network with an AID of FFh.
LSB
Version
0 = Low Power
1 = High Power
Set to:
6
0 = Low Speed
Reserved
1 = High Speed
All stations will transmit the following status messages
in the HomePNA header control word of all outgoing
frames:
1. VERSION_STATUS: The HomePNA PHY version
of the slave station.
2. POWER_STATUS: The transmit power level of the
transmitting slave station for the current frame. All
HomePNA units support LOW_POWER and
HIGH_POWER modes.
3. SPEED_STATUS: The transmit speed of the slave
station for the current frame. Receiving stations will
adjust their receiver parameters to correctly interpret this frame.
The slave control word bit encoding and possible values are also described in Table 14.
PHY Control and Management Block (PCM
Block)
Register Administration for 10BASE-T PHY Device
The management interface specified in Clause 22 of
the IEEE 802.3u standard provides for a simple two
wire, serial interface to connect a management entity
and a managed PHY for the purpose of controlling the
PHY and gathering status information. The two lines
are Management Data Input/Output (MDIO) and Management Data Clock (MDC). A station management
entity which is attached to multiple PHY entities must
have prior knowledge of the appropriate PHY address
for each PHY entity.
Description of the Methodology
The management interface physically transports management information across the internal and external
MII. The information is encapsulated in a frame format
as specified in Clause 22 of the IEEE 802.3u draft standard and is shown in Table 15.
Table 15.
MII Control Frame Format
PRE
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
READ
1.1
01
10
AAAAA
RRRRR
Z0
D31………D0
Z
WRITE
1.1
01
01
AAAAA
RRRRR
10
D31………D0
Z
Am79C978
81
The start field (ST) is followed by the operation field
(OP). The operation field (OP) indicates whether the
operation is a read or a write operation. This is followed
by the PHY address (PHYAD) and the register address
(REGAD) that was programed into BCR33 of the Fast
Ethernet controller. This field is followed by a bus turnaround field (TA). During the read operation, the bus
turnaround field is used to determine if the PHY is responding properly to the read request. The data field
to/from the MAC controller is then written to or read
from BCR34. The final field is the idle field, and it is required to allow the drivers to turn off.
The PHYADD field, which is five bits wide, allows 32
unique PHY addresses. The managed PHY layer device that is connected to a station management entity
via the MII interface has to respond to transactions addressed to the PHY’s address. A station management
entity attached to multiple PHYs is required to have
prior knowledge of the appropriate PHY address.
SRAM Configuration
If the SRAM_SIZE (BCR25, bits 7-0) value is 0 in the
SRAM size register, the controller will assume that
there is no SRAM present and will reconfigure the four
internal FIFOs into two FIFOs, one for transmit and one
for receive. The FIFOs will operate the same as in the
PCnet-PCI II controller. When the SRAM_SIZE
(BCR25, bits 7-0) value is 0, the SRAM_BND (BCR26,
bits 7-0) are ignored by the controller. See Figure 43.
Low Latency Receive Configuration
If the LOLATRX (BCR27, bit 4) bit is set to 1, then the
controller will configure itself for a low latency receive
configuration. In this mode, SRAM is required at all
times. If the SRAM_SIZE (BCR25, bits 7-0) value is 0,
the controller will not configure for low latency receive
mode. The controller will provide a fast path on the receive side bypassing the SRAM. All transmit traffic will
go to the SRAM, so SRAM_BND (BCR26, bits 7-0) has
no meaning in low latency receive mode. When the
controller has received 16 bytes from the network, it will
start a DMA request to the PCI Bus Interface Unit. The
controller will not wait for the first 64 bytes to pass to
check for collisions in Low Latency Receive mode. The
controller must be in STOP before switching to this
mode. See Figure 44.
CAUTION: To provide data integrity when switching
into and out of the low latency mode, DO NOT SET the
FASTSPNDE bit when setting the SPND bit. Receive
frames WILL be overwritten and the controller may give
erratic behavior when it is enabled again.
Direct SRAM Access
The SRAM can be accessed through the Expansion
Bus Data port (BCR30). To access this data port, the
user must load the upper address EPADDRU (BCR29,
bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the
user will load the lower 16 bits of address EPADDRL
(BCR28, bits 15-0). To initiate a read, the user reads
the Expansion Bus Data Port (BCR30). This slave access from the PCI will result in a retry for the very first
access. Subsequent accesses may give a retry or not,
depending on whether or not the data is present and
valid. The direct SRAM access uses the same FLASH/
EPROM access except for accessing the SRAM in
word format instead of byte format. This access is
meant to be a diagnostic access only. The SRAM can
only be accessed while the controller is in STOP or
SPND (FASTSPNDE is set to 0) mode.
.
Bus
Rcv
FIFO
MAC
Rcv
FIFO
PCI Bus
Interface
Unit
MAC
Xmt
FIFO
Bus
Xmt
FIFO
Buffer
Management
Unit
802.3
MAC
Core
and
10BASE-T
and
HomePNA
PHYs
FIFO
Control
22206B-47
Figure 43.
82
Block Diagram SRAM Configuration
Am79C978
Bus
Rcv
FIFO
PCI Bus
Interface
Unit
MAC
Rcv
FIFO
Bus
Xmt
FIFO
Buffer
Management
Unit
802.3
MAC
Core
SRAM
MAC
Xmt
FIFO
and
10BASE-T
and
HomePNA
PHYs
FIFO
Control
22206B-48
Figure 44. Block Diagram Low Latency Receive Configuration
Am79C978
83
EEPROM Interface
The controller contains a built-in capability for reading
and writing to an external serial 93C46 EEPROM. This
built-in capability consists of an interface for direct connection to a 93C46 compatible EEPROM, an automatic
EEPROM read feature, and a user-programmable register that allows direct access to the interface pins.
Automatic EEPROM Read Operation
Shortly after the deassertion of the RST pin, the controller will read the contents of the EEPROM that is attached to the interface. Because of this automatic-read
capability of the controller, an EEPROM can be used to
program many of the features of the controller at
power-up, allowing system-dependent configuration information to be stored in the hardware instead of inside
the device driver.
If an EEPROM exists on the interface, the controller will
read the EEPROM contents at the end of the
H_RESET operation. The EEPROM contents will be
serially shifted into a temporary register and then sent
to various register locations on board the controller. Access to the Am79C978 configuration space or any I/O
resource is not possible during the EEPROM read operation. The controller will terminate any access attempt with the assertion of DEVSEL and STOP while
TRDY is not asserted, signaling to the initiator to disconnect and retry the access at a later time.
A checksum verification is performed on the data that
is read from the EEPROM. If the checksum verification
passes, PVALID (BCR19, bit 15) will be set to 1. If the
checksum verification of the EEPROM data fails,
PVALID will be cleared to 0, and the controller will force
all EEPROM-programmable BCR registers back to
their H_RESET default values. However, the content of
the Address PROM locations (offsets 0h - Fh from the
I/O or memory mapped I/O base address) will not be
cleared. The 8-bit checksum for the entire 82 bytes of
the EEPROM should be FFh.
If no EEPROM is present at the time of the automatic
read operation, the controller will recognize this condition, abort the automatic read operation, and clear both
the PREAD and PVALID bits in BCR19. All EEPROMprogrammable BCR registers will be assigned their default values after H_RESET. The content of the Address PROM locations (offsets 0h - Fh from the I/O or
memory mapped I/O base address) will be undefined.
EEPROM Auto-Detection
The controller uses the EESK/LED1 pin to determine if
an EEPROM is present in the system. At the rising
edge of CLK during the last clock during which RST is
asserted, the controller will sample the value of the
EESK/LED1 pin. If the sampled value is a 1, then the
controller assumes that an EEPROM is present, and
the EEPROM read operation begins shortly after the
84
RST pin is deasserted. If the sampled value of EESK/
LED1 is a 0, the controller assumes that an external
pull-down device is holding the EESK/LED1 pin low, indicating that there is no EEPROM in the system. Note
that if the designer creates a system that contains an
LED circuit on the EESK/LED1 pin, but has no EEPROM present, then the EEPROM auto-detection
function will incorrectly conclude that an EEPROM is
present in the system. However, this will not pose a
problem for the controller, since the checksum verification will fail.
Direct Access to the Interface
The user may directly access the port through the
EEPROM register, BCR19. This register contains bits
that can be used to control the interface pins. By performing an appropriate sequence of accesses to
BCR19, the user can effectively write to and read from
the EEPROM. This feature may be used by a system
configuration utility to program hardware configuration
information into the EEPROM.
EEPROM-Programmable Registers
The following registers contain configuration information that will be programmed automatically during the
EEPROM read operation:
n I/O offsets 0h-Fh Address PROM locations
n BCR2
Miscellaneous Configuration
n BCR4
LED0 Status
n BCR5
LED1 Status
n BCR6
LED2 Status
n BCR7
LED3 Status
n BCR9
Full-Duplex Control
n BCR18
Burst and Bus Control
n BCR22
PCI Latency
n BCR23
PCI Subsystem Vendor ID
n BCR24
PCI Subsystem ID
n BCR25
SRAM Size
n BCR26
SRAM Boundary
n BCR27
SRAM Interface Control
n BCR32
PHY Control and Status
n BCR33
PHY Address
n BCR35
PCI Vendor ID
n BCR36
PCI Power Management Capabilities (PMC) Alias Register
n BCR37
PCI DATA Register 0 (DATA0)
Alias Register
n BCR38
PCI DATA Register 1 (DATA1)
Alias Register
n BCR39
PCI DATA Register 2 (DATA2)
Alias Register
Am79C978
n BCR40
PCI DATA Register 3 (DATA3)
Alias Register
n BCR41
PCI DATA Register 4 (DATA4)
Alias Register
n BCR42
PCI DATA Register 5 (DATA5)
Alias Register
n BCR43
PCI DATA Register 6 (DATA6)
Alias Register
n BCR44
PCI DATA Register 7 (DATA7)
Alias Register
n BCR45
OnNow Pattern Matching
Register 1
n BCR46
OnNow Pattern Matching
Register 2
n BCR47
OnNow Pattern Matching
Register 3
n BCR48
LED4 Status
There are two checksum locations within the EEPROM. The first checksum will be used by AMD driver
software to verify that the ISO 8802-3 (IEEE/ANSI
802.3) station address has not been corrupted. The
value of bytes 0Ch and 0Dh should match the sum of
bytes 00h through 0Bh and 0Eh and 0Fh. The second
checksum location (byte 51h) is not a checksum total,
but is, instead, a checksum adjustment. The value of
this byte should be such that the total checksum for the
entire 82 bytes of EEPROM data equals the value FFh.
The checksum adjust byte is needed by the controller
in order to verify that the EEPROM content has not
been corrupted.
n BCR49
PHY Select
LED Support
n CRS12
Physical Address Register 0
n CRS13
Physical Address Register 1
n CRS14
Physical Address Register 2
The controller can support up to five LEDs. LED outputs LED0, LED1, LED2, LED3, and LED4 allow for direct connection of an LED and its supporting pull-up
device.
n CSR116
OnNow Miscellaneous
If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)
are cleared to 0, then the EEPROM read has experienced a failure and the contents of the EEPROM programmable BCR register will be set to default
H_RESET values. The content of the Address PROM
locations, however, will not be cleared.
EEPROM MAP
The automatic EEPROM read operation will access 41
words (i.e., 82 bytes) of the EEPROM. The format of
the EEPROM contents is shown in Table 16, beginning
with the byte that resides at the lowest EEPROM address.
Note: The first bit out of any word location in the EEPROM is treated as the MSB of the register being programmed. For example, the first bit out of EEPROM
word location 09h will be written into BCR4, bit 15; the
second bit out of EEPROM word location 09h will be
written into BCR4, bit 14, etc.
In applications that want to use the pin to drive an LED
and also have an EEPROM, it might be necessary to
buffer the LED3 circuit from the EEPROM connection.
When an LED circuit is directly connected to the
EEDO/LED3 pin, then it is not possible for most EEPROM devices to sink enough IOL to maintain a valid
low level on the EEDO input to the controller. Use of
buffering can be avoided if a low power LED is used.
Each LED can be programmed through a BCR register
to indicate one or more of the following network status
or activities: Collision Status, Full-Duplex Link Status,
Half-Duplex Link Status, Receive Match, Receive Status, Magic Packet, Disable Transceiver, Transmit Status, Power, and Speed.
Am79C978
85
Table 16. EEPROM Map
Word
Address
Byte
Addr.
00h*
01h
01h
02h
03h
03h
05h
07h
04h
09h
05h
0Bh
06h
0Dh
07h
0Fh
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
11h
13h
15h
17h
19h
1Bh
1Dh
1Fh
21h
23h
25h
27h
29h
2Bh
2Dh
2Fh
31h
33h
35h
37h
39h
3Bh
3Dh
3Fh
41h
43h
45h
47h
49h
4Bh
4Dh
4Fh
28h
51h
3Eh
3Fh
7Dh
7Fh
Most Significant Byte
2nd byte of the ISO 8802-3 (IEEE/ANSI
802.3) station physical address for this node
00h
Least Significant Byte
First byte of the IS0 8802-3 (IEEE/ANSI 802.3)
station physical address for this node, where
“first byte” refers to the first byte to appear on
the 802.3 medium
3rd byte of the node address
5th byte of the node address
CSR116[7:0] (OnNow Misc. Configuration)
4th byte of the node address
02h
6th byte of the node address
04h
CSR116[15:8] (OnNow Misc. Configuration)
06h
Hardware ID: must be 11h if compatibility to
08h
Reserved location: must be 00h
AMD drivers is desired
User programmable space
0Ah
User programmable space
MSB of two-byte checksum, which is the sum
LSB of two-byte checksum, which is the sum
0Ch
of bytes 00h-0Bh and bytes 0Eh and 0Fh
of bytes 00h-0Bh and bytes 0Eh and 0Fh
Must be ASCII “W” (57h) if compatibility to
Must be ASCII “W” (57h) if compatibility to
0Eh
AMD driver software is desired
AMD driver software is desired
BCR2[15:8] (Miscellaneous Configuration)
10h
BCR2[7:0] (Miscellaneous Configuration)
BCR4[15:8] (Link Status LED)
12h
BCR4[7:0] (Link Status LED)
BCR5[15:8] (LED1 Status)
14h
BCR5[7:0] (LED1 Status)
BCR6[15:8] (LED2 Status)
16h
BCR6[7:0] (LED2 Status)
BCR7[15:8] (LED3 Status)
18h
BCR7[7:0] (LED3 Status)
BCR9[15:8] (Full-Duplex control)
1Ah
BCR9[7:0] (Full-Duplex Control)
BCR18[15:8] (Burst and Bus Control)
1Ch
BCR18[7:0] (Burst and Bus Control)
BCR22[15:8] (PCI Latency)
1Eh
BCR22[7:0] (PCI Latency)
BCR23[15:8] (PCI Subsystem Vendor ID)
20h
BCR23[7:0] (PCI Subsystem Vendor ID)
BCR24[15:8] (PCI Subsystem ID)
22h
BCR24[7:0] (PCI Subsystem ID)
BCR25[15:8] (SRAM Size)
24h
BCR25[7:0] (SRAM Size)
BCR26[15:8] (SRAM Boundary)
26h
BCR26[7:0] (SRAM Boundary)
BCR27[15:8] (SRAM Interface Control)
28h
BCR27[7:0] (SRAM Interface Control)
BCR32[15:8] (MII Control and Status)
2Ah
BCR32[7:0] (MII Control and Status)
BCR33[15:8] (MII Address)
2Ch
BCR33[7:0] (MII Address)
BCR35[15:8] (PCI Vendor ID)
2Eh
BCR35[7:0] (PCI Vendor ID)
BCR36[15:8] (Conf. Space. byte 43h alias)
30h
BCR36[7:0] (Conf. Space byte 42h alias)
BCR37[15:8] (DATA_SCALE alias 0)
32h
BCR37[7:0] (Conf. Space byte 47h0alias)
BCR38[15:8] (DATA_SCALE alias 1)
34h
BCR38[7:0] (Conf. Space byte 47h1alias)
BCR39[15:8] (DATA_SCALE alias 2)
36h
BCR39[7:0] (Conf. Space byte 47h2alias)
BCR40[15:8] (DATA_SCALE alias 3)
38h
BCR40[7:0] (Conf. Space byte 47h3alias)
BCR41[15:8] (DATA_SCALE alias 4)
3Ah
BCR41[7:0] (Conf. Space byte 47h4alias)
BCR42[15:8] (DATA_SCALE alias 0)
3Ch
BCR42[7:0] (Conf. Space byte 47h5alias)
BCR43[15:8] (DATA_SCALE alias 0)
3Eh
BCR43[7:0] (Conf. Space byte 47h6alias)
BCR44[15:8] (DATA_SCALE alias 0)
40h
BCR44[7:0] (Conf. Space byte 47h7alias)
BCR48[15:8] (LED4 Status)
42h
BCR48[7:0] (LED4 Status)
BCR49[15:8] (PHY Select)
44h
BCR49[7:0] (PHY Select)
BCR50[15:8]Reserved location: must be 00h
46h
BCR50[7:0]Reserved location: must be 00h
BCR51[15:8]Reserved location: must be 00h
48h
BCR51[7:0]Reserved location: must be 00h
BCR52[15:8]Reserved location: must be 00h
4Ah
BCR52[7:0]Reserved location: must be 00h
BCR53[15:8]Reserved location: must be 00h
4Ch
BCR53[7:0]Reserved location: must be 00h
BCR54[15:8]Reserved location: must be 00h
4Eh
BCR54[7:0]Reserved location: must be 00h
Checksum adjust byte for the 82 bytes of the
EEPROM contents, checksum of the 82 bytes
50h
BCR54[7:0]Reserved location: must be 00h
of the EEPROM should total to FFh
Empty locations – Ignored by device
Reserved
Reserved
7Ch
7Eh
Note: *Lowest EEPROM address.
86
Byte
Addr.
Am79C978
Reserved
Reserved
The LED pins can be configured to operate in either
open-drain mode (active low) or in totem-pole mode
(active high). The output can be stretched to allow the
human eye to recognize even short events that last
only several microseconds. After H_RESET, the five
LED outputs are configured as shown in Table 17.
COL
COLE
FDLS
FDLSE
LNKS
LNKSE
RCV
RCVE
Table 17. LED Default Configuration
To
Pulse
Stretcher
RCVM
RCVME
LED
Output
Indication
Driver Mode
Pulse Stretch
LED0
Link Status
Open Drain Active Low
Enabled
MR_SPEED_SEL
100E
LED1
Receive
Status
Open Drain Active Low
Enabled
MPS
MPSE
LED2
Power
Open Drain Active Low
Enabled
POWER
POWERE
LED3
Transmit
Status
Open Drain Active Low
Enabled
LED4
Speed
Open Drain Active Low
Enabled
XMT
XMTE
Figure 45.
22206B-49
LED Control Logic
The Am79C978 device supports three types of wakeup events:
For each LED register, each of the status signals is
AND’d with its enable signal, and these signals are all
OR’d together to form a combined status signal. Each
LED pin combined status signal can be programmed to
run to a pulse stretcher, which consists of a 3-bit shift
register clocked at 38 Hz (26 ms). The data input of
each shift register is normally at logic 0. The OR gate
output for each LED register asynchronously sets all
three bits of its shift register when the output becomes
asserted. The inverted output of each shift register is
used to control an LED pin. Thus, the pulse stretcher
provides 2 to 3 clocks of stretched LED output, or 52
ms to 78 ms. See Figure 45.
Power Savings Mode
Power Management Support
The controller supports power management as defined
in the PCI Bus Power Management Interface Specification V1.1 and Network Device Class Power Management Reference Specification V1.0a.These
specifications define the network device power states,
PCI power management interface including the Capabilities Data Structure and power management registers block definitions, power management events, and
OnNow network wake-up events.
The general scheme for the Am79C978 power management is that when a PCI wake-up event is detected,
a signal is generated to cause hardware external to the
Am79C978 device to put the computer into the working
(S0) mode.
1. Magic Packet Detect
2. OnNow Pattern Match Detect
3. Link State Change
Figure 46 shows the relationship between these wakeup events and the various outputs used to signal to the
external hardware.
OnNow Wake-Up Sequence
The system software enables the PME pin by setting
the PME_EN bit in the PMCSR register (PCI configuration registers, offset 44h, bit 8) to 1. When a wake-up
event is detected, the controller sets the PME_STATUS
bit in the PMCSR register (PCI configuration registers,
offset 44h, bit 15). Setting this bit causes the PME signal to be asserted. Assertion of the PME signal causes
external hardware to wake up the CPU. The system
software then reads the PMCSR register of every PCI
device in the system to determine which device asserted the PME signal.
When the software determines that the signal came
from the controller, it writes to the device's PMCSR to
put the device into power state D0. The software then
writes a 0 to the PME_STATUS bit to clear the bit and
turn off the PME signal, and it calls the device's software driver to tell it that the device is now in state D0.
The system software can clear the PME_STATUS bit
either before, after, or at the same time that it puts the
device back into the D0 state.
Am79C978
87
Magic Packet
MPPEN
PG
MPMAT
S SET Q
MPMODE
MPEN
R CLR Q
POR
MPDETECT
Link Change
LCMODE
S SET Q
LCDET
S SET Q
Link Change
R CLR Q
H_RESET
R CLR Q
POR
PME_STATUS
S DET Q
Pattern Match
POR
BCR47
Input
Pattern
BCR46
BCR45
S SET Q
Pattern Match RAM (PMR)
R CLR Q
PMAT
R CLR Q
POR
PME Status
PME_EN
MPMAT
PME
PME_EN_OVR
LCEVENT
22206B-50
Figure 46. OnNow Functional Diagram
Link Change Detect
Link change detect is one of wake-up events defined
by the OnNow specification. Link Change Detect mode
is set when the LCMODE bit (CSR116, bit 8) is set either by software or loaded through the EEPROM.
When this bit is set, any change in the Link status will
cause the LCDET bit (CSR116, bit 9) to be set. When
the LCDET bit is set, the PME_STATUS bit (PMCSR
register, bit 15) will be set. If either the PME_EN bit
(PMCSR, bit 8) or the PME_EN_OVR bit (CSR116, bit
10) are set, then the PME will also be asserted.
OnNow Pattern Match Mode
In the OnNow Pattern Match Mode, the Am79C978 device compares the incoming packets with up to eight
patterns stored in the Pattern Match RAM (PMR). The
stored patterns can be compared with part or all of in-
88
coming packets, depending on the pattern length and
the way the PMR is programmed. When a pattern
match has been detected, then PMAT bit (CSR116, bit
7) is set. The setting of the PMAT bit causes the
PME_STATUS bit (PMCSR, bit 15) to be set, which in
turn will assert the PME pin if the PME_EN bit
(PMCSR, bit 8) is set.
Pattern Match RAM (PMR)
PMR is organized as an array of 64 words by 40 bits as
shown in Figure 47. The PMR is programmed indirectly
through BCRs 45, 46, and 47. When BCR45 is written
and the PMAT_MODE bit (BCR45, bit 7) is set to 1,
Pattern Match logic is enabled. No bus accesses into
the PMR are possible when the PMAT_MODE bit is
set, and BCR46, BCR47, and all other bits in BCR45
are ignored. When PMAT_MODE is set, a read of
BCR45 returns all bits undefined except for
Am79C978
PMAT_MODE. In order to access the contents of the
PMR, PMAT_MODE bit should be programmed to 0.
When BCR45 is written to set the PMAT_MODE bit to
0, the Pattern Match logic is disabled and accesses to
the PMR are possible. Bits 6:0 of BCR45 specify the
address of the PMR word to be accessed. Writing to
BCR45 does not immediately affect the contents of the
PMR. Following the write to BCR45, the PMR word addressed by bits 6:0 of BCR45 may be read by reading
BCR45, BCR46, and BCR47 in any order. To write to
the PMR word, the write to BCR45 must be followed
by a write to BCR46 and a write to BCR47 in that order
to complete the operation. The PMR will not actually be
written until the write to BCR47 is complete.
The first two 40-bit words in this RAM serve as pointers
and contain enable bits for the eight possible match
patterns. The remainder of the RAM contains the
match patterns and associated match pattern control
bits. Byte 0 of the first word contains the pattern enable
bits. Any bit position set in this byte enables the corresponding match pattern in the PMR, as an example if
the bit 3 is set, then pattern 3 is enabled for matching.
Bytes 1 to 4 in the first word are pointers to the beginning of the patterns 0 to 3, and bytes 1 to 4 in the second word are pointers to the beginning of patterns 4 to
7, respectively. Byte 0 of the second word has no function associated with it. Byte 0 of the words 2 to 63 is the
control field of the PMR. Bit 7 of this field is the End of
Packet (EOP) bit. When this bit is set, it indicates the
end of a pattern in the PMR. Bits 6-4 of the control field
byte are the SKIP bits. The value of the SKIP field indicates the number of the Dwords to be skipped before
the pattern in this PMR word is compared with data
from the incoming frame. A maximum of seven Dwords
may be skipped. Bits 3-0 of the control field byte are the
MASK bits. These bits correspond to the pattern match
bytes 3-0 of the same PMR word (PMR bytes 4-1). If bit
n of this field is 0, then byte n of the corresponding pattern word is ignored. If this field is programmed to 3,
then bytes 0 and 1 of the pattern match field (bytes 2
and 1 of the word) are used, and bytes 3 and 2 are ignored in the pattern matching operation.
The contents of the PMR ar e not affected by
H_RESET, S_RESET, or STOP. The contents are undefined after a power up reset (POR).
Magic Packet Mode
In Magic Packet mode, the controller remains fully
powered up (all VDD and VDDB pins must remain at
their supply levels). The device will not generate any
bus master transfers. No transmit operations will be initiated on the network. The device will continue to receive frames from the network, but all frames will be
automatically flushed from the receive FIFO. Slave accesses to the controller are still possible. A Magic
Packet is a frame that is addressed to the controller
and contains a data sequence anywhere in its data
field made up of 16 consecutive copies of the device’s
physical address (PADR[47:0]). The controller will
search incoming frames until it finds a Magic Packet
frame. It starts scanning for the sequence after processing the length field of the frame. The data sequence can begin anywhere in the data field of the
frame, but must be detected before the controller
reaches the frame’s FCS field. Any deviation of the incoming frame’s data sequence from the required physical address sequence, even by a single bit, will
prevent the detection of that frame as a Magic Packet
frame.
The controller supports two different modes of address
detection for a Magic Packet frame. If MPPLBA (CSR5,
bit 5) or EMPPLBA (CSR116, bit 6) are at their default
value of 0, the controller will only detect a Magic Packet
frame if the destination address of the packet matches
the content of the physical address register (PADR). If
MPPLBA or EMPPLBA are set to 1, the destination address of the Magic Packet frame can be unicast, multicast, or broadcast.
Note: The setting of MPPLBA or EMPPLBA only effects the address detection of the Magic Packet frame.
The Magic Packet’s data sequence must be made up
of 16 consecutive copies of the device’s physical address (PADR[47:0]), regardless of what kind of destination address it has.
There are two general methods to place the controller
into Magic Packet mode. The first is the software
method. In this method, either the BIOS or other software sets the MPMODE bit (CSR5, bit 1). Then the
controller must be put into suspend mode (see description of CSR5, bit 0), allowing any current network activity to finish. Finally, either PG must be deasserted
(hardware control), or MPEN (CSR5, bit 2) must be set
to 1 (software control).
Note: FASTSPNDE (CSR7, bit 15) has no meaning in
Magic Packet mode.
The second method is the hardware method. In this
method, the MPPEN bit (CSR116, bit 4) is set at power
up by the loading of the EEPROM. This bit can also be
set by software. The controller will be placed in the
Magic Packet Mode when either the PG input is deasserted or the MPEN bit is set. Magic Packet mode can
be disabled at any time by asserting PG or clearing
MPEN bit.
Am79C978
89
BCR 47
BCR Bit Number 15
8
7
PMR_B4
Pattern Match
RAM Address
BCR 46
0 15
8
PMR_B3
PMR_B2
BCR 45
7
0 15
PMR_B1
8
PMR_B0
Pattern Match RAM Bit Number
39
32
31
24
23
16
15
8
7
0
Comments
0
P3 pointer
P2 pointer
P1 pointer
P0 pointer
Pattern Enable
bits
First Address
1
P7 pointer
P6 pointer
P5 pointer
P4 pointer
X
Second
Address
2
Data Byte 3
Data Byte 2
Data Byte1
Data Byte 0
Pattern Control
Start Pattern
P1
2+n
Data Byte 4n+3
Date Byte 4n+2
Data Byte 4n+1
Data Byte 4n+0
J
Data Byte 3
Data Byte 2
Data Byte 1
Data Byte 0
J+m
Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0
Pattern Control End Pattern P1
Pattern Control
Start Pattern
Pk
Pattern Control End Pattern Pk
63
Last Address
7
EOP
6
5 4
SKIP
3
2
1 0
MASK
22206B-51
Figure 47. Pattern Match RAM
When the controller detects a Magic Packet frame, it
sets the MPMAT bit (CSR116, bit 5), the MPINT bit
(CSR5, bit 4), and the PME_STATUS bit (PMCSR, bit
15). If the PME_EN or the PME_EN_OVR bits are set,
the PME will be asserted as well. If IENA (CSR0, bit 6)
and MPINTE (CSR5, bit 3) are set to 1, INTA will be asserted. Any one of the four LED pins can be programmed to indicate that a Magic Packet frame has
been received. MPSE (BCR4-7, bit 9) must be set to 1
to enable that function.
Note: The polarity of the LED pin can be programmed
to be active HIGH by setting LEDPOL (BCR4-7, bit 14)
to 1.
Once a Magic Packet frame is detected, the controller
will discard the frame internally, but will not resume nor-
90
mal transmit and receive operations until PG is asserted or MPEN is cleared. Once both of these events
has occurred, indicating that the system has detected
the Magic Packet and is awake, the controller will continue polling receive and transmit descriptor rings
where it left off. It is not necessary to re-initialize the device. If the part is re-initialized, then the descriptor locations will be reset and the controller will not start where
it left off.
If magic packet mode is disabled by the assertion of
PG, then in order to immediately re-enable Magic
Packet mode, the PG pin must remain deasserted for
at least 200 ns before it is reasserted. If Magic Packet
mode is disabled by clearing MPEN bit, then it may be
immediately re-enabled by setting MPEN back to 1.
Am79C978
The PCI bus interface clock (CLK) is not required to be
running while the device is operating in Magic Packet
mode. Either of the INTA, the LED pins, or the PME signal may be used to indicate the receipt of a Magic
Packet frame when the CLK is stopped. If the system
wishes to stop the CLK, it will do so after enabling the
Magic Packet mode.
CAUTION: To prevent unwanted interrupts from other
active parts of the controller, care must be taken to
mask all likely interruptible events during Magic Packet
mode. An example would be the interrupts from the
Media Independent Interface, which could occur while
the device is in Magic Packet mode.
IEEE 1149.1 (1990) Test Access Port
Interface
An IEEE 1149.1-compatible boundary scan Test Access Port is provided for board-level continuity test and
diagnostics. All digital input, output, and input/output
pins are tested. The following paragraphs summarize
the IEEE 1149.1-compatible test functions implemented in the controller.
Boundary Scan Circuit
Table 18. IEEE 1149.1 Supported Instruction
Summary
Mode
Selected
Data
Register
Test
BSR
Normal
ID REG
Normal
BSR
Force Float
Normal
Bypass
0100
Control
Boundary to
I/0
Test
Bypass
1111
Bypass Scan Normal
Instruction Instruction
Description
Name
Code
EXTEST
0000
IDCODE
0001
SAMPLE
0010
TRIBYP
0011
SETBYP
BYPASS
External Test
ID Code
Inspection
Sample
Boundary
Bypass
Instruction Register and Decoding Logic
After the TAP FSM is reset, the IDCODE instruction is
always invoked. The decoding logic gives signals to
control the data flow in the data registers according to
the current instruction.
Boundary Scan Register
The boundary scan test circuit requires four pins (TCK,
TMS, TDI, and TDO), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an instruction register, a data register array, and a power-on
reset circuit. Internal pull-up resistors are provided for
the TDI, TCK, and TMS pins.
Each Boundary Scan Register (BSR) cell has two
stages. A flip-flop and a latch are used for the Serial
Shift Stage and the Parallel Output Stage, respectively.
There are four possible operation modes in the BSR
cell shown in Table 19.
TAP Finite State Machine
The TAP engine is a 16-state finite state machine
(FSM), driven by the Test Clock (TCK), and the Test
Mode Select (TMS) pins. An independent power-on
reset circuit is provided to ensure that the FSM is in the
TEST_LOGIC_RESET state at power-up. Therefore,
the TRST is not provided. The FSM is also reset when
TMS and TDI are high for five TCK periods.
Table 19. BSR Mode Of Operation
1
2
3
4
Capture
Shift
Update
System Function
Other Data Registers
Other data registers are the following:
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP, and SETBYP) are provided to further ease board-level testing.
All unused instruction codes are reserved. See Table
18 for a summary of supported instructions.
1. Bypass register (1 bit)
2. Device ID register (32 bits) (Table 20).
Table 20. Device ID Register
Bits 31-28
Version
Bits 27-12
Part Number (0010 0110 0010 0110)
Bits 11-1
Manufacturer ID. The 11 bit manufacturer ID
cod for AMD is 00000000001 in accordance
with JEDEC publication 106-A.
Bit 0
Always a logic 1
Note: The content of the Device ID register is the
same as the content of CSR88.
Am79C978
91
NAND Tree Testing
The controller provides a NAND tree test mode to allow
checking connectivity to the device on a printed circuit
board. The NAND tree is built on all PCI bus pins.
NAND tree testing is enabled by asserting RST. PG
input should be driven HIGH during NAND tree testing.
All PCI bus signals will become inputs on the assertion
of RST. The result of the NAND tree test can be observed on the INTA pin. See Figure 48.
Pin 141 (RST) is the first input to the NAND tree. Pin
142 (CLK) is the second input to the NAND tree, followed by pin 143 (GNT). All other PCI bus signals follow, counterclockwise, with pin 61 (AD0) being the last.
Table 21 and Table 22 shows the complete list of pins
connected to the NAND tree.
RST must be asserted low to start a NAND tree test sequence. Initially, all NAND tree inputs except RST
should be driven high. This will result in a high output
at the INTA pin. If the NAND tree inputs are driven from
high to low in the same order as they are connected to
build the NAND tree, INTA will toggle every time an additional input is driven low. INTA will change to low,
when CLK is driven low and all other NAND tree inputs
stay high. INTA will toggle back to high, when GNT is
additionally driven low. The square wave will continue
until all NAND tree inputs are driven low. INTA will be
high, when all NAND tree inputs are driven low. See
Figure 49.
Some of the pins connected to the NAND tree are outputs in normal mode of operation. They must not be
driven from an external source until the controller is
configured for NAND tree testing.
VDD
RST (pin141)
Am79C978
Core
CLK (pin 142)
Am79C972
Core
GNT (pin 143)
....
INTA
B S
O
INTA (pin 140)
A
MUX
AD0 (pin 61)
22206B-52
Figure 48. NAND Tree Circuitry (160 PQFP)
92
Am79C978
Table 21.
NAND
Tree Input
No.
Pin No.
NAND Tree Pin Sequence (160 PQFP)
NAND Tree
Input No. Pin No.
Name
Name
NAND Tree
Input No.
Pin No.
Name
1
141
RST
18
9
AD20
35
36
AD13
2
142
PCI_CLK
19
11
AD19
36
38
AD12
3
143
GNT
20
12
AD18
37
43
AD11
4
144
REQ
21
14
AD17
38
45
AD10
5
146
AD31
22
16
AD16
39
46
AD9
6
149
AD30
23
17
C/BE2
40
47
AD8
7
150
AD29
24
19
FRAME
41
48
C/BE0
8
151
AD28
25
20
IRDY
42
50
AD7
9
152
AD27
26
22
TRDY
43
52
AD6
10
154
AD26
27
24
DEVSEL
44
53
AD5
11
156
AD25
28
25
STOP
45
55
AD4
12
157
AD24
29
27
PERR
46
56
AD3
13
158
C/BE3
30
28
SERR
47
58
AD2
14
3
IDSEL
31
30
PAR
48
60
AD1
15
4
AD23
32
32
C/BE1
49
61
AD0
16
6
AD22
33
33
AD15
50
17
8
AD21
34
35
AD14
51
Pin No.
Name
Table 22. NAND Tree Pin Sequence (144 TQFP)
NAND
Tree Input
No.
Pin No.
Name
NAND Tree
Input No. Pin No.
Name
NAND Tree
Input No.
1
127
RST
18
7
AD20
35
34
AD13
2
128
PCI_CLK
19
9
AD19
36
36
AD12
3
129
GNT
20
10
AD18
37
37
AD11
4
130
REQ
21
12
AD17
38
39
AD10
5
132
AD31
22
14
AD16
39
40
AD9
6
135
AD30
23
15
C/BE2
40
41
AD8
7
136
AD29
24
17
FRAME
41
42
C/BE0
8
137
AD28
25
18
IRDY
42
44
AD7
9
138
AD27
26
20
TRDY
43
46
AD6
10
140
AD26
27
22
DEVSEL
44
47
AD5
11
142
AD25
28
23
STOP
45
49
AD4
12
143
AD24
29
25
PERR
46
50
AD3
13
144
C/BE3
30
26
SERR
47
52
AD2
14
1
IDSEL
31
28
PAR
48
54
AD1
15
2
AD23
32
30
C/BE1
49
55
AD0
16
4
AD22
33
31
AD15
17
6
AD21
34
33
AD14
Am79C978
93
RST
CLK
GNT
REQ
AD[31:0]
C/BE[3:0]
0000FFFF
FFFFFFFF
F
3
7
1
IDSEL
FRAME
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
PAR
...
...
...
INTA
22206B-53
Figure 49. NAND Tree Waveform
Reset
There are four different types of RESET operations that
may b e perfo rme d on the Am7 9C978 dev ic e,
H_RESET, S_RESET, STOP, and POR. The following
is a description of each type of RESET operation.
H_RESET
Hardware Reset (H_RESET) is an Am79C978 reset
operation that has been created by the proper assertion of the RST pin of the Am79C978 device while the
PG pin is HIGH. When the minimum pulse width timing
as specified in the RST pin description has been satisfied, an internal reset operation will be performed.
H_RESET will program most of the CSR and BCR registers to their default value. Note that there are several
CSR and BCR registers that are undefined after
H_RESET. See the sections on the individual registers
for details.
H_RESET will clear most of the registers in the PCI
configuration space. H_RESET will cause the microcode program to jump to its reset state. Following the
end of the H_RESET operation, the controller will attempt to read the EEPROM device through the EEPROM interface.
H_RESET will clear DWIO (BCR18, bit 7) and the controller will be in 16-bit I/O mode after the reset operation. A DWord write operation to the RDP (I/O offset
94
10h) must be performed to set the device into 32-bit
I/O mode.
S_RESET
Software Reset (S_RESET) is an Am79C978 reset operation that has been created by a read access to the
Reset register, which is located at offset 14h in Word
I/O mode or offset 18h in DWord I/O mode from the
Am79C978 I/O or memory mapped I/O base address.
S_RESET will reset all of or some portions of CSR0, 3,
4, 15, 80, 100, and 124 to default values. For the identity of individual CSRs and bit locations that are affected by S_RESET, see the individual CSR register
descriptions. S_RESET will not affect any PCI configuration space location. S_RESET will not affect any of
the BCR register values. S_RESET will cause the microcode program to jump to its reset state. Following
the end of the S_RESET operation, the controller will
not attempt to read the EEPROM device. After
S_RESET, the host must perform a full re-initialization
of the controller before starting network activity.
S_RESET will cause REQ to deassert immediately.
STOP (CSR0, bit 2) or SPND (CSR5, bit 0) can be
used to terminate any pending bus mastership request
in an orderly sequence.
S_RESET terminates all network activity abruptly. The
host can use the suspend mode (SPND, CSR5, bit 0)
to terminate all network activity in an orderly sequence
before issuing an S_RESET.
Am79C978
STOP
A STOP reset is generated by the assertion of the
STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0,
when the stop bit currently has a value of 0, will initiate
a STOP reset. If the STOP bit is already a 1, then writing a 1 to the STOP bit will not generate a STOP reset.
STOP will reset all or some portions of CSR0, 3, and 4
to default values. For the identity of individual CSRs
and bit locations that are affected by STOP, see the individual CSR register descriptions. STOP will not affect
any of the BCR and PCI configuration space locations.
STOP will cause the microcode program to jump to its
reset state. Following the end of the STOP operation,
the controller will not attempt to read the EEPROM device.
Note: STOP will not cause a deassertion of the REQ
signal, if it happens to be active at the time of the write
to CSR0. The controller will wait until it gains bus ownership, and it will first finish all scheduled bus master
accesses before the STOP reset is executed.
STOP terminates all network activity abruptly. The host
can use the suspend mode (SPND, CSR5, bit 0) to ter-
Table 24.
31
24
23
Device ID
Status
16
minate all network activity in an orderly sequence before setting the STOP bit.
Power on Reset
Power on Reset (POR) is generated when the controller is powered up. POR generates a hardware reset
(H_RESET). In addition, it clears some bits that
H_RESET does not affect.
Software Access
PCI Configuration Registers
The controller implements the 256-byte configuration
space as defined by the PCI draft specification revision
2.2. The 64-byte header includes all registers required
to identify the controller and its function. Additionally,
PCI Power Management Interface registers are implemented at location 40h - 47h. The layout of the PCI
configuration space is shown in Table 24.
The PCI configuration registers are accessible only by
configuration cycles. All multi-byte numeric fields follow
little endian byte ordering. All write accesses to Reserved locations have no effect; reads from these locations will return a data value of 0.
PCI Configuration Space Layout
15
8
7
0
Vendor ID
Command
Base-Class
Sub-Class
Programming IF
Revision ID
Reserved
Header Type
Latency Timer
Reserved
I/O Base Address
Memory Mapped I/O Base Address
Reserved
Reserved
Reserved
Reserved
Reserved
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
CAP-PTR
Reserved
MAX_LAT
MIN_GNT
Interrupt Pin
Interrupt Line
PMC
NXT_ITM_PTR
CAP_ID
DATA_REG
PMCSR_BSE
PMCSR
Reserved
.
FCh
Reserved
I/O Resources
The Am79C978 controller requires 32 bytes of address
space for access to all the various internal registers as
well as to some setup information stored in an external
serial EEPROM. A software reset port is available, too.
Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44H
.
The Am79C978 controller supports mapping the address space to both I/O and memory space. The value
in the PCI I/O Base Address register determines the
start address of the I/O address space. The register is
typically programmed by the PCI configuration utility
after system power-up.
Am79C978
95
The PCI configuration utility must also set the IOEN bit
in the PCI Command register to enable I/O accesses to
the Am79C978 controller. For memory mapped I/O access, the PCI Memory Mapped I/O Base Address register controls the start address of the memory space.
The MEMEN bit in the PCI Command register must also
be set to enable the mode. Both base address registers
can be active at the same time.
The Am79C978 controller supports two modes for accessing the I/O resources. For backwards compatibility
with AMD’s 16-bit Ethernet controllers, Word I/O is the
default mode after power up. The device can be configured to DWord I/O mode by software.
I/O Registers
The Am79C978 controller registers are divided into two
groups. The Control and Status Registers (CSR) are
used to configure the Ethernet MAC engine and to obtain status information. The Bus Control Registers
(BCR) are used to configure the bus interface unit and
the LEDs. Both sets of registers are accessed using indirect addressing.
The CSR and BCR share a common Register Address
Port (RAP). There are, however, separate data ports.
The Register Data Port (RDP) is used to access a
CSR. The BCR Data Port (BDP) is used to access a
BCR.
In order to access a particular CSR location, the RAP
should first be written with the appropriate CSR address. The RDP will then point to the selected CSR. A
read of the RDP will yield the selected CSR data. A
write to the RDP will write to the selected CSR. In order
to access a particular BCR location, the RAP should
first be written with the appropriate BCR address. The
BDP will then point to the selected BCR. A read of the
BDP will yield the selected BCR data. A write to the
BDP will write to the selected BCR.
Once the RAP has been written with a value, the RAP
value remains unchanged until another RAP write occurs, or until an H_RESET or S_RESET occurs. RAP
is cleared to all 0s when an H_RESET or S_RESET occurs. RAP is unaffected by setting the STOP bit.
Address PROM Space
The Am79C978 controller allows for connection of a
serial EEPROM. The first 16 bytes of the EEPROM will
be automatically loaded into the Address PROM
(APROM) space after H_RESET. Additionally, the first
six bytes of the EEPROM will be loaded into CSR12 to
CSR14. The Address PROM space is a convenient
place to store the value of the 48-bit IEEE station address. It can be overwritten by the host computer, and
its content has no effect on the operation of the
Am79C978 controller. The software must copy the station address from the Address PROM space to the ini-
96
tialization block in order for the receiver to accept
unicast frames directed to this station.
The six bytes of the IEEE station address occupy the
first six locations of the Address PROM space. The
next six bytes are reserved. Bytes 12 and 13 should
match the value of the checksum of bytes 1 through 11
and 14 and 15. Bytes 14 and 15 should each be ASCII
“W” (57h). The above requirements must be met in
order to be compatible with AMD driver software.
APROMWE bit (BCR2, bit 8) must be set to 1 to enable
write access to the Address PROM space.
Reset Register
A read of the Reset register creates an internal software reset (S_RESET) pulse in the Am79C978 controller. The internal S_RESET pulse that is generated by
this access is different from both the assertion of the
hardware RST pin (H_RESET) and from the assertion
of the software STOP bit. Specifically, S_RESET is the
equivalent of the assertion of the RST pin (H_RESET)
except that S_RESET has no effect on the BCR or PCI
Configuration space locations.
The NE2100 LANCE-based family of Ethernet cards
requires that a write access to the Reset register follows each read access to the Reset register. The
Am79C978 controller does not have a similar requirement. The write access is not required and does not
have any effect.
Note: The Am79C978 controller cannot service any
slave accesses for a very short time after a read access
of the Reset register, because the internal S_RESET
operation takes about 1 ms to finish. The Am79C978
controller will terminate all slave accesses with the assertion of DEVSEL and STOP while TRDY is not asserted, signaling to the initiator to disconnect and retry
the access at a later time.
Word I/O Mode
After H_RESET, the Am79C978 controller is programmed to operate in Word I/O mode. DWIO (BCR18,
bit 7) will be cleared to 0. Table 25 shows how the 32
bytes of address space are used in Word I/O mode.
All I/O resources must be accessed in word quantities
and on word addresses. The Address PROM locations
can also be read in byte quantities. The only allowed
DWord operation is a write access to the RDP, which
switches the device to DWord I/O mode. A read access
other than listed in the table below will yield undefined
data; a write operation may cause unexpected reprogramming of the Am79C978 control registers. Table 26
shows legal I/O accesses in Word I/O mode.
Am79C978
Table 25.
I/O Map in Word I/O Mode (DWIO = 0)
Offset
No. of
Bytes
Register
00h - 0Fh
16
APROM
10h
2
RDP
12h
2
RAP (shared by RDP and BDP)
14h
2
Reset Register
16h
2
BDP
18h - 1Fh
8
Reserved
Double Word I/O Mode
The Am79C978 controller can be configured to operate
in DWord (32-bit) I/O mode. The software can invoke
the DWIO mode by performing a DWord write access
to the I/O location at offset 10h (RDP). The data of the
write access must be such that it does not affect the intended operation of the Am79C978 controller. Setting
the device into 32-bit I/O mode is usually the first operation after H_RESET or S_RESET. The RAP register
will point to CSR0 at that time. Writing a value of 0 to
CSR0 is a safe operation. DWIO (BCR18, bit 7) will be
set to 1 as an indication that the Am79C978 controller
operates in 32-bit I/O mode.
Note: Even though the I/O resource mapping changes
when the I/O mode setting changes, the RDP location
offset is the same for both modes. Once the DWIO bit
has been set to 1, only H_RESET can clear it to 0. The
DWIO mode setting is unaffected by S_RESET or setting of the STOP bit. Table 27 shows how the 32 bytes
of address space are used in DWord I/O mode.
All I/O resources must be accessed in DWord quantities and on DWord addresses. A read access other
than listed in Table 27 will yield undefined data, a write
operation may cause unexpected reprogramming of
the Am79C978 control registers.
Table 26. Legal I/O Accesses in Word I/O Mode (DWIO = 0)
AD[4:0]
BE[3:0]
Type
Comment
0XX00
1110
RD
Byte read of APROM location 0h, 4h, 8h, or Ch
0XX01
1101
RD
Byte read of APROM location 1h, 5h, 9h, or Dh
0XX10
1011
RD
Byte read of APROM location 2h, 6h, Ah, or Eh
0XX11
0111
RD
Byte read of APROM location 3h, 7h, Bh, or Fh
0XX00
1100
RD
Word read of APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h, or
Ch and Dh
0XX10
0011
RD
Word read of APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah, or
Fh and Eh
10000
1100
RD
Word read of RDP
10010
0011
RD
Word read of RAP
10100
1100
RD
Word read of Reset Register
10110
0011
RD
Word read of BDP
0XX00
1100
WR
Word write to APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h, or
Ch and Dh
0XX10
0011
WR
Word write to APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah, or
Fh and Eh
10000
1100
WR
Word write to RDP
10010
0011
WR
Word write to RAP
10100
1100
WR
Word write to Reset Register
10110
0011
WR
Word write to BDP
10000
0000
WR
DWord write to RDP,
switches device to DWord I/O mode
Am79C978
97
Table 27.
I/O Map in DWord I/O Mode (DWIO = 1)
Offset
No. of Bytes
Register
00h - 0Fh
16
APROM
10h
4
RDP
14h
4
RAP (shared by RDP and
BDP)
18h
4
Reset Register
1Ch
4
BDP
Table 28.
AD[4:0]
Legal I/O Accesses in Double Word I/O
Mode (DWIO =1)
BE[3:0]
Type
Comment
0XX00
0000
RD
DWord read of APROM
locations 3h (MSB) to 0h
(LSB),
7h to 4h, Bh to 8h, or Fh to
Ch
10000
0000
RD
DWord read of RDP
10100
0000
RD
DWord read of RAP
11000
0000
RD
DWord read of Reset
Register
WR
DWord write to APROM
locations 3h (MSB) to 0h
(LSB),
7h to 4h, Bh to 8h, or Fh to
Ch
0XX00
0000
10000
0000
WR
DWord write to RDP
10100
0000
WR
DWord write to RAP
11000
0000
WR
DWord write to Reset
Register
IEEE 802.3, Section 14.3.1.2. The load is a twisted pair
cable that meets IEEE 802.3, Section 14.4.
The TX± signal is filtered on the chip to reduce harmonic content per Section 14.3.2.1 (10BASE-T). Since
filtering is performed in silicon, TX± can be connected
directly to a standard transformer. External filtering
modules are not needed.
Twisted Pair Receive Function
The RX+ port is a differential twisted-pair receiver.
When properly terminated, the RX+ port will meet the
electrical requirements for 10BASE-T receivers as
specified in IEEE 802.3, Section 14.3.1.3. The receiver
has internal filtering and does not require external filter
modules or common mode chokes.
Signals appearing at the RX± differential input pair are
routed to the internal decoder. The receiver function
meets the propagation delays and jitter requirements
specified by the 10BASE-T standard. The receiver
squelch level drops to half its threshold value after unsquelch to allow reception of minimum amplitude signals and to mitigate carrier fade in the event of worst
case signal attenuation and crosstalk noise conditions.
Clock
Data
Manchester
Encoder
Clock
Data
Manchester
Decoder
10BASE-T Physical Layer
Squelch
Circuit
The 10BASE-T block consists of the following subblocks:
— Transmit Process
— Receive Process
TX Driver
RX Driver
TX±
RX±
— Interface Status
— Collision Detect Function
— Jabber Function
— Reverse Polarity Detect
Refer to Figure 50 for the 10BASE-T block diagram.
22206B-54
Figure 50. 10BASE-T Transmit and Receive Data
Paths
Twisted Pair Transmit Function
Data transmission over the 10BASE-T medium requires use of the integrated 10BASE-T MAU and uses
the differential driver circuitry on the TX± pins.
TX± is a differential twisted-pair driver. When properly
terminated, TX± will meet the transmitter electrical requirements for 10BASE-T transmitters as specified in
98
Twisted Pair Interface Status
The Am79C978 device will power up in the Link Fail
state. The Auto-Negotiation algorithm will apply to
allow it to enter the Link Pass state.
Am79C978
In the Link Pass state, receive activity which passes
the pulse width/amplitude requirements of the RX± inputs will cause the PCS Control block to assert Carrier
Sense (CRS) signal at the internal MII interface. A collision would cause the PCS Control block to assert Carrier Sense (CRS) and Collision (COL) signals at the
internal MII. In the Link Fail state, this block would
cause the PCS Control block to de-assert Carrier
Sense (CRS) and Collision (COL).
In jabber detect mode, this block would cause the PCS
Control block to assert the COL signal at the internal
MII and allow the PCS Control block to assert or de-assert the CRS pin to indicate the current state of the RX±
pair. If there is no receive activity on RX±, this block
would cause the PCS Control block to assert only the
COL pin at the internal MII. If there is RX± activity, this
block would cause the PCS Control block to assert
both COL and CRS at the internal MII.
Collision Detect Function
Simultaneous activity (presence of valid data signals)
from both the internal encoder transmit function and
the twisted pair RX± pins constitutes a collision,
thereby causing the PCS Control block to assert the
COL pin at the internal MII.
Jabber Function
The Jabber function inhibits the 10BASE-T twisted pair
transmit function of the Am79C978 device if the TX±
circuits are active for an excessive period (20-150 ms).
This prevents one port from disrupting the network due
to a stuck-on or faulty transmitter condition. If the maximum transmit time is exceeded, the data path through
the 10BASE-T transmitter circuitry is disabled (although Link Test pulses will continue to be sent). The
PCS Control block also asserts the COL signal at the
internal MII and sets the Jabber Detect bit in Register 1
of the active PHY. Once the internal transmit data
stream from the Manchester Encoder/Decoder stops,
an unjab time of 250-750 ms will elapse before this
block causes the PCS Control block to de-assert the
COL indication and re-enable the transmit circuitry.
When jabber is detected, this block will cause the PCS
Control block to assert the COL signal and allow the
PCS Control block to assert or de-assert the CRS signal to indicate the current state of the RX± pair. If there
is no receive activity on RX±, this block causes the
PCS Control block to assert only the COL signal at the
internal MII. If there is RX± activity, this block will cause
the PCS Control block to assert both COL and CRS on
the internal MII.
Reverse Polarity Detect
nored, but it will set the polarity to the correct state. The
reception of two consecutive packets will cause the polarity to be locked, based on the polarity of the ETD. In
order to change the polarity once it has been locked,
the link must be brought down and back up again.
Auto-Negotiation
The object of the Auto-Negotiation function is to determine the abilities of the devices sharing a link. After exchanging abilities, the Am79C978 device and remote
link partner device acknowledge each other and make
a choice of which advertised abilities to support. The
Auto-Negotiation function facilitates an ordered resolution between exchanged abilities. This exchange allows both devices at either end of the link to take
maximum advantage of their respective shared abilities.
The Am79C978 device implements the transmit and
receive Auto-Negotiation algorithm as defined in IEEE
802.3u, Section 28. The Auto-Negotiation algorithm
uses a burst of link pulses called Fast Link Pulses
(FLPs). The burst of link pulses are spaced between 55
and 140 µs so as to be ignored by the standard
10BASE-T algorithm. The FLP burst conveys information about the abilities of the sending device. The receiver can accept and decode an FLP burst to learn the
abilities of the sending device. The link pulses transmitted conform to the standard 10BASE-T template. The
device can perform auto-negotiation with reverse polarity link pulses.
The Am79C978 device uses the Auto-Negotiation algorithm to select the type connection to be established
according to the following priority: 10BASE-T full duplex, then 10BASE-T half-duplex. See Table 29.
The Auto-Negotiation algorithm is initiated by the following events: Auto-Negotiation enable bit is set, hardware reset, soft reset, transition to link fail state (when
Auto-Negotiation enable bit is set), or Auto-Negotiation
restart bit is set. The result of the Auto-Negotiation process can be read from the status register (Summary
Status Register, TBR24).
By default, the link partner must be at least 10BASE-T
half-duplex capable. The Am79C978 controller can automatically negotiate with the network and yield the
highest performance possible without software support. See the Network Port Manager section for more
details.
Table 29. Auto-Negotiation Capabilities
Network Speed
20 Mbps
10 Mbps
Physical Network Type
10BASE-T, Full Duplex
10BASE-T, Half Duplex
The polarity for 10BASE-T signals is set by reception of
Normal Link Pulses (NLP) or packets. Polarity is
locked, however, by incoming packets only. The first
NLP received when trying to bring the link up will be ig-
Am79C978
99
Auto-Negotiation goes further by providing a messagebased communication scheme called Next Pages before connecting to the Link Partner. This feature is not
supported in the Am79C978 device unless the DANAS
(BCR32, bit 10) is selected.
Soft Reset Function
The PHY Control Register (TBR0) incorporates the soft
reset function (bit 15). It is a read/write register and is
self-clearing. Writing a 1 to this bit causes a soft reset.
When read, the register returns a 1 if the soft reset is
still being performed; otherwise, it is cleared to 0. Note
100
that the register can be polled to verify that the soft
reset has terminated. Under normal operating conditions, soft reset will be finished in 150 clock cycles.
Soft reset only resets the 10BASE-T PHY unit registers
to default values (some register bits retain their previous values). Refer to the individual registers for values
after a soft reset. Soft reset does not reset the management interface.
Am79C978
USER ACCESSIBLE REGISTERS
The Am79C978 controller has four types of user registers: the PCI configuration registers, the Control and
Status registers (CSRs), the Bus Control registers
(BCRs), 10BASE-T PHY Management registers
(TBRs), and 1 Mbps HomePNA PHY Management registers (HPRs).
The Am79C978 controller implements all PCnet-ISA
(Am79C960) registers, all C-LANCE (Am79C90) registers, plus a number of additional registers. The
Am79C978 CSRs are compatible upon power up with
both the PCnet-ISA CSRs and all of the C-LANCE
CSRs.
The PCI configuration registers can be accessed in any
data width. All other registers must be accessed according to the I/O mode that is currently selected.
When WIO mode is selected, all other register locations are defined to be 16 bits in width. When DWIO
mode is selected, all these register locations are defined to be 32 bits in width, with the upper 16 bits of
most register locations marked as reserved locations
with undefined values. When performing register write
operations in DWIO mode, the upper 16 bits should always be written as zeros. When performing register
read operations in DWIO mode, the upper 16 bits of
I/O resources should always be regarded as having undefined values, except for CSR88.
The following is a list of the registers that would typically need to be programmed once during the setup of
the controller within a system. The control bits in each
of these registers typically do not need to be modified
once they have been written. However, there are no restrictions as to how many times these registers may actually be accessed. Note that if the default power up
values of any of these registers is acceptable to the application, then such registers need never be accessed
at all.
Note: Registers marked with “^” may be programmable through the EEPROM read operation and, therefore, do not necessarily need to be written to by the
system initialization procedure or by the driver software. Registers marked with “*” will be initialized by the
initialization block read operation.
CSR1
Initialization Block Address[15:0]
CSR2*
Initialization Block Address[31:16]
CSR3
Interrupt Masks and Deferral Control
CSR4
Test and Features Control
CSR5
Extended Control and Interrupt
CSR7
Extended Control and Interrupt2
CSR8*
Logical Address Filter[15:0]
CSR9*
Logical Address Filter[31:16]
The Am79C978 registers can be divided into four
groups: PCI Configuration, Setup, Running, and Test.
Registers not included in any of these categories can
be assumed to be intended for diagnostic purposes.
CSR10*
Logical Address Filter[47:32]
CSR11*
Logical Address Filter[63:48]
CSR12*^
Physical Address[15:0]
n PCI Configuration Registers
CSR13*^
Physical Address[31:16]
These registers are intended to be initialized by the
system initialization procedure (e.g., BIOS device initialization routine) to program the operation of the controller PCI bus interface.
CSR14*^
Physical Address[47:32]
CSR15*
Mode
CSR24*
Base Address of Receive Ring Lower
The following is a list of the registers that would typically need to be programmed once during the initialization of the Am79C978 controller within a system:
CSR25*
Base Address of Receive Ring Upper
CSR30*
Base Address of Transmit Ring Lower
CSR31*
Base Address of Transmit Ring Upper
CSR47*
Transmit Polling Interval
— PCI Expansion ROM Base Address register
CSR49*
Receive Polling Interval
— PCI Interrupt Line register
CSR76*
Receive Ring Length
CSR78*
Transmit Ring Length
CSR80
DMA Transfer Counter and FIFO Threshold Control
CSR82
Bus Activity Timer
CSR100
Memory Error Timeout
CSR116^
OnNow Miscellaneous
CSR122
Receiver Packet Alignment Control
— PCI I/O Base Address or Memory Mapped I/O
Base Address register
— PCI Latency Timer register
— PCI Status register
— PCI Command register
— OnNow register
n Setup Registers
These registers are intended to be initialized by the device driver to program the operation of various controller features.
Am79C978
101
CSR125^
MAC Enhanced Configuration Control
n Running Registers
BCR2^
Miscellaneous Configuration
BCR4^
LED0 Status
BCR5^
LED1 Status
These registers are intended to be used by the device
driver software after the Am79C978 controller is running to access status information and to pass control
information.
BCR6^
LED2 Status
BCR7^
LED3 Status
BCR9^
Full-Duplex Control
BCR18^
Bus and Burst Control
BCR19
EEPROM Control and Status
BCR20
Software Style
BCR22^
PCI Latency
BCR23^
PCI Subsystem Vendor ID
BCR24^
PCI Subsystem ID
BCR25^
SRAM Size
BCR26^
SRAM Boundary
BCR27^
SRAM Interface Control
BCR32^
Internal PHY Control and Status
BCR33^
Internal PHY Address
BCR35^
PCI Vendor ID
BCR36
PCI Power Management Capabilities
(PMC) Alias Register
BCR37
PCI DATA Register 0 (DATA0) Alias
Register
BCR38
PCI DATA Register 1 (DATA1) Alias
Register
PCI Configuration Registers
BCR39
PCI DATA Register 2 (DATA2) Alias
Register
Offset 00h
BCR40
PCI DATA Register 3 (DATA3) Alias
Register
BCR41
PCI DATA Register 4 (DATA4) Alias
Register
BCR42
PCI DATA Register 5 (DATA5) Alias
Register
BCR43
BCR44
PCI DATA Register 6 (DATA6) Alias
Register
PCI DATA Register 7 (DATA7) Alias
Register
The following is a list of the registers that would typically need to be periodically read and perhaps written
during the normal running operation of the Am79C978
controller within a system. Each of these registers contains control bits, or status bits, or both.
RAP
Register Address Port
CSR0
Controller Status
CSR3
Interrupt Masks and Deferral Control
CSR4
Test and Features Control
CSR5
Extended Control and Interrupt
CSR7
Extended Control and Interrupt2
CSR112
Missed Frame Count
CSR114
Receive Collision Count
BCR32
Internal PHY Control and Status
BCR33
Internal PHY Address
BCR34
Internal PHY Management Data
n Test Registers
These registers are intended to be used only for testing
and diagnostic purposes. Those registers not included
in any of the above lists can be assumed to be intended
for diagnostic purposes.
PCI Vendor ID Register
The PCI Vendor ID register is a 16-bit register that identifies the manufacturer of the Am79C978 controller.
AMD’s Vendor ID is 1022h. Note that this Vendor ID is
not the same as the Manufacturer ID in CSR88 and
CSR89. The Vendor ID is assigned by the PCI Special
Interest Group.
The PCI Vendor ID register is located at offset 00h in
the PCI Configuration Space. It is read only.
This register is the same as BCR35 and can be written
by the EEPROM.
PCI Device ID Register
BCR45
OnNow Pattern Matching Register 1
Offset 02h
BCR46
OnNow Pattern Matching Register 2
BCR47
OnNow Pattern Matching Register 3
BCR48
LED4 Status
The PCI Device ID register is a 16-bit register that
helps identify the Am79C978 controller within AMD's
product line. The Am79C978 Device ID is 2001h. Note
that this Device ID is not the same as the part number
in CSR88 and CSR89. The Device ID is assigned by
BCR49
PHY Select
102
Am79C978
AMD. The PCI Device ID register is located at offset
02h in the PCI Configuration Space. It is read only.
data parity error occurred during
a master cycle. PERREN also
enables reporting address parity
errors through the SERR pin and
the SERR bit in the PCI Status
register.
PCI Command Register
Offset 04h
The PCI Command register is a 16-bit register used to
control the gross functionality of the Am79C978 controller. It controls the Am79C978 controller’s ability to
generate and respond to PCI bus cycles. To logically
disconnect the Am79C978 device from all PCI bus cycles except configuration cycles, a value of 0 should be
written to this register.
The PCI Command register is located at offset 04h in
the PCI Configuration Space. It is read and written by
the host.
Bit
Name
Description
15-10
RES
Reserved locations. Read as zeros; write operations have no effect.
9
FBTBEN
Fast Back-to-Back Enable. Read
as zero; write operations have no
effect. The Am79C978 controller
will not generate Fast Back-toBack cycles.
8
SERREN
SERR Enable. Controls the assertion of the SERR pin. SERR is
disabled when SERREN is
cleared. SERR will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
SERREN
is
cleared
by
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
7
RES
Reserved location. Read as zeros; write operations have no effect.
6
PERREN
Parity Error Response Enable.
Enables the parity error response
functions. When PERREN is 0
and the Am79C978 controller detects a parity error, it only sets the
Detected Parity Error bit in the
PCI Status register. When PERREN is 1, the Am79C978 controller asserts PERR on the
detection of a data parity error. It
also sets the DATAPERR bit (PCI
Status register, bit 8), when the
PERREN
is
cleared
by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
5
VGASNOOP
VGA Palette Snoop. Read as zero; write operations have no effect.
4
MWIEN
Memory Write and Invalidate Cycle Enable. Read as zero; write
operations have no effect. The
Am79C978 controller only generates Memory Write cycles.
3
SCYCEN
Special Cycle Enable. Read as
zero; write operations have no effect. The Am79C978 controller
ignores all Special Cycle operations.
2
BMEN
Bus Master Enable. Setting
BMEN enables the Am79C978
controller to become a bus master on the PCI bus. The host must
set BMEN before setting the INIT
or STRT bit in CSR0 of the
Am79C978 controller.
BMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
1
Am79C978
MEMEN
Memory Space Access Enable.
The Am79C978 controller will ignore all memory accesses when
MEMEN is cleared. The host
must set MEMEN before the first
memory access to the device.
For memory mapped I/O, the
host must program the PCI Memory Mapped I/O Base Address
register with a valid memory address before setting MEMEN.
For accesses to the Expansion
ROM, the host must program the
PCI Expansion ROM Base Address register at offset 30h with a
valid memory address before setting MEMEN. The Am79C978
103
controller will only respond to accesses to the Expansion ROM
when both ROMEN (PCI Expansion ROM Base Address register,
bit 0) and MEMEN are set to 1.
Since MEMEN also enables the
memory mapped access to the
Am79C978 I/O resources, the
PCI Memory Mapped I/O Base
Address register must be programmed with an address so that
the device does not claim cycles
not intended for it.
• In master mode, during the data
phase of all memory read commands.
In master mode, during the data
phase of the memory write command, the Am79C978 controller
sets the PERR bit if the target reports a data parity error by asserting the PERR signal.
PERR is not effected by the state
of the Parity Error Response enable bit (PCI Command register,
bit 6).
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
0
IOEN
I/O Space Access Enable. The
Am79C978 controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The PCI I/O Base Address register must be programmed with a valid I/O address
before setting IOEN.
PERR is set by the Am79C978
controller and cleared by writing a
1. Writing a 0 has no effect.
PERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
14
SERR
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
SERR is set by the Am79C978
controller and cleared by writing a
1. Writing a 0 has no effect.
SERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
PCI Status Register
Offset 06h
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events. It is
located at offset 06h in the PCI Configuration Space.
Bit
Name
Description
15
PERR
Parity Error. PERR is set when
the Am79C978 controller detects
a parity error.
13
RMABORT Received Master Abort. RMABORT is set when the
Am79C978 controller terminates
a master cycle with a master
abort sequence.
RMABORT is set by the
Am79C978
controller
and
cleared by writing a 1. Writing a 0
has no effect. RMABORT is
cleared by H_RESET and is not
affected by S_RESET or by setting the STOP bit.
The Am79C978 controller samples the AD[31:0], C/BE[3:0], and
the PAR lines for a parity error at
the following times:
• In slave mode, during the address phase of any PCI bus command.
12
• In slave mode, for all I/O, memory, and configuration write commands that select the Am79C978
controller when data is transferred (TRDY and IRDY are asserted).
104
Signaled SERR. SERR is set
when the Am79C978 controller
detects an address parity error
and both SERREN and PERREN
(PCI Command register, bits 8
and 6) are set.
Am79C978
RTABORT
Received Target Abort. RTABORT is set when a target terminates an Am79C978 master
cycle with a target abort sequence.
RTABORT is set by the
Am79C978
controller
and
cleared by writing a 1. Writing a 0
has no effect. RTABORT is
cleared by H_RESET and is not
affected by S_RESET or by setting the STOP bit.
11
STABORT
Send Target Abort. Read as zero; write operations have no effect. The Am79C978 controller
will never terminate a slave access with a target abort sequence.
fast back-to-back transactions
with the first transaction addressing a different target.
6-5
RES
4
NEW_CAP New Capabilities. This bit indicates whether this function implements a list of extended
capabilities such as PCI power
management. When set, this bit
indicates the presence of New
Capabilities. A value of 0 means
that this function does not implement New Capabilities.
STABORT is read only.
10-9
DEVSEL
Device Select Timing. DEVSEL
is set to 01b (medium), which
means that the Am79C978 controller will assert DEVSEL two
clock periods after FRAME is asserted.
Read as one; write operations
have no effect. The Am79C978
controller supports the Linked
Additional Capabilities List.
3-0
DEVSEL is read only.
8
7
DATAPERR
FBTBC
Data Parity Error Detected.
DATAPERR is set when the
Am79C978 controller is the current bus master and it detects a
data parity error and the Parity
Error Response enable bit (PCI
Command register, bit 6) is set.
Reserved locations. Read as
zero; write operations have no effect.
RES
Reserved locations. Read as
zero; write operations have no effect.
PCI Revision ID Register
Offset 08h
The PCI Revision ID register is an 8-bit register that
specifies the Am79C978 controller revision number.
The value of this register is 5Xh with the lower four bits
being silicon-revision dependent.
During the data phase of all
memory read commands, the
Am79C978 controller checks for
parity error by sampling AD[31:0],
C/BE[3:0], and the PAR lines.
During the data phase of all
memory write commands, the
Am79C978 controller checks the
PERR input to detect whether the
target has reported a parity error.
The PCI Revision ID register is located at offset 08h in
the PCI Configuration Space. It is read only.
DATAPERR is set by the
Am79C978
controller
and
cleared by writing a 1. Writing a 0
has no effect. DATAPERR is
cleared by H_RESET and is not
affected by S_RESET or by setting the STOP bit.
The PCI Programming Interface register is located at
offset 09h in the PCI Configuration Space. It is read only.
Fast Back-To-Back Capable.
Read as one; write operations
have no effect. The Am79C978
controller is capable of accepting
PCI Programming Interface Register
Offset 09h
The PCI Programming Interface register is an 8-bit register that identifies the programming interface of
Am79C978 controller. PCI does not define any specific
register-level programming interfaces for network devices. The value of this register is 00h.
PCI Sub-Class Register
Offset 0Ah
The PCI Sub-Class register is an 8-bit register that identifies specifically the function of the Am79C978 controller. The value of this register is 00h which identifies the
Am79C978 device as an Ethernet controller.
The PCI Sub-Class register is located at offset 0Ah in
the PCI Configuration Space. It is read only.
Am79C978
105
PCI Base-Class Register
6-0
LAYOUT
Offset 0Bh
The PCI Base-Class register is an 8-bit register that
broadly classifies the function of the Am79C978 controller. The value of this register is 02h, which classifies
the Am79C978 device as a networking controller.
The PCI Base-Class register is located at offset 0Bh in
the PCI Configuration Space. It is read only.
PCI Latency Timer Register
Offset 0Dh
The PCI Latency Timer register is an 8-bit register that
specifies the minimum guaranteed time the Am79C978
controller will control the bus once it starts its bus mastership period. The time is measured in clock cycles.
Every time the Am79C978 controller asserts FRAME at
the beginning of a bus mastership period, it will copy
the value of the PCI Latency Timer register into a
counter and start counting down. The counter will freeze
at 0. When the system arbiter removes GNT while the
counter is non-zero, the Am79C978 controller will continue with its data transfers. It will only release the bus
when the counter has reached 0.
PCI I/O Base Address Register
Offset 10h
The PCI I/O Base Address register is a 32-bit register
that determines the location of the Am79C978 I/O resources in all of I/O space. It is located at offset 10h in
the PCI Configuration Space.
Bit
Name
Description
31-5
IOBASE
I/O base address most significant
27 bits. These bits are written by
the host to specify the location of
the Am79C978 I/O resources in
all of I/O space. IOBASE must be
written with a valid address before the Am79C978 controller
slave I/O mode is turned on by
setting the IOEN bit (PCI Command register, bit 0).
The PCI Latency Timer is only significant in burst transactions, where FRAME stays asserted until the last data
phase. In a non-burst transaction, FRAME is only asserted during the address phase. The internal latency
counter will be cleared and suspended while FRAME is
deasserted.
When the Am79C978 controller
is enabled for I/O mode (IOEN is
set), it monitors the PCI bus for a
valid I/O command. If the value
on AD[31:5] during the address
phase of the cycles matches the
value of IOBASE, the Am79C978
controller will drive DEVSEL indicating it will respond to the access.
All eight bits of the PCI Latency Timer register are programmable. The host should read the Am79C978 PCI
MIN_GNT and PCI MAX_LAT registers to determine the
latency requirements for the device and then initialize
the Latency Timer register with an appropriate value.
The PCI Latency Timer register is located at offset 0Dh
in the PCI Configuration Space. It is read and written by
the host. The PCI Latency Timer register is cleared by
H_RESET and is not effected by S_RESET or by setting
the STOP bit.
IOBASE is read and written by
the host. IOBASE is cleared by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
PCI Header Type Register
Offset 0Eh
The PCI Header Type register is an 8-bit register that
describes the format of the PCI Configuration Space
locations 10h to 3Ch and that identifies a device to be
single or multi-function. The PCI Header Type register
is located at address 0Eh in the PCI Configuration
Space. It is read only.
Bit
Name
Description
7
FUNCT
Single-function/multi-function device. Read as zero; write operations have no effect. The
Am79C978 controller is a single
function device.
106
PCI configuration space layout.
Read as zeros; write operations
have no effect. The layout of the
PCI configuration space locations 10h to 3Ch is as shown in
Table 24.
4-2
IOSIZE
I/O size requirements. Read as
zeros; write operations have no
effect.
IOSIZE indicates the size of the
I/O space the Am79C978 controller requires. When the host writes
a value of FFFF FFFFh to the I/O
Base Address register, it will read
back a value of 0 in bits 4-2. That
indicates an Am79C978 I/O
space requirement of 32 bytes.
1
Am79C978
RES
Reserved location. Read as zero;
write operations have no effect.
0
IOSPACE
I/O space indicator. Read as one;
write operations have no effect.
Indicating that this base address
register describes an I/O base
address.
memory space requirement of 32
bytes.
3
PCI Memory Mapped I/O Base Address Register
Offset 14h
The PCI Memory Mapped I/O Base Address register is
a 32-bit register that determines the location of the
Am79C978 I/O resources in all of memory space. It is
located at offset 14h in the PCI Configuration Space.
Bit
Name
31-5
MEMBASE Memory mapped I/O base address most significant 27 bits.
These bits are written by the host
to specify the location of the
Am79C978 I/O resources in all of
memory space. MEMBASE must
be written with a valid address
before the Am79C978 controller
slave memory mapped I/O mode
is turned on by setting the MEMEN bit (PCI Command register,
bit 1).
4
MEMSIZE
Description
2-1
0
PREFETCH Prefetchable. Read as zero; write
operations have no effect. Indicates that memory space controlled by this base address
register is not prefetchable. Data
in the memory mapped I/O space
cannot be prefetched. Because
one of the I/O resources in this
address space is a Reset register, the order of the read accesses is important.
TYPE
Memory type indicator. Read as
zeros; write operations have no
effect. Indicates that this base address register is 32 bits wide and
mapping can be done anywhere
in the 32-bit memory space.
MEMSPACE Memory space indicator. Read
as zero; write operations have no
effect. Indicates that this base address register describes a memory base address.
When the Am79C978 controller
is enabled for memory mapped
I/O mode (MEMEN is set), it monitors the PCI bus for a valid memory command. If the value on
AD[31:5] during the address
phase of the cycles matches the
value
of
MEMBASE,
the
Am79C978 controller will drive
DEVSEL indicating it will respond
to the access.
PCI Subsystem Vendor ID Register
MEMBASE is read and written by
the host. MEMBASE is cleared
by H_RESET and is not affected
by S_RESET or by setting the
STOP bit.
The PCI Subsystem Vendor ID register is located at offset 2Ch in the PCI Configuration Space. It is read only.
Memory mapped I/O size requirements. Read as zeros; write
operations have no effect.
MEMSIZE indicates the size of
the
memory
space
the
Am79C978 controller requires.
When the host writes a value of
FFFF FFFFh to the Memory
Mapped I/O Base Address register, it will read back a value of 0 in
bit 4. That indicates a Am79C978
Offset 2Ch
The PCI Subsystem Vendor ID register is a 16-bit register that together with the PCI Subsystem ID uniquely
identifies the add-in card or subsystem the Am79C978
controller is used in. Subsystem Vendor IDs can be obtained from the PCI SIG. A value of 0 (the default) indicates that the Am79C978 controller does not support
subsystem identification. The PCI Subsystem Vendor
ID is an alias of BCR23, bits 15-0. It is programmable
through the EEPROM.
PCI Subsystem ID Register
Offset 2Eh
The PCI Subsystem ID register is a 16-bit register that
together with the PCI Subsystem Vendor ID uniquely
identifies the add-in card or subsystem the Am79C978
controller is used in. The value of the Subsystem ID is
up to the system vendor. A value of 0 (the default) indicates that the Am79C978 controller does not support
subsystem identification. The PCI Subsystem ID is an
alias of BCR24, bits 15-0. It is programmable through
the EEPROM.
The PCI Subsystem ID register is located at offset 2Eh
in the PCI Configuration Space. It is read only.
Am79C978
107
PCI Expansion ROM Base Address Register
19-1, indicating an Expansion
ROM size of 1M.
Offset 30h
The PCI Expansion ROM Base Address register is a
32-bit register that defines the base address, size, and
address alignment of an Expansion ROM. It is located
at offset 30h in the PCI Configuration Space.
Bit
Name
31-20
ROMBASE Expansion ROM base address
most significant 12 bits. These
bits are written by the host to
specify the location of the Expansion ROM in all of memory space.
ROMBASE must be written with a
valid
address
before
the
Am79C978 Expansion ROM access is enabled by setting
ROMEN (PCI Expansion ROM
Base Address register, bit 0) and
MEMEN (PCI Command register,
bit 1).
Description
Since the 12 most significant bits
of the base address are programmable, the host can map the Expansion ROM on any 1M
boundary.
When the Am79C978 controller
is enabled for Expansion ROM
access (ROMEN and MEMEN
are set to 1), it monitors the PCI
bus for a valid memory command. If the value on AD[31:2]
during the address phase of the
cycle falls between ROMBASE
and ROMBASE + 1M - 4, the
Am79C978 controller will drive
DEVSEL indicating it will respond
to the access.
ROMBASE is read and written by
the host. ROMBASE is cleared
by H_RESET and is not affected
by S_RESET or by setting the
STOP bit.
19-1
108
ROMSIZE
Note that ROMSIZE only specifies the maximum size of Expansion ROM the Am79C978
controller supports. A smaller
ROM can also be used. The actual size of the code in the Expansion ROM is always determined
by reading the Expansion ROM
header.
ROM size. Read as zeros; write
operation have no effect. ROMSIZE indicates the maximum size
of the Expansion ROM the
Am79C978 controller can support. The host can determine the
Expansion ROM size by writing
FFFF FFFFh to the Expansion
ROM Base Address register. It
will read back a value of 0 in bit
0
ROMEN
Expansion ROM Enable. Written
by the host to enable access to
the Expansion ROM. The
Am79C978 controller will only respond to accesses to the Expansion ROM when both ROMEN
and MEMEN (PCI Command register, bit 1) are set to 1.
ROMEN is read and written by
the host. ROMEN is cleared by
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
PCI Capabilities Pointer Register
Offset 34h
Bit
Name
Description
7-0
CAP_PTR
The PCI Capabilities Pointer register is an 8-bit register that points
to a linked list of capabilities implemented on this device. This
register has a default value of
40h.
The PCI Capabilities Pointer register is located at offset 34h in the
PCI Configuration Space. It is
read only.
PCI Interrupt Line Register
Offset 3Ch
The PCI Interrupt Line register is an 8-bit register that
is used to communicate the routing of the interrupt.
This register is written by the POST software as it initializes the Am79C978 controller in the system. The
register is read by the network driver to determine the
interrupt channel which the POST software has assigned to the Am79C978 controller. The PCI Interrupt
Line register is not modified by the Am79C978 controller. It has no effect on the operation of the device.
The PCI Interrupt Line register is located at offset 3Ch
in the PCI Configuration Space. It is read and written by
Am79C978
the host. It is cleared by H_RESET and is not affected
by S_RESET or by setting the STOP bit.
the PCI Configuration Space. It is
read only.
PCI Interrupt Pin Register
PCI Next Item Pointer Register
Offset 3Dh
This PCI Interrupt Pin register is an 8-bit register that
indicates the interrupt pin that the Am79C978 controller
is using. The value for the Am79C978 Interrupt Pin register is 01h, which corresponds to INTA.
Offset 41h
Bit
Name
7-0
NXT_ITM_PTR
The PCI Interrupt Pin register is located at offset 3Dh in
the PCI Configuration Space. It is read only.
The Next Item Pointer Register
points to the starting address of
the next capability. The pointer at
this offset is a null pointer, indicating that this is the last capability in the linked list of the
capabilities. This register has a
default value of 0h.
PCI MIN_GNT Register
Offset 3Eh
The PCI MIN_GNT register is an 8-bit register that
specifies the minimum length of a burst period that the
Am79C978 device needs to keep up with the network
activity. The length of the burst period is calculated assuming a clock rate of 33 MHz. The register value
specifies the time in units of 1/4 µs. The PCI MIN_GNT
register is an alias of BCR22, bits 7-0. It is recommended that BCR22 be programmed to a value of
1818h.
The host should use the value in this register to determine the setting of the PCI Latency Timer register.
The PCI MIN_GNT register is located at offset 3Eh in
the PCI Configuration Space. It is read only.
PCI MAX_LAT Register
Offset 3Fh
The PCI MAX_LAT register is an 8-bit register that specifies the maximum arbitration latency the Am79C978
controller can sustain without causing problems to the
network activity. The register value specifies the time in
units of 1/4 µs. The MAX_LAT register is an alias of
BCR22, bits 15-8. It is recommended that BCR22 be
programmed to a value of 1818h.
Description
The PCI Next Pointer Register is
located at offset 41h in the PCI
Configuration Space. It is read
only.
PCI Power Management Capabilities Register
(PMC)
Offset 42h
Note: All bits of this register are loaded from the
EEPROM. The register is aliased to BCR36 for testing
purposes.
Bit
Name
Description
15-11
PME_SPT
PME Support. This 5-bit field indicates the power states in which
the function may assert PME. A
value of 0b for any bit indicates
that the function is not capable of
asserting the PME signal while in
that power state.
The host should use the value in this register to determine the setting of the PCI Latency Timer register.
The PCI MAX_LAT register is located at offset 3Fh in
the PCI Configuration Space. It is read only.
PCI Capability Identifier Register
Offset 40h
Bit(11) XXXX1b - PME can be
asserted from D0.
Bit(12) XXX1Xb - PME can be
asserted from D1.
Bit(13) XX1XXb - PME can be
asserted from D2.
Bit
Name
Description
7-0
CAP_ID
This register, when set to 1, identifies the linked list item as being
the PCI Power Management registers. This register has a default
value of 1h.
Bit(14) X1XXXb - PME can be
asserted from D3hot.
The PCI Capabilities Identifier
register is located at offset 40h in
PME_SPT is read only.
Am79C978
Bit(15) 1XXXXb - PME can be
asserted from D3cold.
109
10
D2_SPT
D2 Support. If this bit is a 1, this
function supports the D2 Power
Management State.
before the generic class device
driver is able to use it.
This bit is read only.
This bit is read only.
9
D1_SPT
D1 Support. If this bit is a 1, this
function supports the D1 Power
Management State.
4
RES
Reserved location.
3
PME_CLK
PME Clock. When this bit is a 1,
it indicates that the function relies
on the presence of the PCI clock
for PME operation. When this bit
is a 0 it indicates that no PCI
clock is required for the function
to generate PME.
This bit is read only.
8-6
AUX_CURRENT
Auxiliary Current Requirements.
This 3-bit field reports the
3.3Vaux current requirements for
the PCI function. If the Data Register has been implemented by
this function, then reads of this
field must return a value of 000b
and the Data Register will take
precedence over this field for
3.3Vaux current requirement reporting.
If PME generation from D3cold is
not supported by the function
(PMC (15) = 0), this field must return a value of 000b when read.
For functions that support PME
from D3cold and do not implement
the Data Register, the following
bit assignments apply:
Bit
876
3.3Vaux
Max. Current Required
111
375 mA
110
320 mA
101
270 mA
100
220 mA
011
160 mA
010
100 mA
001
55 mA
000
0 (self-powered)
Functions that do not support
PME generation in any state
must return 0 for this field.
This bit is read only.
2-0
PCI Power Management Control/Status Register
(PMCSR)
Offset 44h
Bit
15
110
DSI
Name
Description
PME_STATUS PME Status. This bit is set when
the function would normally assert the PME signal independent
of the state of the PME_EN bit.
Writing a 1 to this bit will clear it
and cause the function to stop asserting a PME (if enabled). Writing a 0 has no effect.
If the function supports PME from
D3cold, then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially loaded.
These bits are read only.
5
PMIS_VER Power Management Interface
Specification Version. A value of
001b indicates that this function
complies with revision 1.0 of the
PCI Power Management Interface Specification.
Device Specific Initialization.
When this bit is 1, it indicates that
special initialization of the function is required (beyond the standard PCI configuration header)
Am79C978
This bit is always read/write accessible. Sticky bit. This bit is reset
by
POR.
H_RESET,
S_RESET, or setting the STOP
bit has no effect.
14-13 DATA_SCALE
Data Scale. This 2-bit read-only
field indicates the scaling factor
to be used when interpreting the
value of the Data register. The
value and meaning of this field
will vary depending on the
DATA_SCALE field.
These bits are always read/write
accessible.
PCI PMCSR Bridge Support Extensions Register
Offset 46h
These bits are read only.
12-9
These bits can be written and
read, but their contents have no
effect on the operation of the device.
Bit
DATA_SEL Data Select. This optional 4-bit
field is used to select which data
is reported through the Data register and DATA_SCALE field.
7-0
These bits are always read/write
accessible. Sticky bit. These bits
are reset by POR. H_RESET,
S_RESET, or setting the STOP
bit has no effect.
8
PME_EN
PME Enable. When a 1,
PME_EN enables the function to
assert PME. When a 0, PME assertion is disabled.
Name
Description
PMCSR_BSE The PCI PMCSR Bridge Support
Extensions Register is an 8-bit
register. PMCSR Bridge Support
Extensions are not supported.
This register has a default value
of 00h.
The PCI PMCSR Bridge Support
Extensions register is located at
offset 46h in the PCI Configuration Space. These bits are read
only.
PCI Data Register
Offset 47h
This bit defaults to “0” if the function does not support PME generation from D3cold.
Note: All bits of this register are loaded from the
EEPROM. The register is aliased to lower bytes of the
BCR37-BCR44 for testing purposes.
If the function supports PME from
D3cold, then this bit is sticky and
must be explicitly cleared by the
operating system each time the
operating system is initially loaded.
Bit
Name
7-0
DATA_REG The PCI Data Register is an 8-bit
register. Refer to the “PCI Bus
Power Management Interface
Specification” version 1.0 for a
more detailed description of this
register.
This bit is always read/write accessible. Sticky bit. This bit is reset
by
POR.
H_RESET,
S_RESET, or setting the STOP
bit has no effect.
7-2
1-0
RES
Reserved locations. These bits
are read only.
PWR_STATE Power State. This 2-bit field is
used both to determine the current power state of a function and
to set the function into a new
power state. The definition of the
field values is given below.
00b - D0.
01b - D1.
10b - D2.
11b - D3.
Description
The PCI DATA register is located
at offset 47h in the PCI Configuration Space. It is read only.
RAP Register
The RAP (Register Address Pointer) register is used to
gain access to CSR and BCR registers on board the
Am79C978 controller. The RAP contains the address
of a CSR or BCR.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary
to first load the value 0004h into the RAP by performing
a write access to the RAP offset of 12h (12h when WIO
mode has been selected, 14h when DWIO mode has
been selected). Then a second access is performed,
this time to the RDP offset of 10h (for either WIO or
DWIO mode). The RDP access is a read access, and
Am79C978
111
since RAP has just been loaded with the value of 0004h,
the RDP read will yield the contents of CSR4. A read of
the BDP at this time (offset of 16h when WIO mode has
been selected, 1Ch when DWIO mode has been selected) will yield the contents of BCR4, since the RAP is
used as the pointer into both BDP and RDP space.
This bit is always read accessible
only. Write operations are ignored.
14
RES
Reserved locations. This bit is always
read/write
accessible.
Read returns zero.
13
CERR
Collision Error. Collision Error is
set by the Am79C978 controller
when the device operates in halfduplex mode and the collision inputs to the GPSI port fail to activate within 20 network bit times
after the chip terminates transmission (SQE Test). This feature
is a transceiver test feature.
CERR reporting is disabled when
the GPSI port is active and the
Am79C978 controller operates in
full-duplex mode.
RAP: Register Address Port
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-8
RES
Reserved locations. Read and
written as zeros.
7-0
RAP
Register Address Port. The value
of these 8 bits determines which
CSR or BCR will be accessed
when an I/O access to the RDP
or BDP port, respectively, is performed.
When the MII port is selected,
CERR is only reported when the
external PHY is operating as a
half-duplex 10BASE-T PHY.
A write access to undefined CSR
or BCR locations may cause unexpected reprogramming of the
Am79C978 control registers. A
read access will yield undefined
values.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
These bits are always read/write
accessible. RAP is cleared by
H_RESET or S_RESET and is
unaffected by setting the STOP
bit.
This bit is always read/write accessible. CERR is cleared by the
host by writing a 1. Writing a 0
has no effect. CERR is cleared by
H_RESET, S_RESET, or by setting the STOP bit.
Control and Status Registers (CSRs)
The CSR space is accessible by performing accesses
to the RDP (Register Data Port). The particular CSR
that is read or written during an RDP access will depend
upon the current setting of the RAP. RAP serves as a
pointer into the CSR space.
12
CSR0: Controller Status and Control Register
Certain bits in CSR0 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR0 and write back
the value just read to clear the interrupt condition.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
ERR
Error. Error is set by the OR of
CERR, MISS, and MERR. ERR
remains set as long as any of the
error flags are true.
112
Am79C978
MISS
Missed Frame. Missed Frame is
set by the Am79C978 controller
when it has lost an incoming receive frame resulting from a Receive Descriptor not being
available. This bit is the only immediate indication that receive
data has been lost since there is
no current receive descriptor.
The Missed Frame Counter
(CSR112) also increments each
time a receive frame is missed.
When MISS is set, INTA is asserted if IENA is 1 and the mask
bit MISSM (CSR3, bit 12) is 0.
MISS assertion will set the ERR
bit, regardless of the settings of
IENA and MISSM.
This bit is always read/write accessible. MISS is cleared by the
host by writing a 1. Writing a 0
has no effect. MISS is cleared by
H_RESET, S_RESET, or by setting the STOP bit.
11
MERR
9
TINT
Memory Error. Memory Error is
set by the Am79C978 controller
when it requests the use of the
system interface bus by asserting
REQ and has not received GNT
assertion after a programmable
length of time. The length of time
in microseconds before MERR is
asserted will depend upon the
setting of the Bus Timeout Register (CSR100). The default setting
of CSR100 will give a MERR after
153.6 ms of bus latency.
When MERR is set, INTA is asserted if IENA is 1 and the mask
bit MERRM (CSR3, bit 11) is 0.
MERR assertion will set the ERR
bit, regardless of the settings of
IENA and MERRM.
When TINT is set, INTA is asserted if IENA is 1 and the mask bit
TINTM (CSR3, bit 9) is 0.
TINT will not be set if TINTOKD
(CSR5, bit 15) is set to 1 and the
transmission was successful.
This bit is always read/write accessible. TINT is cleared by the
host by writing a 1. Writing a 0
has no effect. TINT is cleared by
H_RESET, S_RESET, or by setting the STOP bit.
8
IDON
This bit is always read/write accessible. MERR is cleared by the
host by writing a 1. Writing a 0
has no effect. MERR is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
10
RINT
Receive Interrupt is set by the
Am79C978 controller after the
last descriptor of a receive frame
has been update by writing a 0 to
the ownership bit (OWN). RINT
may also be set when the first descriptor of a receive frame has
been updated by writing a 0 to the
ownership bit if the LAPPEN bit of
CSR3 has been set to a 1.
Transmit Interrupt is set by the
Am79C978 controller after the
OWN bit in the last descriptor of a
transmit frame has been cleared
to indicate the frame has been
sent or an error occurred in the
transmission.
Initialization Done is set by the
Am79C978 controller after the
initialization sequence has completed. When IDON is set, the
Am79C978 controller has read
the initialization block from memory.
When IDON is set, INTA is asserted if IENA is 1 and the mask
bit IDONM (CSR3, bit 8) is 0.
This bit is always read/write accessible. IDON is cleared by the
host by writing a 1. Writing a 0
has no effect. IDON is cleared by
H_RESET, S_RESET, or by setting the STOP bit.
7
When RINT is set, INTA is asserted if IENA is 1 and the mask bit
RINTM (CSR3, bit 10) is 0.
This bit is always read/write accessible. RINT is cleared by the
host by writing a 1. Writing a 0
has no effect. RINT is cleared by
H_RESET, S_RESET, or by setting the STOP bit.
Am79C978
INTR
Interrupt Flag indicates that one
or more following interrupt causing conditions has occurred:
EXDINT, IDON, MERR, MISS,
MFCO, RCVCCO, RINT, SINT,
TINT, TXSTRT, UINT, STINT,
MREINT, MCCINT, MIIPDTINT,
MAPINT and the associated
mask or enable bit is programmed to allow the event to
cause an interrupt. If IENA is set
to 1 and INTR is set, INTA will be
active. When INTR is set by SINT
or SLPINT, INTA will be active independent of the state of IENA.
113
This bit is always read accessible. INTR is read only. INTR is
cleared by clearing all of the active individual interrupt bits that
have not been masked out.
6
IENA
will be reset and no Transmit Descriptor Ring access will occur.
TDMD is required to be set if the
TXDPOLL bit in CSR4 is set. Setting TDMD while TXDPOLL = 0
merely hastens the controller’s
response to a Transmit Descriptor Ring Entry.
Interrupt Enable allows INTA to
be active if the Interrupt Flag is
set. If IENA = 0, then INTA will
be disabled regardless of the
state of INTR.
This bit is always read/write accessible. TDMD is set by writing a
1. Writing a 0 has no effect.
TDMD will be cleared by the Buffer Management Unit when it
fetches a Transmit Descriptor.
TDMD is cleared by H_RESET or
S_RESET and setting the STOP
bit.
This bit is always read/write accessible. IENA is set by writing a
1 and cleared by writing a 0. IENA
is cleared by H_RESET or
S_RESET and setting the STOP
bit.
5
RXON
Receive On indicates that the receive function is enabled. RXON
is set if DRX (CSR15, bit 0) is set
to 0 after the START bit is set. If
INIT and START are set together,
RXON will not be set until after
the initialization block has been
read in.
2
STOP
This bit is always read accessible. RXON is read only. RXON is
cleared
by
H_RESET
or
S_RESET and setting the STOP
bit.
4
TXON
Transmit On indicates that the
transmit function is enabled.
TXON is set if DTX (CSR15, bit 1)
is set to 0 after the START bit is
set. If INIT and START are set together, TXON will not be set until
after the initialization block has
been read in.
This bit is always read/write accessible. STOP is set by writing a
1, by H_RESET or S_RESET.
Writing a 0 has no effect. STOP is
cleared by setting either STRT or
INIT.
1
STRT
This bit will reset if the DXSUFLO
bit (CSR3, bit 6) is reset and there
is an underflow condition encountered.
Read accessible always. TXON
is read only. TXON is cleared by
H_RESET or S_RESET and setting the STOP bit.
3
114
TDMD
STOP assertion disables the chip
from all DMA activity. The chip remains inactive until either STRT
or INIT are set. If STOP, STRT,
and INIT are all set together,
STOP will override STRT and
INIT.
STRT assertion enables the
Am79C978 controller to send and
receive frames and perform buffer management operations. Setting STRT clears the STOP bit. If
STRT and INIT are set together,
the Am79C978 controller initialization will be performed first.
This bit is always read/write accessible. STRT is set by writing a
1. Writing a 0 has no effect. STRT
is
cleared
by
H_RESET,
S_RESET, or by setting the
STOP bit.
0
Transmit Demand, when set,
causes the Buffer Management
Unit to access the Transmit Descriptor Ring without waiting for
the poll-time counter to elapse. If
TXON is not enabled, TDMD bit
Am79C978
INIT
INIT assertion enables the
Am79C978 controller to begin the
initialization procedure which
reads in the initialization block
from memory. Setting INIT clears
the STOP bit. If STRT and INIT
are set together, the Am79C978
controller initialization will be per-
formed first. INIT is not cleared
when the initialization sequence
has completed.
dress. Therefore, whenever
SSIZE32 = 0, the IADR[31:24]
bits will be appended to the 24-bit
initialization address, to each 24bit descriptor base address, and
to each beginning 24-bit buffer
address in order to form complete
32-bit addresses. The upper 8
bits that exist in the descriptor address registers and the buffer address registers which are stored
on board the Am79C978 controller will be overwritten with the
IADR[31:24] value, so that CSR
accesses to these registers will
show the 32-bit address that includes the appended field.
This bit is always read/write accessible. INIT is set by writing a 1.
Writing a 0 has no effect. INIT is
cleared
by
H_RESET,
S_RESET, or by setting the
STOP bit.
CSR1: Initialization Block Address 0
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IADR[15:0] Lower 16 bits of the address of
the Initialization Block. Bit locations 1 and 0 must both be 0 to
align the initialization block to a
DWord boundary.
If SSIZE32 = 1, then software will
provide 32-bit pointer values for
all of the shared software structures - i.e., descriptor bases and
buffer addresses, and therefore,
IADR[31:24] will not be written to
the upper 8 bits of any of these
resources, but it will be used as
the upper 8 bits of the initialization address.
This register is aliased with
CSR16.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
This register is aliased with
CSR17.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
CSR2: Initialization Block Address 1
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-8
IADR[31:24] If SSIZE32 is set (BCR20, bit 8),
then the IADR[31:24] bits will be
used strictly as the upper 8 bits of
the initialization block address.
However, if SSIZE32 is reset
(BCR20, bit 8), then the
IADR[31:24] bits will be used to
generate the upper 8 bits of all
bus mastering addresses, as required for a 32-bit address bus.
Note that the 16-bit software
structures specified by the
SSIZE32 = 0 setting will yield
only 24 bits of address for the
Am79C978 bus master accesses, while the 32-bit hardware for
which the Am79C978 controller is
intended will require 32 bits of ad-
7-0
IADR[23:16] Bits 23 through 16 of the address
of the Initialization Block. Whenever this register is written,
CSR17 is updated with CSR2’s
contents.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
CSR3: Interrupt Masks and Deferral Control
Bit
31-16
Am79C978
Name
RES
Description
Reserved locations. Written as
zeros and read as undefined.
115
15-13
RES
Reserved locations. Read and
written as zero.
off when an UFLO error occurs
(CSR0, TXON = 0).
12
MISSM
Missed Frame Mask. If MISSM is
set, the MISS bit will be masked
and unable to set the INTR bit.
When DXSUFLO is set to 1, the
Am79C978 controller gracefully
recovers from an UFLO error. It
scans the transmit descriptor ring
until it finds the start of a new
frame and starts a new transmission.
This bit is always read/write accessible. MISSM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
11
MERRM
This bit is always read/write accessible. DXSUFLO is cleared by
H_RESET or S_RESET and is
not affected by STOP.
Memory Error Mask. If MERRM
is set, the MERR bit will be
masked and unable to set the
INTR bit.
5
This bit is always read/write accessible. MERRM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
10
RINTM
Receive Interrupt Mask. If RINTM
is set, the RINT bit will be masked
and unable to set the INTR bit.
This bit is always read/write accessible. RINTM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
9
TINTM
Transmit Interrupt Mask. If
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
This bit is always read/write accessible. TINTM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
8
IDONM
Initialization Done Mask. If
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
This bit is always read/write accessible. IDONM is cleared by
H_RESET or S_RESET and is
not affected by STOP.
7
RES
Reserved location. Read and
written as zero.
6
DXSUFLO
Disable Transmit Stop on Underflow error.
When DXSUFLO (CSR3, bit 6) is
set to 0, the transmitter is turned
116
Am79C978
LAPPEN
Look Ahead Packet Processing
Enable. When set to a 1, the
LAPPEN bit will cause the
Am79C978 controller to generate
an interrupt following the descriptor write operation to the first buffer of a receive frame. This
interrupt will be generated in addition to the interrupt that is generated following the descriptor
write operation to the last buffer
of a receive packet. The interrupt
will be signaled through the RINT
bit of CSR0.
Setting LAPPEN to a 1 also enables the Am79C978 controller to
read the STP bit of receive descriptors. The Am79C978 controller will use the STP
information to determine where it
should begin writing a receive
packet’s data. Note that while in
this mode, the Am79C978 controller can write intermediate
packet data to buffers whose descriptors do not contain STP bits
set to 1. Following the write to the
last descriptor used by a packet,
the Am79C978 controller will
scan through the next descriptor
entries to locate the next STP bit
that is set to a 1. The Am79C978
controller will begin writing the
next packets data to the buffer
pointed to by that descriptor.
Note that because several descriptors may be allocated by the
host for each packet, and not all
messages may need all of the descriptors that are allocated between descriptors that contain
STP = 1, then some descriptors/
buffers may be skipped in the
ring. While performing the search
for the next STP bit that is set to
1, the Am79C978 controller will
advance through the receive descriptor ring regardless of the
state of ownership bits. If any of
the entries that are examined
during this search indicate
Am79C978 controller ownership
of the descriptor but also indicate
STP = 0, then the Am79C978
controller will reset the OWN bit
to 0 in these entries. If a scanned
entry indicates host ownership
with
STP = 0,
then
the
Am79C978 controller will not alter the entry, but will advance to
the next entry.
When the STP bit is found to be
true, but the descriptor that contains this setting is not owned by
the Am79C978 controller, then
the Am79C978 controller will stop
advancing through the ring entries and begin periodic polling of
this entry. When the STP bit is
found to be true, and the descriptor that contains this setting is
owned by the Am79C978 controller, then the controller will stop
advancing through the ring entries, store the descriptor information that it has just read, and
wait for the next receive to arrive.
See Appendix B for more information on the Look Ahead Packet Processing concept.
4
DXMT2PD
Disable Transmit Two Part Deferral (see Medium Allocation section in the Media Access
Management section for more
details). If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
This bit is always read/write accessible. DXMT2PD is cleared by
H_RESET or S_RESET and is
not affected by STOP.
3
EMBA
Enable Modified Back-off Algorithm (see the Contention Resolution section in Media Access
Management section for more
details). If EMBA is set, a modified back-off algorithm is implemented.
This bit is always read/write accessible. EMBA is cleared by
H_RESET or S_RESET and is
not affected by STOP.
2
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
header portion of a receive packet will always be written to a particular memory area, and the data
portion of a receive packet will always be written to a separate
memory area. The interrupt is
generated when the header bytes
have been written to the header
memory area.
This bit is always read/write accessible. The LAPPEN bit will be
reset to 0 by H_RESET or
S_RESET and will be unaffected
by STOP.
Am79C978
BSWP
Byte Swap. This bit is used to
choose between big and little Endian modes of operation. When
BSWP is set to a 1, big Endian
mode is selected. When BSWP is
set to 0, little Endian mode is selected.
When big Endian mode is selected, the Am79C978 controller will
swap the order of bytes on the AD
bus during a data phase on accesses to the FIFOs only. Specifically, AD[31:24] becomes Byte
0, AD[23:16] becomes Byte 1,
AD[15:8] becomes Byte 2, and
AD[7:0] becomes Byte 3 when
big Endian mode is selected.
When little Endian mode is selected, the order of bytes on the
AD bus during a data phase is:
AD[31:24] is Byte 3, AD[23:16] is
Byte 2, AD[15:8] is Byte 1, and
AD[7:0] is Byte 0.
Byte swap only affects data
transfers that involve the FIFOs.
Initialization block transfers are
not affected by the setting of the
117
BSWP bit. Descriptor transfers
are not affected by the setting of
the BSWP bit. RDP, RAP, BDP
and PCI configuration space accesses are not affected by the
setting of the BSWP bit. Address
PROM transfers and Expansion
ROM accesses are not affected
by the setting of the BSWP bit.
13
RES
Reserved Location. Written as
zero and read as undefined.
12
TXDPOLL
Disable Transmit Polling. If TXDPOLL is set, the Buffer Management Unit will disable transmit
polling. Likewise, if TXDPOLL is
cleared, automatic transmit polling is enabled. If TXDPOLL is set,
TDMD bit in CSR0 must be set in
order to initiate a manual poll of a
transmit descriptor. Transmit descriptor polling will not take place
if TXON is reset. Transmit polling
will take place following Receive
activities.
Note that the byte ordering of the
PCI bus is defined to be little Endian. BSWP should not be set to
1 when the Am79C978 controller
is used in a PCI bus application.
This bit is always read/write accessible. BSWP is cleared by
H_RESET or S_RESET and is
not affected by STOP.
1-0
RES
Reserved locations. The default
values of these bits are zeros.
Writing a 1 to this bit has no effect
on device function. If a 1 is written
to these bits, then a 1 will be read
back. Existing drivers may write a
1 to these bits for compatibility,
but new drivers should write a 0
to these bits and should treat the
read value as undefined.
This bit is always read/write accessible. TXDPOLL is cleared by
H_RESET or S_RESET and is
unaffected by the STOP bit.
11
CSR4: Test and Features Control
Certain bits in CSR4 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR4 and write back
the value just read to clear the interrupt condition.
Bit
Name
This bit is always read/write accessible. APAD_XMT is cleared
by H_RESET or S_RESET and is
unaffected by the STOP bit.
Description
10
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
RES
Reserved location. It is OK for
legacy software to write a 1 to this
location. This bit must be set
back to 0 before setting INIT or
STRT bits.
This bit is always read/write accessible. This bit is cleared by
H_RESET or S_RESET and is
unaffected by the STOP bit.
14
118
APAD_XMT Auto Pad Transmit. When set,
APAD_XMT enables the automatic padding feature. Transmit
frames will be padded to extend
them to 64 bytes including FCS.
The FCS is calculated for the entire frame, including pad, and appended after the pad field.
APAD_XMT will override the programming of the DXMTFCS bit
(CSR15, bit 3) and of the
ADD_FCS bit (TMD1, bit 29).
ASTRP_RCV Auto Strip Receive. When set,
ASTRP_RCV enables the automatic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
This bit is always read/write accessible. ASTRP_RCV is cleared
by H_RESET or S_RESET and is
unaffected by the STOP bit.
9
DMAPLUS Writing and reading from this bit
has no effect. DMAPLUS is always set to 1.
Am79C978
MFCO
Missed Frame Counter Overflow
is set by the Am79C978 controller when the Missed Frame
Counter (CSR112 and CSR113)
has wrapped around.
When MFCO is set, INTA is asserted if IENA is 1 and the mask
bit MFCOM is 0.
This bit is always read/write accessible. MFCO is cleared by the
host by writing a 1. Writing a 0
has no effect. MFCO is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
8
MFCOM
UINTCMD
4
Missed Frame Counter Overflow
Mask. If MFCOM is set, the
MFCO bit will be masked and unable to set the INTR bit.
This bit is always read/write accessible. MFCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
7
This bit is always read/write accessible. RCVCCO is cleared by
the host by writing a 1. Writing a
0 has no effect. RCVCCO is
cleared
by
H_RESET,
S_RESET, or by setting the
STOP bit.
RCVCCOM Receive Collision Counter Overflow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
This bit is always read/write accessible. RCVCCOM is set to 1
by H_RESET or S_RESET and is
not affected by the STOP bit.
3
TXSTRT
User
Interrupt
Command.
UINTCMD can be used by the
host to generate an interrupt unrelated to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1. Write
a 1 to UINT to clear UINTCMD
and stop interrupts.
When TXSTRT is set, INTA is asserted if IENA is 1 and the mask
bit TXSTRTM is 0.
This bit is always read/write accessible. TXSTRT is cleared by
the host by writing a 1. Writing a
0 has no effect. TXSTRT is
cleared
by
H_RESET,
S_RESET, or by setting the
STOP bit.
This bit is always read/write accessible. UINTCMD is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
2
6
5
UINT
RCVCCO
Transmit Start status is set by the
Am79C978 controller whenever it
begins transmission of a frame.
TXSTRTM
User Interrupt. UINT is set by the
Am79C978 controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
Transmit Start Mask. If TXSTRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
This bit is always read/write accessible. TXSTRTM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
This bit is always read/write accessible. UINT is cleared by the
host by writing a 1. Writing a 0
has no effect. UINT is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
1-0
Receive Collision Counter Overflow is set by the Am79C978 controller when the Receive Collision
Counter (CSR114 and CSR115)
has wrapped around.
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR5 and write back
the value just read to clear the interrupt condition.
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
RES
Reserved locations. Written as
zeros and read as undefined.
CSR5: Extended Control and Interrupt 1
Am79C978
119
15
TOKINTD
Transmit OK Interrupt Disable. If
TOKINTD is set to 1, the TINT bit
in CSR0 will not be set when a
transmission was successful.
Only a transmit error will set the
TINT bit.
TOKINTD has no effect when
LTINTEN (CSR5, bit 14) is set to
1. A transmit descriptor with
LTINT set to 1 will always cause
TINT to be set to 1, independent
of the success of the transmission.
has no effect. The state of SINT is
not affected by clearing any of the
PCI Status register bits that get
set when a data parity error
(DATAPERR, bit 8), master abort
(RMABORT, bit 13), or target
abort (RTABORT, bit 12) occurs.
SINT is cleared by H_RESET or
S_RESET and is not affected by
setting the STOP bit.
10
SINTE
This bit is always read/write accessible. TOKINTD is cleared by
H_RESET or S_RESET and is
unaffected by STOP.
14
LTINTEN
Last Transmit Interrupt Enable.
When set to 1, the LTINTEN bit
will cause the Am79C978 controller to read bit 28 of TMD1 as
LTINT. The setting LTINT will determine if TINT will be set at the
end of the transmission.
This bit is always read/write accessible. SINTE is set to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
9-8
RES
Reserved locations. Written as
zeros and read as undefined.
7
EXDINT
Excessive Deferral Interrupt is
set by the Am79C978 controller
when the transmitter has experienced Excessive Deferral on a
transmit frame, where Excessive
Deferral is defined in the ISO
8802-3 (IEEE/ANSI 802.3) standard.
This bit is always read/write accessible. LTINTEN is cleared by
H_RESET or S_RESET and is
unaffected by STOP.
13-12
RES
Reserved locations. Written as
zeros and read as undefined.
11
SINT
System Interrupt is set by the
Am79C978 controller when it detects a system error during a bus
master transfer on the PCI bus.
System errors are data parity error, master abort, or a target
abort. The setting of SINT due to
data parity error is not dependent
on the setting of PERREN (PCI
Command register, bit 6).
When EXDINT is set, INTA is asserted if the enable bit EXDINTE
is 1.
This bit is always read/write accessible. EXDINT is cleared by
the host by writing a 1. Writing a
0 has no effect. EXDINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
6
EXDINTE
When SINT is set, INTA is asserted if the enable bit SINTE is 1.
Note that the assertion of an interrupt due to SINT is not dependent on the state of the INEA bit,
since INEA is cleared by the
STOP reset generated by the
system error.
This bit is always read/write accessible. SINT is cleared by the
host by writing a 1. Writing a 0
120
System Interrupt Enable. If SINTE is set, the SINT bit will be able
to set the INTR bit.
Excessive Deferral Interrupt Enable. If EXDINTE is set, the
EXDINT bit will be able to set the
INTR bit.
This bit is always read/write accessible. EXDINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
5
Am79C978
MPPLBA
Magic Packet Physical Logical
Broadcast Accept. If MPPLBA is
at its default value of 0, the
Am79C978 controller will only detect a Magic Packet frame if the
destination address of the packet
matches the content of the physical address register (PADR). If
MPPLBA is set to 1, the destination address of the Magic Packet
frame can be unicast, multicast,
or broadcast. Note that the setting of MPPLBA only affects the
address detection of the Magic
Packet frame. The Magic Packet
frame’s data sequence must be
made up of 16 consecutive physical addresses (PADR[47:0]) regardless of what kind of
destination address it has. This
bit is OR’ed with the EMPPLBA
bit (CSR116, bit 6).
This bit is always read/write accessible. MPPLBA is set to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
4
MPINT
both MPEN and MPMODE are
set to 1.
This bit is always read/write accessible. MPEN is cleared to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
1
MPINTE
0
Magic Packet Interrupt. Magic
Packet Interrupt is set by the
Am79C978 controller when the
device is in Magic Packet mode
and the Am79C978 controller receives a Magic Packet frame.
When MPINT is set to 1, INTA is
asserted if IENA (CSR0, bit 6)
and the enable bit MPINTE are
set to 1.
Magic Packet Interrupt Enable. If
MPINTE is set to 1, the MPINT bit
will be able to set the INTR bit.
This bit is always read/write accessible. MPINT is cleared to 0
by H_RESET or S_RESET and is
not affected by setting the STOP
bit.
2
MPEN
The Am79C978 controller will enter the Magic Packet mode when
MPMODE is set to 1 and either
PG is asserted or MPEN is set to
1.
This bit is always read/write accessible. MPMODE is cleared to
0 by H_RESET or S_RESET and
is not affected by setting the
STOP bit
This bit is always read/write accessible. MPINT is cleared by the
host by writing a 1. Writing a 0
has no affect. MPINT is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
3
MPMODE
Magic Packet Enable. MPEN allows activation of the Magic
Packet mode by the host. The
Am79C978 controller will enter
the Magic Packet mode when
Am79C978
SPND
Suspend. Setting SPND to 1 will
cause the Am79C978 controller
to start requesting entrance into
suspend mode. The host must
poll SPND until it reads back 1 to
determine that the Am79C978
controller has entered the suspend mode. Setting SPND to 0
will get the Am79C978 controller
out of suspend mode. SPND can
only be set to 1 if STOP (CSR0,
bit 2) is set to 0. H_RESET,
S_RESET, or setting the STOP
bit will get the Am79C978 controller out of suspend mode.
Requesting entrance into the
suspend mode by the host depends on the setting of the
FASTSPNDE bit (CSR7, bit 15).
Refer to the bit description of the
FASTSPNDE bit and the Suspend section in Detailed Functions, Buffer Management Unit
for details.
In suspend mode, all of the CSR
and BCR registers are accessible. As long as the Am79C978
controller is not reset while in
suspend mode (by H_RESET,
S_RESET, or by setting the
STOP bit), no re-initialization of
the device is required after the
device comes out of suspend
mode. The Am79C978 controller
will continue at the transmit and
receive descriptor ring locations
121
from where it had left, when it entered the suspend mode.
This bit is always read/write accessible. SPND is cleared by
H_RESET, S_RESET, or by setting the STOP bit.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
CSR6: RX/TX Descriptor Table Length
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-12
TLEN
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during the Am79C978 controller
initialization. This field is written
during the Am79C978 initialization routine.
Read accessible only when either
the STOP or the SPND bit is set.
Write operations have no effect
and should not be performed.
TLEN is only defined after initialization. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
11-8
RLEN
Contains a copy of the receive
encoded ring length (RLEN) read
from the initialization block during
Am79C978 controller initialization. This field is written during
the Am79C978 initialization routine.
Read accessible only when either
the STOP or the SPND bit is set.
Write operations have no effect
and should not be performed.
RLEN is only defined after initialization. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
7-0
RES
Reserved locations. Read as 0s.
Write operations are ignored.
CSR7: Extended Control and Interrupt 2
Certain bits in CSR7 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR7 and write back
the value just read to clear the interrupt condition.
122
Am79C978
FASTSPNDE Fast Suspend Enable. When
FASTSPNDE is set to 1, the
Am79C978 controller performs a
fast suspend whenever the
SPND bit is set.
When a fast suspend is requested, the Am79C978 controller performs a quick entry into the
suspend mode. At the time the
SPND bit is set, the Am79C978
controller will complete the DMA
process of any transmit and/or receive packet that had already begun DMA activity. In addition, any
transmit packet that had started
transmission will be fully transmitted, and any receive packet that
had begun reception will be fully
received. However, no additional
packets will be transmitted or received and no additional transmit
or receive DMA activity will begin.
Hence, the Am79C978 controller
may enter the suspend mode
with transmit and/or receive
packets still in the FIFOs or the
SRAM.
When FASTSPNDE is 0 and the
SPND bit is set, the Am79C978
controller may take longer before
entering the suspend mode. At
the time the SPND bit is set, the
Am79C978 controller will complete the DMA process of a transmit packet if it had already begun,
and the Am79C978 controller will
completely receive a receive
packet if it had already begun.
Additionally, all transmit packets
stored in the transmit FIFOs and
the transmit buffer area in the
SRAM (if one is enabled) will be
transmitted and all receive packets stored in the receive FIFOs,
and the receive buffer area in the
SRAM (if one is enabled) will be
transferred into system memory.
Since the FIFO and SRAM contents are flushed, it may take
much
longer
before
the
Am79C978 controller enters the
suspend mode. The amount of
time that it takes depends on
many factors including the size of
the SRAM, bus latency, and network traffic level.
When a write to CSR5 is performed with bit 0 (SPND) set to 1,
the value that is simultaneously
written to FASTSPNDE is used to
determine which approach is
used to enter suspend mode.
This bit is always read/write accessible. RXDPOLL is cleared by
H_RESET. RXDPOLL is unaffected by S_RESET or by setting
the STOP bit.
11
STINT
This bit is always read/write accessible. FASTSPNDE is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
14
RES
Reserved location.
13
RDMD
Receive Demand, when set,
causes the Buffer Management
Unit to access the Receive Descriptor Ring without waiting for
the receive poll-time counter to
elapse. If RXON is not enabled,
RDMD has no meaning and no
receive Descriptor Ring access
will occur.
When STINT is set to 1, INTA is
asserted if the enable bit STINTE
is set to 1.
This bit is always read/write accessible. STINT is cleared by the
host by writing a 1. Writing a 0
has no effect. STINT is cleared
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
10
STINTE
RDMD is required to be set if the
RXDPOLL bit in CSR7 is set. Setting RDMD while RXDPOLL = 0
merely hastens the Am79C978
controller’s response to a receive
Descriptor Ring Entry.
9
RXDPOLL
Software Timer Interrupt Enable.
If STINTE is set, the STINT bit
will be able to set the INTR bit.
This bit is always read/write accessible. STINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP bit
This bit is always read/write accessible. RDMD is set by writing
a 1. Writing a 0 has no effect.
RDMD will be cleared by the Buffer Management Unit when it
fetches a receive Descriptor.
RDMD is cleared by H_RESET.
RDMD
is
unaffected
by
S_RESET or by setting the STOP
bit.
12
Software Timer Interrupt. The
Software Timer interrupt is set by
the Am79C978 controller when
the Software Timer counts down
to 0. The Software Timer will immediately load the STVAL (BCR
31, bits 5-0) into the Software
Timer and begin counting down.
Receive Disable Polling. If RXDPOLL is set, the Buffer Management Unit will disable receive
polling. Likewise, if RXDPOLL is
cleared, automatic receive polling is enabled. If RXDPOLL is
set, RDMD bit in CSR7 must be
set in order to initiate a manual
poll of a receive descriptor. Receive Descriptor Polling will not
take place if RXON is reset.
Am79C978
MREINT
PHY Management Read Error Interrupt. The PHY Read Error interrupt is set by the Am79C978
controller to indicate that the currently read register from the PHY
is invalid, the contents of BCR34
are incorrect, and the operation
should be performed again. The
indication of an incorrect read
comes from the internal PHY.
When MREINT is set to 1, INTA is
asserted if the enable bit MREINTE is set to 1.
This bit is always read/write accessible. MREINT is cleared by
the host by writing a 1. Writing a
0 has no effect. MREINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
123
8
MREINTE
PHY Management Read Error Interrupt Enable. If MREINTE is
set, the MREINT bit will be able to
set the INTR bit.
When MCCINT is set to 1, INTA
is asserted if the enable bit MCCINTE is set to 1.
This bit is always read/write accessible. MCCINT is cleared by
the host by writing a 1. Writing a
0 has no effect. MCCINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
This bit is always read/write accessible. MREINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP bit
7
MAPINT
PHY Management Auto-Poll Interrupt. The PHY Auto-Poll interrupt is set by the Am79C978
controller to indicate that the currently read status does not match
the stored previous status indicating a change in state for the internal PHY. A change in the AutoPoll Access Method (BCR32, Bit
11) will reset the shadow register
and will not cause an interrupt on
the first access from the Auto-Poll
section. Subsequent accesses
will generate an interrupt if the
shadow register and the read
register produce differences.
4
MCCINTE
When MAPINT is set to 1, INTA is
asserted if the enable bit MAPINTE is set to 1.
This bit is always read/write accessible. MAPINT is cleared by
the host by writing a 1. Writing a
0 has no effect. MAPINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
6
MAPINTE
This bit is always read/write accessible. MCCINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
3
PHY Auto-Poll Interrupt Enable.
If MAPINTE is set, the MAPINT
bit will be able to set the INTR bit.
This bit is always read/write accessible. MAPINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
5
124
MCCINT
PHY Management Command
Complete Interrupt Enable. If
MCCINTE is set to 1, the MCCINT bit will be able to set the
INTR bit when the host reads or
writes to the internal PHY Data
Port (BCR34) only. Internal PHY
Management Commands will not
generate an interrupt. For instance Auto-Poll state machine
generated management frames
will not generate an interrupt
upon completion unless there is a
compare error which gets reported through the MAPINT (CSR7,
bit 6) interrupt or the MCCIINTE
is set to 1.
PHY Management Command
Complete Interrupt. The PHY
Management Command Complete Interrupt is set by the
Am79C978 controller when a
read or write operation to the internal PHY Data Port (BCR34) is
complete.
Am79C978
MCCIINT
PHY Management Command
Complete Internal Interrupt. The
PHY Management Command
Complete Interrupt is set by the
Am79C978 controller when a
read or write operation on the internal PHY management port is
complete from an internal operation. Examples of internal operations are Auto-Poll or PHY
Management Port generated
management frames. These are
normally hidden to the host.
When MCCIINT is set to 1, INTA
is asserted if the enable bit MCCINTE is set to 1.
This bit is always read/write accessible. MCCIINT is cleared by
the host by writing a 1. Writing a
0 has no effect. MCCIINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
2
MCCIINTE PHY Management Command
Complete Internal Interrupt Enable. If MCCIINTE is set to 1, the
MCCIINT bit will be able to set
the INTR bit when the internal
state machines generate management frames. For instance,
when MCCIINTE is set to 1 and
the Auto-Poll state machine generates a management frame, the
MCCIINT will set the INTR bit
upon completion of the management frame regardless of the
comparison outcome.
This bit is always read/write accessible. MCCIINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
1
MIIPDTINT PHY Detect Transition Interrupt.
The PHY Detect Transition Interrupt is set by the Am79C978 controller whenever the MIIPD bit
(BCR32, bit 14) transitions from 0
to 1 or vice versa.
This bit is always read/write accessible. MIIPDTINT is cleared
by the host by writing a 1. Writing
a 0 has no effect. MIIPDTINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
0
MIIPDTINTE PHY Detect Transition Interrupt
Enable. If MIIPDTINTE is set to 1,
the MIIPDTINT bit will be able to
set the INTR bit.
This bit is always read/write accessible. MIIPDTINTE is set to 0
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
is undefined until loaded from the
initialization block after the INIT
bit in CSR0 has been set or a direct register write has been performed on this register.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR9: Logical Address Filter 1
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0 LADRF[31:16] Logical Address Filter, LADRF[31:16]. The content of this register is undefined until loaded from
the initialization block after the
INIT bit in CSR0 has been set or
a direct register write has been
performed on this register.
These bits are These bits are
read/write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR10: Logical Address Filter 2
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0 LADRF[47:32] Logical
Address
Filter,
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
CSR8: Logical Address Filter 0
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
These bit are read/write accessible only when either the STOP or
the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
LADRF[15:0] Logical Address Filter, LADRF[15:0]. The content of this register
Am79C978
125
CSR11: Logical Address Filter 3
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
15-0 LADRF[63:48] Logical
Address
Filter,
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
PADR[31:16] Physical
Address
Register,
PADR[31:16]. The contents of
this register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the contents of this register are undefined.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR12: Physical Address Register 0
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16
15-0
Name
RES
Description
Reserved locations. Written as
zeros and read as undefined.
PADR[15:0] Physical
Address
Register,
PADR[15:0]. The contents of this
register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the contents of this register are undefined.
CSR14: Physical Address Register 2
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR13: Physical Address Register 1
Note: Bits 15-0 in this register are programmable
through the EEPROM.
126
Am79C978
PADR[47:32] Physical
Address
Register,
PADR[47:32]. The contents of
this register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the contents of this register are undefined.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR15: Mode
This register’s fields are loaded during the Am79C978
controller initialization routine with the corresponding
Initialization Block values, or when a direct register write
has been performed on this register.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
PROM
Promiscuous
Mode.
When
PROM = 1, all incoming receive
frames are accepted.
SPND bit is set. Cleared by
H_RESET or S_RESET and is
unaffected by STOP.
6
INTL
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
5
DRTY
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
14
DRCVBC
Disable Receive Broadcast.
When
set,
disables
the
Am79C978 controller from receiving broadcast messages.
Used for protocols that do not
support broadcast addressing,
except as a function of multicast.
DRCVBC is cleared by activation
of H_RESET or S_RESET
(broadcast messages will be received) and is unaffected by
STOP.
DRCVPA
4
Disable Receive Physical Address. When set, the physical address detection (Station or node
ID) of the Am79C978 controller
will be disabled. Frames addressed to the nodes individual
physical address will not be recognized.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
12-9
RES
Disable Retry. When DRTY is set
to 1, the Am79C978 controller will
attempt only one transmission. In
this mode, the device will not protect the first 64 bytes of frame
data in the Transmit FIFO from
being overwritten, because automatic retransmission will not be
necessary. When DRTY is set to
0, the Am79C978 controller will
attempt 16 transmissions before
signaling a retry error.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
13
Internal Loopback. See the description of LOOP (CSR15, bit 2).
FCOLL
Force Collision. This bit allows
the collision logic to be tested.
The Am79C978 controller must
be in internal loopback for FCOLL
to be valid. If FCOLL = 1, a collision will be forced during loopback transmission attempts,
which will result in a Retry Error.
If FCOLL = 0, the Force Collision
logic will be disabled. FCOLL is
defined after the initialization
block is read.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
3
Reserved locations. Written as
zeros and read as undefined.
8-7 PORTSEL[1:0] Port Select bits allow for software
controlled selection of the network medium. The only legal values for this field is 11.
This bit is read/write accessible
only when either the STOP or the
Am79C978
DXMTFCS Disable Transmit CRC (FCS).
When DXMTFCS is set to 0, the
transmitter will generate and append an FCS to the transmitted
frame. When DXMTFCS is set to
1, no FCS is generated or sent
with the transmitted frame.
DXMTFCS is overridden when
ADD_FCS and ENP bits are set
in TMD1.
When the APAD_XMT bit (CSR4,
bit11) is set to 1, the setting of
DXMTFCS has no effect.
127
If DXMTFCS is set and
ADD_FCS is clear for a particular
frame, no FCS will be generated.
If ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be appended on that frame by the
transmit circuitry. See also the
ADD_FCS bit in TMD1.
This bit was called DTCR in the
LANCE (Am7990) device.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
2
LOOP
Loopback Enable allows the
Am79C978 controller to operate
in full-duplex mode for test purposes. The setting of the fullduplex control bits in BCR9 have
no effect when the device operates in loopback mode. When
LOOP = 1, loopback is enabled.
In combination with INTL and
MIIILP, various loopback modes
are defined as follows in Table
30.
ing the Receive Descriptor Ring
and, therefore, all receive frame
data are ignored. DRX = 0 will set
RXON bit (CSR0 bit 5) if STRT
(CSR0 bit 1) is asserted.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
CSR16: Initialization Block Address Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IADRL
This register is an alias of CSR1.
These bits are read/write accessible only when either the STOP
or the SPND bit is set.
CSR17: Initialization Block Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IADRH
This register is an alias of CSR2.
Table 30. Loopback Configuration
LOOP
INTL
MIIILP
0
0
0
Normal Operation
0
0
1
Internal Loop
1
0
0
External Loop
These bits are read/write accessible only when either the STOP
or the SPND bit is set.
Function
CSR18: Current Receive Buffer Address Lower
Refer to Loopback Operation
section for more details.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set. LOOP is cleared
by H_RESET or S_RESET and
is unaffected by STOP.
1
DTX
Disable Transmit results in
Am79C978 controller not accessing the Transmit Descriptor Ring
and, therefore, no transmissions
are attempted. DTX = 0, will set
TXON bit (CSR0 bit 4) if STRT
(CSR0 bit 1) is asserted.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
0
128
DRX
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRBAL
Contains the lower 16 bits of the
current receive buffer address at
which the Am79C978 controller
will store incoming frame data.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR19: Current Receive Buffer Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
Disable Receiver results in the
Am79C978 controller not access-
Am79C978
15-0
CRBAU
Contains the upper 16 bits of the
current receive buffer address at
which the Am79C978 controller
will store incoming frame data.
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR23: Next Receive Buffer Address Upper
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR20: Current Transmit Buffer Address Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CXBAL
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRBAU
Contains the upper 16 bits of the
next receive buffer address to
which the Am79C978 controller
will store incoming frame data.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Contains the lower 16 bits of the
current transmit buffer address
from which the Am79C978 controller is transmitting.
CSR24: Base Address of Receive Ring Lower
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR21: Current Transmit Buffer Address Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CXBAU
Contains the upper 16 bits of the
current transmit buffer address
from which the Am79C978 controller is transmitting.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADRL
Contains the lower 16 bits of the
base address of the Receive
Ring.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR25: Base Address of Receive Ring Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADRU
Contains the upper 16 bits of the
base address of the Receive
Ring.
CSR22: Next Receive Buffer Address Lower
Bit
Name
Description
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRBAL
Contains the lower 16 bits of the
next receive buffer address to
which the Am79C978 controller
will store incoming frame data.
CSR26: Next Receive Descriptor Address Lower
Bit
Name
Description
These bits are read/write accessible only when either the STOP
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
Am79C978
129
15-0
NRDAL
Contains the lower 16 bits of the
next receive descriptor address
pointer.
CSR30: Base Address of Transmit Ring Lower
Bit
Name
Description
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADXL
Contains the lower 16 bits of the
base address of the Transmit
Ring.
CSR27: Next Receive Descriptor Address Upper
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRDAU
Contains the upper 16 bits of the
next receive descriptor address
pointer.
CSR31: Base Address of Transmit Ring Upper
Bit
Name
Description
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADXU
Contains the upper 16 bits of the
base address of the Transmit
Ring.
CSR28: Current Receive Descriptor Address Lower
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRDAL
Contains the lower 16 bits of the
current receive descriptor address pointer.
CSR32: Next Transmit Descriptor Address Lower
Bit
Name
Description
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NXDAL
Contains the lower 16 bits of the
next transmit descriptor address
pointer.
CSR29: Current Receive Descriptor Address Upper
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRDAU
Contains the upper 16 bits of the
current receive descriptor address pointer.
CSR33: Next Transmit Descriptor Address Upper
Bit
Name
Description
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NXDAU
Contains the upper 16 bits of the
next transmit descriptor address
pointer.
130
Am79C978
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR34: Current Transmit Descriptor Address
Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CXDAL
CSR35: Current Transmit Descriptor Address
Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
CXDAU
CSR36: Next Next Receive Descriptor Address
Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
NNRDAL
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NNRDAU
Contains the upper 16 bits of the
next next receive descriptor address pointer.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR38: Next Next Transmit Descriptor Address
Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NNXDAL
Contains the lower 16 bits of the
next next transmit descriptor address pointer.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Contains the upper 16 bits of the
current transmit descriptor address pointer.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
15-0
Bit
Contains the lower 16 bits of the
current transmit descriptor address pointer.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
15-0
CSR37: Next Next Receive Descriptor Address
Upper
CSR39: Next Next Transmit Descriptor Address
Upper
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NNXDAU
Contains the upper 16 bits of the
next next transmit descriptor address pointer.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Contains the lower 16 bits of the
next next receive descriptor address pointer.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR40: Current Receive Byte Count
Bit
31-16
Am79C978
Name
RES
Description
Reserved locations. Written as
zeros and read as undefined.
131
15-12
11-0
RES
CRBC
Reserved locations. Read and
written as zeros.
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD1 of the current receive descriptor.
CSR43: Current Transmit Status
Bit
Name
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Current Transmit Status. This
field is a copy of bits 31-16 of
TMD1 of the current transmit descriptor.
CXST
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR41: Current Receive Status
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRST
Current Receive Status. This
field is a copy of bits 31-16 of
RMD1 of the current receive descriptor.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR44: Next Receive Byte Count
Bit
Name
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-12
RES
Reserved locations. Read and
written as zeros.
11-0
CXBC
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the current transmit descriptor.
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 RES
Reserved locations. Read and
written as zeros.
11-0
Next Receive Byte Count. This
field is a copy of the BCNT field of
RMD1 of the next receive descriptor.
NRBC
CSR42: Current Transmit Byte Count
Bit
Description
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR45: Next Receive Status
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Next Receive Status. This field is
a copy of bits 31-16 of RMD1 of
the next receive descriptor.
NRST
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR46: Transmit Poll Time Counter
Bit
Name
31-16 RES
132
Am79C978
Description
Reserved locations. Written as
zeros and read as undefined.
15-0
TXPOLL
Transmit Poll Time Counter. This
counter is incremented by the
Am79C978 controller microcode
and is used to trigger the transmit
descriptor ring polling operation
of the Am79C978 controller.
overwritten with the desired user
value.
If the user does not use the standard initialization procedure
(standard implies use of an initialization block in memory and setting the INIT bit of CSR0), but
instead chooses to write directly
to each of the registers that are
involved in the INIT operation,
then it is imperative that the user
also writes all zeros to CSR47 as
part of the alternative initialization
sequence.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR47: Transmit Polling Interval
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 TXPOLLINT
Transmit Polling Interval. This
register contains the time that the
Am79C978 controller will wait between successive polling operations. The TXPOLLINT value is
expressed as the two’s complement of the desired interval,
where each bit of TXPOLLINT
represents 1 clock period of time.
TXPOLLINT[3:0] are ignored.
(TXPOLLINT[16] is implied to be
a one, so TXPOLLINT[15] is significant and does not represent
the sign of the two’s complement
TXPOLLINT value.)
The default value of this register
is 0000h. This corresponds to a
polling interval of 65,536 clock
periods
(1.966
ms
when
CLK = 33 MHz). The TXPOLLINT value of 0000h is created
during the microcode initialization
routine and, therefore, might not
be seen when reading CSR47 after H_RESET or S_RESET.
If the user desires to program a
value for POLLINT other than the
default, then the correct procedure is to first set INIT only in
CSR0. Then, when the initialization sequence is complete, the
user must set STOP (CSR0, bit
2). Then the user may write to
CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000h in CSR47 will be
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR48: Receive Poll Time Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Receive Poll Time Counter. This
counter is incremented by the
Am79C978 controller microcode
and is used to trigger the receive
descriptor ring polling operation
of the Am79C978 controller.
RXPOLL
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR49: Receive Polling Interval
Bit
Name
31-16 RES
15-0
Am79C978
Description
Reserved locations. Written as
zeros and read as undefined.
RXPOLLINT Receive Polling Interval. This register contains the time that the
Am79C978 controller will wait between successive polling operations. The RXPOLLINT value is
expressed as the two’s complement of the desired interval,
where each bit of RXPOLLINT
represents approximately one
clock time period. RXPOLLINT[3:0] are ignored. (RXPOL-
133
LINT[16] is implied to be a 1, so
RXPOLLINT[15] is significant
and does not represent the sign
of the two’s complement RXPOLLINT value.)
10
APERREN
The default value of this register
is 0000h. This corresponds to a
polling interval of 65,536 clock
periods
(1.966
ms
when
CLK = 33 MHz). The RXPOLLINT value of 0000h is created
during the microcode initialization
routine and, therefore, might not
be seen when reading CSR49 after H_RESET or S_RESET.
If the user desires to program a
value for RXPOLLINT other than
the default, then the correct procedure is to first set INIT only in
CSR0. Then, when the initialization sequence is complete, the
user must set STOP (CSR0, bit
2). Then the user may write to
CSR49 and set STRT in CSR0.
In this way, the default value of
0000h in CSR47 will be overwritten with the desired user value.
If the user does not use the standard initialization procedure
(standard implies use of an initialization block in memory and setting the INIT bit of CSR0), but
instead chooses to write directly
to each of the registers that are
involved in the INIT operation, it
is imperative that the user also
writes all zeros to CSR49 as part
of the alternative initialization sequence.
APERREN does not affect the reporting of address parity errors or
data parity errors that occur when
the Am79C978 controller is the
target of the transfer.
Read anytime, write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
9
RES
Reserved location. Written as
zero and read as undefined.
8
SSIZE32
Software Size 32 bits. When set,
this bit indicates that the
Am79C978 controller utilizes 32bit software structures for the initialization block and the transmit
and receive descriptor entries.
When cleared, this bit indicates
that the Am79C978 controller utilizes 16-bit software structures for
the initialization block and the
transmit and receive descriptor
entries. In this mode, the
Am79C978 controller is backwards compatible with the
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR58: Software Style
This register is an alias of the location BCR20. Accesses
to and from this register are equivalent to accesses to
BCR20.
Bit
Name
31-11 RES
134
Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity error handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2 or 3 to program the Am79C978
controller to use 32-bit software
structures.
Description
Reserved locations. Written as
zeros and read as undefined.
Am79C978
The value of SSIZE32 is determined by the Am79C978 controller according to the setting of the
Software Style (SWSTYLE, bits
7-0 of this register).
Read
accessible
always.
SSIZE32 is read only; write operations will be ignored. SSIZE32
will be cleared after H_RESET
(since SWSTYLE defaults to 0)
and is not affected by S_RESET
or STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32-bit address
bus during master accesses initiated by the Am79C978 controller.
This action is required because
the 16-bit software structures
specified by the SSIZE32 = 0 setting will yield only 24 bits of address
for
the
Am79C978
controller bus master accesses.
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit
(BCR18, bit 7).
7-0
SWSTYLE
If SSIZE32 is set, then the software structures that are common
to the Am79C978 controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the Am79C978
controller for performing master
accesses.
Software Style register. The value in this register determines the
style of register and memory resources that shall be used by the
Am79C978 controller. The Software Style selection will affect the
interpretation of a few bits within
the CSR space, the order of the
descriptor entries and the width of
the descriptors and initialization
block entries.
All Am79C978 controller CSR
bits and BCR bits and all descriptor, buffer, and initialization block
entries not cited in Table 31 are
unaffected by the Software Style
selection and are, therefore, always fully functional as specified
in the CSR and BCR sections.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 address pins are always driven, regardless of the state of the
SSIZE32 bit.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. The SWSTYLE register will contain the
value 00h following H_RESET
and will be unaffected by
S_RESET or STOP.
Note that the setting of the
SSIZE32 bit has no effect on the
Table 31. Software Styles
SWSTYLE
[7:0]
Style
Name
SSIZE32
00h
LANCE/PCnet-ISA
controller
0
01h
RES
1
02h
PCnet-PCI
controller
1
03h
All Other
PCnet-PCI
controller
RES
1
Undefined
Am79C978
Initialization Block
Entries
Descriptor Ring Entries
16-bit software structures,
16-bit software structures,
non-burst or burst access
non-burst access only
RES
RES
32-bit software structures,
32-bit software structures,
non-burst or burst access
non-burst access only
32-bit software structures,
32-bit software structures,
non-burst or burst access
non-burst or burst access
Undefined
Undefined
135
CSR60: Previous Transmit Descriptor Address
Lower
Bit
Name
CSR63: Previous Transmit Status
Bit
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Contains the lower 16 bits of the
previous transmit descriptor address pointer. The Am79C978
controller has the capability to
stack multiple transmit frames.
PXDAL
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Name
Reserved locations. Written as
zeros and read as undefined.
15-0
Previous Transmit Status. This
field is a copy of bits 31-16 of
TMD1 of the previous transmit
descriptor.
PXST
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR64: Next Transmit Buffer Address Lower
Name
Reserved locations. Written as
zeros and read as undefined.
15-0
Contains the upper 16 bits of the
previous transmit descriptor address pointer. The Am79C978
controller has the capability to
stack multiple transmit frames.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
15-0
Contains the lower 16 bits of the
next transmit buffer address from
which the Am79C978 controller
will transmit an outgoing frame.
NXBAL
These bits are read/write accessible only when either the STOP or
the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR65: Next Transmit Buffer Address Upper
Bit
Name
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 RES
Reserved locations.
11-0
Previous Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the previous
transmit descriptor.
PXBC
Reserved locations. Written as
zeros and read as undefined.
15-0
Contains the upper 16 bits of the
next transmit buffer address from
which the Am79C978 controller
will transmit an outgoing frame.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
136
Description
31-16 RES
CSR62: Previous Transmit Byte Count
Bit
Description
31-16 RES
Description
31-16 RES
PXDAU
Description
31-16 RES
Bit
CSR61: Previous Transmit Descriptor Address
Upper
Bit
Name
Description
Am79C978
NXBAU
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR66: Next Transmit Byte Count
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 RES
Reserved locations. Read and
written as zeros.
11-0
NXBC
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Next Transmit Byte Count. This
field is a copy of the BCNT field of
TMD1 of the next transmit descriptor.
CSR74: Transmit Ring Counter
Bit
Name
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Transmit Ring Counter location.
Contains a two’s complement binary number used to number the
current transmit descriptor. This
counter interprets the value in
CSR78 as pointing to the first descriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
XMTRC
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR67: Next Transmit Status
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Next Transmit Status. This field is
a copy of bits 31-16 of TMD1 of
the next transmit descriptor.
NXST
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
7-0
RES
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR76: Receive Ring Length
Bit
Name
15-0
Receive Ring Length. Contains
the two’s complement of the receive descriptor ring length. This
register is initialized during the
Am79C978 controller’s initialization routine based on the value in
the RLEN field of the initialization
block. However, this register can
be manually altered. The actual
receive ring length is defined by
the current value in this register.
The ring length can be defined as
any value from 1 to 65535.
Description
Reserved locations. Written as
zeros and read as undefined.
15-0
Receive Ring Counter location.
Contains a two’s complement binary number used to number the
current receive descriptor. This
counter interprets the value in
CSR76 as pointing to the first descriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
RCVRC
Description
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Read and
written as zeros. Accessible only
when either the STOP or the
SPND bit is set.
31-16 RES
Name
31-16 RES
CSR72: Receive Ring Counter
Bit
Description
Am79C978
RCVRL
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
137
CSR78: Transmit Ring Length
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the Am79C978 controller’s initialization routine based on the value
in the TLEN field of the initialization block. However, this register
can be manually altered. The actual transmit ring length is defined
by the current value in this register. The ring length can be defined as any value from 1 to
65535.
XMTRL
work interface is operating in fullduplex mode, receive DMA will
be requested as soon as either
the RCVFW threshold is reached
or a complete valid receive frame
is detected (regardless of length).
When the FDRPAD (BCR9, bit 2)
is set and the Am79C978 controller is in full-duplex mode, in order
for receive DMA to be performed
for a new frame at least 64 bytes
must have been received. This
effectively disables the runt packet accept feature in full duplex.
When operating in the NO-SRAM
mode (no SRAM enabled), the
Bus Receive FIFO and the MAC
Receive operate like a single
FIFO and the watermark value
selected by RCVFW[1:0] sets the
number of bytes that must be
present in the FIFO before receive DMA is requested.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
When operating with the SRAM,
the Bus Receive FIFO, and the
MAC Receive FIFO operate independently on the bus side and
MAC side of the SRAM, respectively. In this case, the watermark
value set by RCVFW[1:0] sets the
number of bytes that must be
present in the Bus Receive FIFO
only. See Table 32.
CSR80: DMA Transfer Counter and FIFO Threshold
Control
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-14 RES
Reserved locations. Written as
zeros and read as undefined.
13-12 RCVFW[1:0] Receive
FIFO
Watermark.
RCVFW controls the point at
which receive DMA is requested
in relation to the number of received bytes in the Receive FIFO.
RCVFW specifies the number of
bytes which must be present
(once the frame has been verified
as a non-runt) before receive
DMA is requested. Note, however, that if the network interface is
operating in half-duplex mode, in
order for receive DMA to be performed for a new frame at least
64 bytes must have been received. This effectively avoids
having to react to receive frames
which are runts or suffer a collision during the slot time (512 bit
times). If the Runt Packet Accept
feature is enabled or if the net138
Table 32.
Receive Watermark Programming
RCVFW[1:0]
Bytes Received
00
16
01
64
10
112
11
Reserved
These bits are read/write accessible only when either the STOP
or the SPND bit is set.
RCVFW[1:0] is set to a value of
01b (64 bytes) after H_RESET or
S_RESET and is unaffected by
STOP.
11-10 XMTSP[1:0] Transmit Start Point. XMTSP
controls the point at which preamble transmission attempts to commence in relation to the number
of bytes written to the MAC
Transmit FIFO for the current
Am79C978
transmit frame. When the entire
frame is in the MAC Transmit
FIFO, transmission will start regardless of the value in XMTSP.
If the network interface is operating in half-duplex mode, regardless of XMTSP, the FIFO will not
internally overwrite its data until
at least 64 bytes (or the entire
frame if shorter than 64 bytes)
have been transmitted onto the
network. This ensures that for
collisions within the slot time window, transmit data need not be
rewritten to the Transmit FIFO,
and retries will be handled autonomously by the MAC. If the Disable Retry feature is enabled, or if
the network is operating in full-duplex mode, the Am79C978 controller
can
overwrite
the
beginning of the frame as soon as
the data is transmitted, because
no collision handling is required in
these modes.
Table 33.
Transmit Start Point Programming
XMTSP[1:0]
SRAM_SIZE
Bytes Written
00
0
20
01
0
64
10
0
128
11
0
220 max
00
>0
36
01
>0
64
10
>0
128
11
>0
Full Packet
>0
Full Packet when
NOUFLO bit is set
XX
9-8
Note that when the SRAM is being used, if the NOUFLO bit
(BCR18, bit 11) is set to 1, there
is the additional restriction that
the complete transmit frame must
be DMA’d into the Am79C978
controller and reside within a
combination of the Bus Transmit
FIFO, the SRAM, and the MAC
Transmit FIFO.
When the SRAM is used and
SRAM_SIZE > 0, there is a restriction that the number of bytes
written is a combination of bytes
written into the Bus Transmit
FIFO and the MAC Transmit
FIFO. The Am79C978 controller
supports a mode that will wait until a full packet is available before
commencing with the transmission of preamble. This mode is
useful in a system where high latencies cannot be avoided. See
Table 33.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. XMTSP is
set to a value of 01b (64 bytes) after H_RESET or S_RESET and
is unaffected by STOP.
Am79C978
XMTFW[1:0] Transmit FIFO Watermark. XMTFW specifies the point at which
transmit DMA is requested,
based upon the number of bytes
that could be written to the Transmit FIFO without FIFO overflow.
Transmit DMA is requested at
any time when the number of
bytes specified by XMTFW could
be written to the FIFO without
causing Transmit FIFO overflow
and the internal microcode engine has reached a point where
the Transmit FIFO is checked to
determine if DMA servicing is required.
When operating in the NO-SRAM
mode (no SRAM enabled) and
SRAM_SIZE is set to 0, the Bus
Transmit FIFO and the MAC
Transmit FIFO operate like a single FIFO and the watermark value selected by XMTFW[1:0] sets
the number of FIFO byte locations that must be available in the
FIFO before receive DMA is requested.
When operating with the SRAM,
the Bus Transmit FIFO and the
MAC Transmit FIFO operate independently on the bus side and
MAC side of the SRAM, respectively. In this case, the watermark
value set by XMTFW[1:0] sets the
number of FIFO byte locations
that must be available in the Bus
Transmit FIFO. See Table 34
139
.
15-0
Table 34.
DMABAL
Transmit Watermark Programming
XMTFW[1:0]
Bytes Available
00
16
01
64
10
108
11
Reserved
These bits are read/write accessible only when either the STOP
or the SPND bit is set. XMTFW is
set to a value of 00b (16 bytes) after H_RESET or S_RESET and
is unaffected by STOP.
7-0
DMATC[7:0] DMA Transfer Counter. Writing
and reading to this field has no effect.
Use
MAX_LAT
and
MIN_GNT in the PCI configuration space.
CSR82: Transmit Descriptor Address Pointer
Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Contains the lower 16 bits of the
transmit descriptor address corresponding to the last buffer of
the previous transmit frame. If the
previous transmit frame did not
use buffer chaining, then TXDAPL contains the lower 16 bits of
the previous frame’s transmit descriptor address.
TXDAPL
When both the STOP or SPND
bits are cleared, this register is
updated by the Am79C978 controller immediately before a transmit descriptor write.
Read accessible always. Write
accessible through the PXDAL
bits (CSR60) when the STOP or
SPND bit is set. TXDAPL is set to
0 by H_RESET and are unaffected by S_RESET or STOP.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR85: DMA Address Register Upper
Bit
Name
31-16 RES
140
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
This register contains the upper
16 bits of the address of system
memory for the current DMA cycle. The Bus Interface Unit controls the Address Register by
issuing increment commands to
increment the memory address
for sequential operations. The
DMABAU register is undefined
until the first Am79C978 controller DMA operation.
DMABAU
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR86: Buffer Byte Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 RES
Reserved. Read and written with
ones.
11-0
DMA Byte Count Register. Contains the two's complement of the
current size of the remaining
transmit or receive buffer in
bytes. This register is incremented by the Bus Interface Unit. The
CSR84: DMA Address Register Lower
Bit
This register contains the lower
16 bits of the address of system
memory for the current DMA cycle. The Bus Interface Unit controls the Address Register by
issuing increment commands to
increment the memory address
for sequential operations. The
DMABAL register is undefined
until the first Am79C978 controller DMA operation.
Description
Reserved locations. Written as
zeros and read as undefined.
Am79C978
DMABC
DMABC register is undefined until written.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR89: Chip ID Register Upper
Bit
Name
31-16 RES
Reserved locations. Read as undefined.
15-12 VER
Version. This 4-bit pattern is
silicon-revision dependent.
CSR88: Chip ID Register Lower
Bit
Name
31-28 VER
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. Write operations are ignored.
Description
Version. This 4-bit pattern is
silicon-revision dependent.
11-0
PARTIDU
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. Write operations are ignored.
27-12 PARTID
Read accessible only when either
the STOP or the SPND bit is set.
PARTID is read only. Write operations are ignored.
11-1
MANFID
CSR92: Ring Length Conversion
Bit
Name
Reserved locations. Written as
zeros and read as undefined.
15-0
Ring Length Conversion Register. This register performs a ring
length conversion from an encoded value as found in the initialization block to a two’s complement
value used for internal counting.
By writing bits 15-12 with an encoded ring length, a two’s complemented value is read. The
RCON register is undefined until
written.
RCON
Note that this code is not the
same as the Vendor ID in the PCI
configuration space.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR100: Bus Timeout
Bit
0
ONE
Description
31-16 RES
Manufacturer ID. The 11-bit manufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. MANFID is
read only. Write operations are
ignored.
Upper 12 bits of the Am79C978
controller part number, i.e., 0010
0110 0010b (262h).
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. PARTIDU is
read only. Write operations are
ignored.
Part number. The 16-bit code for
the Am79C978 controller is
0010 0110 0010 0110 (2626h).
This register is exactly the same
as the Device ID register in the
JTAG description. However, this
part number is different from that
stored in the Device ID register in
the PCI configuration space.
Description
Name
Description
Always a logic 1.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. ONE is read
only. Write operations are ignored.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
This register contains the value of
the longest allowable bus latency
(interval between assertion of
REQ and assertion of GNT) that a
Am79C978
MERRTO
141
system may insert into an
Am79C978 controller master
transfer. If this value of bus latency is exceeded, then a MERR will
be indicated in CSR0, bit 11, and
an interrupt may be generated,
depending upon the setting of the
MERRM bit (CSR3, bit 11) and
the IENA bit (CSR0, bit 6).
The value in this register is interpreted as the unsigned number of
bus clock periods divided by two,
(i.e., the value in this register is
given in 0.1 ms increments). For
example, the value 0600h (1536
decimal) will cause a MERR to be
indicated after 153.6 ms of bus
latency. A value of 0 will allow an
infinitely long bus latency, i.e.,
bus timeout error will never occur.
These bits are read/write accessible only when either the STOP
or the SPND bit is set. This register is set to 0600h by H_RESET
or S_RESET and is unaffected by
STOP.
sions encountered by the
receiver since the last reset of the
counter.
RCC will roll over to a count of 0
from the value 65535. The
RCVCCO bit of CSR4 (bit 5) will
be set each time that this occurs.
These bits are read accessible always. RCC is read only, write operations are ignored. RCC is
cleared
by
H_RESET
or
S_RESET, or by setting the
STOP bit.
CSR116: OnNow Power Mode Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
31-16 RES
Name
Reserved locations. Written as
zeros and read as undefined.
15-0
Missed Frame Count. Indicates
the number of missed frames.
MFC
These bits are read/write accessible only when either the STOP bit
or the SPND bit is set. Cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Description
31-16 RES
9
LCDET
MFC will roll over to a count of 0
from the value 65535. The MFCO
bit of CSR4 (bit 8) will be set each
time that this occurs.
Read accessible always. MFC is
read only, write operations are ignored. MFC is cleared by
H_RESET, or S_RESET or by
setting the STOP bit.
Name
This bit is always read/write accessible.
8
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Receive Collision Count. Indicates the total number of colli-
142
RCC
Link Change Detected. This bit is
set when the MII auto-polling logic detects a change in link status
and the LCMODE bit is set.
LCDET is cleared when power is
initially applied (POR).
CSR114: Receive Collision Count
Bit
Reserved locations. Written as
zeros and read as undefined.
10 PME_EN_OVR PME_EN Overwrite. When this
bit is set and the MPMAT or
LCDET bit is set, the PME pin will
always be asserted regardless of
the state of the PME_EN bit.
CSR112: Missed Frame Count
Bit
Description
Am79C978
LCMODE
Link Change Wake-up Mode.
When this bit is set to 1, the
LCDET bit gets set when the MII
auto polling logic detects a Link
Change.
Read/Write accessible only when
either the STOP bit or the SPND
bit is set. Cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
7
PMAT
Pattern Matched. This bit is set
when the PMMODE bit is set and
an OnNow pattern match occurs.
Read/Write accessible only when
either the STOP bit or the SPND
bit is set. Cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
PMAT is cleared when power is
initially applied (POR).
3-1
This bit is read accessible always.
6
EMPPLBA
Magic Packet Physical Logical
Broadcast Accept. If both EMPPLBA and MPPLBA (CSR5, bit 5)
are at their default value of 0, the
Am79C978 controller will only detect a Magic Packet frame if the
destination address of the packet
matches the content of the physical address register (PADR). If either EMPPLBA or MPPLBA is set
to 1, the destination address of
the Magic Packet frame can be
unicast, multicast, or broadcast.
Note that the setting of EMPPLBA and MPPLBA only affects the
address detection of the Magic
Packet frame. The Magic Packet
frame’s data sequence must be
made up of 16 consecutive physical addresses (PADR[47:0]) regardless of what kind of
destination address it has.
0 RST_POL
MPMAT
Bit
Description
RES
Reserved locations. Written as
zeros and read as undefined.
0
RCVALGN
Receive Packet Align. When set,
this bit forces the data field of ISO
8802-3 (IEEE/ANSI 802.3) packets to align to 0 MOD 4 address
boundaries (i.e., DWord aligned
addresses). It is important to note
that this feature will only function
correctly if all receive buffer
boundaries are DWord aligned
and all receive buffers have 0
MOD 4 lengths. In order to accomplish the data alignment, the
Am79C978 controller simply inserts two bytes of random data at
the beginning of the receive packet (i.e., before the ISO 8802-3
(IEEE/ANSI 802.3) destination
address field). The MCNT field
reported to the receive descriptor
will not include the extra two
bytes.
Magic Packet Match. This bit is
set when the integrated Ethernet
controller detects a Magic Packet
while it is in Magic Packet mode.
Magic Packet Pin Enable. When
this bit is set, the device enters
the Magic Packet mode when the
PG input goes LOW or MPEN bit
(CSR5, bit 2) gets set to 1. This
bit is OR’ed with MPEN bit
(CSR5, bit 2).
Name
31-1
This bit is always read/write accessible.
MPPEN
PHY_RST Pin Polarity. If the
PHY_POL is set to 1, the
PHY_RST pin is active LOW; otherwise PHY_RST is active HIGH.
CSR122: Advanced Feature Control
MPMAT is cleared when power is
initially applied (POR).
4
Reserved locations.
This bit is read/write accessible
only when either the STOP bit or
the SPND bit is set. Cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
This bit is always read/write accessible. EMPPLBA is set to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
5
RES
This bit is always read/write accessible. RCVALGN is cleared by
H_RESET or S_RESET and is
not affected by STOP.
CSR124: Test Register 1
This register is used to place the Am79C978 controller
into various test modes. The Runt Packet Accept is the
only user accessible test mode. All other test modes are
for AMD internal use only.
Am79C978
143
Bit
Name
Description
31-4
RES
Reserved locations. Written as
zeros and read as undefined.
3
RPA
Runt Packet Accept. This bit
forces the Am79C978 controller
to accept runt packets (packets
shorter than 64 bytes).
match due to delays in the part
used to make up the final IPG.
Changes should be added or subtracted from the provided hex value on a one-for-one basis.
CAUTION: Use this parameter
with care. By lowering the IPG
below the ISO/IEC 8802-3 standard 96 bit times, the
Am79C978 controller can interrupt normal network behavior.
This bit is read accessible always; write accessible only when
STOP is set to 1. RPA is cleared
by H_RESET or S_RESET and is
not affected by STOP.
2-0
RES
These bits are read accessible always. Write accessible when the
STOP bit is set to 1. IPG is set to
60h (96 Bit times) by H_RESET
or S_RESET and is not affected
by STOP.
Reserved locations. Written as
zeros and read as undefined.
CSR125: MAC Enhanced Configuration Control
Bit
Name
7-0
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8
Inter Packet Gap. Changing IPG
allows the user to program the
Am79C978 controller for aggressiveness on a network. By changing the default value of 96 bit
times (60h) the user can adjust
the fairness or aggressiveness of
the Am79C978 integrated MAC
on the network. By programming
a lower number of bit times other
then the ISO/IEC 8802-3 standard requires, the Am79C978
controller will become more aggressive on the network. This aggressive nature will give rise to
the Am79C978 controller possibly “capturing the network” at
times by forcing other less aggressive nodes to defer. By programming a larger number of bit
times, the Am79C978 home networking MAC will become less
aggressive on the network and
may defer more often than normal. The performance of the
Am79C978 controller may decrease as the IPG value is increased from the default value.
IPG
Note: Programming of the IPG
should be done in nibble intervals
instead of absolute bit times. The
decimal and hex values do not
144
Am79C978
IFS1
InterFrameSpacingPart1. Changing IFS1 allows the user to program the value of the InterFrameSpacePart1
timing.
The
Am79C978 controller sets the default value at 60 bit times (3ch).
See the subsection on Medium
Allocation in the section Media
Access Management for more
details. The equation for setting
IFS1 when IPG ≥ 96 bit times is:
IFS1 = IPG - 36 bit times
Note: Programming of the IPG
should be done in nibble intervals
instead of absolute bit times due
to the MII. The decimal and hex
values do not match due to delays in the part used to make up
the final IPG.
Changes should be added or
subtracted from the provided hex
value on a one-for-one basis.
Due to changes in synchronization delays internally through different network ports, the IFS1
can be off by as much as +12 bit
times.
These bits are read accessible always. Write accessible only when
the SPND bit or the STOP bit is
set to 1. IFS1 is set to 3ch (60 bit
times)
by
H_RESET
or
S_RESET and is not affected by
STOP.
Bus Configuration Registers (BCRs)
The BCRs are used to program the configuration of the
bus interface and other special features of the
Am79C978 controller that are not related to the IEEE
802.3 MAC functions. The BCRs are accessed by first
setting the appropriate RAP value and then by performing a slave access to the BDP. See Table 35.
All BCR registers are 16 bits in width in Word I/O mode
(DWIO = 0, BCR18, bit 7) and 32 bits in width in DWord
I/O mode (DWIO = 1). The upper 16 bits of all BCR registers is undefined when in DWord I/O mode. These
bits should be written as zeros and should be treated
as undefined when read. The default value given for
any BCR is the value in the register after H_RESET.
Some of these values may be changed shortly after
H_RESET when the contents of the external EEPROM
is automatically read in. None of the BCR register values are affected by the assertion of the STOP bit or
S_RESET.
Note that several registers have no default value.
BCR0, BCR1, BCR3, BCR8, BCR10-17, and BCR21
are reserved and have undefined values. BCR2 and
BCR34 are not observable without first being programmed through the EEPROM read operation or a
user register write operation.
BCR0, BCR1, BCR16, BCR17, and BCR21 are registers that are used by other devices in the PCnet family.
Writing to these registers have no effect on the operation of the Am79C978 controller.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Reserved
locations.
After
H_RESET, the value in this register will be 0005h. The setting of
this register has no effect on any
Am79C978 controller function. It
is only included for software compatibility with other PCnet family
devices.
Read always. MSWRA is read
only. Write operations have no effect.
BCR2: Miscellaneous Configuration
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
15-14 RES
Reserved locations. Written and
read as zeros.
13
Reserved locations. Written as
zeros and read as undefined.
15-0
Reserved
locations.
After
H_RESET, the value in this register will be 0005h. The setting of
this register has no effect on any
Am79C978 controller function. It
is only included for software compatibility with other PCnet family
devices.
MSRDA
This bit is always read/write accessible. TSTSHDEN is cleared
to 0 by H_RESET and is unaffected by S_RESET or by setting the
STOP bit.
12
Read always. MSRDA is read
only. Write operations have no effect.
BCR1: Master Mode Write Active
Bit
Name
PHYSELEN This bit enables writes to
BCR18[4:3] for software selection of various operation and test
modes. When PHYSELEN is set
to 0 (default), the two bits can
only be written from the EEPROM. When PHYSELEN is set
to 1, writes to BCR18[4:3] are enabled.
Description
31-16 RES
Description
Reserved locations. Written as
zeros and read as undefined.
BCR0: Master Mode Read Active
Name
Name
31-16 RES
Writes to those registers marked as “Reserved” will
have no effect. Reads from these locations will produce
undefined values.
Bit
MSWRA
LEDPE
LED Program Enable. When
LEDPE is set to 1, programming
of the LED0 (BCR4), LED1
(BCR5), LED2 (BCR6), LED3
(BCR7), and LED4 (BCR48) registers is enabled. When LEDPE is
cleared to 0, programming of
LED0 (BCR4), LED1 (BCR5),
LED2 (BCR6), LED3 (BCR7),
and LED4 (BCR48) registers is
disabled. Writes to those registers will be ignored.
Description
Am79C978
145
Table 35. BCR Registers
RAP
0
1
2
3
4
5
6
7
8
9
10-15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Mnemonic
MSRDA
MSWRA
MC
Reserved
LED0
LED1
LED2
LED3
Reserved
FDC
Reserved
IOBASEL
IOBASEU
BSBC
EECAS
SWS
INTCON
PCILAT
PCISID
PCISVID
SRAMSIZ
SRAMB
SRAMIC
EBADDRL
EBADDRU
EBD
STVAL
MIICAS
MIIADDR
MIIMDR
PCIVID
Default
0005h
0005h
0002h
N/A
00C0h
0084h
0088h
0090h
N/A
0000h
N/A
N/A
N/A
9001h
0002h
0000h
N/A
FF06h
0000h
0000h
0000h
0000h
0000h
N/A
N/A
N/A
FFFFh
0000h
0000h
N/A
1022h
36
PMC_A
C811h
37
38
39
40
41
42
43
44
45
46
47
48
49
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
PMR1
PMR2
PMR3
LED4
PHY Select
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N/A
N/A
N/A
0082h
8101h
146
Name
Reserved
Reserved
Miscellaneous Configuration
Reserved
LED0 Status
LED1 Status
LED2 Status
LED3 Status
Reserved
Full-Duplex Control
Reserved
Reserved
Reserved
Burst and Bus Control
EEPROM Control and Status
Software Style
Reserved
PCI Latency
PCI Subsystem ID
PCI Subsystem Vendor ID
SRAM Size
SRAM Boundary
SRAM Interface Control
Expansion Bus Address Lower
Expansion Bus Address Upper
Expansion Bus Data Port
Software Timer Value
PHY Control and Status
PHY Address
PHY Management Data
PCI Vendor ID
PCI Power Management Capabilities (PMC)
Alias Register
PCI DATA Register 0 Alias Register
PCI DATA Register 1 Alias Register
PCI DATA Register 2 Alias Register
PCI DATA Register 3 Alias Register
PCI DATA Register 4 Alias Register
PCI DATA Register 5 Alias Register
PCI DATA Register 6 Alias Register
PCI DATA Register 7 Alias Register
Pattern Matching Register 1
Pattern Matching Register 2
Pattern Matching Register 3
LED4 Status
PHY Select
Am79C978
Programmability
User
EEPROM
No
No
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
No
No
No
No
Yes
Yes
Yes
No
Yes
No
No
No
Yes
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
This bit is always read/write accessible. LEDPE is cleared to 0
by H_RESET and is unaffected
by S_RESET or by setting the
STOP bit.
11-9
8
RES
APROMWE Address PROM Write Enable.
The Am79C978 controller contains a shadow RAM on board for
storage of the first 16 bytes loaded from the serial EEPROM.
Accesses to Address PROM I/O
Resources will be directed toward
this RAM. When APROMWE is
set to 1, then write access to the
shadow RAM will be enabled.
INTLEVEL
INTLEVEL should not be set to 1
when the Am79C978 controller is
used in a PCI bus application.
Reserved locations. Written and
read as zeros.
This bit is always read/write accessible. APROMWE is cleared
to 0 by H_RESET and is unaffected by S_RESET or by setting the
STOP bit.
7
terrupt channels to be shared by
multiple devices.
Interrupt Level. This bit allows the
interrupt output signals to be programmed for level or edgesensitive applications.
When INTLEVEL is cleared to 0,
the INTA pin is configured for
level-sensitive applications. In
this mode, an interrupt request is
signaled by a low level driven on
the INTA pin by the Am79C978
controller. When the interrupt is
cleared, the INTA pin is tri-stated
by the Am79C978 controller and
allowed to be pulled to a high level by an external pullup device.
This mode is intended for systems which allow the interrupt
signal to be shared by multiple
devices.
When INTLEVEL is set to 1, the
INTA pin is configured for edgesensitive applications. In this
mode, an interrupt request is signaled by a high level driven on
the INTA pin by the Am79C978
controller. When the interrupt is
cleared, the INTA pin is driven to
a low level by the Am79C978
controller. This mode is intended
for systems that do not allow in-
This bit is always read/write accessible. INTLEVEL is cleared to
0 by H_RESET and is unaffected
by S_RESET or by setting the
STOP bit.
6-3
RES
Reserved locations. Written as
zeros and read as undefined.
2-0
RES
Reserved locations. Written and
read as zeros.
BCR4: LED0 Status
BCR4 controls the function(s) that the LED0 pin displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the
logical OR of the enabled functions. BCR4 defaults to
Link Status (LNKST) with pulse stretcher enabled
(PSE = 1) and is fully programmable.
Note: When LEDPE (BCR2, bit 12) is set to 1, programming of the LED0 Status register is enabled.
When LEDPE is cleared to 0, programming of the
LED0 register is disabled. Writes to those registers will
be ignored.
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
This bit indicates the current
(non-stretched) value of the LED
output pin. A value of 1 in this bit
indicates that the OR of the enabled signals is true.
LEDOUT
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of the LED register
(bits 8 and 6-0).
This bit is read accessible always. This bit is read only; writes
have no effect. LEDOUT is unaffected by H_RESET, S_RESET,
or STOP.
14
Am79C978
LEDPOL
LED Polarity. When this bit has
the value 0, then the LED pin will
147
be driven to a LOW level whenever the OR of the enabled signals
is true, and the LED pin will be
disabled and allowed to float high
whenever the OR of the enabled
signals is false (i.e., the LED output will be an Open Drain output
and the output value will be the
inverse of the LEDOUT status
bit).
When this bit has the value 1,
then the LED pin will be driven to
a HIGH level whenever the OR of
the enabled signals is true, and
the LED pin will be driven to a
LOW level whenever the OR of
the enabled signals is false (i.e.,
the LED output will be a Totem
Pole output and the output value
will be the same polarity as the
LEDOUT status bit.).
11-10 RES
Reserved locations. Written and
read as zeros.
9
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when Magic Packet
frame mode is enabled and a
Magic Packet frame is detected
on the network.
MPSE
This bit is always read/write accessible. MPSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
8
FDLSE
The setting of this bit will not effect the polarity of the LEDOUT
bit for this register.
This bit is always read/write accessible. LEDPOL is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
13
LEDDIS
LED Disable. This bit is used to
disable the LED output. When
LEDDIS has the value 1, then the
LED output will always be disabled. When LEDDIS has the value 0, then the LED output value
will be governed by the LEDOUT
and LEDPOL values.
This bit is always read/write accessible. FDLSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
7
PSE
This bit is always read/write accessible. LEDDIS is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
12
100E
100 Mbps Enable. When this bit
is set to 1, a value of 1 is passed
to the LEDOUT bit in this register
when the Am79C978 controller is
operating at 100 Mbps mode.
Pulse Stretcher Enable. When
this bit is set, the LED illumination
time is extended for each new occurrence of the enabled function
for this LED output. A value of 0
disables the pulse stretcher.
This bit is always read/write accessible. PSE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
6
This bit is always read/write accessible. 100E is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
148
Full-Duplex Link Status Enable.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LEDOUT signal when the Am79C978
controller is functioning in a Link
Pass state and full-duplex operation is enabled. When the
Am79C978 controller is not functioning in a Link Pass state with
full-duplex operation being enabled, a value of 0 is passed to
the LEDOUT signal.
Am79C978
LNKSE
Link Status Enable. When this bit
is set, a value of 1 will be passed
to the LEDOUT bit in this register
when in Link Pass state.
This bit is always read/write accessible. LNKSE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
5
RCVME
Receive Match Status Enable.
When this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive activity on the network that has
passed the address match function for this node. All address
matching modes are included:
physical, logical filtering, broadcast, and promiscuous.
This bit is always read/write accessible. RCVME is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
4
XMTE
Transmit Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
This bit is always read/write accessible. XMTE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
3
2
POWER
RCVE
This bit is always read/write accessible. COLE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
BCR5: LED1 Status
BCR5 controls the function(s) that the LED1 pin displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the
logical OR of the enabled functions. BCR5 defaults to
Receive Status (RCV) with pulse stretcher enabled
(PSE = 1) and is fully programmable.
Note: When LEDPE (BCR2, bit 12) is set to 1, programming of the LED1 Status register is enabled.
When LEDPE is cleared to 0, programming of the
LED1 register is disabled. Writes to those registers will
be ignored.
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
This bit indicates the current
(non-stretched) value of the LED
output pin. A value of 1 in this bit
indicates that the OR of the enabled signals is true.
LEDOUT
Power. When this bit is set to 1,
the device is operating in HIGH
power mode.
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of the LED register
(bits 8 and 6-0).
Receive Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive activity on the network.
This bit is always read/write accessible. RCVE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
1
SPEED
Speed. When this bit is set to 1,
the device is operating in HIGH
speed mode.
0
COLE
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network.
Description
This bit is always read accessible. This bit is read only; writes
have no effect. LEDOUT is unaffected by H_RESET, S_RESET,
or STOP.
14
Am79C978
LEDPOL
LED Polarity. When this bit has
the value 0, then the LED pin will
be driven to a LOW level whenever the OR of the enabled signals
is true, and the LED pin will be
disabled and allowed to float high
whenever the OR of the enabled
signals is false (i.e., the LED output will be an Open Drain output
and the output value will be the
inverse of the LEDOUT status
bit).
149
When this bit has the value 1,
then the LED pin will be driven to
a HIGH level whenever the OR of
the enabled signals is true, and
the LED pin will be driven to a
LOW level whenever the OR of
the enabled signals is false (i.e.,
the LED output will be a Totem
Pole output and the output value
will be the same polarity as the
LEDOUT status bit).
This bit is always read/write accessible. MPSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
8
FDLSE
The setting of this bit will not effect the polarity of the LEDOUT
bit for this register.
This bit is always read/write accessible. LEDPOL is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
13
LEDDIS
LED Disable. This bit is used to
disable the LED output. When
LEDDIS has the value 1, then the
LED output will always be disabled. When LEDDIS has the value 0, then the LED output value
will be governed by the LEDOUT
and LEDPOL values.
This bit is always read/write accessible. FDLSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
7
PSE
This bit is always read/write accessible. LEDDIS is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
12
100E
100 Mbps Enable. When this bit
is set to 1, a value of 1 is passed
to the LEDOUT bit in this register
when the Am79C978 controller is
operating at 100 Mbps mode.
9
150
MPSE
Reserved locations. Written and
read as zeros.
Pulse Stretcher Enable. When
this bit is set, the LED illumination
time is extended for each new occurrence of the enabled function
for this LED output. A value of 0
disables the pulse stretcher.
This bit is always read/write accessible. PSE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
6
LNKSE
This bit is always read/write accessible. 100E is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
11-10 RES
Full-Duplex Link Status Enable.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LEDOUT signal when the Am79C978
controller is functioning in a Link
Pass state and full-duplex operation is enabled. When the
Am79C978 controller is not functioning in a Link Pass state with
full-duplex operation being enabled, a value of 0 is passed to
the LEDOUT signal.
Link Status Enable. When this bit
is set, a value of 1 will be passed
to the LEDOUT bit in this register
in Link Pass state.
This bit is always read/write accessible. LNKSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
5
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when Magic Packet
mode is enabled and a Magic
Packet frame is detected on the
network.
Am79C978
RCVME
Receive Match Status Enable.
When this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive activity on the network that has
passed the address match function for this node. All address
matching modes are included:
physical, logical filtering, broadcast, and promiscuous.
This bit is always read/write accessible. RCVME is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Note: When LEDPE (BCR2, bit 12) is set to 1, programming of the LED2 Status register is enabled.
When LEDPE is cleared to 0, programming of the
LED2 register is disabled. Writes to those registers will
be ignored.
Note: Bits 15-0 in this register are programmable
through the EEPROM PREAD operation.
Bit
4
XMTE
Transmit Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
This bit indicates the current
(non-stretched) value of the LED
output pin. A value of 1 in this bit
indicates that the OR of the enabled signals is true.
LEDOUT
This bit is always read/write accessible. XMTE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
3
POWER
Power. When this bit is set to 1,
the device is operating in HIGH
power mode.
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of the LED register
(bits 8 and 6-0).
2
RCVE
Receive Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive activity on the network.
This bit is read accessible always. This bit is read only; writes
have no effect. LEDOUT is unaffected by H_RESET, S_RESET,
or STOP.
This bit is always read/write accessible. RCVE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
1
SPEED
Speed. When this bit is set to 1,
the device is operating in HIGH
speed mode.
0
COLE
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network.
14
This bit is always read/write accessible. COLE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
BCR6: LED2 Status
BCR6 controls the function(s) that the LED2 pin displays. Multiple functions can be simultaneously enabled
on this LED pin. The LED display will indicate the logical
OR of the enabled functions.
Am79C978
LEDPOL
LED Polarity. When this bit has
the value 0, then the LED pin will
be driven to a LOW level whenever the OR of the enabled signals
is true, and the LED pin will be
disabled and allowed to float high
whenever the OR of the enabled
signals is false (i.e., the LED output will be an Open Drain output
and the output value will be the
inverse of the LEDOUT status
bit).
When this bit has the value 1,
then the LED pin will be driven to
a HIGH level whenever the OR of
the enabled signals is true, and
the LED pin will be driven to a
LOW level whenever the OR of
the enabled signals is false (i.e.,
the LED output will be a Totem
Pole output and the output value
will be the same polarity as the
LEDOUT status bit).
The setting of this bit will not effect the polarity of the LEDOUT
bit for this register.
151
13
LEDDIS
This bit is always read/write accessible. LEDPOL is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Am79C978 controller is not functioning in a Link Pass state with
full-duplex operation being enabled, a value of 0 is passed to
the LEDOUT signal.
LED Disable. This bit is used to
disable the LED output. When
LEDDIS has the value 1, then the
LED output will always be disabled. When LEDDIS has the value 0, then the LED output value
will be governed by the LEDOUT
and LEDPOL values.
This bit is always read/write accessible. FDLSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
7
PSE
This bit is always read/write accessible. LEDDIS is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
12
100E
100 Mbps Enable. When this bit
is set to 1, a value of 1 is passed
to the LEDOUT bit in this register
when the Am79C978 controller is
operating at 100 Mbps mode.
This bit is always read/write accessible. PSE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
6
LNKSE
This bit is always read/write accessible. 100E is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
11-10 RES
Reserved locations. Written and
read as zeros.
9
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when Magic Packet
frame mode is enabled and a
Magic Packet frame is detected
on the network.
MPSE
152
FDLSE
Full-Duplex Link Status Enable.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LEDOUT signal when the Am79C978
controller is functioning in a Link
Pass state and full-duplex operation is enabled. When the
Link Status Enable. When this bit
is set, a value of 1 will be passed
to the LEDOUT bit in this register
in Link Pass state.
This bit is always read/write accessible. LNKSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
5
RCVME
This bit is always read/write accessible. MPSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
8
Pulse Stretcher Enable. When
this bit is set, the LED illumination
time is extended for each new occurrence of the enabled function
for this LED output. A value of 0
disables the pulse stretcher.
Receive Match Status Enable.
When this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive activity on the network that has
passed the address match function for this node. All address
matching modes are included:
physical, logical filtering, broadcast, and promiscuous.
This bit is always read/write accessible. RCVME is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
4
Am79C978
XMTE
Transmit Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
This bit is always read/write accessible. XMTE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
3
POWER
Power. When this bit is set to 1,
the device is operating in HIGH
power mode.
2
RCVE
Receive Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive activity on the network.
This bit is always read/write accessible. RCVE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
1
SPEED
Speed. When this bit is set to 1,
the device is operating in HIGH
speed mode.
0
COLE
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network.
15
LEDOUT
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of the LED register
(bits 8 and 6-0).
This bit is read accessible always. This bit is read only; writes
have no effect. LEDOUT is unaffected by H_RESET, S_RESET,
or STOP.
14
LEDPOL
BCR7: LED3 Status
BCR7 controls the function(s) that the LED3 pin displays. Multiple functions can be simultaneously enabled
on this LED pin. The LED display will indicate the logical
OR of the enabled functions. BCR7 defaults to Transmit
Status (XMT) with pulse stretcher enabled (PSE = 1)
and is fully programmable.
The setting of this bit will not effect the polarity of the LEDOUT
bit for this register.
Note: When LEDPE (BCR2, bit 12) is set to 1, programming of the LED3 Status register is enabled.
When LEDPE is cleared to 0, programming of the
LED3 register is disabled. Writes to those registers will
be ignored.
Bit
Name
31-16 RES
Description
LED Polarity. When this bit has
the value 0, then the LED pin will
be driven to a LOW level whenever the OR of the enabled signals
is true, and the LED pin will be
disabled and allowed to float high
whenever the OR of the enabled
signals is false (i.e., the LED output will be an Open Drain output
and the output value will be the
inverse of the LEDOUT status
bit.).
When this bit has the value 1,
then the LED pin will be driven to
a HIGH level whenever the OR of
the enabled signals is true, and
the LED pin will be driven to a
LOW level whenever the OR of
the enabled signals is false (i.e.,
the LED output will be a Totem
Pole output and the output value
will be the same polarity as the
LEDOUT status bit).
This bit is always read/write accessible. COLE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Note: Bits 15-0 in this register are programmable
through the EEPROM.
This bit indicates the current
(non-stretched) value of the LED
output pin. A value of 1 in this bit
indicates that the OR of the enabled signals is true.
This bit is always read/write accessible. LEDPOL is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
13
Reserved locations. Written as
zeros and read as undefined.
Am79C978
LEDDIS
LED Disable. This bit is used to
disable the LED output. When
LEDDIS has the value 1, then the
LED output will always be disabled. When LEDDIS has the value 0, then the LED output value
153
will be governed by the LEDOUT
and LEDPOL values.
time is extended for each new occurrence of the enabled function
for this LED output. A value of 0
disables the pulse stretcher.
This bit is always read/write accessible. LEDDIS is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
12
100E
100 Mbps Enable. When this bit
is set to 1, a value of 1 is passed
to the LEDOUT bit in this register
when the Am79C978 controller is
operating at 100 Mbps mode.
This bit is always read/write accessible. PSE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
6
LNKSE
This bit is always read/write accessible. 100E is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
11-10 RES
9
MPSE
Reserved locations. Written and
read as zeros.
This bit is always read/write accessible. LNKSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
5
RCVME
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when magic frame
mode is enabled and a magic
frame is detected on the network.
This bit is always read/write accessible. MPSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
8
FDLSE
Full-Duplex Link Status Enable.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LEDOUT signal when the Am79C978
controller is functioning in a Link
Pass state and full-duplex operation is enabled. When the
Am79C978 controller is not functioning in a Link Pass state with
full-duplex operation being enabled, a value of 0 is passed to
the LEDOUT signal.
This bit is always read/write accessible. FDLSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
7
154
PSE
Link Status Enable. When this bit
is set, a value of 1 will be passed
to the LEDOUT bit in this register
in Link Pass state.
Receive Match Status Enable.
When this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive activity on the network that has
passed the address match function for this node. All address
matching modes are included:
physical, logical filtering, broadcast, and promiscuous.
This bit is always read/write accessible. RCVME is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
4
XMTE
Transmit Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
This bit is always read/write accessible. XMTE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
3
POWER
Power. When this bit is set to 1,
the device is operating in HIGH
power mode.
2
RCVE
Receive Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
Pulse Stretcher Enable. When
this bit is set, the LED illumination
Am79C978
register when there is receive activity on the network.
This bit is always read/write accessible. RCVE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
1
SPEED
Speed. When this bit is set to 1,
the device is operating in HIGH
speed mode.
0
COLE
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network.
S_RESET or by setting the STOP
bit.
1
RES
Reserved locations. Written as
zeros and read as undefined.
0
FDEN
Full-Duplex Enable. FDEN controls whether full-duplex operation is enabled. When FDEN is
cleared and the Auto-Negotiation
is disabled, full-duplex operation
is
not enabled and the
Am79C978 controller will always
operate in half-duplex mode.
When FDEN is set, the
Am79C978 controller will operate
in full-duplex mode. Do not set
this bit when Auto-Negotiation
is enabled.
This bit is always read/write accessible. COLE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
This bit is always read/write accessible. FDEN is reset to 0 by
H_RESET, and is unaffected by
S_RESET and the STOP bit.
BCR9: Full-Duplex Control
BCR16: I/O Base Address Lower
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Bit
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-5
Reserved
locations.
After
H_RESET, the value of these bits
will be undefined. The settings of
these bits will have no effect on
any Am79C978 controller function.
Name
31-3
RES
Reserved locations. Written as
zeros and read as undefined.
2
FDRPAD
Full-Duplex Runt Packet Accept
Disable. When FDRPAD is set to
1 and full-duplex mode is enabled, the Am79C978 controller
will only receive frames that meet
the minimum Ethernet frame
length of 64 bytes. Receive DMA
will not start until at least 64 bytes
or a complete frame have been
received. By default, FDRPAD is
cleared to 0. The Am79C978 controller will accept any length
frame and receive DMA will start
according to the programming of
the receive FIFO watermark.
Note that there should not be any
runt packets in a full-duplex network, since the main cause for
runt packets is a network collision
and there are no collisions in a
full-duplex network.
Name
IOBASEL
Description
These bits are always read/write
accessible. IOBASEL is not affected by S_RESET or STOP.
4-0
RES
Reserved locations. Written as
zeros, read as undefined.
BCR17: I/O Base Address Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Reserved
locations.
After
H_RESET, the value in this register will be undefined. The settings
of this register will have no effect
on any Am79C978 controller
function.
This bit is always read/write accessible. FDRPAD is cleared by
H_RESET and is not affected by
Am79C978
IOBASEU
155
This bit is always read/write accessible. IOBASEU is not affected by S_RESET or STOP.
tACC = ROMTMG * CLK period
*CLK_FAC - (tv_A_D) + (ts_D)
The access time for the Expansion ROM or for the EBDATA
(BCR30) device (tACC) during
write operations can be calculated by subtracting the clock to output delay for the EBUA EBA[7:0]
outputs (tv_A_D) and by adding
the input to clock setup time for
Flash/EPRO inputs (ts_D) from
the time defined by ROMTMG.
BCR18: Burst and Bus Control Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 ROMTMG
Expansion ROM Timing. The value of ROMTMG is used to tune
the timing for all EBDATA
(BCR30) accesses to Flash/
EPROM as well as all Expansion
ROM accesses to Flash/EPROM.
tACC = ROMTMG * CLK period *
CLK_FAC - (tv_A_D) - (ts_D)
For an adapter card application,
the value used for clock period
should be 30 ns to guarantee correct interface timing at the maximum clock frequency of 33 MHz.
ROMTMG, during read operations, defines the time from when
the Am79C978 controller drives
the lower 8 or 16 bits of the Expansion Bus Address bus to
when the Am79C978 controller
latches in the data on the 8 or 16
bits of the Expansion Bus Data
inputs. ROMTMG, during write
operations, defines the time from
when the Am79C978 controller
drives the lower 8 or 16 bits of the
Expansion Bus Data to when the
EBWE and EROMCS deassert.
These bits are read accessible always; write accessible only when
the STOP bit is set. ROMTMG is
set to the value of 1001b by
H_RESET and is not affected by
S_RESET or STOP. The default
value allows using an Expansion
ROM with an access time of 250
ns in a system with a maximum
clock frequency of 33 MHz.
11
The register value specifies the
time in number of clock cycles +1
according to Table 36.
Table 36. ROMTNG Programming Values
ROMTMG (bits 15-12)
No. of Expansion Bus Cycles
1h<=n <=Fh
n+1
Note: Programming ROMTNG
with a value of 0 is not permitted.
The access time for the Expansion ROM or the EBDATA
(BCR30) device (tACC) during
read operations can be calculated by subtracting the clock to output delay for the EBUA_EBA[7:0]
outputs (tv_A_D) and by subtracting the input to clock setup time
for the EBD[7:0] inputs (ts_D)
from the time defined by ROMTMG:
156
Am79C978
NOUFLO
No Underflow on Transmit. When
the NOUFLO bit is set to 1, the
Am79C978 controller will not start
transmitting the preamble for a
packet until the Transmit Start
Point (CSR80, bits 10-11) requirement (except when XMTSP
= 3h, Full Packet has no meaning
when NOUFLO is set to 1) has
been met and the complete packet has been DMA’d into the
Am79C978 controller. The complete packet may reside in any
combination of the Bus Transmit
FIFO, the SRAM, and the MAC
Transmit FIFO as long as enough
of the packet is in the MAC Transmit FIFO to meet the Transmit
Start Point requirement. When
the NOUFLO bit is cleared to 0,
the Transmit Start Point is the
only restriction on when preamble
transmission begins for transmit
packets.
Setting the NOUFLO bit guarantees that the Am79C978 controller will never suffer transmit
underflows, because the arbiter
that controls transfers to and from
the SRAM guarantees a worst
case latency on transfers to and
from the MAC and Bus Transmit
FIFOs such that it will never underflow if the complete packet
has been DMA’d into the
Am79C978 controller before
packet transmission begins.
the system arbiter also removes
GNT at the beginning of the burst
transaction. If EXTREQ is set to
1, REQ stays asserted until the
last but one data phase of the
burst transaction is done. This
mode is useful for systems that
implement an arbitration scheme
without preemption and require
that REQ stays asserted throughout the transaction.
EXTREQ should not be set to 1
when the Am79C978 controller is
used in a PCI bus application.
The NOUFLO bit has no effect
when the Am79C978 controller is
operating in the NO-SRAM mode.
This bit is read accessible always, write accessible only when
either the STOP or the SPND bit
is set. EXTREQ is cleared by
H_RESET and is not affected by
S_RESET or STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. NOUFLO is cleared to 0 after H_RESET or S_RESET and
is unaffected by STOP.
7
10
RES
Reserved location. Written as
zero and read as undefined.
9
MEMCMD
Memory Command used for burst
read accesses to the transmit
buffer. When MEMCMD is set to
0, all burst read accesses to the
transmit buffer are of the PCI
command type Memory Read
Line (type 14). When MEMCMD
is set to 1, all burst read accesses
to the transmit buffer are of the
PCI command type Memory
Read Multiple (type 12).
This bit is read accessible always; write accessible only when
either the STOP or the SPND bit
is set. MEMCMD is cleared by
H_RESET and is not affected by
S_RESET or STOP.
8
EXTREQ
Extended Request. This bit controls the deassertion of REQ for a
burst transaction. If EXTREQ is
set to 0, REQ is deasserted at the
beginning of a burst transaction.
(The Am79C978 controller never
performs more than one burst
transaction within a single bus
mastership period.) In this mode,
the Am79C978 controller relies
on the PCI latency timer to get
enough bus bandwidth, in case
Am79C978
DWIO
Double Word I/O. When set, this
bit indicates that the Am79C978
controller is programmed for
DWord I/O (DWIO) mode. When
cleared, this bit indicates that the
Am79C978 controller is programmed for Word I/O (WIO)
mode. This bit affects the I/O Resource Offset map and it affects
the defined width of the
Am79C978 controller’s I/O resources. See the DWIO and WIO
sections for more details.
The initial value of the DWIO bit is
determined by the programming
of the EEPROM.
The value of DWIO can be altered automatically by the
Am79C978 controller. Specifically, the Am79C978 controller will
set DWIO if it detects a DWord
write access to offset 10h from
the Am79C978 controller’s I/O
base address (corresponding to
the RDP resource).
Once the DWIO bit has been set
to a 1, only a H_RESET or an EEPROM read can reset it to a 0.
(Note that the EEPROM read operation will only set DWIO to a 0 if
the appropriate bit inside of the
EEPROM is set to 0.)
157
This bit is read accessible always. DWIO is read only, write
operations have no effect. DWIO
is cleared by H_RESET and is
not affected S_RESET or by setting the STOP bit.
6
BREADE
The normal mode of operation is
when both bits 0 and 1 are set to
0 to select the Expansion ROM/
Flash. Setting bit 0 to 1 and bit 1
to 0 allows snooping of the internal MII-compatible bus to allow
External Address Detection Interface (EADI). See Table 37 for details.
Burst Read Enable. When set,
this bit enables burst mode during
memory read accesses. When
cleared, this bit prevents the device from performing bursting
during read accesses. The
Am79C978 controller can perform burst transfers when reading
the initialization block, the descriptor ring entries (when
SWSTYLE = 3), and the buffer
memory.
Table 37.
PHYSEL [1:0]
5
BWRITE
Burst Write Enable. When set,
this bit enables burst mode during
memory write accesses. When
cleared, this bit prevents the device from performing bursting
during write accesses. The
Am79C978 controller can perform burst transfers when writing
the descriptor ring entries (when
SWSTYLE = 3), and the buffer
memory.
BWRITE should be set to 1 when
the Am79C978 controller is used
in a PCI bus application to guarantee maximum performance.
Expansion ROM/Flash
01
EADI/Internal MII Snoop
10
Reserved
11
Reserved
These bits are read accessible always, these bits can only be written from the EEPROM unless a
write-enable bit, BCR2[13], is set.
PHYSEL [1:0] is cleared by
H_RESET and is not affected by
S_RESET or STOP.
2-0
158
LINBC
Reserved locations. These bits
are read accessible always; write
accessible only when either the
STOP or the SPND bit is set. After H_RESET, the value in these
bits will be 001b. The setting of
these bits have no effect on any
Am79C978 controller’s function.
LINBC is not affected by
S_RESET or STOP.
BCR19: EEPROM Control and Status
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
EEPROM Valid status bit. This bit
is read accessible only. PVALID
is read only; write operations
have no effect. A value of 1 in this
bit indicates that a PREAD operation has occurred, and that (1)
there is an EEPROM connected
to the Am79C978 controller interface pins and (2) the contents
read from the EEPROM have
passed the checksum verification
operation.
This bit is read accessible always, write accessible only when
either the STOP or the SPND bit
is set. BWRITE is cleared by
H_RESET and is not affected by
S_RESET or STOP.
4-3
Mode
00
BREADE should be set to 1 when
the Am79C978 controller is used
in a PCI bus application to guarantee maximum performance.
This bit is read accessible always; write accessible only when
either the STOP or the SPND bit
is set. BREADE is cleared by
H_RESET and is not affected by
S_RESET or STOP.
PHY Select Programming
PHYSEL[1:0] PHYSEL[1:0] bits allow for software controlled selection of different operation and test modes.
Am79C978
PVALID
A value of 0 in this bit indicates a
failure in reading the EEPROM.
The checksum for the entire 82
bytes of EEPROM is incorrect or
no EEPROM is connected to the
interface pins.
PVALID is set to 0 during
H_RESET and is unaffected by
S_RESET or the STOP bit. However, following the H_RESET operation, an automatic read of the
EEPROM will be performed. Just
as it is true for the normal PREAD
command, at the end of this automatic read operation the PVALID
bit may be set to 1. Therefore,
H_RESET will set the PVALID bit
to 0 at first, but the automatic EEPROM read operation may later
set PVALID to a 1.
If PVALID becomes 0 following
an EEPROM read operation (either automatically generated after H_RESET, or requested
through PREAD), then all EEPROM-programmable BCR locations will be reset to their
H_RESET values. The content of
the Address PROM locations,
however, will not be cleared.
If no EEPROM is present at the
EESK, EEDI, and EEDO pins,
then all attempted PREAD commands will terminate early and
PVALID will not be set. This applies to the automatic read of the
EEPROM after H_RESET, as
well as to host-initiated PREAD
commands.
14
PREAD
EEPROM Read command bit.
When this bit is set to a 1 by the
host, the PVALID bit (BCR19, bit
15) will immediately be reset to a
0, and then the Am79C978 controller will perform a read operation of 82 bytes from the
EEPROM through the interface.
The EEPROM data that is
fetched during the read will be
stored in the appropriate internal
registers
on
board
the
Am79C978 controller. Upon completion of the EEPROM read operation, the Am79C978 controller
Am79C978
will assert the PVALID bit. EEPROM contents will be indirectly
accessible to the host through
read accesses to the Address
PROM (offsets 0h through Fh)
and through read accesses to
other EEPROM programmable
registers. Note that read accesses from these locations will not
actually access the EEPROM itself, but instead will access the
Am79C978 internal copy of the
EEPROM contents. Write accesses to these locations may
change the Am79C978 register
contents, but the EEPROM locations will not be affected. EEPROM
locations
may
be
accessed
directly
through
BCR19.
At the end of the read operation,
the PREAD bit will automatically
be reset to a 0 by the Am79C978
controller and PVALID will be set,
provided that an EEPROM existed on the interface pins and that
the checksum for the entire 68
bytes of EEPROM was correct.
Note that when PREAD is set to a
1, then the Am79C978 controller
will no longer respond to any accesses directed toward it, until
the PREAD operation has completed
successfully.
The
Am79C978 controller will terminate these accesses with the assertion of DEVSEL and STOP
while TRDY is not asserted, signaling to the initiator to disconnect and retry the access at a
later time.
If a PREAD command is given to
the Am79C978 controller but no
EEPROM is attached to the interface pins, the PREAD bit will be
cleared to a 0, and the PVALID bit
will remain reset with a value of 0.
This applies to the automatic
read of the EEPROM after
H_RESET as well as to host initiated PREAD commands. EEPROM programmable locations
on board the Am79C978 controller will be set to their default values by such an aborted PREAD
159
operation. For example, if the
aborted PREAD operation immediately followed the H_RESET
operation, then the final state of
the EEPROM programmable locations will be equal to the
H_RESET programming for
those locations.
12-5
RES
Reserved locations. Written as
zeros; read as undefined.
4
EEN
EEPROM Port Enable. When this
bit is set to a 1, it causes the values of ECS, ESK, and EDI to be
driven onto the EECS, EESK,
and EEDI pins, respectively. If
EEN = 0 and no EEPROM read
function is currently active, then
EECS will be driven LOW. When
EEN = 0 and no EEPROM read
function is currently active, EESK
and EEDI pins will be driven by
the LED registers BCR5 and
BCR4, respectively. See Table
39.
If a PREAD command is given to
the Am79C978 controller and the
auto-detection pin (EESK/LED1)
indicates that no EEPROM is
present, then the EEPROM read
operation will still be attempted.
Note that at the end of the
H_RESET operation, a read of
the EEPROM will be performed
automatically. This H_RESETgenerated EEPROM read function will not proceed if the autodetection pin (EESK/LED1) indicates that no EEPROM is
present.
This bit is read accessible always; write accessible only when
either the STOP or the SPND bit
is set. PREAD is set to 0 during
H_RESET and is unaffected by
S_RESET or the STOP bit.
13
EEDET
This bit is read accessible always, write accessible only when
either the STOP or the SPND bit
is set. EEN is set to 0 by
H_RESET and is unaffected by
the S_RESET or STOP bit.
3
RES
Reserved location. Written as
zero and read as undefined.
2
ECS
EEPROM Chip Select. This bit is
used to control the value of the
EECS pin of the interface when
the EEN bit is set to 1 and the
PREAD bit is set to 0. If EEN = 1
and PREAD = 0 and ECS is set to
a 1, then the EECS pin will be
forced to a HIGH level at the rising edge of the next clock following bit programming.
EEPROM Detect. This bit indicates the sampled value of the
EESK/LED1 pin at the end of
H_RESET. This value indicates
whether or not an EEPROM is
present at the EEPROM interface. If this bit is a 1, it indicates
that an EEPROM is present. If
this bit is a 0, it indicates that an
EEPROM is not present.
This bit is read accessible only.
EEDET is read only; write operations have no effect. The value of
this bit is determined at the end of
the H_RESET operation. It is unaffected by S_RESET or the
STOP bit.
Table 38 indicates the possible
combinations of EEDET and the
existence of an EEPROM and the
resulting operations that are possible on the EEPROM interface.
160
Am79C978
If EEN = 1 and PREAD = 0 and
ECS is set to a 0, then the EECS
pin will be forced to a LOW level
at the rising edge of the next
clock following bit programming.
ECS has no effect on the output
value of the EECS pin unless the
PREAD bit is set to 0 and the
EEN bit is set to 1.
This bit is read accessible always, write accessible only when
either the STOP or the SPND bit
is set. ECS is set to 0 by
H_RESET and is not affected by
S_RESET or STOP.
Table 38. EEDET Setting
EEDET Value
(BCR19[13])
EEPROM
Connected?
0
No
0
Yes
1
No
1
Yes
Result if PREAD is Set to 1
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
Table 39.
RST Pin
Low
High
PREAD or Auto
Read in Progress
X
1
EEN
X
X
High
0
1
High
0
0
1
ESK
Interface Pin Assignment
EECS
0
Active
From ECS
Bit of BCR19
0
EEPROM Serial Clock. This bit
and the EDI/EDO bit are used to
control host access to the EEPROM. Values programmed to
this bit are placed onto the EESK
pin at the rising edge of the next
clock following bit programming,
except when the PREAD bit is set
to 1 or the EEN bit is set to 0. If
both the ESK bit and the EDI/
EDO bit values are changed during one BCR19 write operation,
while EEN = 1, then setup and
hold times of the EEDI pin value
with respect to the EESK signal
edge are not guaranteed.
ESK has no effect on the EESK
pin unless the PREAD bit is set to
0 and the EEN bit is set to 1.
This bit is read accessible always, write accessible only when
either the STOP or the SPND bit
is set. ESK is reset to 1 by
H_RESET and is not affected by
S_RESET or STOP.
0
EDI/EDO
Result of Automatic EEPROM Read
Operation Following H_RESET
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
EESK
Tri-State
Active
EEDI
Tri-State
Active
From ESK Bit of
BCR19
From EEDI Bit of
BCR19
LED1
LED0
this bit will appear on the EEDI
output of the interface, except
when the PREAD bit is set to 1 or
the EEN bit is set to 0. Data that
is read from this bit reflects the
value of the EEDO input of the interface.
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit is
set to 0 and the EEN bit is set to
1.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set. EDI/
EDO is reset to 0 by H_RESET
and is not affected by S_RESET
or STOP.
BCR20: Software Style
This register is an alias of the location CSR58. Accesses
to and from this register are equivalent to accesses to
CSR58.
Bit
Name
31-11 RES
EEPROM Data In/EEPROM
Data Out. Data that is written to
Am79C978
Description
Reserved locations. Written as
zeros and read as undefined.
161
10
APERREN
Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity error handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2 or 3 to program the Am79C978
controller to use 32-bit software
structures.
faults to 0) and is not affected by
S_RESET or STOP.
APERREN does not affect the reporting of address parity errors or
data parity errors that occur when
the Am79C978 controller is the
target of the transfer.
If SSIZE32 is set, then the software structures that are common
to the Am79C978 controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the Am79C978
controller for performing master
accesses.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32-bit address
bus during master accesses initiated by the Am79C978 controller.
This action is required, since the
16-bit software structures specified by the SSIZE32 = 0 setting
will yield only 24 bits of address
for Am79C978 controller bus
master accesses.
Read anytime; write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
9
RES
Reserved location. Written as zero; read as undefined.
8
SSIZE32
Software Size 32 bits. When set,
this bit indicates that the
Am79C978 controller utilizes 32bit software structures for the initialization block and the transmit
and receive descriptor entries.
When cleared, this bit indicates
that the Am79C978 controller utilizes 16-bit software structures for
the initialization block and the
transmit and receive descriptor
entries. In this mode, the
Am79C978 controller is backwards compatible with the
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 address pins are always driven, regardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit
(BCR18, bit 7).
7-0
The value of SSIZE32 is determined by the Am79C978 controller according to the setting of the
Software Style (SWSTYLE, bits
7-0 of this register).
This bit is always read accessible. SSIZE32 is read only; write
operations will be ignored.
SSIZE32 will be cleared after
H_RESET (since SWSTYLE de-
162
Am79C978
SWSTYLE
Software Style register. The value in this register determines the
style of register and memory resources that shall be used by the
Am79C978 controller. The Software Style selection will affect the
interpretation of a few bits within
the CSR space, the order of the
descriptor entries and the width of
the descriptors and initialization
block entries.
All Am79C978 CSR bits and all
descriptor, buffer, and initialization block entries not cited in the
Table 40 are unaffected by the
Software Style selection and are,
therefore, always fully functional
as specified in the CSR and BCR
sections.
Read/Write accessible only when
either the STOP or the SPND bit
is set. The SWSTYLE register will
contain the value 00h following
H_RESET and will be unaffected
by S_RESET or STOP.
Table 40. Software Styles
SWSTYLE
[7:0]
Style
Name
LANCE/
00h
PCnet-ISA
controller
RES
01h
02h
03h
1
1
PCnet-PCI
1
controller
RES
16-bit software
structures, non-burst or
burst access
0
PCnet-PCI
controller
All Other
Initialization Block
Entries
SSIZE32
Undefined
RES
32-bit software
structures, non-burst or
burst access
32-bit software
structures, non-burst or
burst access
Undefined
BCR22: PCI Latency Register
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8
Maximum Latency. Specifies the
maximum arbitration latency the
Am79C978 controller can sustain
without causing problems to the
network activity. The register value specifies the time in units of 1/
4 microseconds. MAX_LAT is
aliased to the PCI configuration
space register MAX_LAT (offset
3Fh). The host will use the value
in the register to determine the
setting of the Am79C978 Latency
Timer register.
MAX_LAT
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set.
MAX_LAT is set to the value of
FFh by H_RESET which results
in a default maximum latency of
63.75 microseconds. It is recommended to program the value of
18h via EEPROM. MAX_LAT is
not affected by S_RESET or
STOP.
7-0
MIN_GNT
Minimum Grant. Specifies the
minimum length of a burst period
the Am79C978 controller needs
to keep up with the network activ-
16-bit software structures,
non-burst access only
RES
32-bit software structures,
non-burst access only
32-bit software structures,
non-burst or burst access
Undefined
ity. The length of the burst period
is calculated assuming a clock
rate of 33 MHz. The register value specifies the time in units of 1/
4 ms. MIN_GNT is aliased to the
PCI Configuration Space register
MIN_GNT (offset 3Eh). The host
will use the value in the register to
determine the setting of the
Am79C978 Latency Timer register.
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Descriptor Ring Entries
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set.
MIN_GNT is set to the value of
06h by H_RESET which results
in a default minimum grant of
1.5 ms, which is the time it takes
to Am79C978 controller to read/
write half of the FIFO. (16 DWord
transfers in burst mode with one
extra wait state per data phase
inserted by the target.) Note that
the default is only a typical value.
It also does not take into account
any descriptor accesses. It is recommended to program the value
of 18h via EEPROM. MIN_GNT
is not affected by S_RESET or
STOP.
BCR23: PCI Subsystem Vendor ID Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Am79C978
Name
Description
163
31-0
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SVID
Subsystem Vendor ID. SVID is
used together with SID (BCR24,
bits 15-0) to uniquely identify the
add-in board or subsystem the
Am79C978 controller is used in.
Subsystem Vendor IDs can be
obtained from the PCI SIG. A value of 0 (the default) indicates that
the Am79C978 controller does
not support subsystem identification. SVID is aliased to the PCI
Configuration Space register
Subsystem Vendor ID (offset
2Ch).
Note: Bits 7-0 in this register are programmable
through the EEPROM.
31-8
7-0
This bit is always read accessible. SVID is read only. Write operations are ignored. SVID is
cleared to 0 by H_RESET and is
not affected by S_RESET or by
setting the STOP bit.
RES
SRAM_SIZE SRAM Size. Specifies the upper
8 bits of the 16-bit total size of the
SRAM buffer. Each bit in
SRAM_SIZE accounts for a 512byte page. The starting address
for the lower 8 bits is assumed to
be 00h and the ending address
for the lower is assumed to be
FFh. Therefore, the maximum address range is the starting address of 0000h to ending address
of ((SRAM_SIZE+1) * 256 words)
or 17FFh. An SRAM_SIZE value
of all zeros specifies that no
SRAM will be used and the internal FIFOs will be joined into a
contiguous FIFO similar to the
PCnet-PCI II controller.
Note: The minimum allowed
number of pages is eight for normal network operation. The
Am79C978 controller will not operate correctly with less than the
eight pages of memory. When
the minimum number of pages is
used, these pages must be allocated four each for transmit and
receive.
BCR24: PCI Subsystem ID Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Subsystem ID. SID is used together with SVID (BCR23, bits
15-0) to uniquely identify the addin board or subsystem the
Am79C978 controller is used in.
The value of SID is up to the system vendor. A value of 0 (the default)
indicates
that
the
Am79C978 controller does not
support subsystem identification.
SID is aliased to the PCI configuration space register Subsystem
ID (offset 2Eh).
SID
This bit is always read accessible. SID is read only. Write operations are ignored. SID is cleared
to 0 by H_RESET and is not affected by S_RESET or by setting
the STOP bit.
BCR25: SRAM Size Register
Bit
164
Name
Description
Reserved locations. Written as
zeros and read as undefined.
CAUTION:
Programming
SRAM_BND and SRAM_SIZE
to the same value will cause
data corruption except in the
case where SRAM_SIZE is 0.
This bit is always read accessible; write accessible only when
the STOP bit is set. SRAM_SIZE
is set to 000000b during
H_RESET and is unaffected by
S_RESET or STOP.
BCR26: SRAM Boundary Register
Bit
Name
Description
Note: Bits 7-0 in this register are programmable
through the EEPROM.
31-8
7-0
Am79C978
RES
Reserved locations. Written as
zeros and read as undefined.
SRAM_BND SRAM Boundary. Specifies the
upper 8 bits of the 16-bit address
boundary where the receive buffer
begins in the SRAM. The transmit
buffer in the SRAM begins at address 0 and ends at the address
located just before the address
specified by SRAM_BND. Therefore, the receive buffer always begins on a 512 byte boundary. The
lower bits are assumed to be zeros. SRAM_BND has no effect in
the Low Latency Receive mode.
14
LOLATRX
Note: The minimum allowed
number of pages is four. The
Am79C978 controller will not operate correctly with less than four
pages of memory per queue. See
Table 41 for SRAM_BND programming details.
Table 41.
SRAM_BND Programming
SRAM Addresses
Minimum SRAM_BND
Address
Maximum SRAM_BND Address
SRAM_BND [7:0]
04h
13h
When the LOLATRX bit is set to
0, the Am79C978 controller will
return to a normal receive configuration. The runt packet accept
bit (RPA, CSR124, bit 3) must be
set when LOLATRX is set.
CAUTION:
Programming
SRAM_BND and SRAM_SIZE
to the same value will cause
data corruption except in the
case where SRAM SIZE is 0.
CAUTION: To provide data integrity when switching into
and out of the low latency
mode, DO NOT SET the
FASTSPNDE (CSR7, bit 15) bit
when setting the SPND bit. Receive frames WILL be overwritten
and
the
Am79C978
controller may give erratic behavior when it is enable again.
The minimum allowed number
of pages
is four.
The
Am79C978 controller will not
operate correctly in the LOLATRX mode with less than four
pages of memory.
Read accessible always; write
accessible only when the STOP
bit is set. SRAM_BND is set to
00000000b during H_RESET
and is unaffected by S_RESET or
STOP.
BCR27: SRAM Interface Control Register
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
Reserved. Reserved for manufacturing tests. Written as zero
and read as undefined.
PTR TST
Read/Write accessible only when
the STOP bit is set. LOLATRX is
cleared to 0 after H_RESET or
S_RESET and is unaffected by
STOP.
Note: Use of this bit will cause
data corruption and erroneous
operation.
This bit is always read/write accessible. PTR_TST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
Low Latency Receive. When the
LOLATRX bit is set to 1, the
Am79C978 controller will switch
to an architecture applicable to
cut-through
switches.
The
Am79C978 controller will assert a
receive frame DMA after only 16
bytes of the current receive frame
has been received regardless of
where the RCVFW (CSR80, bits
13-12) are set. The watermark is
a fixed value and cannot be
changed. The receive FIFOs will
be in NO_SRAM mode while all
transmit traffic is buffered through
the SRAM. This bit is only valid
and the low latency receive only
enabled when the SRAM_SIZE
(BCR25, bits 7-0) bits are non-zero. SRAM_BND (BCR26, bits 70) has no meaning when the
Am79C978 controller is in the
Low Latency mode. See the section on SRAM Configuration for
more details.
13-6
Am79C978
RES
Reserved locations. Written as
zeros and read as undefined.
165
5-3
EBCS
Expansion Bus Clock Source.
These bits are used to select the
source of the fundamental clock
to drive the SRAM and Expansion
ROM access cycles. Table 42
shows the selected clock source
for the various values of EBCS.
Note that the actual frequency
that the Expansion Bus access
cycles run at is a function of both
the EBCS and CLK_FAC
(BCR27, bits 2-0) bit field settings. When EBCS is set to either
the PCI clock or the Time Base
clock, no external clock source is
required as the clocks are routed
internally and the EBCLK pin
should be pulled to VDD through
a resistor.
clock data, corruption will result.
CAUTION: The Time Base
Clock will not support 100
Mbps operation and should
only be selected in 10 Mbpsonly configurations.
CAUTION: The external clock
source used to drive the
EBCLK pin must be a continuous clock source at all times.
2-0
CLK_FAC
Table 42. EBCS Values
EBCS
000
001
010
011
1XX
Expansion Bus Clock Source
CLK pin (PCI Clock)
Time Base Clock
EBCLK pin
Reserved
Reserved
Table 43. CLK_FAC Values
Read accessible always; write
accessible only when the STOP
bit is set. EBCS is set to 000b
(PCI clock selected) during
H_RESET and is unaffected by
S_RESET or the STOP bit.
Note: The clock frequency driving the Expansion Bus access cycles that results from the settings
of the EBCS and CLK FAC bits
must not exceed 33 MHz at any
time. When EBCS is set to either
the PCI clock or the Time Base
clock, no external clock source is
required because the clocks are
routed internally and the EBCLK
pin should be pulled to VDD
through a resistor.
CLK_FAC
000
001
010
011
1XX
Clock Factor
1
1/2 (divide by 2)
Reserved
1/4 (divide by 4)
Reserved
Read accessible always; write
accessible only when the STOP
bit is set. CLK_FAC is set to 000b
during H_RESET and is unaffected by S_RESET or STOP.
BCR28: Expansion Bus Port Address Lower (Used
for Flash/EPROM and SRAM Accesses)
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
Expansion Port Address Lower.
This address is used to provide
addresses for the Flash and
SRAM port accesses.
CAUTION: Care should be exercised when choosing the PCI
clock pin because of the nature
of the PCI clock signal. The PCI
specification states that the
PCI clock can be stopped. If
that can occur while it is being
used for the Expansion Bus
166
Clock Factor. These bits are used
to select whether the clock selected by EBCS is used directly or if it
is divided down to give a slower
clock for running the Expansion
Bus access cycles. The possible
factors are given in Table 43.
Am79C978
EPADDRL
SRAM accesses are started
when a read or write is performed
on BCR30 and the FLASH (BCR
29, bit 15) is set to 0. During
SRAM accesses only bits in the
EPADDRL are valid. Since all
SRAM accesses are word oriented only, EPADDRL[0] is the least
significant word address bit. On
any byte write accesses to the
SRAM, the user will have to follow
the
read-modify-write
scheme. On any byte read accesses to the SRAM, the user will
have to chose which byte is
needed from the complete word
returned in BCR30.
Flash accesses are started when
a read or write is performed on
BCR30 and the FLASH (BCR 29,
bit 15) is set to 1. During Flash
accesses all bits in EPADDR are
valid.
Read accessible always; write
accessible only when the STOP
is set or when SRAM SIZE
(BCR25, bits 7-0) is 0. EPADDRL
is undefined after H_RESET and
is unaffected by S_RESET or
STOP.
Port Lower Address (EPADDRL)
will roll over to 0000h. When the
LAAINC bit is set to 0, the Expansion Port Lower Address will not
be affected in any way after an
access to EBDATA (BCR30) and
must be programmed.
This bit is always read accessible; write accessible only when
the STOP bit is set. LAINC is 0 after H_RESET and is unaffected
by S_RESET or the STOP bit.
13-4
RES
Reserved locations. Written as
zeros and read as undefined.
3-0
EPADDRU
Expansion Port Address Upper.
This upper portion of the Expansion Bus address is used to provide addresses for Flash/EPROM
port accesses.
This bit is always read accessible; write accessible only when
the STOP bit is set or when
SRAM SIZE (BCR25, bits 7-0) is
0. EPADDRU is undefined after
H_RESET and is unaffected by
S_RESET or the STOP bit.
BCR29: Expansion Port Address Upper (Used for
Flash/EPROM Accesses)
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
Flash Access. When the FLASH
bit is set to 1, the Expansion Bus
access will be a Flash cycle.
When FLASH is set to 0, the Expansion Bus access will be a
SRAM cycle. For a complete description, see the section on Expansion Bus Accesses. This bit is
only applicable to reads or writes
to EBDATA (BCR30). It does not
affect Expansion ROM accesses
from the PCI system bus.
14
FLASH
LAAINC
BCR30: Expansion Bus Data Port Register
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
This bit is always read accessible; write accessible only when
the STOP bit is set. FLASH is 0
after H_RESET and is unaffected
by S_RESET or the STOP bit.
Expansion Bus Data Port. EBDATA is the data port for operations
on the Expansion Port accesses
involving SRAM and Flash accesses. The type of access is set
by the FLASH bit (BCR 29, bit
15). When the FLASH bit is set to
1, the Expansion Bus access will
follow the Flash access timing.
When the FLASH bit is set to 0,
the Expansion Bus access will
follow the SRAM access timing.
Lower Address Auto Increment.
When the LAAINC bit is set to 1,
the Expansion Port Lower Address will automatically increment
by one after a read or write access to EBDATA (BCR30). When
EBADDRL reaches FFFFh and
LAAINC is set to 1, the Expansion
Note: It is important to set the
FLASH bit and load Expansion
Port Address EPADDR (BCR28,
BCR29) with the required address before attempting read or
write to the Expansion Bus data
port. The Flash and SRAM accesses use different address
Am79C978
EBDATA
167
phases. Incorrect configuration
will result in a possible corruption
of data.
The STVAL value is interpreted
as an unsigned number with a
resolution of 256 Time Base
Clock periods. For instance, a
value of 122 ms would be programmed with a value of 9531
(253Bh) if the Time Base Clock is
running at 20 MHz. A value of 0 is
undefined and will result in erratic
behavior.
Flash read cycles are performed
when BCR30 is read and the
FLASH bit (BCR29, bit 15) is set
to 1. Upon completion of the read
cycle, the 8-bit result for Flash access is stored in EBDATA[7:0],
EBDATA[15:8] is undefined.
Flash write cycles are performed
when BCR30 is written and the
FLASH bit (BCR29, bit 15) is set
to 1. EBDATA[7:0] only is valid
for write cycles.
SRAM read cycles are performed
when BCR30 is read and the
FLASH bit (BCR29, bit 15) is set
to 0. Upon completion of the read
cycle, the 16-bit result for SRAM
access is stored in EBDATA.
Write cycles to the SRAM are invoked when BCR30 is written
and the FLASH bit (BCR29, bit
15) is set to 0. Byte writes to the
SRAM must use a read-modifywrite scheme since the word is always valid for SRAM write or
read accesses.
Read and write accessible always. STVAL is set to FFFFh after H_RESET and is unaffected
by S_RESET and the STOP bit.
BCR32: PHY Control and Status Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
Reserved for manufacturing
tests. Written as 0 and read as
undefined.
ANTST
Note: Use of this bit will cause
data corruption and erroneous
operation.
This bit is read and write accessible only when the STOP is set or
when SRAM SIZE (BCR25, bits
7-0) is 0. EBDATA is undefined
after H_RESET and is unaffected
by S_RESET and the STOP bit.
BCR31: Software Timer Register
Bit
Name
14
Reserved locations. Written as
zeros and read as undefined.
15-0
Software Timer Value. STVAL
controls the maximum time for
the Software Timer to count before generating the STINT
(CSR7, bit 11) interrupt. The Software Timer is a free-running timer
that is started upon the first write
to STVAL. After the first write, the
Software Timer will continually
count and set the STINT interrupt
at the STVAL period.
168
STVAL
This bit is always read/write accessible. ANTST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
Description
31-16 RES
Description
Am79C978
MIIPD
MII PHY Detect (is used for manufacturing tests). MIIPD reflects
the quiescent state of the MDIO
pin. MIIPD is continuously updated whenever there is no management operation in progress on the
MII interface. When a management operation begins on the interface, the state of MIIPD is
preserved until the operation
ends, when the quiescent state is
again monitored and continuously updates the MIIPD bit. When
the MDIO pin is at a quiescent
LOW state, MIIPD is cleared to 0.
When the MDIO pin is at a quiescent HIGH state, MIIPD is set to
1. MIIPD is used by the automatic
port selection logic to select the
MII port. When the Auto Select bit
(ASEL, BCR2, bit 1) is a 1 and the
MIIPD bit is a 1, the MII port is selected. Any transition on the MIIPD bit will set the MIIPDTI bit in
CSR7, bit 3.
10-8
Read accessible always. MIIPD
is read only. Write operations are
ignored and should not be performed.
13-12 FMDC
Fast Management Data Clock (is
used for manufacturing tests).
When FMDC is set to 1h, the MII
Management Data Clock will run
at 5 MHz max. The Management
Data Clock will no longer be IEEE
802.3u-compliant and setting this
bit should be used with care. The
accompanying external PHY
must also be able to accept management frames at the new clock
rate. When FMDC is set to 0h, the
MII Management Data Clock will
run at 2.5 MHz max and will be
fully compliant to IEEE 802.3u
standards. See Table 44.
APDW
Table 45. APDW Values
APDW
000
001
010
011
100
101
Auto-Poll Dwell Time
Continuous (26µs @ 2.5 MHz)
Every 128 MDC cycles (103µs @ 2.5 MHz)
Every 256 MDC cycles (206µs @ 2.5 MHz)
Every 512 MDC cycles (410 µs @ 2.5 MHz)
Every 1024 MDC cycles (819 µs @ 2.5 MHz)
Every 2048 MDC cycles (1640 µs @ 2.5 MHz)
110-111 Reserved
This bit is always read/write accessible. APDW is set to 100h after H_RESET and is unaffected
by S_RESET and the STOP bit.
7
DANAS
Table 44. FMDC Values
FMDC
00
01
10
11
Fast Management Data Clock
2.5 MHz max
5 MHz max
Reserved
Reserved
This bit is always read/write accessible. FMDC is set to 0 during
H_RESET, and is unaffected by
S_RESET and the STOP bit
11
APEP
Auto-Poll PHY. When APEP is
set to 1 the Am79C978 controller
will poll the status register in the
PHY. This feature allows the software driver or upper layers to see
any changes in the status of the
PHY. An interrupt when enabled
is generated when the contents of
the new status is different from
the previous status.
Auto-Poll Dwell Time. APDW determines the dwell time between
PHY
Management
Frame
accesses when Auto-Poll is
turned on. See Table 45.
Disable Auto-Negotiation Auto
Setup. When DANAS is set, the
Am79C978 controller after a
H_RESET or S_RESET will remain dormant and not automatically startup the Auto-Negotiation
section or the enhanced automatic port selection section. Instead,
the Am79C978 controller will wait
for the software driver to setup
the Auto-Negotiation portions of
the device. The PHY Address
and Data programming in BCR33
and BCR34 is still valid. The
Am79C978 controller will not
generate
any
management
frames unless Auto-Poll is enabled.
This bit is always read/write accessible. DANAS is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
6
This bit is always read/write accessible. APEP is set to 0 during
H_RESET and is unaffected by
S_RESET and the STOP bit.
Am79C978
XPHYRST
PHY Reset. When XPHYRST is
set, the Am79C978 controller after an H_RESET or S_RESET
will issue management frames
that will reset the PHY. This bit is
needed when there is no way to
guarantee the state of the external PHY. This bit must be reprogrammed after every H_RESET.
169
This bit is always read/write accessible. XPHYRST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYRST is only valid when the
internal Network Port Manager is
scanning for a network port.
5
XPHYANE
PHY Auto-Negotiation Enable.
This bit will force the PHY into enabling Auto-Negotiation. When
set to 0 the Am79C978 controller
will send a management frame
disabling Auto-Negotiation.
This bit is always read/write accessible. XPHYANE is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYANE is only valid when the
internal Network Port Manager is
scanning for a network port.
4
XPHYFD
XPHYSP
0
RES
Reserved location. Written as
zero and read as undefined.
BCR33: PHY Address Register
Bit
Name
Description
Reserved locations. Written as
zeros and read as undefined.
15
SHADOW
If the user wishes to update the
contents of the BCR33 shadow
register, setting the MSB of the
value written into BCR33 (bit 15)
will enable the contents to be simultaneously written to BCR33
shadow.
14
MII_SEL
MII selected. This bit indicates
whether the internal PHY is selected.
PHY Speed. When set, this bit
will force the PHY into 100 Mbps
mode when Auto-Negotiation is
not enabled.
13
AUTONEG_COMPLETE
This bit is always read/write accessible. XPHYSP is set to 0 by
H_RESET, and is unaffected by
S_RESET and the STOP bit.
12
11
PHY Full Duplex. When set, this
bit will force the PHY into full duplex when Auto-Negotiation is not
enabled.
2
RES
Reserved location. Written as
zero and read as undefined.
1
MIIILP
Media Independent Interface Internal Loopback. When set, this
bit will cause the internal portion
of the MII data port to loopback
on itself. The interface is mapped
in the following way. The
TXD[3:0] nibble data path is
looped back onto the RXD[3:0]
nibble data path. TX_CLK is
looped back as RX_CLK. TX_EN
is looped back as RX_DV. CRS is
correctly OR’d with TX_EN and
RX_DV and always encompass-
170
This bit is always read/write accessible. MIIILP is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
31-16 RES
This bit is always read/write accessible. XPHYFD is set to 0 by
H_RESET, and is unaffected by
S_RESET and the STOP bit.
3
es the transmit frame. TX_ER is
looped back as RX_ER. However, TX_ER will not get asserted
by the Am79C978 controller to
signal an error. The TX_ER function is reserved for future use.
Internal Auto-Negotiation complete. Valid for internal PHY only.
LINK STATUS
Link Status. This bit is a valid link
status indication.
FULL_DUPLEX
Full Duplex. This bit indicates that
the MAC is configured for FullDuplex operation.
10
SPEED_SEL Speed Selected. This bit indicates if High or Low speed has
been selected by MAC.
9-5
PHYAD
Am79C978
Management Frame PHY Address. PHYAD contains the 5-bit
PHY Address field that is used in
the management frame that gets
clocked out via the MII management port pins (MDC and MDIO)
whenever a read or write transaction occurs to BCR34. The PHY
address 1Fh is not valid.
ten to MIIMD is the value used in
the data field of the management
write frame.
The Network Port Manager copies the PHYAD after the
Am79C978 controller reads the
EEPROM and uses it to communicate with the external PHY. The
PHY address must be programmed into the EEPROM prior
to starting the Am79C978 controller.
These bits are always read/write
accessible. MIIMD is undefined
after H_RESET and is unaffected
by S_RESET and the STOP bit.
These bits are always read/write
accessible. PHYAD is undefined
after H_RESET and is unaffected
by S_RESET and the STOP bit.
4-0
REGAD
BCR35: PCI Vendor ID Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Reserved locations. Written as
zeros and read as undefined.
15-0
Vendor ID. The PCI Vendor ID
register is a 16-bit register that
identifies the manufacturer of the
Am79C978 controller. AMD’s
Vendor ID is 1022h. Note that this
Vendor ID is not the same as the
Manufacturer ID in CSR88 and
CSR89. The Vendor ID is assigned by the PCI Special Interest Group.
Management Frame Register Address. REGAD contains the 5-bit
Register Address field that is
used in the management frame
that gets clocked out via the internal MII management interface
whenever a read or write transaction occurs to BCR34.
BCR34: PHY Management Data Register
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
MII Management Data. MIIMD is
the data port for operations on the
MII management interface (MDIO
and MDC). The Am79C978 controller builds management frames
using the PHYAD and REGAD
values from BCR33. The operation code used in each frame is
based upon whether a read or
write operation has been performed to BCR34. Read cycles
on the MII management interface
are invoked when BCR34 is read.
Upon completion of the read cycle, the 16-bit result of the read
operation is stored in MIIMD.
Write cycles on the MII management interface are invoked when
BCR34 is written. The value writ-
MIIMD
Description
31-16 RES
These bits are always read/write
accessible. REGAD is undefined
after H_RESET and is unaffected
by S_RESET and the STOP bit.
Bit
Name
Am79C978
VID
The Vendor ID is not normally
programmable,
but
the
Am79C978 controller allows this
due to legacy operating systems
that do not look at the PCI Subsystem Vendor ID and the Vendor ID to uniquely identify the
add-in board or subsystem that
the Am79C978 controller is used
in.
Note: If the operating system
or the network operating system supports PCI Subsystem
Vendor ID and Subsystem ID,
use those to identify the add-in
board or subsystem and program the VID with the default
value of 1022h.
VID is aliased to the PCI configuration space register Vendor ID
(offset 00h).
Read accessible always. VID is
read only. Write operations are
ignored. VID is set to 1022h by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
171
BCR36: PCI Power Management Capabilities (PMC)
Alias Register
BCR38: PCI DATA Register 1 (DATA1) Alias
Register
Note: This register is an alias of the PMC register
located at offset 42h of the PCI Configuration Space.
Since PMC register is read only, BCR36 provides a
means of programming it through the EEPROM. The
contents of this register are copied into the PMC register. For the definition of the bits in this register, refer to
the PMC register definition. Bits 15-0 in this register are
programmable through the EEPROM. Read accessible
always. Read only. Cleared by H_RESET and is not affected by S_RESET or setting the STOP bit.
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PMCSR register.
Since these two are read only, BCR38 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corresponding fields pointed with the DATA_SEL field set to
one. Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
15-10 RES
BCR37: PCI DATA Register 0 (DATA0) Alias
Register
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PMCSR register.
Since these two are read only, BCR37 provides a
means of programming them indirectly. The contents of
this register are copied into the corresponding fields
pointed with the DATA_SEL field set to zero. Bits 15-0
in this register are programmable through the EEPROM.
Bit
Name
15-10 RES
9-8
9-8
These bits are always read accessible. D1_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
Reserved locations. Written as
zeros and read as undefined.
7-0
DATA1
DATA0
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
This bit is always read accessible. DATA0 is read only. Cleared
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
BCR39: PCI DATA Register 2 (DATA2) Alias
Register
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PMCSR register.
Since these two are read only, BCR39 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corresponding fields pointed with the DATA_SEL field set to
two. Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
15-10 RES
172
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
These bits are always read accessible. DATA1 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
Read
accessible
always.
D0_SCALE is read only. Cleared
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
7-0
Reserved locations. Written as
zeros and read as undefined.
D1_SCALE These bits correspond to the
DATA_SCALE field of the PMCSR (offset Register 44 of the PCI
configuration space, bits 14-13).
Refer to the description of
DATA_SCALE for the meaning of
this field.
Description
D0_SCALE These bits correspond to the
DATA_SCALE field of the
PMCSR (offset Register 44 of the
PCI configuration space, bits 1413). Refer to the description of
DATA_SCALE for the meaning of
this field.
Description
Am79C978
Description
Reserved locations. Written as
zeros and read as undefined.
9-8
D2_SCALE These bits correspond to the
DATA_SCALE field of the
PMCSR (offset Register 44 of the
PCI configuration space, bits 1413). Refer to the description of
DATA_SCALE for the meaning of
this field.
7-0
DATA3
These bits are always read accessible. DATA3 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
These bits are always read accessible. D2_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
7-0
DATA2
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
These bits are always read accessible. DATA2 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
BCR40: PCI DATA Register 3 (DATA3) Alias
Register
Bit
Name
15-10 RES
9-8
BCR41: PCI DATA Register 4 (DATA4) Alias
Register
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PCMCR register.
Since these two are read only, BCR41 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corresponding fields pointed with the DATA_SEL field set to
four. Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
15-10 RES
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PCMCR register.
Since these two are read only, BCR40 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corresponding fields pointed with the DATA_SEL field set to
three. Bits 15-0 in this register are programmable
through the EEPROM.
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
9-8
Description
Reserved locations. Written as
zeros and read as undefined.
D4_SCALE These bits correspond to the
DATA_SCALE field of the PMCSR (offset register 44 of the PCI
configuration space, bits 14-13).
Refer to the description of
DATA_SCALE for the meaning of
this field.
Description
Read
accessible
always.
D4_SCALE is read only. Cleared
by H_RESET and is not affected
by S_RESET or setting the STOP
bit
Reserved locations. Written as
zeros and read as undefined.
D3_SCALE These bits correspond to the
DATA_SCALE field of the PMCSR (offset Register 44 of the PCI
configuration space, bits 14-13).
Refer to the description of
DATA_SCALE for the meaning of
this field.
7-0
These bits are always read accessible. D3_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
Am79C978
DATA4
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
Read accessible always. DATA4
is read only. Cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
173
BCR42: PCI DATA Register 5 (DATA5) Alias
Register
9-8
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PCMCR register.
Since these two are read only, BCR42 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corresponding fields pointed with the DATA_SEL field set to
five. Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
15-10 RES
9-8
These bits are always read accessible. D6_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit
Description
Reserved locations. Written as
zeros and read as undefined.
7-0
DATA5
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
These bits are always read accessible. DATA5 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
BCR44: PCI DATA Register 7 (DATA7) Alias
Register
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PCMCR register.
Since these two are read only, BCR44 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corresponding fields pointed with the DATA_SEL field set to
seven. Bits 15-0 in this register are programmable
through the EEPROM.
Bit
15-10 RES
174
Name
15-10 RES
Note: This register is an alias of the DATA register and
also of the DATA_SCALE field of the PCMCR register.
Since these two are read only, BCR43 provides a
means of programming them through the EEPROM.
The contents of this register are copied into the corresponding fields pointed with the DATA_SEL field set to
six. Bits 15-0 in this register are programmable through
the EEPROM.
Name
Description
Reserved locations. Written as
zeros and read as undefined.
D7_SCALE These bits correspond to the
DATA_SCALE field of the PMCSR (offset Register 44 of the PCI
configuration space, bits 14-13).
Refer to the description of
DATA_SCALE for the meaning of
this field.
These bits are always read accessible. D7_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
Description
Reserved locations. Written as
zeros and read as undefined.
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
These bits are always read accessible. DATA6 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
9-8
BCR43: PCI DATA Register 6 (DATA6) Alias
Register
Bit
DATA6
D5_SCALE These bits correspond to the
DATA_SCALE field of the PMCSR (offset Register 44 of the PCI
configuration space, bits 14-13).
Refer to the description of
DATA_SCALE for the meaning of
this field.
These bits are always read accessible. D5_SCALE is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit
7-0
D6_SCALE These bits correspond to the
DATA_SCALE field of the PMCSR (offset Register 44 of the PCI
configuration space, bits 14-13).
Refer to the description of
DATA_SCALE for the meaning of
this field.
7-0
Am79C978
DATA7
These bits correspond to the PCI
DATA register (offset register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.
unaffected by S_RESET and the
STOP bit.
6-0 PMR_ADDR
These bits are always read accessible. DATA7 is read only.
Cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
These bits are read and write accessible always. PMR_ADDR is
reset to 0 after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
BCR45: OnNow Pattern Matching Register 1
Note: This register is used to control and indirectly access the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the address of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to whatever PMR word is addressed by bits 6:0 of BCR45.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8
Pattern Match RAM Byte 0. This
byte is written into or read from
Byte 0 of the Pattern Match RAM.
PMR_B0
BCR46: OnNow Pattern Matching Register 2
Note: This register is used to control and indirectly access the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the address of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to whatever PMR word is addressed by bits 6:0 of BCR45.
Bit
Name
Pattern Match Mode. Writing a 1
to this bit will enable Pattern
Match Mode and should only be
done after the Pattern Match
RAM has been programmed.
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8
Pattern Match RAM Byte 2. This
byte is written into or read from
Byte 2 of the Pattern Match RAM.
PMR_B2
These bits are read and write accessible always. PMR_B0 is undefined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
7 PMAT_MODE
Pattern Match Ram Address.
These bits are the Pattern Match
Ram address to be written to or
read from.
These bits are read and write accessible always. PMR_B2 is undefined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
7-0
These bits are read and write accessible always. PMAT_MODE is
reset to 0 after H_RESET, and is
Am79C978
PMR_B1
Pattern Match RAM Byte 1. This
byte is written into or read from
Byte 1 of Pattern Match RAM.
These bits are read and write accessible always. PMR_B1 is un-
175
defined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
BCR47: OnNow Pattern Matching Register 3
Note: This register is used to control and indirectly access the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the address of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to whatever PMR word is addressed by bits 6:0 of BCR45.
BCR48: LED4 Status
This register defines the functionality of LED4. LED4
will default to indicating the selected SPEED with Pulse
stretching enabled (default = 0082h).
BCR48 controls the function(s) that the LED4 pin displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the
logical OR of the enabled functions.
Note: When LEDPE (BCR2, bit 12) is set to 1, programming of the LED2 Status register is enabled.
When LEDPE is cleared to 0, programming of the
LED2 register is disabled. Writes to those registers will
be ignored.
Note: Bits 15-0 in this register are programmable
through the EEPROM PREAD operation.
Bit
Name
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
This bit indicates the current
(non-stretched) value of the LED
output pin. A value of 1 in this bit
indicates that the OR of the enabled signals is true.
LEDOUT
When PMAT_MODE is 0, the contents of the word addressed by bits 6:0 of BCR45 can be read by reading
BCR45-47 in any order.
Bit
Name
Reserved locations. Written as
zeros and read as undefined.
15-8
Pattern Match RAM Byte 4. This
byte is written into or read from
Byte 4 of Pattern Match RAM.
PMR_B4
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of the LED register
(bits 8 and 6-0).
Description
31-16 RES
Read accessible always. This bit
is read only; writes have no effect. LEDOUT is unaffected by
H_RESET, S_RESET, or STOP.
14
These bits are read and write accessible always. PMR_B4 is undefined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
7-0
PMR_B3
Pattern Match RAM Byte 3. This
byte is written into or read from
Byte 3 of Pattern Match RAM.
These bits are read and write accessible always. PMR_B3 is undefined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
176
Description
Am79C978
LEDPOL
LED Polarity. When this bit has
the value 0, then the LED pin will
be driven to a LOW level whenever the OR of the enabled signals
is true, and the LED pin will be
disabled and allowed to float high
whenever the OR of the enabled
signals is false (i.e., the LED output will be an Open Drain output
and the output value will be the
inverse of the LEDOUT status
bit).
When this bit has the value 1,
then the LED pin will be driven to
a HIGH level whenever the OR of
the enabled signals is true, and
the LED pin will be driven to a
LOW level whenever the OR of
the enabled signals is false (i.e.,
the LED output will be a Totem
Pole output and the output value
will be the same polarity as the
LEDOUT status bit).
8
FDLSE
The setting of this bit will not effect the polarity of the LEDOUT
bit for this register.
This bit is always read/write accessible. LEDPOL is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
13
LEDDIS
LED Disable. This bit is used to
disable the LED output. When
LEDDIS has the value 1, then the
LED output will always be disabled. When LEDDIS has the value 0, then the LED output value
will be governed by the LEDOUT
and LEDPOL values.
This bit is always read/write accessible. FDLSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
7
PSE
This bit is always read/write accessible. LEDDIS is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
12
100E
100 Mbps Enable. When this bit
is set to 1, a value of 1 is passed
to the LEDOUT bit in this register
when the Am79C978 controller is
operating in 100 Mbps mode.
Reserved locations. Written and
read as zeros.
9
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when Magic Packet
frame mode is enabled and a
Magic Packet frame is detected
on the network.
MPSE
Pulse Stretcher Enable. When
this bit is set, the LED illumination
time is extended for each new occurrence of the enabled function
for this LED output. A value of 0
disables the pulse stretcher.
This bit is always read/write accessible. PSE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
6
LNKSE
This bit is always read/write accessible. 100E is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
11-10 RES
Full-Duplex Link Status Enable.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LEDOUT signal when the Am79C978
controller is functioning in a Link
Pass state and full-duplex operation is enabled. When the
Am79C978 controller is not functioning in a Link Pass state with
full-duplex operation being enabled, a value of 0 is passed to
the LEDOUT signal.
Link Status Enable. When this bit
is set, a value of 1 will be passed
to the LEDOUT bit in this register
in Link Pass state.
This bit is always read/write accessible. LNKSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
5
This bit is always read/write accessible. MPSE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Am79C978
RCVME
Receive Match Status Enable.
When this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive activity on the network that has
passed the address match function for this node. All address
matching modes are included:
physical, logical filtering, broadcast, and promiscuous.
This bit is always read/write accessible. RCVME is cleared by
H_RESET and is not affected by
177
S_RESET or setting the STOP
bit.
4
XMTE
Transmit Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
This bit is always read/write accessible. XMTE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
3
2
POWER
RCVE
Power. When this bit is set to 1,
the device is operating in HIGH
power mode.
0
SPEED
COLE
This register defines which PHY will be able to send
and receive data over the MII interface. Bits 15:8 are
updated whenever the EEPROM is read, and bits 6:0
are updated only if bit 7 is cleared. The bits are defined
as follows:
Bit
Name
15
PC_NET
14-10 RES
9-8
Speed. When this bit is set to 1,
the device is operating in HIGH
speed mode.
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network.
This bit is always read/write accessible. COLE is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Description
PCnet mode. This bit must always be set.
Reserved locations. These bits
must be written as zeros.
PHY_SEL_Default
PHY Select Default. These bits
store the desired default PHY.
These bits have no effect on the
operation of the device and are
provided only as a storage location.
Receive Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive activity on the network.
This bit is always read/write accessible. RCVE is set to 1 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
1
BCR49: PHY Select
7
PHY_SEL_Lock
PHY Select Lock. Setting this bit
prevents the PHY_SEL bits from
being overwritten by subsequent
soft resets. The user may write
this bit at any time. It is cleared
during Power-On Reset.
6-2
RES
Reserved. Must be written as
zero.
1-0
PHY_SEL
PHY Select. These bits define the
active PHY as follows:
00
10BASE-T PHY
01
HomePNA PHY
10
External PHY
11
Reserved/Undefined
BCR50-BCR55: Reserved Locations
These registers must be 00h.
178
Am79C978
1 Mbps HomePNA PHY Internal Registers
BCR33, and BCR34) in the integrated PCnet controller
to control and communicate to the HomePNA PHY via
the MDC and MDIO signals.
The registers of the HomePNA PHY are accessible via
the internal MII interface. This interface uses the MII
Control, Address, and Data Registers (BCR32,
See Table 46 through Table 63.
HPR0: HomePNA PHY MII Control (Register 0)
Table 46.
Bits
HPR0: HomePNA PHY MII Control (Register 0)
Mnemonic
Description
Read/
Write
Default
Hex
Soft
Reset
R/W
0
0
R/W
0
0
R
0
0
R/W
0
0
R/W
0
0
R/W
1
1
R/W
0
0
R/W
0
0
MII_CONTROL
1 = RESET
15
RESET
0 = Normal operation
** Self Clearing
14
Loopback
13
Speed Selection
12
Auto-Negotiation Enabled
1 = MII Loopback enabled
0 = MII Loopback disabled
0 = 10 Mbps
1 = Enabled
0 = Disabled
1 = Power down
11
Power Down
0 = Normal operation
(This bit is mirrored in PHY Control bit 4)
10
Isolate
9
Restart Auto-Negotiation
1 = Electrically isolate PHY from MII
0 = Normal operation
1 = Restart Auto-Negotiation
0 = Normal operation
** Self Clearing
1 = Full-Duplex (for test purposes only)
8
Duplex Mode
7
Collision Test
0 = Disable COL test signal
R/W
0
0
Reserved
Write as 0, Ignore Read
R/W
0
0
6:0
0 = Half-Duplex
Am79C978
179
HPR1: HomePNA PHY MII Status
(Register 1)
Table 47. HPR1: HomePNA PHY MII Status (Register 1)
Bits
Mnemonic
Description
Read/
Write
Default
Hex
Soft
Reset
MII_Status
15
100BASE-T4
0 = PHY not able to perform 100BASE-T4
R
0
0
14
100BASE-X Full-Duplex
0 = PHY not able to perform Full-Duplex
100BASE-X
R
0
0
13
100BASE-X Half-Duplex
0 = PHY not able to perform Half-Duplex
100BASE-X
R
0
0
12
10 Mbps Full-Duplex
0 = PHY not able to perform 10 Mbps in FullDuplex
R
0
0
11
10 Mbps Half-Duplex
1 = PHY able to perform 10 Mbps in HalfDuplex
R
1
1
Reserved
Reads will produce undefined results
R
R
1
1
R
0
0
R
0
0
R
0
0
R
0
0
R
0
0
R
1
1
10:7
6
MF Preamble Suppression
5
Auto-Negotiation Complete
4
Remote Fault
3
Auto-Negotiation Ability
1 = PHY will accept management frames with
Preamble suppressed
0 = PHY will not accept management frames
with Preamble suppressed
1 = Auto-Negotiation completed
0 = Auto-Negotiation not completed
1 = Remote fault detected
0 = Normal operation
1 = PHY is able to perform Auto-Negotiation
0 = PHY is not able to perform Auto-Negotiation
1 = Link is up
0 = Link is down
180
2
Link Status
1
Jabber Detect
0
Extended Capability
This bit will be RESET (latched low and reenabled on Read) on the first occurrence of lost
link and will be SET after completion of valid
LINK process.
1 = Jabber condition detected
0 = Normal operation
1 = Extended Register Capability
0 = Basic Register Set Capability
Am79C978
HPR2 and HPR3: HomePNA PHY MII PHY ID
(Registers 2 and 3)
Table 48. HPR2 and HPR3: HomePNA PHY MII ID (Registers 2 and 3)
Description
Read/
Write
Default
Hex
Soft
Reset
Most significant bytes of the PHY_ID (Bits 3-18)
R
0000
0000
PHY_ID LSB (15-10)
IEEE Address (Bits 19-24)
R
1A
1A
9:4
PHY_ID LSB (9-4)
Manufacturer Model Number
R
39
39
3:0
PHY_ID LSB (3-0)
Revision Number
R
0
0
Read/
Write
Default
Hex
Soft
Reset
Bits
Mnemonic
MII_PHY_ID
15:0
PHY_ID MSB (31-16)
MII_PHY_ID
15:10
HPR4-HPR7: HomePNA PHY Auto-Negotiation
(Registers 4 - 7)
Table 49. HPR4-HPR7: HomePNA PHY Auto-Negotiation (Registers 4 - 7)
Hex
Mnemonic
Description
04
Auto-Negotiation Register 4
Advertisement
R
0021
0021
05
Auto-Negotiation Register 5
Link Partner Ability
R
0000
0000
06
Auto-Negotiation Register 6
Expansion
R
0000
0000
07
Auto-Negotiation Register 7
Next Page
R
0000
0000
Reserved Registers: HPR8 - HPR15
These registers should be ignored when read and
should not be written to at any time.
Am79C978
181
HPR16: HomePNA PHY Control (Register 16)
Table 50.
Bits
HPR16: HomePNA PHY Control (Register 16)
Mnemonic
Description
Read/
Write
Default
Hex
Soft
Reset
R/W
0
0
R/W
0
0
R/W
0
0
R/W
0
0
R/W
0
0
R/W
0
0
R/W
0
0
R/W
0
0
R
0
0
R
1
1
R
0
0
PHY_Control
15
14:12
Remote Command
Reserved
11
Command Low Power
10
Command High Power
9
Command Low Speed
8
Command High Speed
7
Disable AID Negotiation
6
Clear PHY-Event Counter
5
Disable Squelch adaptation
1 = Ignore Remote Commands
0 = Normal operation
Reads will produce undefined results
1 = Command low power
0 = Normal operation
1 = Command high power
0 = Normal operation
1 = Command low speed
0 = Normal operation
1 = Command high speed
0 = Normal operation
1 = Disable AID negotiation
0 = Normal operation
1 = Clear PHY event counter
0 = Normal operation
1 = Disable Squelch adaptation
0 = Normal operation
R/W
1 = Power down
4
Power Down
0 = Normal operation
(This bit is controlled by HPR0)
182
3
Reserved
2
High Speed
1
High Power
0
Reserved
Reads will produce undefined results
1 = Set node to High speed
0 = Set node to Low speed
1 = Set node to High power
0 = Set node to Low power
Reads will produce undefined results
Am79C978
R
R/W
HPR17: HomePNA Status Control (Register 17)
Table 51. HPR17: HomePNA Status Control (Register 17)
Bits
Mnemonic
15:13
Reserved
12
Any1home
11:7
Reserved
Description
Reads will produce undefined results;
Writes = 0
1 = Any1Home Link Packet Disable
0 = Any1Home Link Packet Enable
Reads will produce undefined results;
Writes = 0
1 = Last packet received was sent at high power
6
Received_Power
5
Received_Speed
4
Received_Ver
1 = Last packet received was sent at Version
XX
Reserved
Reads will produce undefined results;
Writes = 0
3:0
0 = Last packet received was sent at low power
1 = Last packet received was sent at high power
0 = Last packet received was sent at low power
Read/
Write
Default
Hex
Soft
Reset
R/W
R/W
0
R/W
R
0
R
0
R
0
R/W
HPR18 and HPR19: HomePNA PHY TxCOMM
(Registers 18 and 19)
Table 52. HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19)
Hex
12-13
Mnemonic
PHY_TX_COMM (4)
Description
The 32-bit preamble transmitted on the
HomePNA PHY. Register 12 contains the high
word and Register 13 the low word.
The 32-bit transmitted data field is to be used for outof-band communication between PHY management
entities. No protocol for out-of-band management has
been defined. Accessing the low word causes the PHY
to send all-0 PCOMs until the high word has been accessed. Once accessed, the next transmitted packet
will cause this register’s contents to be shifted out in
Read/
Write
Default
Hex
Soft
Reset
R/W
All 0s
All 0s
the PCOM field of the transmitted packet. Upon transmission, this register will read back as all 0s. A non-null
transmitted PCOM will set the TxPCOM Ready bit in
the Event Status Register (Register HPR26). An access to any of the two TxPCOM words will clear the TxPCOM Ready bit in the ISTAT register.
Am79C978
183
HPR20 and HPR21: HomePNA PHY RxCOMM
(Registers 20 and 21)
Table 53.
Hex
14-15
HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21)
Mnemonic
PHY_RX_COMM (4)
Description
The 32-bit preamble received on the
HomePNA PHY. Register 14 contains the high
word and Register 15 the low word.
The 32-bit received data field to be used for out-ofband communication between PHY management entities. No protocol for out-of-band management has
been defined. Accessing the low word of the register is
sufficient to ensure that subsequently received packets
will not over-write the register contents. A non-null re-
Read/
Write
Default
Hex
Soft
Reset
R
All 0s
All 0s
ceived PCOM will set the RxPCOM Valid bit of the
Event Status Register (Register HPR26). Accessing
the high word of the register clears this bit and allows
over-writing of the register by subsequent received
packets.
HPR22: HomePNA PHY AID (Register 22)
Table 54. HPR22: HomePNA PHY AID (Register 22)
Bits
Mnemonic
Description
Read/
Write
Default
Hex
Soft
Reset
R/W
00
00
R/W
00
00
PHY_AID
The Address ID of this PHY
15:8
7:0
PHY_AID
If PHY_Control Disable AID Negotiation is not
set then writes to this bit will have no effect.
An 8-bit counter that records the number of
noise events detected. Overflows are held as
FFh. Can be cleared by setting bit 6 of the
control register.
Noise Events
The PHY’s AID address is used for collision detection.
Unless bit 7 of the CONTROL register is set, the PHY
is assured to select a unique AID address. Addresses
above EFh are reserved. Address FFh is defined to indicate a remote command.
HPR23: HomePNA PHY Noise Control (Register 23)
Table 55.
Bits
Mnemonic
HPR23: HomePNA PHY Noise Control (Register 23)
Description
Read/
Write
Default
Hex
Soft
Reset
PHY_NOISE_CTRL1
15:8
Noise Floor
The minimum value of the NOISE
measurement.
R/W
03
03
7:0
Noise Ceiling
The maximum value if the NOISE
measurement. If it is exceeded, NOISE is reset
to the FLOOR.
R/W
FF
FF
184
Am79C978
HPR24: HomePNA PHY Noise Control 2 (Register
24)
Table 56. HPR24: HomePNA PHY Noise Control 2 (Register 24)
Bits
Mnemonic
Description
Read/
Write
Default
Hex
Soft
Reset
R/W
F4
F4
Read/
Write
Default
Hex
Soft
Reset
R/W
03
03
R/W
FF
FF
PHY_NOISE_CTRL2
15:8
Noise Attack
Sets the attack characteristics of the NOISE
algorithm. High nibble sets number of noise
events needed to raise the NOISE level
immediately, while the low nibble is the number
of noise events needed to raise the level at the
end of an 870 ms period.
7:0
Reserved
Reads will produce undefined results
R
HPR25: HomePNA PHY Noise Statistics (Register
25)
Table 57.
Bits
Mnemonic
HPR25: HomePNA PHY Noise Statistics (Register 25)
Description
PHY_NOISE_STAT
15:8
Noise Level
This is the digital value of the
SLICE_LVL_NOISE output. It is effectively a
measure of the noise level on the wire and
tracks noise by counting the number of false
triggers of the NOISE comparator in an 800 ms
window. When auto-adaptation is enabled (bit 5
of the PHY_Control Register is false), this
register is updated with the current NOISE
count every 50 ns. When adaptation is
disabled, this register may be written to and is
used to generate both the SLICE_LVL_NOISE
and SLICE_LVL_DATA signals.
7:0
Peak Level
This is a measurement of the peak level of the
last valid (non-collision) AID received.
Am79C978
185
HPR26: HomePNA PHY Event Status (Register 26)
Table 58.
Bits
HPR26: HomePNA PHY Event Status (Register 26)
Mnemonic
Description
Read/
Write
Default
Hex
Soft
Reset
R
0
0
PHY_Event Status
15:10
Reserved
9
RxPCOM
Indicates a valid RxPCOM. An access to the
RxCOM MSB Register 21 will clear this bit.
R
0
0
8
TxPCOM
Indicates a valid TxPCOM. Any access to the
TxCOM registers (Registers 18 and 19) will
clear this bit.
R
0
0
7:4
Reserved
Reads will produce undefined results.
R
3
Packet Received
Status is cleared by writing a 0.
R/W
0
0
2
Packet Transmitted
Status is cleared by writing a 0.
R/W
0
0
1
Remote Command Received
R/W
0
0
0
Remote Command Sent
R/W
0
0
Read/
Write
Default
Hex
Soft
Reset
A valid remote command was received.
Status is cleared by writing a 0.
A remote command has been sent.
Status is cleared by writing a 0.
HPR27: HomePNA PHY Event Status (Register 27)
The Event Status register reports the state of each
event source. Any bit may be written and so facilitate
software-stimulated event testing.
Table 59.
Bits
HPR27: HomePNA PHY Event Status (Register 27)
Mnemonic
Description
AID_CTRL
15:8
AID_INTERVAL
This value defines the number of TCLKs (116.6
ns) separating AID symbols.
R/W
14
14
7:0
AID_ISBI
This value defines the number of TCLKs (116.6
ns) separating AID symbol 0.
R/W
40
40
Read/
Write
Default
Hex
Soft
Reset
HPR28: HomePNA PHY ISBI Control (Register 28)
Table 60. HPR8: HomePNA PHY ISBI Control (Register 28)
Bits
Mnemonic
Description
ISBI_CTRL
15:8
ISBI_SLOW
This value defines the number of TCLKs (116.6
ns) separating data pulses for Symbol 0 in low
speed mode.
R/W
2C
2C
7:0
ISBI_FAST
This value defines the number of TCLKs (116.6
ns) separating data pulses for Symbol 0 in high
speed mode.
R/W
1C
1C
186
Am79C978
HPR29: HomePNA PHY TX Control (Register 29)
Table 61.
Bits
HPR29: HomePNA PHY TX Control (Register 29)
Mnemonic
Description
Read/
Write
Default
Hex
Soft
Reset
R/W
04
04
TX_CTRL
15:8
TX_PULSE_WIDTH
This value defines the duration of a transmit
pulse in OSC cycles (16.7 ns). This will
effectively determine the transmit spectrum of
the PHY.
7:4
TX_PULSE_CYCLES_N
This value defines the number of pulses that
will be driven onto the HRTXRX_N pin.
R/W
4
4
3:0
TX_PULSE_CYCLES_P
This value defines the number of pulses that
will be driven onto the HRTXRX_P pin.
R/W
4
4
HPR30: 1 Mbps HomePNA PHY Drive Level Control
Test Register (Register 30)
Table 62.
Bits
15:12
HPR30: HomePNA PHY Drive Level Control Test Register (Register 30)
Mnemonic
Description
Read/
Write
Default
Hex
R
YX
RES
Reserved; Write = 0; Read = X
11:6
High Level Control
Defines the drive level that will be utilized in the
High Power mode.
R/W
15
5:0
Low Level Control
Defines the drive level that will be utilized in the
Low Power mode.
R/W
09
Soft
Reset
HPR31: 1 Mbps HomePNA PHY Analog Control
Register (Register 31)
Table 63.
Bits
Mnemonic
HPR31: HomePNA PHY Analog Control Register (Register 31)
Description
15:11
Level_Adjust
Global output slope adjustment. These bits
control the number of current sources enable
for transmit. Each bit represents a single
current source. Thus 10101 enables three
current sources as does 11100.
10:8
Reserved
Reserved; Write = 0
7
6:0
Force_Link_Valid
Reserved
1 = Link Status bit will be held valid
0 = Normal operation
Reserved; Write = 0
Read/
Write
Default
Hex
Soft
Reset
R/W
18
18
R/W
0
0
R/W
0
0
R/W
0
0
Note: 1. Writes to these bits will cause undefined functionality.
Am79C978
187
10BASE-T PHY Management Registers
(TBRs)
The Am79C978 home networking device supports the
MII basic register set and extended register set. Both
sets of registers are accessible through the PHY Management Interface. As specified in the IEEE standard,
the basic register set consists of the Control Register
(Register 0) and the Status Register (Register 1). The
extended register set consists of Registers 2 to 31
(decimal).
Table 64 lists all the 10BASE-T registers implemented
in the device. All the reserved registers should not be
written to, and reading them will return a zero value.
Table 64. Am79C978 10BASE-T PHY Management
Register Set
Register
Address
(in Decimal)
Register Name
Basic/
Extended
0
PHY Control
B
1
PHY Status
B
2-3
PHY Identifier
E
4
Auto-Negotiation
Advertisement
E
5
Auto-Negotiation Link
Partner Ability
E
6
Auto-Negotiation
Expansion
E
7
Auto-Negotiation Next
Page
E
8-15
Reserved
E
16
Interrupt Enable and
Status
E
17
PHY Control/Status
E
18
Reserved
E
19
PHY Management
Extension
E
20-23
Reserved
E
24
Summary Status
E
25-31
Reserved
E
188
Am79C978
TBR0: 10BASE-T PHY Control Register (Register 0)
Table 65. TBR0: 10BASE-T PHY Control Register (Register 0)
Reg
Bits
Read/Write
(Note 1)
Default
Value
Soft
Reset
R/W, SC
0
0
0 = asserts Loopback mode,
1 = deasserts Loopback mode
R/W
0
0
Name
Soft Reset (Note 2)
Description
When write: 1 = PHY software reset,
0 = normal operation.
0
15
0
14
0
13
Speed Selection
(Note 3)
1 = 100 Mbps,
0 = 10 Mbps
R/W
1
1
0
12
Auto-Negotiation
Enable
1 = enable Auto-Negotiation,
0 = disable Auto-Negotiation
R/W
1
1
0
11
Power Down
1 = power down,
0 = normal operation
R/W
0
0
0
10
1 = electrically isolate PHY
0 = normal operation
R/W
1
1
0
9
Restart AutoNegotiation
1 = restart Auto-Negotiation,
0 = normal operation
R/W, SC
0
0
0
8
Duplex Mode
(Note 3)
1 = Full-Duplex,
0 = Half-Duplex
R/W
1
Retains
previous
value
0
7
Collision Test
1 = enable COL signal test,
0 = disable COL signal test
R/W
0
0
0
6-0
Reserved
Write as 0, ignore on read
RO
0
0
Loopback
Isolate
(Note 4)
When read: 1 = reset in process,
0 = reset done.
Notes:
1. R/W = Read/Write, SC = Self Clearing, RO = Read only.
2. Soft Reset does not reset the PDX block. Refer to the Soft Reset Section for details.
3. Bits 8 and 13 have no effect if Auto-Negotiation is enabled (Bit 12 = 1).
4. If the ISOL pin of the chip and the Isolate bit in Register 0 is 1, this bit will be set.
Am79C978
189
TBR1: 10BASE-T Status Register (Register 1)
The Status Register identifies the physical and Autonegotiation capabilities of the local PHY. This register is
read only; a write will have no effect.
Table 66. TBR1: 10BASE-T PHY Status Register (Register 1)
Bits
Name
Description
Default
Value
15
100BASE-T4
1 = 100BASE-T4 able,
0 = not 100BASE-T4 able
RO
0
14
100BASE-X Full-Duplex
1 = 100BASE-X full-duplex able,
0 = not 100BASE-X full-duplex able
RO
0
13
100BASE-X Half-Duplex
1 = 100BASE-X half-duplex able,
0 = not 100BASE-X half-duplex able
RO
0
12
10 Mbps Full-Duplex
1 = 10 Mbps full-duplex able,
0 = not 10 Mbps full-duplex able
RO
1
11
10 Mbps Half-Duplex
1 = 10 Mbps half-duplex able,
0 = not 10 Mbps half-duplex able
RO
1
Reserved
Ignore when read
RO
NA
6
MF Preamble Suppression
1 = PHY can accept management (mgmt)
frames with or without preamble, 0 = PHY
can only accept mgmt frames with
preamble
RO
1
5
Auto-Negotiation Complete
1 = Auto-Negotiation completed,
0 = Auto-Negotiation not completed
RO
0
4
Remote Fault
1 = remote fault detected,
0 = no remote fault detected
RO, LH
0
3
Auto-Negotiation Ability
1 = PHY able to auto-negotiate,
0 = PHY not able to auto-negotiate
RO
1
2
Link Status
1 = link is up,
0 = link is down
RO, LL
0
1
Jabber Detect
1 = jabber condition detected,
0 = no jabber condition detected
RO
0
0
Extended Capability
1 = extended register capabilities,
0 = basic register set capabilities only
RO
1
10-7
Note:
1. LH = Latching High, LL = Latching Low.
190
Read/Write
(Note 1)
Am79C978
TBR2 and TBR3: 10BASE-T PHY Identifier
(Registers 2 and 3)
Registers 2 and 3 contain a unique PHY identifier, consisting of 22 bits of the organizationally unique IEEE
Identifier, a 6-bit manufacturer’s model number, and a
4-bit manufacturer’s revision number. The most significant bit of the PHY identifier is bit 15 of register 2; the
least significant bit of the PHY identifier is bit 0 of reg-
Table 67.
Bits
15-0
Name
PHY_ID[31-16]
Name
TBR2: 10BASE-T PHY Identifier (Register 2)
Read/
Write
Description
IEEE Address (bits 3-18); Register
2, bit 15 is MS bit of PHY Identifier
Table 68.
Bits
ister 3. Register 2, bit 15 corresponds to bit 3 of the
IEEE Identifier and register 2, bit 0 corresponds to bit
18 of the IEEE Identifier. Register 3, bit 15 corresponds
to bit 19 of the IEEE Identifier and register 3, bit 10 corresponds to bit 24 of the IEEE Identifier. Register 3, bits
9-4 contain the manufacturer’s model number and bits
3-0 contain the manufacturer’s revision number. These
registers are shown in Table 67 and Table 68.
RO
Default Value
0000000000000000
(0000 Hex)
Soft Reset
Retains original
Value
TBR3: 10BASE-T PHY Identifier (Register 3)
Description
Read/Write
15-10
PHY_ID[15-10]
IEEE Address (bits 1924)
RO
9-4
PHY_ID[9-4]
Manufacturer’s Model
Number (bits 5-0)
RO
3-0
PHY_ID[3-0]
Revision Number (bits
3-0); Register 3, bit 0 is
LS bit of PHY Identifier
RO
Am79C978
Default Value
011010
(1A Hex)
110111
(37 Hex)
0000
Soft Reset
Retains original value
Retains original value
Retains original value
191
TBR4: 10BASE-T Auto-Negotiation Advertisement
Register (Register 4)
this register is to advertise the technology ability to the
link partner device. See Table 69.
This register contains the advertised ability of the
Am79C978 home networking device. The purpose of
When this register is modified, Restart AutoNegotiation (Register 0, bit 9) must be enabled to guarantee the change is implemented.
Table 69. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4)
Bit(s)
Name
Description
15
Next Page
When set, the device wishes to engage in next page exchange. If
clear, the device does not wish to engage in next page exchange.
14
Reserved
When set, a remote fault bit is inserted into the base link code
word during the Auto Negotiation process. When cleared, the
base link code work will have the bit position for remote fault as
cleared.
Read/
Write
H/W or Soft
Reset
R/W
0
RO
0
R/W
0
RO
0
R/W
0
RO
0
13
Remote Fault
12:11
Reserved
10
PAUSE
9
Reserved
8
Full-Duplex 100BASE-TX
This bit advertises Full-Duplex capability. When set, Full-Duplex
capability is advertised. When cleared, Full-Duplex capability is
not advertised.
R/W
0
7
Half-Duplex 100BASE-TX
This bit advertises Half-Duplex capability for the Auto-negotiation
process. Setting this bit advertises Half-Duplex capability.
Clearing this bit does not advertise Half-Duplex capability.
R/W
0
6
Full-Duplex 10BASE-T
This bit advertises Full-Duplex capability. When set, Full-Duplex
capability is advertised. When cleared, Full-Duplex capability is
not advertised.
R/W
1
5
Half-Duplex 10BASE-T
This bit advertises Half-Duplex capability for the Auto-negotiation
process. Setting this bit advertises Half-Duplex capability.
Clearing this bit does not advertise Half-Duplex capability.
R/W
1
4:0
Selector Field
The Am79C978 home networking device is an 802.3 compliant
device
RO
0x01
192
This bit should be set if the PAUSE capability is to be advertised.
Am79C978
TBR5: 10BASE-T Auto-Negotiation Link Partner
Ability Register (Register 5)
The Auto-Negotiation Link Partner Ability Register is
Read Only. The register contains the advertised ability
of the link partner. The bit definitions represent the received link code word. This register contains either the
base page or the link partner’s next pages. See Table
70 and Table 71.
Table 70. TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page Format
Read/
Write
H/W or Soft
Reset
Link partner next page request
RO
0
Acknowledge
Link partner acknowledgment
RO
0
Remote Fault
Link partner remote fault request
RO
0
RO
0
RO
0
Bit(s)
Name
15
Next Page
14
13
12:5
Description
Technology Ability Link partner technology ability field
4:0
Table 71.
Selector Field
Link partner selector field
TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register 5) - Next Page Format
Bit(s)
Name
15
Next Page
14
Acknowledge
13
Message Page
12
Acknowledge 2
11
Toggle
10:0
Message Field
Read/
Write
H/W or Soft
Reset
Link partner next page request
RO
0
Link partner acknowledgment
RO
0
Link partner message page request
RO
0
RO
0
Link partner toggle bit
RO
0
Link partner’s message code
RO
0
Description
1 = Link partner can comply with the request
0 = Link partner cannot comply with the request
Am79C978
193
TBR6: 10BASE-T Auto-Negotiation Expansion
Register (Register 6)
process. The Auto-Negotiation Expansion Register bits
are Read Only. See Table 72.
The Auto-Negotiation Expansion Register provides additional information which aids the Auto-Negotiation
Table 72.
Bit(s)
Name
15:5
Reserved
TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register 6)
Description
4
Parallel Detection 1=Parallel detection fault
Fault
0=No parallel detection fault
3
Link Partner Next
Page Able
2
Next Page Able
1
Page Received
0
1 = Link partner is next page able
0 = Link partner is not next page able
1 = Am79C978 home networking device channel is next page
able
0 = Am79C978 home networking device channel is not next page
able
1 = A new page has been received
Read/
Write
H/W or Soft
Reset
RO
0
RO, LH
0
RO
0
RO
1
RO, LH
0 = A new page has not been received
Link Partner ANEG 1 = Link partner is Auto-Negotiation able
Able
0 = Link partner is not Auto-Negotiation able
TBR7: 10BASE-T Auto-Negotiation Next Page
Register (Register 7)
RO
0
0
up the default value of 2001h represents a message
page with the message code set to null. See Table 73.
The Auto-Negotiation Next Page Register contains the
next page link code word to be transmitted. On power-
Table 73. TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register 7)
Bit(s)
Name
Description
Read/
Write
H/W or Soft
Reset
15
Next Page
Am79C978 home networking device channel next page request
R/W
0
14
Reserved
RO
0
13
Message Page
R/W
1
R/W
0
Am79C978 home networking device channel toggle bit
RO
0
Message code field
R/W
0x001
12
Acknowledge 2
11
Toggle
10:0
Message Field
Am79C978 home networking device channel message page
request
1 = Am79C978 home networking device channel can comply with
the request
0 = Am79C978 home networking device channel cannot comply
with the request
Reserved Registers (Registers 8-15, 18, 20-23, and
25-31)
31. These registers should be ignored when read and
should not be written at any time.
The Am79C978 home networking device contains reserved registers at addresses 8-15, 18, 20-23, and 25-
194
Am79C978
TBR16: 10BASE-T INTERRUPT Status and Enable
Register (Register 16)
and interrupt enable bits. The status is always updated
whether or not the interrupt enable bits are set. When
an interrupt occurs, the system will need to read the interrupt register to clear the status bits and determine
the course of action needed. See Table 74.
The Interrupt bits indicate when there is a change in the
Link Status, Duplex Mode, Auto-Negotiation status, or
Speed status. Register 16 contains the interrupt status
Table 74.
TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16)
Bit(s)
Name
15:14
Reserved
13
Interrupt Test Enable
(Note 1)
Description
1 = When this bit is set, setting bits 12:9 of this register
will cause a condition that will set bits 4:1
accordingly. The effect is to test the register bits with
a forced interrupt condition.
Read/
Write
H/W or Soft
Reset
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
0 = Bits 4:1 are only set if the interrupt condition (if any
bits in 12:9 are set) occurs.
Link Status Change
12
Enable
Duplex Mode Change
11
Enable
Auto-Neg Change
10
Enable
Speed Change
9
1 = Link Status Change enable
0 = This interrupt is masked
1 = Duplex Mode Change enable
0 = This interrupt is masked
1 = Auto-Negotiation Change enable
0 = This interrupt is masked
1 = Speed Change enable
Enable
0 = This interrupt is masked
Global
1= Global Interrupt enable
8
Enable
0 = This interrupt is masked
7:5
Reserved
4
Link Status Change
3
Duplex Mode Change
2
Auto-Negotiation Change
1
Speed Change
0
Global
1 = Link Status has changed on a port
RO,
0 = No change in Link Status
LH
1 = Duplex Mode has changed on a port
RO,
0 = No change in Duplex mode
LH
1 = Auto-Neg status has changed on a port
RO,
0 = No change in Auto-Neg status
LH
1 = Speed status has changed on a port
RO,
0 = No change
LH
1 = Indicates a change in status of any of the above
interrupts
RO,
0 = Indicates no change in Interrupt Status
LH
0
0
0
0
0
Note:
1. All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.
Am79C978
195
TBR17: 10BASE-T PHY Control/Status Register
(Register 17)
This register is used to control the configuration of the
10 Mbps PHY unit of the Am79C978 home networking
device. See Table 75.
Table 75. TBR17: 10BASE-T PHY Control/Status Register (Register 17)
Read/Write
H/W
Reset
Reserved
R/W
0
Retains
Previous
Value
14
Reserved
R/W
0
Retains
Previous
Value
13
Force Link Good
Enable
1 = link status forced to link up state
0 = link status is determined by the device
R/W
0
0
12
Disable Link Pulse
1 = Link pulses sent from the
10BASE-T transmitter are suppressed
R/W
0
0
1 = Disables the SQE heartbeat which occurs
after each 10BASE-T transmission
0 = The heart beat assertion occurs on the
COL pin approximately 1 µs after transmission
and for a duration of 1 µs.
R/W
0
0
R/W
0
0
R/W
0
0
R/W
00
00
RO
0
0
R/W
0
0
1 = 10BASE-T receive squelch thresholds are
reduced to allow reception of frames which are
greater than 100 meters
0 = Squelch thresholds are set for standard
distance of 100 meters
R/W
0
0
1 = TX± outputs not active for 10BASE-T. TX±
outputs to logical “0” for PECL.
0 = Transmit valid data
R/W
0
0
1 = CRS is asserted when transmit or receive
medium is active
0 = CRS is asserted when receive medium is
active
RO
0
0
RO
0
0
RO
0/1
0/1
Bits
Name
15
11
SQE_TEST Disable
10
Reserved
9
Jabber Detect Disable
8:7
Reserved
6
Receive Polarity
Reversed
5
4
3
Description
1 = disable jabber detect
0 = enable jabber detect
1 = Receive polarity of the 10BASE-T receiver
is reversed
0 = Receive polarity is correct
1 = polarity correction circuit is disabled for
Auto Receive Polarity 10BASE-T
Correction Disable
0 = Self correcting polarity circuit is enabled
Extended Distance
Enable
TX_DISABLE
2
TX_CRS_EN
1
Reserved
0
PHY Isolated
1 = Internal PHY is isolated
0 = Internal PHY is enabled
Note:
1. For these loopback paths, the data is also transmitted out of the MDI pins (TX±).
196
Am79C978
Soft Reset
TBR19: 10BASE-T PHY Management Extension
Register (Register 19)
Table 76 contains the PHY Management Extension
Register (Register 19) bits.
Table 76. TBR19: 10BASE-T PHY Management Extension Register (Register 19)
Bits
Name
15:6
Reserved
5
4-0
Description
Write as 0; ignore on read
1 = last management frame was
Mgmt Frame Format invalid (opcode error, etc.) 0 = last
management frame was valid
PHY Address
PHY Address defaults to 11110
Read/Write
Default Value
Soft Reset
RO
0
0
RO
0
0
RO
11110
Retains
Previous Value
Reserved Register: 10BASE-T Configuration
Register (Register 22)
TBR24: 10BASE-T Summary Status Register
(Register 24)
This register is reserved.
The Summary Status register is a global register containing status information. This register is Read/Only
and represents the most important data which a single
register access can convey. The Summary Status register indicates the following: Link Status, Full-Duplex
Status, Auto-Negotiation Alert, and Speed. See Table
77.
Reserved Register: 10BASE-T Carrier Status
Register (Register 23)
This register is reserved.
Table 77.
Bit(s)
Name
15-4
Reserved
3
Link Status
2
Full-Duplex
1
0
AutoNEG
Alert
Speed
TBR24: 10BASE-T Summary Status Register (Register 24)
Description
Write as 0; Ignore on Read
1 = Link Status is up
0 = Link Status is down
Operating in Full-Duplex mode
Operating in Half-Duplex mode
1 = AutoNEG status has changed
0 = AutoNEG status unchanged
1 = Operating at 100 Mbps
0 = Operating at 10 Mbps
Am79C978
Read/
Write
H/W or Soft
Reset
0
0
R/O
0
R/O
0
R/O
0
R/O
0
197
Initialization Block
Note: When SSIZE32 (BCR20, bit 8) is set to 0, the
software structures are defined to be 16 bits wide. The
base address of the initialization block must be aligned
to a DWord boundary, i.e., CSR1, bit 1 and 0 must be
cleared to 0. When SSIZE32 is set to 0, the initialization
block looks like Table 78.
Note: The Am79C978 controller performs DWord accesses to read the initialization block. This statement is
Table 78.
Address
Bits 15-13
always true, regardless of the setting of the SSIZE32
bit.
When SSIZE32 (BCR20, bit 8) is set to 1, the software
structures are defined to be 32 bits wide. The base address of the initialization block must be aligned to a
DWord boundary, i.e., CSR1, bits 1 and 0 must be
cleared to 0. When SSIZE32 is set to 1, the initialization
block looks like Table 79.
Initialization Block (SSIZE32 = 0)
Bit 12
Bits 11-8
IADR+00h
MODE 15-00
IADR+02h
PADR 15-00
IADR+04h
PADR 31-16
IADR+06h
PADR 47-32
IADR+08h
LADRF 15-00
IADR+0Ah
LADRF 31-16
IADR+0Ch
LADRF 47-32
IADR+0Eh
LADRF 63-48
IADR+10h
RDRA 15-00
IADR+12h
RLEN
0
TLEN
0
Bits 7-4
RES
IADR+14h
Bits 3-0
TDRA 23-16
TDRA 15-00
IADR+16h
RES
TDRA 23-16
Table 79. Initialization Block (SSIZE32 = 1)
Address
Bits
31-28
Bits
27-24
Bits
23-20
Bits
19-16
IADR+00h
TLEN
RES
RLEN
RES
IADR+04h
IADR+08h
Bits
15-12
Bits
7-4
Bits
3-0
MODE
PADR 31-00
RES
PADR 47-32
IADR+0Ch
LADRF 31-00
IADR+10h
LADRF 63-32
IADR+14h
RDRA 31-00
IADR+18h
TDRA 31-00
RLEN and TLEN
When SSIZE32 (BCR20, bit 8) is set to 0, the software
structures are defined to be 16 bits wide, and the RLEN
and TLEN fields in the initialization block are each three
bits wide. The values in these fields determine the number of transmit and receive Descriptor Ring Entries
(DRE) which are used in the descriptor rings. Their
meaning is shown in Table 80. If a value other than those
198
Bits
11-8
listed in Table 80 is desired, CSR76 and CSR78 can be
written after initialization is complete.
When SSIZE32 (BCR20, bit 8) is set to 1, the software
structures are defined to be 32 bits wide, and the RLEN
and TLEN fields in the initialization block are each 4 bits
wide. The values in these fields determine the number
of transmit and receive Descriptor Ring Entries (DRE)
which are used in the descriptor rings. Their meaning
is shown in Table 81.
Am79C978
If a value other than those listed in Table 80 is desired,
CSR76 and CSR78 can be written after initialization is
complete.
Table 80.
R/TLEN Decoding (SSIZE32 = 0)
R/TLEN
000
001
010
011
100
101
110
111
Number of DREs
1
2
4
8
16
32
64
128
A logical address is passed through the CRC generator,
producing a 32-bit result. The high order 6 bits of the
CRC is used to select one of the 64 bit positions in the
Logical Address Filter. If the selected filter bit is set, the
address is accepted and the frame is placed into memory.
The Logical Address Filter is used in multicast addressing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the node’s responsibility
to determine if the message is actually intended for the
node by comparing the destination address of the stored
message with a list of acceptable logical addresses.
RDRA and TDRA
RDRA and TDRA indicate where the transmit and receive descriptor rings begin. Each DRE must be located
at a 16-byte address boundary when SSIZE32 is set to
1 (BCR20, bit 8). Each DRE must be located at an 8byte address boundary when SSIZE32 is set to 0
(BCR20, bit 8).
If the Logical Address Filter is loaded with all zeros and
promiscuous mode is disabled, all incoming logical addresses except broadcast will be rejected. If the
DRCVBC bit (CSR15, bit 14) is set as well, the broadcast packets will be rejected. See Figure 51.
PADR
This 48-bit value represents the unique node address
assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and
used for internal address comparison. PADR[0] is compared with the first bit in the destination address of the
incoming frame. It must be 0 since only the destination
address of a unicast frames is compared to PADR. The
six hex-digit nomenclature used by the ISO 8802-3
(IEEE/ANSI 802.3) maps to the Am79C978 home networking PADR register as follows: the first byte is compared with PADR[7:0] with PADR[0] being the least
significant bit of the byte. The second ISO 8802-3
(IEEE/ANSI 802.3) byte is compared with PADR[15:8],
again from the least significant bit to the most significant bit, and so on. The sixth byte is compared with
PADR[47:40], the least significant bit being PADR[40].
Table 81. R/TLEN Decoding (SSIZE32 = 1)
R/TLEN
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
11XX
1X1X
against the physical address that was loaded through
the initialization block.
Number of DREs
1
2
4
8
16
32
64
128
256
512
512
512
Mode
LADRF
The Logical Address Filter (LADRF) is a 64-bit mask
that is used to accept incoming Logical Addresses. If
the first bit in the incoming address (as transmitted on
the wire) is a 1, it indicates a logical address. If the first
bit is a 0, it is a physical address and is compared
The mode register field of the initialization block is copied into CSR15 and interpreted according to the description of CSR15.
Am79C978
199
32-Bit Resultant CRC
Received Message
Destination Address
47
1 0
1
31
26
0
CRC
GEN
63
SEL
Logical
Address Filter
(LADRF)
0
64
MUX
Match = 1 Packet Accepted
Match = 0 Packet Rejected
Match
6
22206B-54
Figure 51. Address Match Logic
Receive Descriptors
receive descriptors look like Table 83 (CRDA = Current
Receive Descriptor Address).
When SWSTYLE (BCR20, bits 7-0) is set to 0, then the
software structures are defined to be 16 bits wide, and
receive descriptors look like Table 82 (CRDA = Current
Receive Descriptor Address).
When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the
software structures are defined to be 32 bits wide, and
receive descriptors look like Table 84 (CRDA = Current
Receive Descriptor Address).
When SWSTYLE (BCR 20, bits 7-0) is set to 2, then the
software structures are defined to be 32 bits wide, and
Table 82. Receive Descriptor (SWSTYLE = 0)
Address
CRDA+00h
CRDA+02h
CRDA+04h
CRDA+06h
Address
CRDA+00h
31
15
14
13
12
OWN
1
0
ERR
1
0
FRAM
1
0
OFLO
1
0
30
29
CRDA+04h OWN ERR
FRA
M
STP
8
28
26
27
OFL
BUF
CRC
O
F
25
24
23
22
RBADR[31:0]
STP
ENP BPE
PAM
7-0
ENP
BCNT
MCNT
Receive Descriptor (SWSTYLE = 2)
RBADR[23:16]
21
20
19-16
15-12
11-0
LAFM
BAM
RES
1111
BCNT
0000
MCNT
RFRTAG[14:0]
USER SPACE
Table 84.
200
9
Table 83.
CRDA+08h RES
CRDA+0Ch
Address
CRDA+00h
CRDA+04h
CRDA+08h
CRDA+0Ch
11
10
RBADR[15:0]
CRC
BUFF
31
30
29
OWN
ERR
FRAM
28
Receive Descriptor (SWSTYLE = 3)
27
RES
OFLO CRC
26
25
24
BUFF
STP
ENP
RBADR[31:0]
USER SPACE
Am79C978
23
RES
BPE
22-16
RES
RES
15-12
0000
1111
11-0
MCNT
BCNT
RMD0
Bit
31-0
Name
RBADR
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is set by the
Am79C978
controller
and
cleared by the host. CRC will also
be set when Am79C978 home
networking receives an RX_ER
indication from the external PHY
through the MII.
Description
Receive Buffer address. This field
contains the address of the
receive buffer that is associated
with this descriptor.
RMD1
Bit
31
Name
OWN
Description
26
BUFF
This bit indicates whether the descriptor entry is owned by the
host (OWN = 0) or by the
Am79C978 controller (OWN = 1).
The Am79C978 controller clears
the OWN bit after filling the buffer
that the descriptor points to. The
host sets the OWN bit after emptying the buffer.
1. The OWN bit of the next buffer
is 0.
2. FIFO overflow occurred before
the Am79C978 controller was
able to read the OWN bit of
the next descriptor.
Once the Am79C978 controller or
host has relinquished ownership
of a buffer, it must not change any
field in the descriptor entry.
30
ERR
ERR is the OR of FRAM, OFLO,
CRC, BUFF, or BPE. ERR is set
by the Am79C978 controller and
cleared by the host.
29
FRAM
Framing error indicates that the
incoming frame contains a noninteger multiple of eight bits and
there was an FCS error. If there
was no FCS error on the incoming frame, then FRAM will not be
set even if there was a noninteger multiple of eight bits in the
frame. FRAM is not valid in internal loopback mode. FRAM is valid only when ENP is set and
OFLO is not. FRAM is set by the
Am79C978
controller
and
cleared by the host.
28
27
OFLO
CRC
Overflow error indicates that the
receiver has lost all or part of the
incoming frame, due to an inability to move data from the receive
FIFO into a memory buffer before
the internal FIFO overflowed.
OFLO is set by the Am79C978
controller and cleared by the
host.
Buffer error is set any time the
Am79C978 controller does not
own the next buffer while data
chaining a received frame. This
can occur in either of two ways:
If a Buffer Error occurs, an Overflow Error may also occur internally in the FIFO, but will not be
reported in the descriptor status
entry unless both BUFF and
OFLO errors occur at the same
time. BUFF is set by the
Am79C978
controller
and
cleared by the host.
25
STP
Start of Packet indicates that this
is the first buffer used by the
Am79C978 controller for this
frame. If STP and ENP are both
set to 1, the frame fits into a single
buffer. Otherwise, the frame is
spread over more than one buffer. When LAPPEN (CSR3, bit 5)
is cleared to 0, STP is set by the
Am79C978
controller
and
cleared by the host. When LAPPEN is set to 1, STP must be set
by the host.
24
ENP
End of Packet indicates that this
is the last buffer used by the
Am79C978 controller for this
frame. It is used for data chaining
buffers. If both STP and ENP are
set, the frame fits into one buffer
and there is no data chaining.
ENP is set by the Am79C978
controller and cleared by the
host.
CRC indicates that the receiver
has detected a CRC (FCS) error
Am79C978
201
23
BPE
Bus Parity Error is set by the
Am79C978 controller when a parity error occurred on the bus interface during data transfers to a
receive buffer. BPE is valid only
when ENP, OFLO, or BUFF are
set. The Am79C978 controller will
only set BPE when the advanced
parity error handling is enabled
by setting APERREN (BCR20, bit
10) to 1. BPE is set by the
Am79C978
controller
and
cleared by the host.
that a Broadcast frame would
pass the hash filter, LAFM will be
set on the reception of a Broadcast frame.
This bit does not exist when the
Am79C978 controller is programmed to use 16-bit software
structures for the descriptor ring
entries (BCR20, bits 7-0, SWSTYLE is cleared to 0).
20
BAM
This bit does not exist when the
Am79C978 controller is programmed to use 16-bit software
structures for the descriptor ring
entries (BCR20, bits 7-0, SWSTYLE is cleared to 0).
22
PAM
Physical Address Match is set by
the Am79C978 controller when it
accepts the received frame due
to a match of the frame’s destination address with the content of
the physical address register.
PAM is valid only when ENP is
set. PAM is set by the Am79C978
controller and cleared by the
host.
This bit does not exist when the
Am79C978 controller is programmed to use 16-bit software
structures for the descriptor ring
entries (BCR20, bits 7-0, SWSTYLE is cleared to 0).
21
LAFM
Logical Address Filter Match is
set by the Am79C978 controller
when it accepts the received
frame based on the value in the
logical address filter register.
LAFM is valid only when ENP is
set. LAFM is set by the
Am79C978
controller
and
cleared by the host.
Note that if DRCVBC (CSR15, bit
14) is cleared to 0, only BAM, but
not LAFM will be set when a
Broadcast frame is received,
even if the Logical Address Filter
is programmed in such a way that
a Broadcast frame would pass
the hash filter. If DRCVBC is set
to 1 and the Logical Address Filter is programmed in such a way
202
Broadcast Address Match is set
by the Am79C978 controller
when it accepts the received
frame, because the frame’s destination address is of the type
’Broadcast.’ BAM is valid only
when ENP is set. BAM is set by
the Am79C978 controller and
cleared by the host.
This bit does not exist when the
Am79C978 controller is programmed to use 16-bit software
structures for the descriptor ring
entries (BCR20, bits 7-0, SWSTYLE is cleared to 0).
19-16 RES
Reserved locations. These locations should be read and written
as zeros.
15-12 ONES
These four bits must be written as
ones. They are written by the host
and
unchanged
by
the
Am79C978 controller.
11-0
Buffer Byte Count is the length of
the buffer pointed to by this descriptor, expressed as the two’s
complement of the length of the
buffer. This field is written by the
host and unchanged by the
Am79C978 controller.
BCNT
RMD2
Bit
31
Name
ZERO
30-16 RFRTAG
Am79C978
Description
This field is reserved. The
Am79C978 controller will write a
zero to this location.
Receive Frame Tag. Indicates
the Receive Frame Tag applied
from the EADI interface. This field
is user defined and has a default
value of all zeros. When RXFRTG (CSR7, bit 14) is set to 0,
15-12 ZEROS
11-0
MCNT
RFRTAG will be read as all zeros.
See the section on Receive
Frame Tagging for details.
RMD3
This field is reserved. The
Am79C978 controller will write
zeros to these locations.
31-0
Message Byte Count is the length
in bytes of the received message,
expressed as an unsigned binary
integer. MCNT is valid only when
ERR is clear and ENP is set.
MCNT is written by the
Am79C978
controller
and
cleared by the host.
When SWSTYLE (BCR20, bits 7-0) is set to 0, the software structures are defined to be 16 bits wide, and
transmit descriptors look like Table 85 (CXDA = Current
Transmit Descriptor Address).
Bit
Name
Description
US
User Space. Reserved for user
defined space.
Transmit Descriptors
When SWSTYLE (BCR 20, bits 7-0) is set to 2, the
software structures are defined to be 32 bits wide, and
transmit descriptors look like Table 86 (CXDA = Current
Transmit Descriptor Address).
When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the
software structures are defined to be 32 bits wide, and
transmit descriptors look like Table 87 (CXDA = Current
Transmit Descriptor Address).
Table 85. Transmit Descriptor (SWSTYLE = 0)
Address
CXDA+00h
15
14
CXDA+02h
OWN
ERR
CXDA+04h
1
1
CXDA+06h
BUFF
UFLO
13
12
ADD_
FCS
1
EX
DEF
MORE/
LTINT
1
Table 86.
Address
CXDA+00h
31
30
CXDA+04h
OWN
ERR
CXDA+08h
BUFF
UFLO
11
10
TBADR[15:0]
ONE
8
7-0
STP
ENP
TBADR[23:16]
BCNT
LCOL
LCAR
RTRY
TDR
Transmit Descriptor (SWSTYLE = 2)
29
28
27
26
ADD_
FCS
EX
DEF
MORE/
LTINT
ONE
DEF
STP
LCOL
LCAR
RTRY
RES
CXDA+0Ch
25
24
TBADR[31:0]
23
22-16
15-12
11-4
3-0
ENP
BPE
RES
1111
RES
RES
RES
RES
RES
TRC
22-16
15-12
11-4
3-0
RES
TRC
BCNT
USER SPACE
Table 87.
Address
31
30
CXDA+00h
BUFF
UFLO
CXDA+04h
OWN
ERR
CXDA+08h
CXDA+0Ch
DEF
9
29
EX
DEF
ADD_
FCS
Transmit Descriptor (SWSTYLE = 3)
28
27
26
25
LCOL
LCAR
RTRY
MORE/
LTINT
ONE
DEF
24
23
RES
STP
ENP
BPE
RES
1111
BCNT
TBADR[31:0]
USER SPACE
Am79C978
203
TMD0
Bit
Name
31-0
TBADR
ler and is read by the host. When
LTINTEN is cleared to 0 (CSR5,
bit 14), the Am79C978 controller
will never look at the contents of
bit 28, write operations by the
host have no effect. When LTINTEN is set to 1 bit 28 changes its
function to LTINT on host write
operations and on Am79C978
controller read operations.
Description
Transmit Buffer address. This
field contains the address of the
transmit buffer that is associated
with this descriptor.
TMD1
Bit
31
Name
OWN
Description
30
ERR
ERR is the OR of UFLO, LCOL,
LCAR, RTRY or BPE. ERR is set
by the Am79C978 controller and
cleared by the host. This bit is set
in the current descriptor when the
error occurs and, therefore, may
be set in any descriptor of a
chained buffer transmission.
29
ADD_FCS
ADD_FCS dynamically controls
the generation of FCS on a frame
by frame basis. This bit should be
set with the ENP bit. However, for
backward compatibility, it is recommended that this bit be set for
every descriptor of the intended
frame. When ADD_FCS is set,
the state of DXMTFCS is ignored
and transmitter FCS generation is
activated. When ADD_FCS is
cleared to 0, FCS generation is
controlled by DXMTFCS. When
APAD_XMT (CSR4, bit 11) is set
to 1, the setting of ADD_FCS has
no effect. ADD_FCS is set by the
host, and is not changed by the
Am79C978 controller. This is a
reserved bit in the C-LANCE
(Am79C90) controller.
28
204
MORE
MORE indicates that more than
one retry was needed to transmit
a frame. The value of MORE is
written by the Am79C978 controller. This bit has meaning only if
the ENP bit is set.
LTINT
LTINT is used to suppress interrupts after successful transmission on selected frames. When
LTINT is cleared to 0 and ENP is
set to 1, the Am79C978 controller
will not set TINT (CSR0, bit 9) after a successful transmission.
TINT will only be set when the
last descriptor of a frame has
both LTINT and ENP set to 1.
When LTINT is cleared to 0, it will
only cause the suppression of interrupts for successful transmission. TINT will always be set if the
transmission has an error. The
LTINTEN overrides the function
of TOKINTD (CSR5, bit 15).
27
ONE
ONE indicates that exactly one
retry was needed to transmit a
frame. ONE flag is not valid when
LCOL is set. The value of the
ONE bit is written by the
Am79C978 controller. This bit
has meaning only if the ENP bit is
set.
26
DEF
Deferred indicates that the
Am79C978 controller had to defer while trying to transmit a
frame. This condition occurs if the
channel is busy when the
Am79C978 controller is ready to
transmit. DEF is set by the
Am79C978
controller
and
cleared by the host.
25
STP
Start of Packet indicates that this
is the first buffer to be used by the
Am79C978 controller for this
frame. It is used for data chaining
This bit indicates whether the descriptor entry is owned by the
host (OWN = 0) or by the
Am79C978 controller (OWN = 1).
The host sets the OWN bit after
filling the buffer pointed to by the
descriptor entry. The Am79C978
controller clears the OWN bit after transmitting the contents of
the buffer. Both the Am79C978
controller and the host must not
alter a descriptor entry after it has
relinquished ownership.
MORE/LTINT Bit 28 always functions as
MORE. The value of MORE is
written by the Am79C978 control-
Am79C978
buffers. The STP bit must be set
in the first buffer of the frame, or
the Am79C978 controller will skip
over the descriptor and poll the
next descriptor(s) until the OWN
and STP bits are set. STP is set
by the host and is not changed by
the Am79C978 controller.
24
23
ENP
BPE
the Am79C978 controller. There
are no minimum buffer size restrictions.
TMD2
Bit
31
Name
BUFF
End of Packet. End of Packet indicates that this is the last buffer
to be used by the Am79C978
controller for this frame. It is used
for data chaining buffers. If both
STP and ENP are set, the frame
fits into one buffer and there is no
data chaining. ENP is set by the
host and is not changed by the
Am79C978 controller.
2. FIFO underflow occurred before the Am79C978 controller obtained
the
STATUS
byte
(TMD1[31:24]) of the next descriptor. BUFF is set by the
Am79C978
controller
and
cleared by the host.
If a Buffer Error occurs, an Underflow Error will also occur.
BUFF is set by the Am79C978
controller and cleared by the
host.
30
UFLO
This bit does not exist, when the
Am79C978 controller is programmed to use 16-bit software
structures for the descriptor ring
entries (BCR20, bits 7-0, SWSTYLE is cleared to 0).
Reserved locations.
15-12 ONES
These four bits must be written as
ones. This field is written by the
host and unchanged by the
Am79C978 controller.
11-00 BCNT
Buffer Byte Count is the usable
length of the buffer pointed to by
this descriptor, expressed as the
two’s complement of the length of
the buffer. This is the number of
bytes from this buffer that will be
transmitted by the Am79C978
controller. This field is written by
the host and is not changed by
Buffer error is set by the
Am79C978 controller during
transmission
when
the
Am79C978 controller does not
find the ENP flag in the current
descriptor and does not own the
next descriptor. This can occur in
either of two ways:
1. The OWN bit of the next buffer
is 0.
Bus Parity Error is set by the
Am79C978 controller when a parity error occurred on the bus interface during a data transfers from
the transmit buffer associated
with
this
descriptor.
The
Am79C978 controller will only set
BPE when the advanced parity
error handling is enabled by setting APERREN (BCR20, bit 10) to
1. BPE is set by the Am79C978
controller and cleared by the
host.
22-16 RES
Description
Underflow error indicates that the
transmitter has truncated a message because it could not read
data from memory fast enough.
UFLO indicates that the FIFO has
emptied before the end of the
frame was reached.
When DXSUFLO (CSR3, bit 6) is
cleared to 0, the transmitter is
turned off when an UFLO error
occurs (CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C978 controller gracefully
recovers from an UFLO error. It
scans the transmit descriptor ring
until it finds the start of a new
frame and starts a new transmission.
UFLO is set by the Am79C978
controller and cleared by the
host.
29
Am79C978
EXDEF
Excessive Deferral. Indicates that
the transmitter has experienced
205
Excessive Deferral on this transmit frame, where Excessive Deferral is defined in the ISO 8802-3
(IEEE/ANSI 802.3) standard. Excessive Deferral will also set the
interrupt bit EXDINT (CSR5, bit
7).
28
27
LCOL
LCAR
Late Collision indicates that a collision has occurred after the first
channel slot time has elapsed.
The
Am79C978
home
networkingAm79C978 controller
does not retry on late collisions.
LCOL is set by the Am79C978
controller and cleared by the
host.
Loss of Carrier is set when the
carrier is lost during an
Am79C978 controller initiated
transmission when operating in
half-duplex
mode.
The
Am79C978 controller does not
retry upon loss of carrier. It will
continue to transmit the whole
frame until done. LCAR will not
be set when the device is operating in full-duplex mode. LCAR is
not valid in Internal Loopback
Mode. LCAR is set by the
Am79C978
controller
and
cleared by the host.
26
RTRY
Retry error indicates that the
transmitter has failed after 16 attempts to successfully transmit a
message, due to repeated collisions on the medium. If DRTY is
set to 1 in the MODE register,
RTRY will set after one failed
transmission attempt. RTRY is
set by the Am79C978 controller
and cleared by the host.
25-4
RES
Reserved locations.
3-0
TRC
Transmit Retry Count. Indicates
the number of transmit retries of
the associated packet. The maximum count is 15. However, if a
RETRY error occurs, the count
will roll over to 0.
In this case only, the Transmit
Retry Count value of 0 should be
interpreted as meaning 16. TRC
is written by the Am79C978 controller into the last transmit descriptor of a frame, or when an
error terminates a frame. Valid
only when OWN is cleared to 0.
TMD3
Bit
31-0
LCAR will be set when the PHY is
in Link Fail state during transmission.
206
Am79C978
Name
US
Description
User Space. Reserved for user
defined space.
REGISTER SUMMARY
PCI Configuration Registers
Table 88. PCI Configuration Registers
Offset
Name
Width
in Bit
Access
Mode
Default
Value
RO
1022h
00h
PCI Vendor ID
16
02h
PCI Device ID
16
RO
2001h
04h
PCI Command
16
RW
0000h
06h
PCI Status
16
RW
0290h
08h
PCI Revision ID
8
RO
50h
09h
PCI Programming IF
8
RO
00h
0Ah
PCI Sub-Class
8
RO
00h
0Bh
PCI Base-Class
8
RO
02h
0Ch
Reserved
8
RO
00h
0Dh
PCI Latency Timer
8
RW
00h
0Eh
PCI Header Type
8
RO
00h
0Fh
Reserved
8
RO
00h
10h
PCI I/O Base Address
32
RW
0000 0001h
14h
PCI Memory Mapped I/O Base Address
32
RW
0000 0000h
Reserved
8
RO
00h
2Ch
PCI Subsystem Vendor ID
16
RO
00h
2Eh
PCI Subsystem ID
16
RO
00h
30h
PCI Expansion ROM Base Address
32
RW
0000 0000h
34h
Capabilities Pointer
8
RO
40h
Reserved
8
RO
00h
3Ch
PCI Interrupt Line
8
RW
00h
3Dh
PCI Interrupt Pin
8
RO
01h
3Eh
PCI MIN_GNT
8
RO
06h
3Fh
PCI MAX_LAT
8
RO
FFh
40h
PCI Capability Identifier
8
RO
01h
41h
PCI Next Item Pointer
8
RO
00h
42h
PCI Power Management Capabilities
16
RO
00h
44h
PCI Power Management Control/Status
16
RO
00h
46h
PCI PMCSR Bridge Support Extensions
8
RO
00h
47h
PCI Data
8
RO
00h
48h - FFh
Reserved
8
RO
00h
18h - 2Bh
31h - 3Bh
Note: RO = read only, RW = read/write
Am79C978
207
Control and Status Registers
Table 89.
Control and Status Registers (CSRs)
RAP
Addr
Symbol
Default Value
00
CSR0
uuuu 0004
Am79C978 Controller Status Register
R
01
CSR1
uuuu uuuu
Lower IADR: maps to location 16
S
02
CSR2
uuuu uuuu
Upper IADR: maps to location 17
S
03
CSR3
uuuu 0000
Interrupt Masks and Deferral Control
S
04
CSR4
uuuu 0115
Test and Features Control
R
05
CSR5
uuuu 0000
Extended Control and Interrupt 1
R
06
CSR6
uuuu uuuu
RXTX: RX/TX Encoded Ring Lengths
S
07
CSR7
0uuu 0000
Extended Control and Interrupt 1
R
08
CSR8
uuuu uuuu
LADRF0: Logical Address Filter — LADRF[15:0]
S
09
CSR9
uuuu uuuu
LADRF1: Logical Address Filter — LADRF[31:16]
S
10
CSR10
uuuu uuuu
LADRF2: Logical Address Filter — LADRF[47:32]
S
Comments
Use
11
CSR11
uuuu uuuu
LADRF3: Logical Address Filter — LADRF[63:48]
S
12
CSR12
uuuu uuuu
PADR0: Physical Address Register — PADR[15:0][
S
13
CSR13
uuuu uuuu
PADR1: Physical Address Register — PADR[31:16]
S
14
CSR14
uuuu uuuu
PADR2: Physical Address Register — PADR[47:32]
S
15
CSR15
see register
description
MODE: Mode Register
S
16
CSR16
uuuu uuuu
IADRL: Base Address of INIT Block Lower (Copy)
T
17
CSR17
uuuu uuuu
IADRH: Base Address of INIT Block Upper (Copy)
T
18
CSR18
uuuu uuuu
CRBAL: Current RCV Buffer Address Lower
T
19
CSR22
uuuu uuuu
CRBAU: Current RCV Buffer Address Upper
T
20
CSR20
uuuu uuuu
CXBAL: Current XMT Buffer Address Lower
T
21
CSR21
uuuu uuuu
CXBAU: Current XMT Buffer Address Upper
T
22
CSR22
uuuu uuuu
NRBAL: Next RCV Buffer Address Lower
T
23
CSR23
uuuu uuuu
NRBAU: Next RCV Buffer Address Upper
T
24
CSR24
uuuu uuuu
BADRL: Base Address of RCV Ring Lower
S
25
CSR25
uuuu uuuu
BADRU: Base Address of RCV Ring Upper
S
26
CSR26
uuuu uuuu
NRDAL: Next RCV Descriptor Address Lower
T
27
CSR27
uuuu uuuu
NRDAU: Next RCV Descriptor Address Upper
T
28
CSR28
uuuu uuuu
CRDAL: Current RCV Descriptor Address Lower
T
29
CSR29
uuuu uuuu
CRDAU: Current RCV Descriptor Address Upper
T
30
CSR30
uuuu uuuu
BADXL: Base Address of XMT Ring Lower
S
31
CSR31
uuuu uuuu
BADXU: Base Address of XMT Ring Upper
S
32
CSR32
uuuu uuuu
NXDAL: Next XMT Descriptor Address Lower
T
33
CSR33
uuuu uuuu
NXDAU: Next XMT Descriptor Address Upper
T
Note:
u = undefined value, R = Running register, S = Setup register, T = Test register; all default values are in hexadecimal format.
208
Am79C978
Control and Status Registers (Continued)
RAP
Addr
Symbol
Default Value
After H_RESET
34
CSR34
uuuu uuuu
CXDAL: Current XMT Descriptor Address Lower
T
35
CSR35
uuuu uuuu
CXDAU: Current XMT Descriptor Address Upper
T
36
CSR36
uuuu uuuu
NNRDAL: Next Next Receive Descriptor Address Lower
T
37
CSR37
uuuu uuuu
NNRDAU: Next Next Receive Descriptor Address Upper
T
38
CSR38
uuuu uuuu
NNXDAL: Next Next Transmit Descriptor Address Lower
T
39
CSR39
uuuu uuuu
NNXDAU: Next Next Transmit Descriptor Address Upper
T
40
CSR40
uuuu uuuu
CRBC: Current Receive Byte Count
T
41
CSR41
uuuu uuuu
CRST: Current Receive Status
T
42
CSR42
uuuu uuuu
CXBC: Current Transmit Byte
T
43
CSR43
uuuu uuuu
CXST: Current Transmit Status
T
44
CSR44
uuuu uuuu
NRBC: Next RCV Byte Count
T
45
CSR45
uuuu uuuu
NRST: Next RCV Status
T
46
CSR46
uuuu uuuu
POLL: Poll Time Counter
T
47
CSR47
uuuu uuuu
PI: Polling Interval
S
48
CSR48
uuuu uuuu
Reserved
49
CSR49
uuuu uuuu
Reserved
50
CSR50
uuuu uuuu
Reserved
51
CSR51
uuuu uuuu
Reserved
52
CSR52
uuuu uuuu
Reserved
53
CSR53
uuuu uuuu
Reserved
54
CSR54
uuuu uuuu
Reserved
55
CSR55
uuuu uuuu
Reserved
56
CSR56
uuuu uuuu
Reserved
57
CSR57
uuuu uuuu
Reserved
58
CSR58
see register
description
SWS: Software Style
S
59
CSR59
uuuu uuuu
Reserved
T
60
CSR60
uuuu uuuu
PXDAL: Previous XMT Descriptor Address Lower
T
61
CSR61
uuuu uuuu
PXDAU: Previous XMT Descriptor Address Upper
T
62
CSR62
uuuu uuuu
PXBC: Previous Transmit Byte Count
T
63
CSR63
uuuu uuuu
PXST: Previous Transmit Status
T
64
CSR64
uuuu uuuu
NXBAL: Next XMT Buffer Address Lower
T
65
CSR65
uuuu uuuu
NXBAU: Next XMT Buffer Address Upper
T
66
CSR66
uuuu uuuu
NXBC: Next Transmit Byte Count
T
67
CSR67
uuuu uuuu
NXST: Next Transmit Status
T
68
CSR68
uuuu uuuu
Reserved
69
CSR69
uuuu uuuu
Reserved
70
CSR70
uuuu uuuu
Reserved
Comments
Am79C978
Use
209
Control and Status Registers (Continued)
RAP
Addr
Symbol
Default Value
After H_RESET
71
CSR71
uuuu uuuu
Reserved
72
CSR72
uuuu uuuu
RCVRC: RCV Ring Counter
73
CSR73
uuuu uuuu
Reserved
74
CSR74
uuuu uuuu
XMTRC: XMT Ring Counter
75
CSR75
uuuu uuuu
Reserved
76
CSR76
uuuu uuuu
RCVRL: RCV Ring Length
77
CSR77
uuuu uuuu
Reserved
78
CSR78
uuuu uuuu
XMTRL: XMT Ring Length
79
CSR79
uuuu uuuu
Reserved
80
CSR80
uuuu 1410
DMATCFW: DMA Transfer Counter and FIFO Threshold
81
CSR81
uuuu uuuu
Reserved
82
CSR82
uuuu uuuu
Transmit Descriptor Pointer Address Lower
83
CSR83
uuuu uuuu
Reserved
84
CSR84
uuuu uuuu
DMABA: Address Register Lower
T
85
CSR85
uuuu uuuu
DMABA: Address Register Upper
T
86
CSR86
uuuu uuuu
DMABC: Buffer Byte Counter
T
87
CSR87
uuuu uuuu
Reserved
88
CSR88
262 5003
Chip ID Register Lower
T
89
CSR89
uuuu 262
Chip ID Register Upper
T
90
CSR90
uuuu uuuu
Reserved
91
CSR91
uuuu uuuu
Reserved
T
92
CSR92
uuuu uuuu
RCON: Ring Length Conversion
T
93
CSR93
uuuu uuuu
Reserved
94
CSR94
uuuu uuuu
Reserved
95
CSR95
uuuu uuuu
Reserved
96
CSR96
uuuu uuuu
Reserved
97
CSR97
uuuu uuuu
Reserved
98
CSR98
uuuu uuuu
Reserved
99
CSR99
uuuu uuuu
Reserved
100
CSR100
uuuu 0200
Bus Timeout
101
CSR101
uuuu uuuu
Reserved
102
CSR102
uuuu uuuu
Reserved
103
CSR103
uuuu 0105
Reserved
104
CSR104
uuuu uuuu
Reserved
105
CSR105
uuuu uuuu
Reserved
106
CSR106
uuuu uuuu
Reserved
107
CSR107
uuuu uuuu
Reserved
210
Comments
Use
T
T
S
S
S
S
S
Am79C978
Control and Status Registers (Concluded)
RAP
Addr
Symbol
Default Value
After H_RESET
108
CSR108
uuuu uuuu
Reserved
109
CSR109
uuuu uuuu
Reserved
110
CSR110
uuuu uuuu
Reserved
Comments
111
CSR111
uuuu uuuu
Reserved
112
CSR112
uuuu uuuu
Missed Frame Count
113
CSR113
uuuu uuuu
Reserved
114
CSR114
uuuu uuuu
Received Collision Count
115
CSR115
uuuu uuuu
Reserved
116
CSR116
0000 0000
OnNow Miscellaneous
117
CSR117
uuuu uuuu
Reserved
118
CSR118
uuuu uuuu
Reserved
Use
R
R
S
119
CSR119
uuuu 0105
Reserved
120
CSR120
uuuu uuuu
Reserved
121
CSR121
uuuu uuuu
Reserved
122
CSR226
uuuu 0000
Receive Frame Alignment Control
123
CSR237
uuuu uuuu
Reserved
124
CSR248
uuuu 0000
Test Register 1
T
125
CSR125
003c 0060
MAC Enhanced Configuration Control
T
126
CSR126
uuuu uuuu
Reserved
127
CSR127
uuuu uuuu
Reserved
Am79C978
S
211
Bus Configuration Registers
Writes to those registers marked as “Reserved” will have no effect. Reads from these locations will produce undefined values.
Table 90. Bus Configuration Registers (BCRs)
212
RAP
0
1
2
3
4
5
6
7
8
9
10-15
16
17
18
19
20
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Mnemonic
MSRDA
MSWRA
MC
Reserved
LED0
LED1
LED2
LED3
Reserved
FDC
Reserved
IOBASEL
IOBASEU
BSBC
EECAS
SWS
PCILAT
PCISID
PCISVID
SRAMSIZ
SRAMB
SRAMIC
EBADDRL
EBADDRU
EBDR
STVAL
MIICAS
MIIADDR
MIIMDR
PCIVID
Default
0005h
0005h
0002h
N/A
00C0h
0084h
0088h
0090h
N/A
0000h
N/A
N/A
N/A
9001h
0002h
0200h
FF06h
0000h
0000h
0000h
0000h
0000h
N/A
N/A
N/A
FFFFh
0000h
N/A
N/A
1022h
36
PMC_A
C811h
37
38
39
40
41
42
43
44
45
46
47
48
49
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
PMR1
PMR2
PMR3
LED4
PHY_SEL
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N/A
N/A
N/A
0082h
8000h
Name
Reserved
Reserved
Miscellaneous Configuration
Reserved
LED0 Status
LED1 Status
LED2 Status
LED3 Status
Reserved
Full-Duplex Control
Reserved
Reserved
Reserved
Burst and Bus Control
EEPROM Control and Status
Software Style
PCI Latency
PCI Subsystem ID
PCI Subsystem Vendor ID
SRAM Size
SRAM Boundary
SRAM Interface Control
Expansion Bus Address Lower
Expansion Bus Address Upper
Expansion Bus Data Port
Software Timer Value
PHY Control and Status
PHY Address
PHY Management Data
PCI Vendor ID
PCI Power Management Capabilities
(PMC) Alias Register
PCI DATA Register Zero Alias Register
PCI DATA Register One Alias Register
PCI DATA Register Two Alias Register
PCI DATA Register Three Alias Register
PCI DATA Register Four Alias Register
PCI DATA Register Five Alias Register
PCI DATA Register Six Alias Register
PCI DATA Register Seven Alias Register
Pattern Matching Register 1
Pattern Matching Register 2
Pattern Matching Register 3
LED4 Status
PHY Select
Am79C978
Programmability
User
EEPROM
No
No
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
No
No
No
No
Yes
Yes
Yes
No
Yes
No
Yes
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
No
Yes
No
Yes
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
10BASE-T PHY Management Registers
Writes to registers marked “Reserved” will be written as
zeros. Reads from these locations will produce undefined values.
Table 91.
10BASE-T PHY Management Registers (TBRs)
Register
Address
0
Symbol
TBR0
PHY Control Register
Default Value After
H_RESET
2500h
1
TBR1
PHY Status Register
7849h
2
TBR2
PHY_ID[31:16]
0000h
3
TBR3
PHY_ID[15:0]
6BA0h
4
TBR4
Auto-Negotiation Advertisement Register
03C1h
5
TBR5
Auto-Negotiation Link Partner Ability Register
0000h
6
TBR6
Auto-Negotiation Expansion Register
0004h
7
TBR7
Auto-Negotiation Next Page Register
2001h
8-15
TBR8-TBR15
16
TBR16
Interrupt Status and Enable Register
0000h
17
TBR17
PHY Control/Status Register
0001h
18
TBR18
Reserved
--
PHY Management Extension Register
--
Reserved
--
19
TBR19
20-23
TBR20-TBR23
24
TBR24
25-31
TBR25-TBR31
Name
Reserved
--
Summary Status Register
Reserved
0001h
--
Am79C978
213
1 Mbps HomePNA PHY Management Registers
Table 92. 1 Mbps HomePNA PHY Management Registers (HPRs)
Register
Address
0
Symbol
HPR0
MII Control Register
Default Value After
H_RESET
0400h
1
HPR1
MII Status Register
0841h
2
HPR2
MII PHY_ID Register
0000h
3
HPR3
MII PHY_ID Register
6B90h
4
HPR4
Auto-Negotiation Register
0021h
5
HPR5
Auto-Negotiation Register
0000h
6
HPR6
Auto-Negotiation Register
0000h
7
HPR7
Auto-Negotiation Register
0000h
8-15
HPR8-HPR15
16
HPR16
PHY Control Register
17
HPR17
Status and Control
18
HPR18
PHY TXCOMM Register
0000h
19
HPR19
PHY TXCOMM Register
0000h
20
HPR20
PHY RXCOMM Register
0000h
21
HPR21
PHY RXCOMM Register
0000h
22
HPR22
PHY AID Register
0000h
23
HPR23
PHY Noise Control Register
04FFh
24
HPR24
PHY Noise Control 2 Register
F4xxh
25
HPR25
PHY Noise Statistics Register
04D0h
26
HPR26
Event Status Register
0000h
27
HPR27
AID Control Register
1440h
28
HPR28
ISBI Control Register
2C1Ch
29
HPR29
TX Control Register
0444h
30
HPR30
Drive Level Control
x549h
31
HPR31
Analog Control
C000h
214
Name
Reserved
-0005h
--
Am79C978
REGISTER PROGRAMMING SUMMARY
Am79C978 Programmable Registers
Table 93.
Register
CSR0
Control and Status Registers
Contents
Status and control bits: (DEFAULT = 0004)
8000
4000
2000
1000
ERR
-CERR
MISS
0800
0400
0200
0100I
MERR
RINT
TINT
IDON
0080
0040
INTR
IENA
0020
0010
RXON
TXON
Lower IADR (Maps to CSR 16)
Upper IADR (Maps to CSR 17)
Interrupt masks and Deferral Control: (DEFAULT = 0)
8000
-0800
MERRM
0080 -4000
-0400
RINTM
0040 DXSUFLO
2000
-0200
TINTM
0020 LAPPEN
1000
MISSM
0100
IDONM
0010 DXMT2PD
CSR4
Interrupt masks, configuration and status bits: (DEFAULT = 0115)
8000
-0800
APAD_XMT
0080
UNITCMD
4000
DMAPLUS
0400
ASTRP_RCV
0040
UNIT
2000
-0200
MFCO
0020
RCVCCO
1000
TXDPOLL
0100
MFCOM
0010
RCVCCOM
CSR5
Extended Interrupt masks, configuration and status bits: (DEFAULT = 0XXX)
8000
TOKINTD
0800
SINT
0080
EXDINT
4000
LTINTEN
0400
SINTE
0040
EXDINTE
2000
-0200
-0020
MPPLBA
1000
-0100
-0010
MPINT
CSR7
Extended Interrupt masks, configuration and status bits: (DEFAULT = 0000)
8000
FASTSPND 0800
STINT
0080
MAPINT
4000
RXFRMTG
0400
STINTE
0040
MAPINTE
2000
RDMD
0200
MREINT
0020
MCCINT
1000
RXDPOLL
0100
MREINTE
0010
MCCINTE
CSR8 - CSR11 Logical Address Filter
CSR12 - CSR14 Physical Address Register
MODE: (DEFAULT = 0)
0008
0004
0002
TDMD
STOP
STRT
0001
INIT
0008
0004
0002
0001
EMBA
BSWP
---
0008
0004
0002
0001
TXSTRT
TXSTRTM
---
0008
0004
0002
0001
MPINTE
MPEN
MPMODE
SPND
0008
0004
0002
0001
MCCIINT
MCCIINTE
MIIPDTINT
MIIPDTNTE
0008
0004
0002
0001
DXMTFCS
LOOP
DTX
DRX
CSR1
CSR2
CSR3
CSR15
CSR47
CSR49
CSR58
bits [8:7] = PORTSEL, Port Selection
11
PHY Selected
10
Reserved
8000
PROM
0800
-4000
DRCVBC
0400
-2000
DRCVPA
0200
-1000
-0100
PORTSEL1
TXPOLLINT: Transmit Polling Interval
RXPOLLINT: Receive Polling Interval
Software Style (mapped to BCR20)
0080
0040
0020
0010
PORTSEL0
INTL
DRTY
FCOLL
bits [7:0] = SWSTYLE, Software Style Register.
8000
4000
2000
1000
0000
LANCE/PCnet-ISA
0002
-----
PCnet-32
0800
0400
0200
0100
-APERREN
-SSIZE32
Am79C978
0080
0040
0020
0010
-----
0008
0004
0002
0001
SWSTYLE3
SWSTYLE2
-SWSTYLE0
215
Am79C978 Programmable Registers (Continued)
Register
CSR76
CSR78
CSR80
Contents
RCVRL: RCV Descriptor Ring length
XMTRL: XMT Descriptor Ring length
FIFO threshold and DMA burst control (DEFAULT = 2810)
8000 Reserved
4000
Reserved
bits [13:12] = RCVFW, Receive FIFO Watermark
0000 Request DMA when 16 bytes are present
1000 Request DMA when 64 bytes are present
2000 Request DMA when 112 bytes are present
3000 Reserved
bits [11:10] = XMTSP, Transmit Start Point
0000 Start transmission after 20/36 (No SRAM/SRAM) bytes have been written
0400 Start transmission after 64 bytes have been written
0800 Start transmission after 128 bytes have been written
0C00 Start transmission after 220 max/Full Packet (No SRAM/SRAM with UFLO bit set) bytes
have been written
bits [9:8] = XMTFW, Transmit FIFO Watermark
0000 Start DMA when 16 write cycles can be made
0100 Start DMA when 32 write cycles can be made
0200 Start DMA when 64 write cycles can be made
CSR88~89
CSR112
CSR114
CSR116
CSR122
CSR124
CSR125
0300 Start DMA when 128 write cycles can be made
bits [7:0] = DMA Burst Register
Chip ID (Contents = v12626003; v = Version Number)
Missed Frame Count
Receive Collision Count
OnNow Miscellaneous
8000
-0800
-0080
PMAT
0008
RWU_DRIVER
4000
--
0400
--
0040
EMPPLBA
0004
RWU_GATE
2000
--
0200
PME_EN_OVR
0020
MPMAT
0002
RWU_POL
1000
-0100
LCDET
Receive Frame Alignment Control
8000
-0800
--
0010
MPPEN
0001
RST_POL
0080
--
0008
--
4000
--
0400
--
0040
--
0004
--
2000
--
0200
--
0020
--
0002
--
1000
-0100
-BMU Test Register (DEFAULT = 0000)
8000
-0800
--
0010
--
0001
RCVALGN
0080
--
0008
--
4000
--
0400
--
0040
--
0004
RPA
2000
--
0200
--
0020
--
0002
--
1000
-0100
-0010
MAC Enhanced Configuration Control (DEFAULT = 603c)
--
0001
--
bits [15:8] = IPG, InterPacket Gap (Default = 60xx, 96 bit times)
bits [8:0] = IFS1, InterFrame Space Part 1 (Default = xx3c, 60 bit times)
216
Am79C978
Am79C978 Programmable Registers (Continued)
Table 94. Bus Configuration Registers
RAP Addr Register
0
MSRDA
1
MSWRA
2
MC
4
5
6
7
9
16
17
18
19
20
LED0
LED1
LED2
LED3
FDC
IOBASEL
IOBASEU
BSBC
EECAS
Contents
Programs width of DMA read signal (DEFAULT = 5)
Programs width of DMA write signal (DEFAULT = 5)
Miscellaneous Configuration bits: (DEFAULT = 2)
8000
-0800
-0080
4000
--
0400
--
0040
INITLEVEL 0008
0004
--
2000
--
0200
--
0020
--
1000
-0100
APROMWE 0010
-Programs the function and width of the LED0 signal. (DEFAULT = 00C0)
8000
LEDOUT
0800
-0080
PSE
EADISEL
--
0002
--
ASEL 0001
0008
POWER
4000
LEDPOL
0400
--
0040
LNKSE
0004
RCVE
2000
LEDDIS
0200
MPSE
0020
RCVME
0002
SPEED
1000
100E
0100
FDLSE
0010
XMTE
Programs the function and width of the LED1 signal. (DEFAULT = 0084)
8000
LEDOUT
0800
-0080
PSE
0001
COLE
0008
POWER
4000
LEDPOL
0400
--
0040
LNKSE
0004
RCVE
2000
LEDDIS
0200
MPSE
0020
RCVME
0002
SPEED
1000
100E
0100
FDLSE
0010
XMTE
Programs the function and width of the LED2 signal. (DEFAULT = 0088)
8000
LEDOUT
0800
-0080
PSE
0001
COLE
0008
POWER
4000
LEDPOL
0400
--
0040
LNKSE
0004
RCVE
2000
LEDDIS
0200
MPSE
0020
RCVME
0002
SPEED
1000
100E
0100
FDLSE
0010
XMTE
Programs the function and width of the LED3 signal. (DEFAULT = 0090)
8000
LEDOUT
0800
-0080
PSE
0001
COLE
0008
POWER
4000
LEDPOL
0400
--
0040
LNKSE
0004
RCVE
2000
LEDDIS
0200
MPSE
0020
RCVME
0002
SPEED
1000
100E
0100
FDLSE
Full-Duplex Control. (DEFAULT= 0000)
8000
-0800
--
0010
XMTE
0001
COLE
0080
--
0008
--
4000
--
0400
--
0040
--
0004
FDRPAD
2000
--
0200
--
0020
--
0002
--
1000
-0100
-I/O Base Address Lower
I/O Base Address Upper
Burst Size and Bus Control (DEFAULT = 2101)
8000
ROMTMG3 0800
NOUFLO
0010
--
0001
FDEN
0080
DWIO
0008
--
4000
ROMTMG2 0400
--
0040
BREADE
0004
--
2000
ROMTMG1 0200
MEMCMD 0020
BWRITE
0002
--
--
0001
--
1000
ROMTMG0 0100
EXTREQ
EEPROM Control and Status (DEFAULT = 0002)
8000
PVALID
0800
--
0010
0080
--
0008
4000
PREAD
0400
--
0040
--
0004
ECS
2000
EEDET
0200
--
0020
--
0002
ESK
EEN
0001
EDI/EDO
1000
-0100
-0010
SWSTYLE Software Style (DEFAULT = 0000, maps to CSR 58)
Am79C978
--
217
Am79C978 Programmable Registers (Continued)
RAP Addr
22
Register
PCILAT
Contents
PCI Latency (DEFAULT = FF06)
bits [15:8] = MAX_LAT
bits [7:0] = MIN_GNT
25
SRAMSIZE
SRAM Size (DEFAULT = 0000)
bits [7:0] = SRAM_SIZE
26
SRAMBND
SRAM Boundary (DEFAULT = 0000)
bits [7:0] = SRAM_BND
27
SRAMIC
SRAM Interface Control (Default = 0000)
8000PTR TST
4000LOLATRX
bits [5:3] = EBCS, Expansion Bus Clock Source
0000 CLK pin, PCI clock
0008 Time Base Clock
0010 EBCLK pin, Expansion Bus Clock
bits [2:0] = CLK_FAC, Expansion Bus Clock Factor
0000 1/1 clock factor
0001 1/2 clock factor
0002 -0003 --
28
EPADDRL
Expansion Port Address Lower (Default = 0000)
29
EPADDRU
Expansion Port Address Upper (Default = 0000)
8000
4000
2000
1000
FLASH
LAINC
---
0800
0400
0200
0100
-----
0080
0040
0020
0010
30
EBDATA
Expansion Bus Data Port
31
STVAL
Software Timer Interrupt Value (DEFAULT = FFFF)
32
MIICAS
PHY Status and Control (DEFAULT = 0000)
8000
4000
2000
1000
33
MIIADDR
ANTST
MIIPD
FMDC1
FMDC0
0800
0400
0200
0100
APEP
APDW2
APDW1
APDW0
0080
0040
0020
0010
-----
0008
0004
0002
0001
EPADDRU3
EPADDRU2
EPADDRU1
EPADDRU0
DANAS
XPHYRST
XPHYANE
XPHYFD
0008
0004
0002
0001
XPHYSP
-MIILP
--
PHY Address (DEFAULT = 0000)
bits [9:5] = PHYAD, Physical Layer Device Address
bits [4:0] = REGAD, Auto-Negotiation Register Address
218
34
MIIMDR
35
PCI Vendor ID PCI Vendor ID Register (DEFAULT = 1022h)
PHY Data Port
36
PMC Alias
PCI Power Management Capabilities (DEFAULT = 0000)
37
DATA 0
PCI Data Register Zero Alias Register (DEFAULT = 0000)
38
DATA 1
PCI Data Register One Alias Register (DEFAULT = 0000)
39
DATA 2
PCI Data Register Two Alias Register (DEFAULT = 0000)
40
DATA 3
PCI Data Register Three Alias Register (DEFAULT = 0000)
41
DATA 4
PCI Data Register Four Alias Register (DEFAULT = 0000)
42
DATA 5
PCI Data Register Five Alias Register (DEFAULT = 0000)
43
DATA 6
PCI Data Register Six Alias Register (DEFAULT = 0000)
44
DATA 7
PCI Data Register Seven Alias Register (DEFAULT = 0000)
45
PMR 1
OnNow Pattern Matching Register 1
46
PMR 2
OnNow Pattern Matching Register 2
47
PMR 3
OnNow Pattern Matching Register 3
Am79C978
Am79C978 Programmable Registers (Concluded)
RAP Addr
48
49
Register
LED4
PHY_SEL
Contents
Programs the function and width of the LED3 signal. (DEFAULT = 0082)
8000
LEDOUT
0800
--
0080
PSE
0008
4000
LEDPOL
2000
LEDDIS
1000
100E
POWER
0400
--
0040
LNKSE
0004
RCVE
0200
MPSE
0020
RCVME
0002
SPEED
0100
FDLSE
0010
XMTE
0001
COLE
PHY Select
8000
10BASE_T PHY
8101
HomeRun PHY
8202
External PHY
Am79C978
219
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature. . . . . . . . . . . . . -65°C to +70°C
Temperature (TA) . . . . . . . . . . . . . . . . . .0°C to +70°C
Supply voltage
with respect to VSSB, VSS . . . . . . . . . –0.3 V to 3.63 V
Supply Voltages
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to
Absolute Maximum Ratings for extended periods may
affect device reliability.
All inputs within the range: . . . . . . VSS - 0.5 V to 5.5 V
(VDD, VDDR, VDD_PCI) . . . . . . . . . . . . . . . +3.3 V ±10%
Operating ranges define those limits between which
the functionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES unless otherwise
specified
Parameter
Parameter Description
Symbol
Digital I/O (Non-PCI Pins)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Test Conditions
Min
Max
Units
0.8
V
V
0.4
V
2.0
IOL1 = 4 mA
VOL
Output LOW Voltage
IOL2 = 6 mA
IOL3 = 12 mA (Note 1)
IOH1 = -4 mA
VOH
Output HIGH Voltage (Notes 2, 3)
IOZ
Output Leakage Current (Note 4)
IIX
Input Leakage Current (Note 5)
IIL
Input LOW Current (Note 6)
IIH
Input HIGH Current (Note 6)
PCI Bus Interface - 5 V Signaling
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZ
Output Leakage Current (Note 4)
IIL
Input LOW Current
IIH
Input HIGH Current
IIX_PME
Input Leakage Current (Note 7)
VOH
Output HIGH Voltage (Note 2)
VOL
Output LOW Voltage
IOH2 = -2 mA
(Note 3)
0 V <VOUT <VDD
0 V <VIN <VDD
VIN = 0 V; VDD = 3.6 V
VIN = 2.7 V; VDD = 3.6 V
0 V <VIN < VDD_PCI
VIN = 0.5 V
VIN = 2.7 V
0 V = < VIN < 5.5 V
IOH = -2 mA
IOL4 = 3 mA
2.4
V
-10
-10
-200
-50
10
10
-10
10
µA
µA
µA
µA
2.0
-0.5
-10
---1
2.4
5.5
0.8
10
-70
70
1
V
V
µA
µA
µA
µA
V
0.55
V
IOL2 = 6 mA (Note 1)
PCI Bus Interface - 3.3 V Signaling
VIH
Input HIGH Voltage
VIL
IOZ
IIL
IIH
IIX_PME
VOH
VOL
Input LOW Voltage
Output Leakage Current (Note 4)
Input LOW Current
Input HIGH Current
Input Leakage Current (Note 7)
Output HIGH Voltage (Note 2)
Output LOW Voltage
220
0.5 VDD_PCI
0 V < VOUT < VDD_PCI
VIN = 2.7 V
VIN = 2.7 V
0 V = < VIN < 3.6 V
IOH = -500 µA
IOL = 1500 µA
Am79C978
-0.5
-10
-10
-10
-1
2.4
VDD_PCI +
0.5
0.3 VDD_PCI
10
10
10
1
0.1 VDD_PCI
V
V
µA
µA
µA
µA
V
V
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES unless otherwise
specified (Concluded)
Parameter
Parameter Description
Symbol
Pin Capacitance
CIN
Pin Capacitance
CCLK
CLK Pin Capacitance
CIDSEL
IDSEL Pin Capacitance
LPIN
Pin Inductance
Power Supply Current (Note 11)
IDD
Dynamic Current
IDD_WU1
Wake-up current when the device is
in the D1, D2, or D3 state and the
PCI bus is in the B0 or B1 state.
IDD_WU2
Wake-up current when the device is
in the D2 or D3 state and the PCI bus
is in the B2 or B3 state.
IDD_WU3
Wake-up current when the device is
in the D2 or D3 state and the PCI bus
is in the B2 or B3 state.
IDD_WU4
Wake-up current when the device is
in the D2 or D3 state and the PCI bus
is in the B2 or B3 state.
IDD_S
Static IDD
Test Conditions
FC = 1 MHz (Note 8)
FC = 1 MHz (Notes 8,9)
Fc = 1 MHz (Notes 8, 10
Fc = 1 MHz (Note 8)
PCI CLK at 33 MHz
PCI CLK at 33 MHz, device in Magic
Packet or OnNow mode, receiving
non-matching packets in 10BASE-T
mode
PCI CLK LOW, PG LOW, device at
Magic Packet or OnNow mode,
receiving non-matching packets in
10BASE-T mode
PCI CLK at 33 MHz, device in Magic
Packet or OnNow mode, receiving
non-matching packets in HomePNA
mode
PCI CLK LOW, PG LOW, device at
Magic Packet or OnNow mode,
receiving non-matching packets in
HomePNA mode
PCI CLK, RST, and TBC_EN pin
HIGH.
Min
5
Max
Units
10
12
8
20
pF
pF
pF
nH
300
mA
110
mA
80
mA
110
mA
80
mA
100
mA
Notes:
1. IOL2 applies to DEVSEL, FRAME, INTA, IRDY, PERR, SERR, STOP, TRDY, EECS, EEDI, EBUA_EBA[7:0], EBDA[15:8],
EBD[7:0], EROMCS, AS_EBOE, EBWE, and PHY_RST.
IOL3 applies to LED0, LED1, LED2, LED3, and LED4.
IOL4 applies to AD[31:0], C/BE[3:0], PAR, and REQ pins in 5 V signalling environment.
2. VOH does not apply to open-drain output pins.
3. IOH2 applies to all other outputs.
4. IOZ applies to all output and bidirectional pins, except the PME pin. Tests are performed at VIN = 0 V and at VDD only.
5. IIX applies to all input pins except PME, TDI, TCLK, and TMS pins.
6. IIL and IIH apply to the TDI, TCLK, and TMS pins.
7. IIX_PME applies to the PME pin only. Tests are performed at VIN = 0 V and 5.5 V only.
8. Parameter not tested. Value determined by characterization.
9. CCLK applies only to the CLK pin.
10. CIDSEL applies only to the IDSEL pin.
11. Power supply current values listed here are preliminary estimates and are not guaranteed.
Am79C978
221
SWITCHING CHARACTERISTICS: BUS INTERFACE
Parameter
Parameter Name
Symbol
Clock Timing
FCLK
CLK Frequency
tCYC
CLK Period
tHIGH
CLK High Time
tLOW
CLK Low Time
tFALL
CLK Fall Time
Test Condition
@ 1.5 V for 5 V signaling
@ 0.4 VDD for 3.3 V signaling
@ 2.0 V for 5 V signaling
@ 0.4 VDD for 3.3 signaling
@ 0.8 V for 5 V signaling
@ 0.3 VDD for 3.3 V signaling
over 2 V p-p for 5 V signaling
over 0.4 VDD for 3.3 V signaling
Min
Max
Unit
0
33
MHz
30
_
ns
12
ns
12
ns
1
4
V/ns
1
4
V/ns
2
11
ns
2
12
ns
(Note 1)
over 2 V p-p for 5 V signaling
tRISE
CLK Rise Time
over 0.4 VDD for 3.3 V signaling
(Note 1)
Output and Float Delay Timing
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, DEVSEL, PERR,
tVAL
SERR
Valid Delay
tVAL (REQ)
REQ Valid Delay
AD[31:00], C/BE[3:0], PAR, FRAME,
tON
IRDY, TRDY, STOP, DEVSEL Active
Delay
AD[31:00], C/BE[3:0], PAR, FRAME,
tOFF
IRDY, TRDY, STOP, DEVSEL Float
Delay
Setup and Hold Timing
AD[31:00], C/BE[3:0], PAR, FRAME,
tSU
IRDY, TRDY, STOP, DEVSEL, IDSEL
Setup Time
AD[31:00], C/BE[3:0], PAR, FRAME,
tH
IRDY, TRDY, STOP, DEVSEL, IDSEL
Hold Time
tSU (GNT)
GNT Setup Time
tH (GNT)
GNT Hold Time
222
2
ns
28
Am79C978
ns
7
ns
0
ns
10
0
ns
ns
SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED)
Parameter
Symbol
Parameter Name
Test Condition
Min
Max
Unit
EEPROM Timing
fEESK
EESK Frequency
tHIGH (EESK)
EESK High Time
(Note 2)
780
650
kHz
tLOW (EESK)
EESK Low Time
780
tVAL (EEDI)
EEDI Valid Output Delay from EESK (Note 2)
-15
15
ns
tVAL (EECS)
EECS Valid Output Delay from EESK (Note 2)
-15
15
ns
tLOW (EECS)
EECS Low Time
1550
ns
tSU (EEDO)
EEDO Setup Time to EESK
(Note 2)
50
ns
tH (EEDO)
EEDO Hold Time from EESK
(Note 2)
0
ns
ns
ns
JTAG (IEEE 1149.1) Test Signal Timing
tJ1
TCK Frequency
10
tJ2
TCK Period
100
ns
tJ3
TCK High Time
@ 2.0 V
45
ns
tJ4
TCK Low Time
@ 0.8 V
45
tJ5
TCK Rise Time
tJ6
TCK Fall Time
tJ7
TDI, TMS Setup Time
8
tJ8
TDI, TMS Hold Time
10
tJ9
TDO Valid Delay
3
tJ10
TDO Float Delay
tJ11
All Outputs (Non-Test) Valid Delay
tJ12
All Outputs (Non-Test) Float Delay
tJ13
All Inputs (Non-Test)) Setup Time
8
ns
tJ14
All Inputs (Non-Test) Hold Time
7
ns
3
MHz
ns
4
ns
4
ns
ns
ns
30
ns
50
ns
25
ns
36
ns
Notes:
1. Not tested; parameter guaranteed by design characterization.
2. Parameter value is given for automatic EEPROM read operation. When EEPROM port (BCR19) is used to access the EEPROM, software is responsible for meeting EEPROM timing requirements.
Am79C978
223
SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED)
10BASE-T Mode
Symbol
Parameter Description
VOUT
Minimum
Maximum
Unit
Output Voltage on TX± (peak)
1.55
1.98
V
VDIFF
Input Differential Squelch
Assert on RX± (peak)
300
520
mV
VDIFF
Input Differential De-Assert
Voltage on RX± (peak)
150
300
mV
Input Leakage Current
-300
300
µa
IIX
Test Conditions
Note: VOUT reflects output levels prior to 1:√2 transformer stage.
Power Supply Current
Symbol
ICC
(1 Mbps)
ICC
(10 Mbps)
224
Parameter Description
Test Conditions
Maximum
Unit
1Mbps mode on TX± and RX±.
Outputs driving load.
VDD= Maximum
480
mA
10BASE-T mode on TX± and RX±.
Outputs driving load.
VDD= Maximum
480
mA
Am79C978
SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED)
External Clock (XTAL) Timing Specifications
Clock Timing
No.
Symbol
Parameter Description
Min
Max
Unit
1
tPER
Cycle time
49.995
50.005
ns
2
tPWH
Cycle high time
0.4* Tcycle
0.6*Tcycle
ns
3
tPWL
Clock low time
0.4*Tcycle
0.6*Tcycle
ns
Min
Max
Unit
16.665
16.669
ns
External Clock (Oscillator) Timing Specification
Clock Timing
No.
Symbol
Parameter Description
1
tPER
Cycle time
2
tPWH
Cycle high time
0.4* Tcycle
0.6*Tcycle
ns
3
tPWL
Clock low time
0.4*Tcycle
0.6*Tcycle
ns
1
2
3
XCLK
22206B-55
Figure 52. Clock Timing
PMD Interface
PECL
No.
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
160
tR (Note 1)
TX+, TX- Rise Time
PECL Load
0.5
3
ns
161
tF (Note 1)
TX+, TX- Fall Time
PECL Load
0.5
3
ns
162
tSK (Note 1) TX+ to TX- skew
PECL Load
--
+200
ps
163
tS
SDI setup time to XCLK high
--
7
--
ns
164
tH
SDI hold time to XCLK high
--
5
--
ns
Note:
1. Not included in the production test.
161
160
80%
20%
TX+,TX–
TX+
TX–
162
Figure 53.
22206B-56
PMD Interface Timing (PECL)
Am79C978
225
SWITCHING CHARACTERISTICS: BUS INTERFACE (CONCLUDED)
10BASE-T
Symbol
tTETD
tPWKRD
Parameter Description
Test Conditions
Transmit End of Transmission
RX± Pulse Width Maintain/Turn Off Threshold
|VIN| > |VTHS| (Note 1)
Min
Max
Unit
250
375
ns
136
200
ns
Note: RX± pulses narrower than tPWDRD (min) will maintain internal Carrier Sense on. RX± pulses wider than tPWKRD (max) will
turn internal Carrier Sense off.
tTETD
TX±
22206B-57
Figure 54.
10 Mbps Transmit (TX±) Timing Diagram
t(PWKRD)
t(PWKRD)
VTSQ+
RX±
VTSQtPWKRD
22206B-58
Figure 55. 10 Mbps Receive (RX±) Timing Diagram
226
Am79C978
SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE
Parameter
Symbol
Transmit Timing
tTVAL
Parameter Name
TX_EN and TXD valid from
↑ TX_CLK
Test Condition
Min
Max
Unit
measured from Vilmax = 0.8 V or
measured from Vihmin = 2.0V
0
25
ns
(Note 1)
Receive Timing
tRSU
tRH
RX_DV, RX_ER, RXD setup to
↑ RX_CLK
RX_DV, RX_ER, RXD hold to
↑ RX_CLK
Management Cycle Timing
tMHIGH
MDC Pulse Width HIGH Time
tMLOW
MDC Pulse Width LOW Time
tMCYC
MDC Cycle Period
tMSU
MDIO setup to ↑ MDC
measured from Vilmax = 0.8 V or
measured from Vihmin = 2.0V
10
ns
10
ns
160
160
400
ns
ns
ns
10
ns
10
ns
tMCYC tMSU
ns
(Note 1)
measured from Vilmax = 0.8 V or
measured from Vihmin = 2.0V
(Note 1)
CLOAD = 390 pf
CLOAD = 390 pf
CLOAD = 390 pf
CLOAD = 470 pf,
measured from Vilmax = 0.8 V or
measured from Vihmin = 2.0V
(Note 1)
CLOAD = 470 pf,
tMH
MDIO hold to ↑ MDC
measured from Vilmax = 0.8 V or
measured from Vihmin = 2.0V
(Note 1)
CLOAD = 470 pf,
tMVAL
MDIO valid from ↑ MDC
measured from Vilmax = 0.8 V or
measured from Vihmin = 2.0V,
(Note 1)
Notes:
1. MDIO valid measured at the exposed mechanical Media Independent Interface.
2. TXCLK and RXCLK frequency and timing parameters are defined for the external physical layer transceiver as defined in the
IEEE 802.3u standard. They are not replicated here.
Am79C978
227
SWITCHING WAVEFORMS
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUITS
IOL
VTHRESHOLD
Sense Point
CL
IOH
22206B-59
Figure 56.
228
Normal and Tri-State Outputs
Am79C978
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE
tHIGH
2.4 V
2.0 V
CLK
2.0 V
1.5 V
tLOW
1.5 V
0.8 V
0.8 V
0.4 V
tCYC
22206B-60
Figure 57. CLK Waveform for 5 V Signaling
tHIGH
0.6 VDD_PCI
0.5 VDD_PCI
CLK
0.5 VDD_PCI
0.4 VDD_PCI
tLOW
0.4 VDD_PCI
0.3 VDD_PCI
0.3 VDD_PCI
0.2 VDD_PCI
tCYC
22206B-61
Figure 58. CLK Waveform for 3.3 V Signaling
Tx
Tx
CLK
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP,
DEVSEL, IDSEL
tSU
tH
tSU(GNT)
tH(GNT)
GNT
22206B-62
Figure 59. Input Setup and Hold Timing
Am79C978
229
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (CONTINUED)
Tx
Tx
Tx
CLK
tVAL
AD[31:00] C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP, DEVSEL,
PERR, SERR
MIN
MAX
Valid n
Valid n+1
tVAL(REQ)
MIN
REQ
MAX
Valid n+1
Valid n
22206B-63
Figure 60.
Output Valid Delay Timing
Tx
Tx
Tx
CLK
tON
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP,
DEVSEL, PERR
Valid n
tOFF
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP,
DEVSEL, PERR
Valid n
22206B-64
Figure 61.
Output Tri-State Delay Timing
EESK
EECS
EEDI
0
1
1
A6
A5
A4
A3
A2
A1
22206B-65
A0
EEDO
D15 D14 D13
D2
D1
D0
22206B-65
Figure 62.
230
EEPROM Read Functional Timing
Am79C978
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (CONTINUED)
tHIGH (EESK)
tLOW (EESK)
tSU (EEDO)
EESK
tH (EEDO)
tVAL (EEDI,EECS)
Stable
EEDO
tLOW (EECS)
EECS
EEDI
22206B-66
Figure 63.
Automatic PREAD EEPROM Timing
tJ3
2.0 V
TCK
tJ4
1.5 V
0.8 V
2.0 V
1.5 V
0.8 V
tJ5
tJ6
tJ2
22206B-67
Figure 64.
JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling
Am79C978
231
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (CONCLUDED)
tJ2
TCK
tJ7
tJ8
TDI, TMS
tJ9
TDO
tJ12
tJ11
Output
Signals
tJ13
tJ14
Input
Signals
22206B-68
Figure 65. JTAG (IEEE 1149.1) Test Signal Timing
232
Am79C978
SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE
Vihmin
Vilmax
TX_CLK
tTVAL
Vihmin
Vilmax
TXD[3:0],
TX_EN
22206B-69
Figure 66. Transmit Timing
Vihmin
Vilmax
RX_CLK
tRSU
RXD[3:0],
RX_ER,
RX_DV
tRH
Vihmin
Vilmax
22206B-70
Figure 67. Receive Timing
tMHIGH
2.4
MDC
2.0 V
1.5 V
0.8 V
tMLOW
0.4
2.0 V
1.5 V
0.8 V
tMCYC
22206B-71
Figure 68. MDC Waveform
Am79C978
233
SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE (CONCLUDED)
Vihmin
Vilmax
MDC
tMSU
tMH
Vihmin
Vilmax
MDIO
22206B-72
Figure 69.
Management Data Setup and Hold Timing
Vihmin
Vilmax
MDC
tTMVAL
Vihmin
Vilmax
MDIO
22206B-73
Figure 70. Management Data Output Valid Delay Timing
234
Am79C978
PHYSICAL DIMENSIONS*
PQL144
Thin Quad Flat Pack (measured in millimeters)
0.20
0.20
0.20
C
A-B
M
M
C
H
A-B
A-B
0.05 MM/MM
D
S
S
D
S
0.13 R. Min.
0.20 R. Max.
S
D
Odd Lead Sides
144
Gage Plane
0.17
0.27
0.25
1
0.13 R. Min.
0.20 Min.
0.45
0.75
21.80
22.20
19.80
20.20
Detail X
Even Lead Sides
0.25 BSC
0.17
0.27
With Lead Finish
0.17
0.23
36
0.09
0.16
0.09
0.20
Detail Y
See Detail A
Base Metal
19.80
20.20
0.20
M
H A S
-B
D
See Detail A
S
0.05
S
0° Min.
A-B
0.05 MM/MM
21.80
22.20
0.20
M
C
A-B
S
D
0.05
0.15
1.60
MAX
S
Seating Plane
Detail Y
11° – 13°
Detail X
1.35
1.45
0.17
0.27
0° – 7°
0.08
0.08
C
M C A-B S D S
1.60 MAX
0.50 BSC
16-038-PQT-1_AN
EP 137
8-11-98 lv
11° – 13°
1.00 REF.
*For reference only. BSC is an ANSI standard for Basic Space Centering.
Am79C978
235
PQR160
Plastic Quad Flat Pack (measured in millimeters)
Pin 160
25.35
REF
27.90
28.10
31.00
31.40
Pin 120
Pin 1 I.D.
25.35
REF
27.90
28.10
31.00
31.40
Pin 40
Pin 80
3.20
3.60
0.65 BASIC
0.25
Min
3.95
MAX
SEATING PLANE
16-038-PQR-1
PQR160
12-22-95 lv
*For reference only. BSC is an ANSI standard for Basic Space Centering.
236
Am79C978
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations
or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no
liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of
merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a
situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make
changes to its products at any time without notice.
© 1999 Advanced Micro Devices, Inc.
All rights reserved.
Trademarks
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Auto-Poll, MACE, Magic Packet, PCnet, PCnet-FAST, PCnet-FAST+, PCnet-Home, PCnet-ISA, PCnet-ISA+, PCnet-ISA II, PCnet-32 are trademarks of Advanced Micro Devices, Inc.
RLL25 is a trademark of Tut Systems, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
238
Am79C978
APPENDIX A
Alternative Method for
Initialization
The controller may be initialized by performing I/O
writes only. That is, data can be written directly to the
appropriate control and status registers (CSR instead
of reading from the initialization block in memory). The
registers that must be written are shown in Table A-1.
Table A-1.
These register writes are followed by writing the
START bit in CSR0.
Registers for Alternative Initialization Method (Note 1)
Control and Status Register
Comment
CSR2
IADR[31:16] (Note 2)
CSR8
LADRF[15:0]
CSR9
LADRF[31:16]
CSR10
LADRF[47:32]
CSR11
LADRF[63:48]
CSR12
PADR[15:0] (Note 3)
CSR13
PADR[31:16] (Note 3)
CSR14
PADR[47:32] (Note 3)
CSR15
MODE
CSR24-25
BADR
CSR30-31
BADX
CSR47
TXPOLLINT
CSR49
RXPOLLINT
CSR76
RCVRL
CSR78
XMTRL
Note:
1. The INIT bit must not be set or the initialization block will be accessed instead.
2. Needed only if SSIZE32 =0.
3. Needed only if the physical address is different from the one stored in EEPROM or if there is no EEPROM present.
Am79C978
A-1
A-2
Am79C978
APPENDIX B
Look-Ahead Packet Processing
(LAPP) Concept
INTRODUCTION
A driver for the controller would normally require that
the CPU copy receive frame data from the controllers
buffer space to the applications buffer space after the
entire frame has been received by the controller. For
applications that use a ping-pong windowing style, the
traffic on the network will be halted until the current
frame has been completely processed by the entire application stack. This means that the time between last
byte of a receive frame arriving at the client’s Ethernet
controller and the client’s transmission of the first byte
of the next outgoing frame will be separated by:
1. The time that it takes the client’s CPU interrupt procedure to pass software control from the current
task to the driver,
2. Plus the time that it takes the client driver to pass
the header data to the application and request an
application buffer,
3. Plus the time that it takes the application to generate the buffer pointer and then return the buffer
pointer to the driver,
4. Plus the time that it takes the client driver to transfer
all of the frame data from the controller’s buffer
space into the application’s buffer space and then
call the application again to process the complete
frame,
5. Plus the time that it takes the application to process
the frame and generate the next outgoing frame,
and
6. Plus the time that it takes the client driver to set up
the descriptor for the controller and then write a
TDMD bit to CSR0.
The sum of these times can often be about the same
as the time taken to actually transmit the frames on the
wire, thereby, yielding a network utilization rate of less
than 50 percent.
An important thing to note is that the controller’s data
transfers to its buffer space are such that the system
bus is needed by the controller for approximately 4 percent of the time. This leaves 96 percent of the system
bus bandwidth for the CPU to perform some of the interframe operations in advance of the completion of
network receive activity, if possible. The question then
becomes: how much of the tasks that need to be performed between reception of a frame and transmission
of the next frame can be performed before the reception of the frame actually ends at the network, and how
can the CPU be instructed to perform these tasks during the network reception time.
The answer depends upon exactly what is happening
in the driver and application code, but the steps that
can be performed at the same time as the receive data
are arriving include as much as the first three steps and
part of the fourth step shown in the sequence above.
By performing these steps before the entire frame has
arrived, the frame throughput can be substantially
increased.
A good increase in performance can be expected when
the first three steps are performed before the end of the
network receive operation. A much more significant
performance increase could be realized if the controller
could place the frame data directly into the application’s buffer space; (i.e., eliminate the need for step 4.)
In order to make this work, it is necessary that the application buffer pointer be determined before the frame
has completely arrived, then the buffer pointer in the
next descriptor for the receive frame would need to be
modified in order to direct the controller to write directly
to the application buffer. More details on this operation
will be given later.
An alternative modification to the existing system can
gain a smaller but still significant improvement in performance. This alternative leaves step 4 unchanged in
that the CPU is still required to perform the copy operation, but is allows a large portion of the copy operation
to be done before the frame has been completely received by the controller, i.e., the CPU can perform the
copy operation of the receive data from the controller’s
buffer space into the application buffer space before
the frame data has completely arrived from the network. This allows the copy operation of step 4 to be
performed concurrently with the arrival of network data,
rather than sequentially, following the end of network
receive activity.
OUTLINE OF LAPP FLOW
This section gives a suggested outline for a driver that
utilizes the LAPP feature of the controller.
Am79C978
B-1
Note: The labels in the following text are used as references in the timeline diagram that follows (Figure
B-1).
Setup
The driver should set up descriptors in groups of three,
with the OWN and STP bits of each set of three descriptors to read as follows: 11b, 10b, 00b.
An option bit (LAPPEN) exists in CSR3, bit position 5;
the software should set this bit. When set, the LAPPEN
bit directs the controller to generate an INTERRUPT
when STP has been written to a receive descriptor by
the controller.
ber 2 will be sufficient or not for this frame, but it has no
way to tell except by trying to move the entire message
into that space. Only when the message does not fit will
it signal a buffer error condition--there is no need to
panic at this point that it discovers that it does not yet
own descriptor number 3.
S2
The first task of the drivers interrupt service
routing is to collect the header information
from the controller’s first buffer and pass it to
the application.
S3
The application will return an application buffer
pointer to the driver. The driver will add an offset to the application data buffer pointer, since
the controller will be placing the first portion of
the message into the first and second buffers.
(the modified application data buffer pointer
will only be directly used by the controller when
it reaches the third buffer.) The driver will place
the modified data buffer pointer into the final
descriptor of the group (#3) and will grant ownership of this descriptor to the controller.
C5
Interleaved with S2, S3, and S4 driver activity,
the controller will write frame data to buffer
number 2.
S4
The driver will next proceed to copy the contents of the controller’s first buffer to the beginning of the application space. This copy will be
to the exact (unmodified) buffer pointer that
was passed by the application.
S5
After copying all of the data from the first buffer
into the beginning of the application data
buffer, the driver will begin to poll the ownership bit of the second descriptor. The driver is
waiting for the controller to finish filling the second buffer.
C6
At this point, knowing that it had not previously
owned the third descriptor and knowing that
the current message has not ended (there is
more data in the FIFO), the controller will make
a last ditch lookahead to the final (third) descriptor. This time the ownership will be TRUE
(i.e., the descriptor belongs tot he controller),
because the driver wrote the application
pointer into this descriptor and then changed
the ownership to give the descriptor to the controller back at S3. Note that if steps S1, S2,
and S3 have not completed at this time, a
BUFF error will result.
C7
After filling the second buffer and performing
the last chance lookahead to the next descriptor, the controller will write the status and
change the ownership bit of descriptor number
2.
Flow
The controller polls the current receive descriptor at
some point in time before a message arrives. The controller determines that this receive buffer is OWNed by
the controller and it stores the descriptor information to
be used when a message does arrive.
N0
Frame preamble appears on the wire, followed
by SFD and destination address.
N1
The 64th byte of frame data arrives from the
wire. This causes the controller to begin frame
data DMA operations to the first buffer.
C0
When the 64th byte of the message arrives,
the controller performs a lookahead operation
to the next receive descriptor. This descriptor
should be owned by the controller.
C1
The controller intermittently requests the bus
to transfer frame data to the first buffer as it arrives on the wire.
S1
The driver remains idle.
C2
When the controller has completely filled the
first buffer, it writes status to the first descriptor.
C3
When the first descriptor for the frame has
been written, changing ownership from the
controller to the CPU, the controller will generate an SRP INTERRUPT. (This interrupt appears as a RINT interrupt in CSR0).
S1
The SRP INTERRUPT causes the CPU to
switch tasks to allow the controller’s driver to
run.
C4
During the CPU interrupt-generated task
switching, the controller is performing a lookahead operation to the third descriptor. At this
point in time, the third descriptor is owned by
the CPU.
Note: Even though the third buffer is not owned by the
controller, existing AMD Ethernet controllers will continue to perform data DMA into the buffer space that the
controller already owns (i.e., buffer number 2). The
controller does not know if buffer space in buffer num-
B-2
Am79C978
S6
C8
N2
After the ownership of descriptor number 2 has
been changed by the controller, the next driver
poll of the second descriptor will show ownership granted to the CPU. The driver now copies the data from buffer number 2 into the
middle section of the application buffer space.
This operation is interleaved with the C7 and
C8 operations.
The controller will perform data DMA to the last
buffer, whose pointer is pointing to application
space. Data entering the least buffer will not
need the infamous double copy that is required
by existing drivers, since it is being placed directly into the application buffer space.
The message on the wire ends.
S7
When the driver completes the copy of buffer
number 2 data to the application buffer space,
it begins polling descriptor number 3.
C9
When the controller has finished all data DMA
operations, it writes status and changes ownership of descriptor number 3.
S8
The driver sees that the ownership of descriptor number 3 has changed, and it calls the application to tell the application that a frame has
arrived.
S9
The application processes the received frame
and generates the next TX frame, placing it
into a TX buffer.
S10
The driver sets up the TX descriptor for the
controller.
Am79C978
B-3
Ethernet
Wire
activity:
Ethernet
Controller
activity:
Software
activity:
S10: Driver sets up TX descriptor.
S9: Application processes packet, generates TX packet.
S8: Driver calls application
to tell application that
packethas arrived.
}
C9: Controller writes descriptor #3.
S7: Driver polls descriptor of buffer #3.
N2:EOM C8: Controller is performing intermittent
bursts of DMA to fill data buffer #3.
Buffer
#3
C6: "Last chance" lookahead to
descriptor #3 (OWN).
S4: Driver copies data from buffer #1 to the application
buffer.
S3: Driver writes modified application
pointer to descriptor #3.
Packet data arriving
C5: Controller is performing intermittent
bursts of DMA to fill data buffer #2
C4: Lookahead to descriptor #3 (OWN).
C3: SRP interrupt is
generated.
S5: Driver polls descriptor #2.
}
Buffer
#2
}
C7: Controller writes descriptor #2.
S6: Driver copies data from buffer #2 to the application
buffer.
S2: Driver call to application to
get application buffer pointer.
S1: Interrupt latency.
}
C2: Controller writes descriptor #1.
C1: Controller is performing intermittent
bursts of DMA to fill data buffer #1.
Buffer
#1
S0: Driver is idle.
C0: Lookahead to descriptor #2.
{
N1: 64th byte of packet
data arrives.
N0: Packet preamble, SFD
and destination address
are arriving.
22206B-B1
Figure B-1. LAPP Timeline
B-4
Am79C978
LAPP Software Requirements
Software needs to set up a receive ring with descriptors
formed into groups of three. The first descriptor of each
group should have OWN = 1 and STP = 1, the second
descriptor of each group should have OWN = 1 and
STP = 0. The third descriptor of each group should
have OWN = 0 and STP = 0. The size of the first buffer
(as indicated in the first descriptor) should be at least
equal to the largest expected header size; however, for
maximum efficiency of CPU utilization, the first buffer
size should be larger than the header size. It should be
equal to the expected number of message bytes,
minus the time needed for interrupt latency and minus
the application call latency, minus the time needed for
the driver to write to the third descriptor, minus the time
Descriptor
#1
OWN = 1 STP = 1
SIZE = A-(S1+S2+S3+S4+S6)
Descriptor
#2
OWN = 1 STP = 0
SIZE = S1+S2+S3+S4
Descriptor
#3
OWN = 0 STP = 0
SIZE = S6
Descriptor
#4
OWN = 1 STP = 1
SIZE = A-(S1+S2+S3+S4+S6)
Descriptor
#5
OWN = 1 STP = 0
SIZE = S1+S2+S3+S4
Descriptor
#6
OWN = 0 STP = 0
SIZE = S6
Descriptor
#7
OWN = 1 STP = 1
SIZE = A-(S1+S2+S3+S4+S6)
Descriptor
#8
OWN = 1 STP = 0
SIZE = S1+S2+S3+S4
Descriptor
#9
OWN = 0 STP = 0
SIZE = S6
needed for the drive to copy data from buffer number 2
to the application buffer space. Note that the time
needed for the copies performed by the driver depends
upon the sizes of the second and third buffers, and that
the sizes of the second and third buffers need to be set
according to the time needed for the data copy operations. This means that an iterative self-adjusting mechanism needs to be placed into the software to
determine the correct buffer sizing for optimal operation. Fixed values for buffer sizes may be used; in such
a case, the LAPP method will still provide a significant
performance increase, but the performance increase
will not be maximized.
Figure B-2 illustrates this setup for a receive ring size
of 9.
A = Expected message size in bytes
S1 = Interrupt latency
S2 = Application call latency
S3 = Time needed for driver to write
to third descriptor
S4 = Time needed for driver to copy
data from buffer #1 to
application buffer space
S6 = Time needed for driver to copy
data from buffer #2 to
application buffer space
Note that the times needed for tasks S1,
S2, S3, S4, and S6 should be divided by
0.8 microseconds to yield an equivalent
number of network byte times before
subtracting these quantities from the
expected message size A.
22206B-B2
Figure B-2. LAPP 3 Buffer Grouping
LAPP Rules for Parsing Descriptors
When using the LAPP method, software must use a
modified form of descriptor parsing as follows:
n Software will examine OWN and STP to determine
where an RCV frame begins. RCV frames will only
begin in buffers that have OWN = 0 and STP = 1.
n Software shall assume that a frame continues until
it finds either ENP = 1 or ERR = 1.
n Software must discard all descriptors with OWN = 0
and STP = 0 and move to the next descriptor when
searching for the beginning of a new frame; ENP and
ERR should be ignored by software during this
search.
n Software cannot change an STP value in the receive
descriptor ring after the initial setup of the ring is
complete, even if software has ownership of the STP
Am79C978
B-5
descriptor, unless the previous STP descriptor in the
ring is also OWNED by the software.
When LAPPEN = 1, then hardware will use a modified
form of descriptor parsing as follows:
n The controller will examine OWN and STP to determine where to begin placing an RCV frame. A new
RCV frame will only begin in a buffer that has
OWN = 1 and STP =1.
n The controller will always obey the OWN bit for determining whether or not it may use the next buffer
for a chain.
used for receive purposes by the controller, and the
driver must recognize this. (The driver will recognize
this if it follows the software rules.)
The controller will ignore all descriptors with OWN = 0
and STP = 0 and move to the next descriptor when
searching for a place to begin a new frame. In other
words, the controller is allowed to skip entries in the
ring that it does not own, but only when it is looking for
a place to begin a new frame.
Some Examples of LAPP Descriptor
Interaction
n The controller will always mark the end of a frame
with either ENP = 1 or ERR = 1.
Choose an expected frame size of 1060 bytes. Choose
buffer sizes of 800, 200, and 200 bytes.
The controller will discard all descriptors with OWN = 1
and STP = 0 and move to the next descriptor when
searching for a place to begin a new frame. It discards
these descriptors by simply changing the ownership bit
from OWN = 1 to OWN = 0. Such a descriptor is un-
n Example 1: Assume that a 1060 byte frame arrives
correctly, and that the timing of the early interrupt
and the software is smooth. The descriptors will
have changed from:
Before the Frame Arrives
After the Frame Arrives
Descriptor
Number
OWN
STP
ENP
OWN
STP
ENPb
Comments (After
Frame Arrival)
1
1
1
x
0
1
0
Bytes 1-800
2
1
0
X
0
0
0
Bytes 801-1000
3
0
0
X
0
0
1
Bytes 1001-1060
4
1
1
X
1
1
X
Controller’s current
location
5
1
0
X
1
0
X
Not yet used
6
0
0
X
0
0
X
Not yet used
etc.
1
1
X
1
1
X
Net yet used
a
a. & b. ENP or ERR.
n Example 2: Assume that instead of the expected
1060 byte frame, a 900 byte frame arrives, either
because there was an error in the network, or be-
cause this is the last frame in a file transmission sequence.
Before the Frame Arrives
Descriptor
Number
OWN
STP
1
1
2
1
3
0
After the Frame Arrives
Comments (After
Frame Arrival)
ENPa
OWN
STP
ENPb
1
x
0
1
0
Bytes 1-800
0
X
0
0
0
Bytes 801-1000
0
X
0
0
?*
Discarded buffer
4
1
1
X
1
1
X
Controller’s current
location
5
1
0
X
1
0
X
Not yet used
6
0
0
X
0
0
X
Not yet used
etc.
1
1
X
1
1
X
Net yet used
a. & b. ENP or ERR.
Note: The controller might write a ZERO to ENP location in the third descriptor. Here are the two possibilities:
modified buffer pointer into the third descriptor, then
the controller will write a ZERO to ENP for this
buffer and will write a ZERO to OWN and STP.
1. If the controller finishes the data transfers into buffer
number 2 after the driver writes the application
2. If the controller finishes the data transfers into buffer
number 2 before the driver writes the applications
B-6
Am79C978
modified buffer point into the third descriptor, then
the controller will complete the frame in buffer number 2 and then skip the then unowned third buffer.
In this case, the controller will not have had the opportunity to RESET the ENP bit in this descriptor,
and it is possible that the software left this bit as
ENP = 1 from the last time through the ring. Therefore, the software must treat the location as a don’t
care. The rule is, after finding ENP = 1 (or ERR = 1)
in descriptor number 2, the software must ignore
ENP bits until it finds the next STP = 1.
n Example 3: Assume that instead of the expected
1060 byte frame, a 100 byte frame arrives, because
there was an error in the network, or because this is
the last frame in a file transmission sequence, or
perhaps because it is an acknowledge frame.
*Same as note in example 2 above, except that in this
case, it is very unlikely that the driver can respond to
the interrupt and get the pointer from the application
before the controller has completed its poll of the next
descriptors. This means that for almost all occurrences
of this case, the controller will not find the OWN bit set
for this descriptor and, therefore, the ENP bit will almost always contain the old value, since the controller
will not have had an opportunity to modify it.
**Note that even though the controller will write a
ZERO to this ENP location, the software should treat
the location as a don’t care, since after finding the ENP
= 1 in descriptor number 2, the software should ignore
ENP bits until it finds the next STP = 1.
Before the Frame Arrives
After the Frame Arrives
Descriptor
Number
OWN
STP
ENP
OWN
STP
ENPb
Comments (After
Frame Arrival)
1
1
1
x
0
1
0
Bytes 1-800
2
1
0
X
0
0
0**
Discarded buffer
3
0
0
X
0
0
?
Discarded buffer
4
1
1
X
1
1
X
Controller’s current
location
5
1
0
X
1
0
X
Not yet used
6
0
0
X
0
0
X
Not yet used
etc.
1
1
X
1
1
X
Net yet used
a
a. & b.ENP or ERR.
Buffer Size Tuning
For maximum performance, buffer sizes should be adjusted depending upon the expected frame size and
the values of the interrupt latency and application call
latency. The best driver code will minimize the CPU utilization while also minimizing the latency from frame
end on the network to the frame sent to application
from driver (frame latency). These objectives are
aimed at increasing throughput on the network while
decreasing CPU utilization.
Note: The buffer sizes in the ring may be altered at
any time that the CPU has ownership of the corresponding descriptor. The best choice for buffer sizes
will maximize the time that the driver is swapped out,
while minimizing the time from the last byte written by
the controller to the time that the data is passed from
the driver to the application. In the diagram, this corresponds to maximizing S0, while minimizing the time between C9 and S8. (the timeline happens to show a
minimal time from C9 to S8.)
Note: By increasing the size of buffer number 1, we increase the value of S0. However, when we increase
the size of buffer number 1, we also increase the value
of S4. If the size of buffer number 1 is too large, then
the driver will not have enough time to perform tasks
S2, S3, S4, S5, and S6. The result is that there will be
delay from the execution of task C9 until the execution
of task S8. A perfectly timed system will have the values for S5 and S7 at a minimum.
An average increase in performance can be achieved,
if the general guidelines of buffer sizes in Figure 2 is followed. However, as was noted earlier, the correct sizing for buffers will depend upon the expected message
size. There are two problems with relating expected
message size with the correct buffer sizing:
1. Message sizes cannot always be accurately predicted, since a single application may expect different message sizes at different times. Therefore, the
buffer sizes chosen will not always maximize
throughput.
2. Within a single application, message sizes might be
somewhat predictable, but when the same driver is
to be shared with multiple applications, there may
not be a common predictable message size.
Additional problems occur when trying to define the
correct sizing because the correct size also depends
upon the interrupt latency, which may vary from system
to system, depending upon both the hardware and the
software installed in each system.
In order to deal with the unpredictable nature of the
message size, the driver can implement a self-tuning
Am79C978
B-7
mechanism that examines the amount of time spent in
tasks S5 and S7. As such, while the driver is polling for
each descriptor, it could count the number of poll operations performed and then adjust the number 1 buffer
size to a larger value, by adding “t” bytes to the buffer
count, if the number of poll operations was greater than
”x.” If fewer than “x” poll operations were needed for
each of S5 and S7, then software should adjust the
buffer size to a smaller value by subtracting “y” bytes
from the buffer count. Experiments with such a tuning
mechanism must be performed to determine the best
values for “x” and “y.”
Note: Whenever the size of buffer number 1 is adjusted, buffer sizes for buffer number 2 and buffer number 3 should also be adjusted.
In some systems, the typical mix of receive frames on
a network for a client application consists mostly of
large data frames, with very few small frames. In this
case, for maximum efficiency of buffer sizing, when a
frame arrives under a certain size limit, the driver
should not adjust the buffer sizes in response to the
short frame.
An Alternative LAPP Flow: Two-Interrupt
Method
An alternative to the above suggested flow is to use two
interrupts, one at the start of the receive frame and the
other at the end of the receive frame, instead of just
looking for the SRP interrupt as described above. This
alternative attempts to reduce the amount of time that
the software wastes while polling for descriptor own
bits. This time would then be available for other CPU
tasks. It also minimizes the amount of time the CPU
needs for data copying. This savings can be applied to
other CPU tasks.
B-8
The time from the end of frame arrival on the wire to delivery of the frame to the application is labeled as frame
latency. For the one-interrupt method, frame latency is
minimized, while CPU utilization increases. For the
two-interrupt method, frame latency becomes greater,
while CPU utilization decreases. See Figure B-3.
Note: Some of the CPU time that can be applied to
non-Ethernet tasks is used for task switching in the
CPU. One task switch is required to swap a non-Ethernet task into the CPU (after S7A) and a second task
switch is needed to swap the Ethernet driver back in
again (at S8A). If the time needed to perform these task
switches exceeds the time saved by not polling descriptors, then there is a net loss in performance with
this method. Therefore, the LAPP method implemented should be carefully chosen.
Figure B-4 shows the buffer sizing for the two-interrupt
method. Note that the second buffer size will be about
the same for each method.
There is another alternative which is a marriage of the
two previous methods. This third possibility would use
the buffer sizes set by the two-interrupt method, but
would use the polling method of determining frame
end. This will give good frame latency but at the price
of very high CPU utilization. And still, there are even
more compromise positions that use various fixed
buffer sizes and, effectively, the flow of the one-interrupt method. All of these compromises will reduce the
complexity of the one-interrupt method by removing the
heuristic buffer sizing code, but they all become less efficient than heuristic code would allow.
Am79C978
Software
activity:
Ethernet
Controller
activity:
Ethernet
Wire
activity:
S10: Driver sets up TX descriptor.
S9: Application processes packet, generates TX packet.
S8: Driver calls application
to tell application that
packethas arrived.
S8A: Interrupt latency.
}
C10: ERP interrupt
is generated.
}
C9: Controller writes descriptor #3.
}
C8: Controller is performing intermittent
bursts of DMA to fill data buffer #3.
N2:EOM
Buffer
#3
C7: Controller writes descriptor #2.
S7: Driver is swapped out, allowing a non-Ethernet
application to run.
S7A: Driver Interrupt Service
Routine executes
RETURN.
S6: Driver copies data from buffer #2 to the application
buffer.
S5: Driver polls descriptor #2.
C6: "Last chance" lookahead to
descriptor #3 (OWN).
S4: Driver copies data from buffer #1 to the application
buffer.
S3: Driver writes modified application
pointer to descriptor #3.
Packet data arriving
C4: Lookahead to descriptor #3 (OWN).
C3: SRP interrupt is
generated.
}
Buffer
#2
}
C5: Controller is performing intermittent
bursts of DMA to fill data buffer #2
S2: Driver call to application to
get application buffer pointer.
S1: Interrupt latency.
}
C2: Controller writes descriptor #1.
C1: Controller is performing intermittent
bursts of DMA to fill data buffer #1.
Buffer
#1
S0: Driver is idle.
C0: Lookahead to descriptor #2.
{
N1: 64th byte of packet
data arrives.
N0: Packet preamble, SFD
and destination address
are arriving.
22206B-B3
Figure B-3.
LAPP Timeline for Two-Interrupt Method
Am79C978
B-9
Descriptor
#1
Descriptor
#2
OWN = 1
STP = 1
SIZE = HEADER_SIZE (minimum 64 bytes)
OWN = 1
SIZE = S1+S2+S3+S4
STP = 0
Descriptor
#3
OWN = 0
STP = 0
SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
Descriptor
#4
OWN = 1
STP = 1
SIZE = HEADER_SIZE (minimum 64 bytes)
Descriptor
#5
OWN = 1
SIZE = S1+S2+S3+S4
Descriptor
#6
OWN = 0
STP = 0
SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
Descriptor
#7
OWN = 1
STP = 1
SIZE = HEADER_SIZE (minimum 64 bytes)
Descriptor
#8
OWN = 1
SIZE = S1+S2+S3+S4
Descriptor
#9
OWN = 0
STP = 0
SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)
STP = 0
STP = 0
A = Expected message size in bytes
S1 = Interrupt latency
S2 = Application call latency
S3 = Time needed for driver to write
to third descriptor
S4 = Time needed for driver to copy
data from buffer #1 to
application buffer space
S6 = Time needed for driver to copy
data from buffer #2 to
application buffer space
Note that the times needed for tasks S1,
S2, S3, S4, and S6 should be divided by
0.8 microseconds to yield an equivalent
number of network byte times before
subtracting these quantities from the
expected message size A.
22206B-B4
Figure B-4.
B-10
LAPP 3 Buffer Grouping for Two-interrupt Method
Am79C978
Numerics
1 Mbps HomePNA PHY Internal Registers 179
1 Mbps HomePNA PHY Management Registers
214
10 Mbps Receive (RX±) Timing Diagram 227
10 Mbps Transmit (TX±) Timing Diagram 227
10/100 Mbps operation 2
10/100 Media Access Control 65
10/100 Media Access Controller 65
10BASE-T 227
10BASE-T Block 98
10BASE-T I/O Buffer Power 32
10BASE-T Mode 224
10BASE-T PDX Analog Ground 32
10BASE-T PDX Block Power 32
10BASE-T PDX Digital Ground 32
10BASE-T PHY Management Registers 213
10BASE-T PHY Management Registers (TBRs)
179
10BASE-T Physical Layer 98
14795
Tabtle
Table 44. R/TLEN Decoding (SSIZE32 =
0) 199
16937
Tabtle
Table 36. Software Styles 163
16-Bit Software Model 61
24958
Tabtle
Table 26. Software Styles 135
24981
Tabtle
Table 35. Interface Pin Assignment 161
C/BE 26
RXD 30
TXD 30
AD 26
31439
Tabtle
Table 25. Loopback Configuration 128
32-Bit Software Model 62
34313
Tabtle
Table 19. Table 18. PCI Configuration
Space Layout 95
38779
Tabtle
Table 49. Transmit Descriptor (SW-
STYLE = 0) 203
40675
TblTitlew
Table 13. MII Control Frame Format 81
41807
TblTitle
Table 11. Master Station Control Word
Functions 81
A
Absolute Maximum Ratings 220
ACCESS ID Intervals 76
ACCESS ID Values 78
Address and Data 26
Address Match Logic 200
Address Matching 71
Address Parity Error Response 41
Address PROM Space 96
Advanced Configuration and Power Interface
(ACPI) specification 1
Advanced Parity Error Handling 52
AID Receive Timing 78
AID Transmit Timing 78
Alternative Method for Initialization 1
Am79C978 10BASE-T PHY Management Register Set 188
Am79C978 Programmable Register 215
An Alternative LAPP Flow
Two-Interrupt Method 8
Analog PLL Power 32
ANR6
Auto-Negotiation Expansion Register (Register 6) 194
APDW Values 169
APP 3 Buffer Grouping for Two-interrupt Method
10
Automatic EEPROM Read Operation 84
Automatic Pad Generation 69
Automatic Pad Stripping 72
Automatic PREAD EEPROM Timing 232
Auto-Negotiation 99
Auto-Negotiation Capabilities 99
Auto-Poll™ 1
B
Basic Burst Read Transfer 43
Basic Burst Write Transfer 45
Basic Non-Burst Read Transfer 43
Basic Non-Burst Write Transfer 45
BCR Registers 146
BCR0
Am79C978
1
Master Mode Read Active 145
BCR1
Master Mode Write Active 145
BCR16
I/O Base Address Lower 155
BCR17
I/O Base Address Upper 155
BCR18
Burst and Bus Control Register 156
BCR19
EEPROM Control and Status 158
BCR2
Miscellaneous Configuration 145
BCR20
Software Style 161
BCR22
PCI Latency Register 163
BCR23
PCI Subsystem Vendor ID Register 163
BCR24
PCI Subsystem ID Register 164
BCR25
SRAM Size Register 164
BCR26
SRAM Boundary Register 164
BCR27
SRAM Interface Control Register 165
BCR28
Expansion Bus Port Address Lower (Used for
Flash/EPROM and SRAM Accesses)
166
BCR29
Expansion Port Address Upper (Used for
Flash/EPROM Accesses) 167
BCR30
Expansion Bus Data Port Register 167
BCR31
Software Timer Register 168
BCR32
PHY Control and Status Register 168
BCR32 PHY Control and Status Register 168
BCR33
PHY Address Register 170
BCR34
PHY Management Data Register 171
BCR35
PCI Vendor ID Register 171
BCR36
PCI Power Management Capabilities (PMC)
2
Alias Register 172
BCR37
PCI DATA Register Zero (DATA0) Alias
Register 172
BCR38
PCI DATA Register 1 (DATA1) Alias Register 172
PCI DATA Register One (DATA1) Alias Register 172
BCR39
PCI DATA Register 0 (DATA2) Alias Register 172
PCI DATA Register Two (DATA2) Alias
Register 172
BCR4
LED 0 Status 147
BCR40
PCI DATA Register 3 (DATA3) Alias Register 173
PCI Data Register Three (DATA3) Alias Register 173
BCR41
PCI DATA Register 4 (DATA4) Alias Register 173
BCR42
PCI DATA Register 5 (DATA5) Alias Register 174
PCI DATA Register Five (DATA5) Alias
Register 174
BCR43
PCI DATA Register 6 (DATA6) Alias Register 174
BCR44
PCI DATA Register Seven (DATA7) Alias
Register 174
PCI DATA Register7 (DATA7) Alias Register 174
BCR45
OnNow Pattern Matching Register 1 175
BCR46
OnNow Pattern Matching Register 2 175
BCR47
OnNow Pattern Matching Register #3 176
OnNow Pattern Matching Register 3 176
BCR48
LED4 Status 176
BCR49
PHY Select 178
BCR5
Am79C978
LED1 Status 149
BCR50-BCR55
Reserved Locations 178
BCR6
LED2 Status 151
BCR7
LED3 Status 153
BCR9
Full-Duplex Control 155
Blanking Interval Speed Settings 79
BLOCK DIAGRAM 4
Block Diagram Low Latency Receive Configuration 83
Block Diagram No SRAM Configuration 82
Board Interface 28
Boundary Scan Circuit 91
Boundary Scan Register 91
BSR Mode Of Operation 91
Buffer Management 60
Buffer Management Unit 3, 59
Buffer Size Tuning 7
Burst FIFO DMA Transfers 57
Burst Write Transfer 46
Bus Acquisition 42, 43
Bus Command and Byte Enables 26
Bus Configuration Registers 145, 212, 217
Bus Configuration Registers (BCRs) 145
Bus Grant 26
Bus Master DMA Transfers 43
Bus Request 27
by Driver Type 24
C
CLK 26
CLK Waveform for 3.3 V Signaling 230
CLK Waveform for 5 V Signaling 230
CLK_FAC Values 166
Clock 26
Clock Interface 31
Clock Timing 222, 225
COL 30
Collision 30
Collision Detect Function 99
Collision Handling 68
CONNECTION DIAGRAM (144 TQFP) 16
CONNECTION DIAGRAM (160 PQFP) 17
Contents 5
Control and Status Registers 112, 208, 215
CRS 30
Crystal 32
Crystal Oscillator In 32
Crystal Oscillator Out 32
CSR0
Controller Status and Control Register 112
CSR1
Initialization Block Address 0 115
CSR10
Logical Address Filter 2 125
CSR100
Bus Timeout 141
CSR11
Logical Address Filter 3 126
CSR112
Missed Frame Count 142
CSR114
Receive Collision Count 142
CSR116
OnNow Power Mode Register 142
CSR12
Physical Address Register 0 126
CSR122
Advanced Feature Control 143
CSR124
Test Register 1 143
CSR125
MAC Enhanced Configuration Control 144
CSR13
Physical Address Register 1 126
CSR14
Physical Address Register 2 126
CSR15
Mode 127
CSR16
Initialization Block Address Lower 128
CSR17
Initialization Block Address Upper 128
CSR18
Current Receive Buffer Address Lower 128
CSR19
Current Receive Buffer Address Upper 128
CSR2
Initialization Block Address 1 115
CSR20
Current Transmit Buffer Address Lower 129
CSR21
Current Transmit Buffer Address Upper 129
CSR22
Next Receive Buffer Address Lower 129
CSR23
Am79C978
3
Next Receive Buffer Address Upper 129
CSR24
Base Address of Receive Ring Lower 129
CSR25
Base Address of Receive Ring Upper 129
CSR26
Next Receive Descriptor Address Lower 129
CSR27
Next Receive Descriptor Address Upper 130
CSR28
Current Receive Descriptor Address Lower
130
CSR29
Current Receive Descriptor Address Upper
130
CSR3
Interrupt Masks and Deferral Control 115
CSR30
Base Address of Transmit Ring Lower 130
CSR31
Base Address of Transmit Ring Upper 130
CSR32
Next Transmit Descriptor Address Lower 130
CSR33
Next Transmit Descriptor Address Upper 130
CSR34
Current Transmit Descriptor Address Lower
131
CSR35
Current Transmit Descriptor Address Upper
131
CSR36
Next Next Receive Descriptor Address Lower
131
CSR37
Next Next Receive Descriptor Address 131
Next Next Receive Descriptor Address Upper
131
CSR38
Next Next Transmit Descriptor Address Lower 131
CSR39
Next Next Transmit Descriptor Address Upper
131
CSR4
Test and Features Control 118
CSR40
Current Receive Byte Count 131
CSR41
4
Current Receive Status 132
CSR42
Current Transmit Byte Count 132
CSR43
Current Transmit Status 132
CSR44
Next Receive Byte Count 132
CSR45
Next Receive Status 132
CSR46
Transmit Poll Time Counter 132
CSR47
Transmit Polling Interval 133
CSR48
Receive Poll Time Counter 133
CSR49
Receive Polling Interval 133
CSR5
Extended Control and Interrupt 1 119
CSR58
Software Style 134
CSR6
RX/TX Descriptor Table Length 122
CSR60
Previous Transmit Descriptor Address Lower
136
CSR61
Previous Transmit Descriptor Address Upper
135, 136
CSR62
Previous Transmit Byte Count 136
CSR63
Previous Transmit Status 136
CSR64
Next Transmit Buffer Address Lower 136
CSR65
Next Transmit Buffer Address Upper 136
CSR66
Next Transmit Byte Count 137
CSR67
Next Transmit Status 137
CSR7
Extended Control and Interrupt 2 122
CSR72
Receive Ring Counter 137
CSR74
Transmit Ring Counter 137
CSR76
Receive Ring Length 137
Am79C978
CSR78
Transmit Ring Length 137
CSR8
Logical Address Filter 0 125
CSR80
DMA Transfer Counter and FIFO Threshold
Control 138
CSR82
Transmit Descriptor Address Pointer Lower
140
CSR84
DMA Address Register Lower 140
CSR85
DMA Address Register Upper 140
CSR86
Buffer Byte Counter 140
CSR88
Chip ID Register Lower 141
CSR89
Chip ID Register Upper 141
CSR9
Logical Address Filter 1 125
CSR92
Ring Length Conversion 141
Cycle Frame 26
D
Data Receive Timing 79
Data Symbol RLL25 Encoding 80
Data Symbols 79
Data Transmit Timing 79
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 220
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES unless otherwise
specified 220
Description of the Methodology 81
Descriptor DMA Transfers 54
Descriptor Ring Read In Burst Mode 55
Descriptor Ring Write In Burst Mode 56
Descriptor Ring Write In Non-Burst Mode 56
Descriptor Rings 60
Destination Address Handling 66
Detailed Functions 75
Device ID Register 91
Device Select 26
DEVSEL 26
Digital Ground (8 Pins) 32
Digital I/O (Non-PCI Pins) 220
Digital Power (6 Pins) 32
Direct Access to the Interface 84
Direct Memory Access (DMA) 2
Direct SRAM Access 82
Disconnect Of Burst Transfer 40
Disconnect Of Slave Burst Transfer - Host Inserts
Wait States 41
Disconnect Of Slave Burst Transfer - No Host
Wait States 40
Disconnect Of Slave Cycle When Busy 40
Disconnect When Busy 40
Disconnect With Data Transfer 46, 47
Disconnect Without Data Transfer 47, 48
DISTINCTIVE CHARACTERISTICS 1
Double Word I/O Mode 97
DVDDA 32
DVDDA_HR 32
DVDDD 32
DVDDRX, DVDDTX 32
DVSSD 32
DVSSX 32
E
EBCS Values 166
EECS 29
EEDET Setting 161
EEDI 29
EEDO 29
EEPROM 86
EEPROM Auto-Detection 84
EEPROM Chip Select 29
EEPROM Data In 29
EEPROM Data Out 29
EEPROM Interface 29, 83, 84
EEPROM MAP 85
EEPROM Map 86
EEPROM Read Functional Timing 231
EEPROM Serial clock 30
EEPROM Timing 223
EEPROM-Programmable Registers 84
EESK 30
Error Detection 66
escriptor Ring Read In Non-Burst Mode 55
Ethernet controllers in the PCnet Family 3
Ethernet Network Interfaces 31
Expansion ROM Read 39
Expansion ROM Transfers 39
External Clock 225
External Clock/Crystal Select 31
F
FIFO Burst Write At End Of Unaligned Buffer 58
Am79C978
5
FIFO Burst Write At Start Of Unaligned Buffer 58
FIFO DMA Transfers 57
Flow, LAPP 2
FMDC Values 169
FRAME 26
Frame Format at the MII Interface Connection 35
Framing 65, 75
Full-Duplex Link Status LED Support 74
Full-Duplex Operation 73
G
GENERAL DESCRIPTION 2
GNT 26
H
H_RESET 94
Header AID Remote Control Word Commands 81
Home Networking Controller 1
Home Phoneline Networking Alliance (HomePNA) 1
HomePNA Analog Ground 32
HomePNA Analog Power 32
HomePNA Digital Power 32
HomePNA PHY Framing 76
HomePNA PHY Network Interface 31
HomePNA Physical Layer (PHY) 1
HPR0
HomePNA PHY MII Control (Register 0) 179
HPR1
HomePNA PHY MII Status (Register 1) 180
HPR16
HomePNA PHY Control (Register 16) 182,
183
HPR18 and HPR19
HomePNA PHY TxCOMM (Registers 18 and
19) 183
HPR2 and HPR3
HomePNA PHY MII PHY ID (Registers 2 and
3) 181
HPR20 and HPR21
HomePNA PHY RxCOMM (Registers 20 and
21) 184
HPR22
HomePNA PHY AID (Register 22) 184
HPR23
HomePNA PHY Noise Control (Register 23)
184
HPR24
HomePNA PHY Noise Control 2 (Register 24)
185
HPR25
6
HomePNA PHY Noise Statistics (Register 25)
185
HPR26
HomePNA PHY Event Status (Register 26)
186
HPR27
HomePNA PHY Event Status (Register 27)
186
HPR28
HomePNA PHY ISBI Control (Register 28)
186
HPR29
HomePNA PHY TX Control (Register 29) 187
HPR4-HPR7
HomePNA PHY Auto-Negotiation (Registers
4 - 7) 181
HRTXRXP/HRTXRXN 31
I
I/O Buffer Ground (17 Pins) 32
I/O Buffer Power (7 Pins) 32
I/O Map In DWord I/O Mode (DWIO = 1) 98
I/O Map in DWord I/O Mode (DWIO = 1) 98
I/O Map In Word I/O Mode (DWIO = 0) 97
I/O Registers 96
I/O Resources 95
IDSEL 26
IEEE 1149.1 (1990) Test Access Port Interface 31,
91
IEEE 1149.1 Supported Instruction Summary 91
IEEE 802.3 Frame And Length Field Transmission Order 73
IEEE 802.3u 2
Initialization 59
Initialization Block 198
Initialization Block (SSIZE32 = 0) 198
Initialization Block (SSIZE32 = 1) 198
Initialization Block DMA Transfers 52
Initialization Block Read In Burst Mode 53
Initialization Block Read In Non-Burst Mode 53
Initialization Device Select 26
Initiator Ready 27
Input Setup and Hold Timing 230
Instruction Register and Decoding Logic 91
INTA 27
Integrated Controllers 15
integrated PCI Ethernet controller 2
Integrated Repeater/Hub Devices 15
Inter Packet Gap (IPG) 2
Interface Pin Assignment 161
Am79C978
Interrupt Request 27
Introduction 1
IRDY 27
IREF 31
J
Jabber Function 99
JAM Signal 78
JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling 232
JTAG (IEEE 1149.1) Test Signal Timing 223, 233
K
Key to Switching Waveforms 229
L
LADRF 199
LAPP 3 Buffer Grouping 5
LAPP Software Requirements 5
LAPP Timeline 4
LAPP Timeline for Two-Interrupt Method 9
Late Collision 70
LED Control Logic 87
LED Default Configuration 87
LED Support 85
LED0 28
LED1 29
LED2 29
LED3 29
LED4 29
Legal I/O Accesses in Double Word I/O Mode
(DWIO =1) 98
Legal I/O Accesses in Word I/O Mode (DWIO =
0) 97
Link Change Detect 88
listed by Group 20
Look-Ahead Packet Processing (LAPP) 2
Look-Ahead Packet Processing (LAPP) Concept 1
Loopback Configuration 128
Loopback Operation 73
Loss of Carrier 70
Low Latency Receive Configuration 82
M
MAC 65, 66, 67
Magic Packet Mode 89
Magic Packet™ mode 1
magnetics module. IREF 31
Management Cycle Timing 228
Management Data Clock 31
Management Data Input/Output 31
Management Data Output Valid Delay Timing
235
Management Data Setup and Hold Timing 235
Management Interfaces 80
Manchester Encoder/Decoder 15
Master Abort 49, 51
Master Bus Interface Unit 42
Master Cycle Data Parity Error Response 51
Master Initiated Termination 48
MDC 31
MDC Waveform 234
MDIO 31
Media Access Controller (MAC) 1, 2
Media Access Management 67
Media Independent Interface 33
Medium Allocation 67
Microsoft OnNow 2
MII Interface 30
MII interface 2
MII Management Frames 35
MII Management Interface 34
MII Network Status Interface 34
MII Receive Interface 34
MII Transmit Interface 33
Miscellaneous Loopback Features 73
Mode 199
N
NAND Tree Circuitry 92
NAND Tree Circuitry (160 PQFP 92
NAND Tree Circuitry (160 PQFP) 92
NAND Tree Pin Sequence (144 TQFP) 93
NAND Tree Pin Sequence (160 PQFP) 93
NAND Tree Testing 92
NAND Tree Waveform 94
Network Interfaces 33
Network Port Manager 36
Non-Burst FIFO DMA Transfers 57
Non-Burst Read Transfer 44
Non-Burst Write Transfer 45
Normal and Tri-State Outputs 229
O
Offset 00h 102
Offset 02h 102
Offset 04h 103
Offset 06h 104
Offset 08h 105
Offset 09h 105
Offset 0Ah 105
Offset 0Bh 106
Offset 0Dh 106
Offset 0Eh 106
Am79C978
7
Offset 10h 106
Offset 14h 107
Offset 2Ch 107
Offset 2Eh 107
Offset 30h 108
Offset 34h 108
Offset 3Ch 108
Offset 3Dh 109
Offset 3Eh 109
Offset 3Fh 109
Offset 40h 109
Offset 41h 109
Offset 42h 109
Offset 44h 110
Offset 46h 111
Offset 47h 111
OnNow Functional Diagram 88
OnNow Pattern Match Mode 88
OnNow Wake-Up Sequence 87
Operating Ranges 220
ordering information 25
Other Data Registers 91
Outline of LAPP Flow 1
Output and Float Delay Timing 222
Output Tri-State Delay Timing 231
Output Tri-state Delay Timing 231
Output Valid Delay Timing 231
P
PADR 199
PAR 27
Parity 27
Parity Error 27
Parity Error Response 41, 49
Pattern Match RAM 90
Pattern Match RAM (PMR) 88
PCI and JTAG Configuration Information 36
PCI Base-Class Register Offset 0Bh 106
PCI Bus Interface Pins - 3.3 V Signaling 220
PCI Bus Interface Pins - 5 V Signaling 220
PCI Bus Power Management Interface specification 2
PCI Capabilities Pointer Register 108
PCI Capability Identifier Register 109
PCI Command Register 103
PCI Command Register Offset 04h 103
PCI Configuration Registers 95, 101, 102, 207
PCI Configuration Space Layout 95
PCI Data Register 111
PCI Data Register Offset 47h 111
8
PCI Device ID Register 102
PCI Device ID Register Offset 02h 102
PCI Expansion ROM Base Address Register 108
PCI Header Type Register 106
PCI Header Type Register Offset 0Eh 106
PCI I/O Base Address Register 106
PCI I/O Base Address Register Offset 10h 106
PCI I/O Buffer Power (9 Pins) 32
PCI Interface 26
PCI Interrupt Line Register 108
PCI Interrupt Line Register Offset 3Ch 108
PCI Interrupt Pin Register 109
PCI Latency Timer Register 106
PCI MAX_LAT Register 109
PCI Memory Mapped I/O Base Address Register
107
PCI MIN_GNT Register 109
PCI Next Item Pointer Register 109
PCI Next Item Pointer Register Offset 41h 109
PCI PMCSR Bridge Support Extensions Register
111
PCI PMCSR Bridge Support Extensions Register
Offset 46h 111
PCI Power Management Capabilities Register
(PMC) 109
PCI Power Management Control/Status Register
(PMCSR) 110
PCI Programming Interface Register 105
PCI Programming Interface Register Offset 09h
105
PCI Revision ID Register 105
PCI Status Register 104
PCI Status Register Offset 06h 104
PCI Sub-Class Register 105
PCI Sub-Class Register Offset 0Ah 105
PCI Subsystem ID Register 107
PCI Subsystem Vendor ID Register 107
PCI Vendor ID Register 102
PCI Vendor ID Register Offset 00h 102
PECL 225
PERR 27
PG 28
PHY Control and Management Block (PCM
Block) 81
PHY Select Programming 158
PHY/MAC Interface 74
PHY_RST 31
PHYSICAL DIMENSIONS 236
Physical Layer Devices (Multi-Port) 15
Am79C978
Physical Layer Devices (Single-Port) 15
Pin Capacitance 221
Pin Descriptions 26
PIN DESIGNATIONS 24
PIN DESIGNATIONS (PQL144 20
PIN DESIGNATIONS (PQL144) 18
PIN DESIGNATIONS (PQR160) 19
listed by Group 22
PMD Interface 225
PMD Interface Timing (PECL) 226
PME 28
Polling 62
Power Good 28, 31
Power Management Event 28
Power Management Support 87
Power on Reset 95
Power Savings Mode 87
Power Supply Current 221, 224
Power Supply Pins 32
PQL144 236
PQR160 237
Preemption During Burst Transaction 48, 50
Preemption During Non-Burst Transaction 48, 50
R
RAP
Register Address Port 112
RAP Register 111
RDRA and TDRA 199
Receive Address Match 72
Receive Carrier Sense 30
Receive Clock 30
Receive Data 30
Receive Data Valid 30
Receive Descriptor (SWSTYLE = 0) 200
Receive Descriptor (SWSTYLE = 2) 200
Receive Descriptor (SWSTYLE = 3) 200
Receive Descriptor Table Entry 64
Receive Descriptors 200
Receive Exception Conditions 72
Receive FCS Checking 72
Receive Frame Queuing 64
Receive Function Programming 70
Receive Operation 70
Receive Symbol Timing 79
Receive Timing 228, 234
Receive Watermark Programming 138
Register Administration for 10BASE-T PHY Device 81
Register Programming Summary 215
Register Summary 207
Re-Initialization 59
RELATED AMD PRODUCTS 15
REQ 27
Reserved Register
10BASE-T Carrier Status Register (Register
23) 197
10BASE-T Configuration Register (Register
22) 197
Reserved Registers
HPR8 - HPR15, HPR17 181
Reserved Registers (Registers 8-15, 18, 20-23, and
25-31) 194
Reset 28, 94
Reset Register 96
Reverse Polarity Detect 99
RLEN and TLEN 198
RLL 25 Coding Tree 80
RMD0 200, 201
RMD1 201
RMD2 202
RMD3 203
ROMTNG Programming Values 156
RST 28
Running Registers 102
RWU 29
RX_CLK 30
RX_DV 30
RX_ER 30
RX± 31
S
S_RESET 94
Serial Receive Data 31
Serial Transmit Data 31
SERR 28
Setup 2
Setup and Hold Timing 222
Setup Registers 101
Silence Interval (AID symbol 7) 78
Slave Bus Interface Unit 36
Slave Configuration Read 38
Slave Configuration Transfers 36
Slave Configuration Write 38
Slave Cycle Data Parity Error Response 42
Slave Cycle Termination 39
Slave I/O Transfers 37
Slave Read Using I/O Command 38
Slave Write Using Memory Command 39
Soft Reset Function 100
Am79C978
9
Software 163
Software Access 95
Software Interface 33
Software Interrupt Timer 65
Some Examples of LAPP Descriptor Interaction 6
SQE Test Error 70
SR2
Initialization Block Address 1 115
SRAM_BND Programming 165
Standard Products 25
STOP 28, 96
Stop 28
Supported Instructions 91
Suspend 59
Switching Characteristics
Bus Interface 222
Media Independent Interface 228
Switching Test Circuits 229
SWITCHING WAVEFORMS 229
Switching Waveforms
Expansion Bus Interface 236
General-Purpose Serial Interface 236
Media Independent Interface 234, 236
System Bus Interface 230
Symbol 0 (SYNC interval) 76
SYNC Receive Timing 76
SYNC Transmit Timing 76
System Bus Interface 33
System Error 28
T
TAP Finite State Machine 91
Target Abort 47, 49
Target Initiated Termination 46
Target Ready 28
TBR0
10BASE-T PHY Control Register (Register 0)
189
TBR16
10BASE-T INTERRUPT Status and Enable
Register (Register 16) 195
TBR17
10BASE-T PHY Control/Status Register
(Register 17) 196
TBR19
10BASE-T PHY Management Extension Register (Register 19) 197
TBR2 191
10BASE-T PHY Identifier (Register 2) 191
TBR24
10
10BASE-T Summary Status Register (Register 24) 197
TBR3
10BASE-T PHY Identifier (Register 3) 191
TBR4
10BASE-T Auto-Negotiation Advertisement
Register (Register 4) 192
TBR5
10BASE-T Auto-Negotiation Link Partner
Ability Register (Register 5) 193
10BASE-T Auto-Negotiation Link Partner
Ability Register (Register 5) - Base
Page Forma 193
10BASE-T Auto-Negotiation Link Partner
Ability Register (Register 5) - Next
Page Format 193
TBR6
10BASE-T Auto-Negotiation Expansion Register (Register 6) 194
TBR7
10BASE-T Auto-Negotiation Next Page Register (Register 7) 194
TCK 31
TDI 31
TDO 31
Test Clock 31
Test Data In 31
Test Data Out 31
Test Mode Select 31
Test Registers 102
Time 76
Time Interval Unit 76
TMD0 204
TMD1 204
TMD2 205
TMD3 206
TMS 31
Transmit and Receive Message Data Encapsulation 65
Transmit Clock 30
Transmit Data 30
Transmit Data Symbol Timing 79
Transmit Descriptor (SWSTYLE = 2) 203
Transmit Descriptor (SWSTYLE = 3) 203
Transmit Descriptor Table Entry 63
Transmit Descriptors 203
Transmit Enable 31
Transmit Exception Conditions 70
Transmit FCS Generation 70
Am79C978
Transmit Function Programming 68
Transmit Operation 68
Transmit Start Point Programming 139
Transmit Timin 234
Transmit Timing 228, 234
Transmit Watermark Programming 140
TRDY 28
Twisted Pair Interface Status 98
Twisted Pair Receive Function 98
TX+, TX- 31
TX_CLK 30
TX_EN 31
U
USER ACCESSIBLE REGISTERS 101
V
VDD 32
VDD_PCI 32
VDDB 32
VDDCO 32
VDDHR 32
VSS 32
VSSB 32
VSSHR 32
W
Word I/O Mode 96
X
XCLK/XTAL 31
XTAL1 32
XTAL2 32
Am79C978
11