LANSDALE ML145170-7P Phase-frequency detector pll frequency synthesizer with serial interface Datasheet

ML145170
Phase–Frequency Detector
PLL Frequency Synthesizer
with Serial Interface
Legacy Device: Motorola/Freescale MC145170-2
The Lansdale ML145170 is a single–chip synthesizer capable of direct
usage in the MF, HF and VHF bands. A special architecture makes this
PLL easy to program. Either a bit– or byte–oriented format may be used.
Due to the patented BitGrabber™ registers, no address/steering bits are
required for random access of the three registers. Thus, tuning can be
accomplished via a 2–byte serial transfer to the 16-bit N register.
The device features fully programmable R and N counters, an amplifier
at the f in pin, on–chip support of an external crystal, a programmable reference output, and both single and double–ended phase detectors with
linear transfer functions (no dead zones). A configuration (C) register
allows the part to be configured to meet various applications. A patented
feature allows the C register to shut off unused outputs, thereby minimizing noise and interference.
In order to reduce lock times and prevent erroneous data from being
loaded into the counters, a patented jam load feature is included.
Whenever a new divide ratio is loaded into the N register, both the N and
R counters are jam–loaded with their respective values and begin counting down together. The phase detectors are also initialized during the jam
load.
• Operating Voltage Range: 2.7 to 5.5 V
• Operating Temperature Range: TA = –40º to +85º C
• Maximum Operating Frequency:
185 MHz @ Vin = 500 mVpp, 4.5 V Minimum Supply
100 MHz @ Vin = 500 mVpp, 3.0 V Minimum Supply
• Operating Supply Current:
0.6 mA @ 3.0 V, 30 MHz
1.5 mA @ 3.0 V, 100 MHz
3.0 mA @ 5.0 V, 50 MHz
5.8 mA @ 5.0 V, 185 MHz
• R Counter Division Range: 1 and 5 to 32,767
• N Counter Division Range: 40 to 65,535
• Direct Interface to Motorola SPI Serial Data Port
• See Application Notes AN1207/D and AN1671/D
• See web site www.lansdale.com for ML145170 control software
16
1
P DIP 16 = EP
PLASTIC PACKAGE
CASE 648
16
16
1
1
SO 16 = -5P
PLASTIC PACKAGE
CASE 751B
TSSOP 16 = -7P
PLASTIC PACKAGE
CASE 948C
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 16
MC145170P2
ML145170EP
SO 16
MC145170D2
ML145170-5P
TSSOP 16
MC145170DT2 ML145170-7P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN CONNECTIONS
φ
φ
BitGrabber™ is a trademark of Motorola/Freescale
Page 1 of 26
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LANSDALE Semiconductor, Inc.
ML145170
ML145170
BLOCK DIAGRAM
φ
φ
This device contains 4,800 active transistors.
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage
VDD
–0.5 to 5.5
V
DC Input Voltage
Vin
–0.5 to VDD + 0.5
V
DC Output Voltage
Vout
–0.5 to VDD + 0.5
V
DC Input Current, per Pin
Iin
±10
mA
DC Output Current, per Pin
Iout
±20
mA
DC Supply Current VDD and VSS Pins
IDD
±30
mA
Power Dissipation, per Package
PD
300
mW
Storage Temperature
Tstg
–65 to 150
°C
Lead Temperature, 1 mm from Case
for 10 seconds
TL
260
°C
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g. either VSS
or VDD). Unused outputs must be left open.
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in teh Electrical Characteristics
tables or Pin Descriptions section.
Page 2 of 26
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ML145170
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS. TA = –40° to 85°C)
Parameter
Test Condition
Power Supply Voltage Range
Symbol
VDD
V
Guaranteed
Limit
Unti
VDD
–
2.7 to 5.5
V
Maximum Low-Level Input Voltage [Note 1]
(Din, CLK, ENB, fin)
DC Coupling to fin
VIL
2.7
4.5
5.5
0.54
1.35
1.65
V
Minimum High-Level Input Voltage [Note 1]
(Din, CLK, ENB, fin)
DC Coupling to fin
VIH
2.7
4.5
5.5
2.16
3.15
3.85
v
VHys
2.7
5.5
0.15
0.20
v
Minimum Hysteresis Voltage (CLK, ENB)
Maximum Low-Level Output Voltage
(Any Output)
Iout = 20 µA
VOL
2.7
5.5
0.1
0.1
v
Minimum high-Level Output Voltage
(Any Output)
Iout = –20 µA
VOH
2.7
5.5
2.6
5.4
v
Minimum Low-Level output Current
(PDout, REFout, fR, fV, LD, φR, φV)
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
IOL
2.7
4.5
5.5
0.12
0.36
0.36
mA
Minimum High-Level Output Current
(PDout, REFout, fR, fV, LD, φR, φV)
Vout = 2.4 V
Vout = 4.1 V
Vout = 5.0 V
IOH
2.7
4.5
5.5
-0.12
-0.36
-0.36
mA
Minimum Low-Level Output Current
(Dout)
Vout = 0.4 V
IOL
4.5
1.6
mA
Maximum High-Level Output Current
(Dout)
Vout = 4.1 V
IOH
4.5
-1.6
mA
Maximum Input Leakage Current
(Din, CLK, ENB, OSCin)
Vin = VDD or VSS
Iin
5.5
±1.0
µA
Maximum Input Current
(fin)
Vin = VDD or VSS
Iin
5.5
±150
µA
Vin = VDD or VSS.
Output in High-Impedance State
IOZ
5.5
±100
nA
5.5
±5.0
µA
Maximum Quieschent Supply Current
Vin = VDD or VSS: Outputs Open;
Excluding fin Amp Input Current Component
IDD
5.5
100
µA
Maximum Operating Supply Current
fin = 500 mVpp;
OSCin = 1.0 MHz @ 1.0 Vpp;
LD, fR, fV, REFout = Inactive and No Connect;
OSCout, φV, φR, PDout = No Connect;
Din, ENB, CLK = VDD or VSS
Idd
–
[Note 2]
mA
Maximum Output Leakage Current
(PDout)
(Dout)
NOTES: 1. When DC coupling to the OSCin pin is used, the pin must be driven rail–to–rail, In this case, OSCout should be floated.
2. The nominal values at 3.0 V are 0.6 mA @ 30 MHz, and 1.5 mA @ 100 MHz. The nominal values at 5.0 V are 3.0 mA @ 50 MHz, and 5.8 mA
@ 185 MHz. These are not guaranteed limits.
Page 3 of 26
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ML145170
AC INTERFACE CHARACTERISTICS ( TA = –40° to 85°C, CL= 50 pF, Input tr = tr = 10 ns, unless otherwise noted.)
Symbol
Figure
No.
VDD
V
Guaranteed
Limit
fclk
1
2.7
4.5
5.5
dc to 3.0
dc to 4.0
dc to 4.0
MHz
Maximum Propagation Delay, CLK to Dout
tPLH, tPHL
1, 5
2.7
4.5
5.5
150
85
85
ns
Maximum Disable Time, Dout Active to High Impedance
tPLZ, tPHZ
2, 6
2.7
4.5
5.5
300
200
200
ns
Access Time, Dout High Impedance to Active
tPZL tPZH
2, 6
2.7
4.5
5.5
0 to 200
0 to 100
0 to 100
ns
tTLH, tTHL
1, 5
2.7
4.5
5.5
150
50
50
ns
1, 5
2.7
4.5
5.5
900
150
150
ns
Parameter
Serial Data Clock Frequency (Note: Refer to Clock t w Below)
Maximum Output Transition Time, D out
CL = 50 pF
CL = 200 pF
Unit
Maximum Input Capacitance – Din, ENB, CLK
Cin
–
10
pF
Maximum Output Capacitance – Dout
Cout
–
10
pF
Unit
TIMING REQUIREMENTS ( TA = –40° to 85°C, Input tr = t = 10 ns, unless otherwise noted.)
f
Parameter
Minimum Setup and Hold Times, Din vs CLK
Minimum Setup, Hold, and Recovery Times, ENB vs CLK
Minimum Inactive–High Pulse Width, ENB
Minimum Pulse Width, CLK
Maximum Input Rise and Fall Times, CLK
Page 4 of 26
Symbol
Figure
No.
VDD
V
Guaranteed
Limit
tsu, th
3
2.7
4.5
5.5
55
40
40
ns
tsu, th, trec
4
2.7
4.5
5.5
135
100
100
ns
tw(H)
4
2.7
4.5
5.5
400
300
300
ns
tw
1
2.7
4.5
5.5
166
125
125
ns
tr, tf
1
2.7
4.5
5.5
100
100
100
µs
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ML145170
SWITCHING WAVEFORMS
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5. Test Circuit
Figure 6. Test Circuit
Ω
*Includes all probe and fixtures capacitance.
Page 5 of 26
*Includes all probe and fixtures capacitance.
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LANSDALE Semiconductor, Inc.
ML145170
LOOP SPECIFICATION ( TA = –40° to 85°C)
Guaranteed Range
Symbol
Figure
No.
VDD
Test Condition
V
Min
Max
Unit
Vin ≥ 500 mVpp Sine Wave
N Counter Set to Divide Ratio
Such that f ≤ 2.0 MHz
f
7
2.7
3.0
4.5
5.5
5.0
5.0
25
45
80
100
185
185
MHz
Input Frequency, OSCin
Externally Driven with AC–coupled
Signal
Vin ≥ 1.0 VPP Sine Wave
OSCout = No Connect
R Counter Set to Divide Ratio
Such that fR ≤ 2 MHz
f
8a
2.7
3.0
4.5
5.5
1.0*
1.0*
1.0*
1.0*
22
25
30
35
MHz
Crystal Frequency, OSCin and OSCout
C1 ≤ 30 pF
C2 ≤ 30pF
Includes Stray Capacitance
fXTAL
9
2.7
3.0
4.5
5.5
2.0
2.0
2.0
2.0
12
12
15
15
MHz
Output Frequency REFout
CL = 30 pF
fout
10, 12
2.7
4.5
5.5
DC
DC
DC
–
10
10
MHz
2.7
4.5
5.5
DC
DC
DC
–
20
20
MHz
Parameter
Input Frequency, fin [Note]
v
Operating Frequency of the
Phase Detectors
f
Output Pulse Width, φR, φV, and LD
fR in Phase with fV
CL = 50 pF
Output Transition Times,
φR, φV, LD, fR, and fV
CL = 50pF
Input Capacitance
fin
OSCin
tw
11, 12
2.7
4.5
5.5
–
20
16
–
100
90
ns
tTLH,
tTHL
11, 12
2.7
4.5
5.5
–
–
–
–
65
60
ns
Cin
–
–
–
–
–
–
7.0
7.0
pF
* IF lower frequency is desired, use wave shaping or higher amplitude sinusoidal signal in AC–coupled case. Also, see Figure 22 for DC coupling
Page 6 of 26
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ML145170
Figure 7. Test Circuit fin
Ω
*Characteristic Impedance
Figure 8.
Figure 8a. Test Circuit, OSC Circuit Externally Driven [Note]
Figure 8b. Circuit to Eliminate Self–Oscillation,
OSC Circuit Externally Driven [Note]
µ
µ
Ω
Ω
Ω
Ω
Ω
Figure 9. Test Circuit, OSC Circuit with Crystal
Figure 10. Switching Waveform
Figure 11. Switching Waveform
Figure 12. Test Load Circuit
*Includes all probe and
fixture capacitance.
NOTE:
Page 7 of 26
Use the circuit of Figure 8b to eliminate self–oscillation of the OSC in pin when the ML145170 has power applied with no external signal.
applied at Vin. (Self–oscillation is not harmful to the ML145170 and does not damage the IC.)
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ML145170
PIN DESCRIPTIONS
DIGITAL INTERFACE PINS
Din
Serial Data Input (Pin 5)
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the N register, or 3 bytes
(24 bits) to access the R register. Additionally, the R register
can be accessed with a 15–bit transfer (see Table 1). An
optional pattern which resets the device is shown in Figure 13.
The values in the C, N, and R registers do not change during
shifting because the transfer of data to the registers is controlled by ENB.
The bit stream needs neither address nor steering bits due to
the innovative BitGrabber registers. Therefore, all bits in the
stream are available to be data for the three registers. Random
access of any register is provided (i.e., the registers may be
accessed in any sequence). Data is retained in the registers
over a supply range of 2.7 to 5.5 V. The formats are shown in
Figures 13, 14, 15, and 16.
Din typically switches near 50% of VDD to maximize noise
immunity. This input can be directly interfaced to CMOS
devices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 to
10 kΩ must be used. Parameters to consider when sizing the
resistor are worst–case IOL of the driving device, maximum
tolerable power consumption, and maximum data rate.
Table 1. Register Access
(MSBs are shifted in first, C0, N0, and R0 are the LSBs)
Number
of Clocks
Accessed
Register
9 to 13
8
16
15 or 24
Other Values ≤ 32
Values > 32
See Figure 13
C Register
N Register
R Register
None
See Figures
24 – 31
Bit
Nomenclature
(Reset)
C7, C6, C5,…, C0
N15, N14, N13,…, N0
R14, R13, R12,…, R0
CLK
Serial Data Clock Input (Pin 7)
Low–to–high transistion on Clock shift bits available at Din,
while high–to–low transitions shift bits from D out. The chip’s
16–1/2–stage shift register is static, allowing clock rates down
to DC in a continuous or intermittent mode.
Four to eight clock cycles followed by five clock cycles are
needed to reset the device; this is optional. Eight clock cycles
are required to access the C register. Sixteen clock cycles are
needed for the N register. Either 15 or 24 cycles can be used
to access the R register (see Table 1 and Figures 13, 14, 15,
and 16). For cascaded devices, see Figures 24 to 31.
CLK typically switches near 50% of VDD and has a
Schmitt–triggered input buffer. Slow CLK rise and fall times
are allowed. See the last paragraph of Din for more information.
Page 8 of 26
NOTE
To guarantee proper operation of the power–on reset
(POR) circuit, the CLK pin must be held at the potential
of either the VSS or VDD pin during power up. That is,
the CLK input should not be floated or toggled while
the VDD pin is ramping from 0 to at least 2.7 V. If control of the CLK pin is not practical during power up, the
initialization sequence shown in Figure 13 must be used.
ENB
Active–Low Enable Input (Pin 6)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an inactive
high state, shifting is inhibited, Dout is forced to the
high–impedance state, and the port is held in the initialized
state. To transfer data to the device, ENB (which must start
inactive high) is taken low, a serial transfer is made via Din and
CLK, and ENB is taken back high. The low–to–high transition
on ENB transfers data to the C, N, or R register depending on
the data stream length per Table 1.
Note
Transitions on ENB must not be attempted while CLK
is high. This puts the device out of synchronization
with the microcontroller. Resynchronization occurs
when ENB is high and CLK is low.
This input is also Schmitt–triggered and switches near 50%
of VDD, thereby minimizing the chance of loading erroneous
data into the registers. See the last paragraph of Din for more
information.
Dout
Three–State Serial Data Output (Pin 8)
Data is transferred out of the 16–1/2–stage shift register
through Dout on the high–to–low transition of CLK. This output is a No Connect, unless used in one of the manners discussed below.
Dout could be fed back to an MCU/MPU to perform a
wrap–around test of serial data. This could be part of a system
check conducted at power up to test the integrity of the system’s processor, PC board traces, solder joints, etc.
Finally, Dout facilitates trouble shooting a system and permits cascading devices.
REFERENCE PINS
OSCin/OSCout
Reference Oscillator Input/Output (Pins 1, 2)
These pins form a reference oscillator when connected to
terminals of an external parallel–resonant crystal. Frequency
setting capacitors of appropriate values as recommended by the
crystal supplier are connected from each pin to ground (up to a
maximum of 30 pF each, including stray capacitance). An
external feedback resistor of 1.0 to 5.0 MΩ is connected
directly across the pins to ensure linear operation of the amplifier. The required connections for the components are shown in
Figure 9.
If desired, an external clock source can be AC coupled to
OSCin. A 0.01 µF coupling capacitor is used for measurement
purposes and is the minimum size recommended for
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applications. An external feedback resistor of approximately
5 MΩ is required across the OSCin and OSCout pins in the
AC–coupled case (see Figure 8a or alternate circuit 8b).
OSCout is an internal node on the device and should not be
used to drive any loads (i.e. OSCout is unbuffered). However,
the buffered REFout is available to drive external loads.
The external signal level must be at least 1 V p–p; the maximum frequencies are given in the Loop Specifications table.
These maximum frequencies apply for R Counter divide ratios
as indicated in the table. For very small ratios, the maximum
frequency is limited to the divide ratio times 2 MHz. (Reason:
the phase/frequency detectors are limited to a maximum input
frequency of 2 MHz.)
If an external source is available which swings virtually
rail–to–rail (VDD to VSS), then DC coupling can be used. In
the DC–coupled case, no external feedback resistor is needed.
OSCout must be a No Connect to avoid loading an internal
node on the device, as noted above. For frequencies below 1
MHz, DC coupling must be used. The R counter is a static
counter and may be operated down to DC. However, wave
shaping by a CMOS buffer may be required to ensure fast rise
and fall times into the OSCin pin. See Figure 22.
Each rising edge on the OSCin pin causes the R counter to
decrement by one.
REFout
Reference Frequency Output (Pin 3)
This output is the buffered output of the crystal–generated
reference frequency or externally provided reference source.
This output may be enabled, disabled, or scaled via bits in the
C register (see Figure 14).
REFout can be used to drive a microprocessor clock input,
thereby saving a crystal. Upon power up, the on–chip
power–on–initialize circuit forces REFout to the OSCin divided–by–8 mode.
REFout is capable of operation to 10 MHz; see the Loop
Specifications table. Therefore, divide values for the reference
divider are restricted to two or higher for OSCin frequencies
above 10 MHz.
If unused, the pin should be floated and should be disabled
via the C register to minimize dynamic power consumption
and electromagnetic interference (EMI).
COUNTER OUTPUT PINS
fR
R Counter Output (Pin 9)
This signal is the buffered output of the 15–stage R counter.
fR can be enabled or disabled via the C register (patented). The
output is disabled (static low logic level) upon power up. If
unused, the output should be left disabled and unconnected to
minimize interference with external circuitry.
The fR signal can be used to verify the R counter’s divide
ratio. This ratio extends from 5 to 32,767 and is determined by
the binary value loaded into the R register. Also, direct access
to the phase detector via the OSCin pin is allowed by choosing
a divide value of 1 (see Figure 15). The maximum frequency
which the phase detectors operate is 2 MHz. Therefore, the frequency of fR must not exceed 2 MHz.
When activated, the f R signal appears as normally low and
pulses high. The pulse width is 4.5 cycles of the OSCin pin sigPage 9 of 26
nal, except when a divide ration of 1 is selected. When 1 is
selected, the OSCin signal is buffered and appears at the fR pin.
fV
N Counter Output (Pin 10)
This signal is the buffered output of the 16–stage N counter.
fV can be enabled or disabled via the C register (patented).
The output is disabled (static low logic level) upon power up.
If unused, the output should be left disabled and unconnected
to minimize interference with external circuitry.
The fV signal can be used to verify the N counter’s divide
ratio. This ratio extends from 40 to 65,535 and is determined
by the binary value loaded into the N register. The maximum
frequency which the phase detectors operate is 2 MHz.
Therefore, the frequency of fV must not exceed 2 MHz.
When activated, the fV signal appears as normally low and
pulses high.
LOOP PINS
f in
Frequency Input (Pin 4)
This pin is a frequency input from the VCO. This pin feeds
the on–chip amplifier which drives the N counter. This signal
is normally sourced from an external voltage–controlled oscillator (VCO), and is AC–coupled into f in. A 100 pF coupling
capacitor is used for measurement purposes and is the minimum size recommended for applications (see Figure 7). The
frequency capability of this input is dependent on the supply
voltage as listed in the Loop Specifications table. For small
divide ratios, the maximum frequency is limited to the divide
ratio times 2 MHz. (Reason: the phase/frequency detectors are
limited to a maximum frequency of 2 MHz.)
For signals which swing from at least the VIL to VIH levels
listed in the Electrical Characteristics table, DC coupling
may be used. Also, for low frequency signals, (less than the
minimum frequencies shown in the Loop Specifications
table), DC coupling is a requirement. The N counter is a static
counter and may be operated down to DC. However, wave
shaping by a CMOS buffer may be required to ensure fast rise
and fall times into the f in pin. See Figure 22.
Each rising edge on the f in pin causes the N counter to decrement by 1.
PDout
Single–Ended Phase/Frequency Detector Output (Pin 13)
This is a three–state output for use as a loop error signal
when combined with an external low–pass filter. The detector’s dead zone has been eliminated. Therefore, the phase/frequency detector is characterized by a linear transfer function.
The operation of the phase/frequency detector is described
below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR: negative
pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: positive
pulses from high impedance
Frequency and Phase of fV = fR; essentially high–impedance
state; voltage at pin determined by loop filter
POL bit (C7) = high
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Frequency of fV > fR or Phase of fV Leading fR: positive
pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: negative
pulses from high impedance
Frequency and Phase of fV = fR: essentially high–impedance
state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the C
register. If desired, PDout can be forced to the high–impedance
state by utilization of the disable feature in the C register
(patented).
φR and φV
Double–Ended Phase/Frequency Detector Outputs (Pins 14,
15)
These outputs can be combined externally to generate a loop
error signal. Through use of a Motorola patented technique,
the detector’s dead zone has been eliminated. Therefore, the
phase/frequency detector is characterized by a linear transfer
function. The operation of the phase/frequency detector is
described below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR: φV = negative pulses, φR = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φV =
essentially high, φR = negative pulses
Frequency and Phase of fV = fR: φV and φR remain essentially high, except for a small minimum time period when both
pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: φR = negative pulses, φV = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φR = essen-
tially high, φV = negative pulses
Frequency and Phase of fV = fR: φV and φR remain essentially high, except for a small minimum time period when both
pulse low in phase
These outputs can be enabled, disabled, and interchanged via
the C register (patented)
LD
Lock Detector Output (Pin 11)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (fR and fV of the
same phase and frequency). The output pulses low when fV
and fR are out of phase or different frequencies (See Figure
17).
This output can be enabled and disabled via the C register
(patented). Upon power up, on–chip initialization circuitry disables LD to a static low logic level to prevent a false “lock”
signal. If unused, LD should be disabled and left open.
POWER SUPPLY
VDD
Most Positive Supply Potential (Pin 16)
This pin may range from 2.7 to 5.5 V with respect to VSS.
For optimum performance, VDD should be bypassed to VSS
using low–inductance capacitor(s) mounted very close to the
device. Lead lengths on the capacitor(s) should be minimized.
(The very fast switching speed of the device causes current
spikes on the power leads.)
VSS
Most Negative Supply Potential (Pin 12)
This pin is usually ground. For measurement purposes, the
VSS pin is tied to a ground plane.
Figure 13. Reset Sequence
NOTE:
Page 10 of 26
This initialization sequence is usually not necessary because the on–chip power–on reset circuit performs the initialization
function. However, this initialization sequence must be used immediately after power up if control of the CLK pin is not
possible. That is, if CLK (Pin 7) toggles or floats upon power up, use the above sequence to reset the device.
Also, use this sequence if power is momentarily interrupted such thh
h at the supply voltage to the device is reduced to below
2.7 V, but not down to at least 1 V (for example, the supply drops down to 2 V). This is necessary because the on–chip
power–on reset is only activated when the supply ramps up from a voltage below approximately 1.0 V.
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LANSDALE Semiconductor, Inc.
ML145170
Figure 14. C Register Access and Format (8 Clock Cycles are Used)
*At this point, the new byte is transferred to the C register and stored. No other registers
are affected.
C7–POL:
C6–PDA/B:
C5–LDE:
C4–C2, OSC2–OSC0:
Page 11 of 26
Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts
PDout and interchanges the φR funtion with φV as depicted in Figure 17. Also see the phase
detector output pin description for more information. This bit is cleared low at power up.
Selects which phase/frequency detector is to be used. When set high, enables the output of
phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing φR
and φV to the static high state. When cleared low, phase/frequency detector B is enabled (φ R
and φV) and phase/frequency detector A is disabled with PDout forced to the high–impedance
state. This bit is cleared low at power up.
Enables the lock detector output when set high. When the bit is cleared low, the LD output is
forced to a static low level. This bit is cleared low at power up.
Reference output controls which determine the REFout characteristics as shown below. Upon
power up, the bits are initialized such that OSCin/8 is selected.
C4
C3
C2
0
0
0
DC (Static Low)
0
0
1
OSCin
0
1
0
OSCin /2
0
1
1
OSCin /4
1
0
0
OSCin /8 (POR Default)
1
0
1
OSCin /16
1
1
0
OSCin /8
1
1
1
OSCin /16
REFout Frequency
C1–fVE:
Enables the fV output when set high. When cleared low, the fV output is forced to a static low
level. The bit is cleared low upon power up.
C0–fRE:
Enables the fR output when set high. When cleared low, the fR output is forced to a static low
level. The bit is cleared low upon power up.
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Page 12 of 26
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*At this point, the new data is transferred to the R register and stored. No other registers are affected.
÷
÷
÷
÷
÷
÷
Figure 15. R Register Access and Formats (Either 24 or 15 Clock Cycles Can Be Used)
ML145170
LANSDALE Semiconductor, Inc.
?????? ???
Issue A
LANSDALE Semiconductor, Inc.
ML145170
Figure 16. N Register Access and Format (16 Clock Cycles Are Used)
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
⋅⋅
⋅
÷
÷
÷
÷
÷
÷
*At this point, the two new bytes are transferred to the N register and stored. No other registers are affected. In addition, the N and
R counters are jam–loaded and begin counting down together.
Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveform
÷
÷
φ
φ
NOTE:
Page 13 of 26
The PDout generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance and
the voltage at that pin is determined by the low–pass filter capacitor. PDout, φR and φV are shown with the polarity bit (POL) - low;
see Figure 14 for POL.
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LANSDALE Semiconductor, Inc.
ML145170
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a reference frequency to Lansdale’s/Motorola’s CMOS frequency
synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscillators provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
DC coupled to OSCin. If the oscillator does not have CMOS
logic levels on the outputs, capacitive or AC coupling to
OSCin may be used (see Figures 8a and 8b).
For additional information about TCXOs, visit freescale.com
on the world wide web.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at the
desired operating frequency, should be connected as shown in
Figure 18.
The crystal should be specified for a loading capacitance
(CL) which does not exceed 20 pF when used at the highest
operating frequencies listed in the Loop Specifications table.
Larger CL values are possible for lower frequencies. Assuming
R1 = 0 Ω, the shunt load capacitance (CL) presented across the
C
L
C C out
in
C
C out
in
Ca
C stray
C1
C1
use of R1 is not necessary in most cases.
To verify that the maximum DC supply voltage does not
cause the crystal to be overdriven, monitor the output frequency at the REFout pin (OSCout is not used because loading
impacts the oscillator). The frequency should increase very
slightly as the DC supply voltage is increased. An overdriven
crystal decreases in frequency or becomes unstable with an
increase in supply voltage. The operating supply voltage must
be reduced or R1 must be increased in value if the overdriven
condition exists. The user should note that the oscillator
start–up time is proportional to the value of R1.
Through the process of supplying crystals for use with CMOS
inverters, many crystal manufacturers have developed expertise
in CMOS oscillator design with crystals. Discussions with
such manufacturers can prove very helpful (see Table 2).
Figure 18. Pierce Crystal Oscillator Circuit
C2
C2
*May be needed in certain cases. See text.
where
Cin =
Cout =
Ca =
C1 and C2 =
Cstray =
5.0 pF (see Figure 19)
6.0 pF (see Figure 19)
1.0 pF (see Figure 19)
external capacitors (see Figure 18)
the total equivalent external circuit stray
capacitance appearing across the crystal
terminals
crystal can be estimated to be:
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin and
OSCout pins to minimize distortion, stray capacitance, stray
inductance, and startup stabilization time. Circuit stray capacitance can also be handled by adding the appropriate stray value
to the values for Cin and Cout. For this approach, the term
Cstray becomes 0 in the above expression for CL.
A good design practice is to pick a small value for C1 such
as 5 o 10 pF. Next, C2 is calculated. C1 < C2 results in a more
robust circuit for start–up and is more tolerant of crystal
parameter variations.
Power is dissipated in the effective series resistance of the
crystal Re, in Figure 20. The maximum drive level specified by
the crystal manufacturer represents the maximum stress that
the crystal can withstand without damage or excessive shift in
operating frequency. R1 in Figure 18 limits the drive level. The
Page 14 of 26
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Figure 19. Parasitic Capacitances of the Amplifier
and Cstray
Figure 20. Equivalent Crystal Networks
NOTE:
Values are supplied by crystal manufacturer
(parallel resonant crystal).
Issue A
LANSDALE Semiconductor, Inc.
ML145170
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit–Definitions and
Method of Measurement”, Proc. IEEE, Vol 57, No. 2, Feb.
1969
D. Kemper, L Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June 1969
P.J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May 1966
D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985
See web site Lansdale.com for ML145170 software.
Table 2. Partial List of Crystal
Manufacturers
CTS Corp.
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE:
Page 15 of 26
Lansdale cannot recommend one
supplier over another and in no
way suggests that this is a
complete listing of crystal
manufactuers.
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Issue A
LANSDALE Semiconductor, Inc.
ML145170
PHASE–LOCKED LOOP—LOW PASS FILTER DESIGN
(A)
φ
ω
ω
ζ
(B)
φ
φ
ω
ζ
ω
(C)
ω
φ
φ
φ
=
ζ=
φ
ω
NOTES:
1. For (C), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor C C is then placed from
the midpoint to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network
does not significantly affect ωn.
2. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of
the op amp.
3. For the latest information on MC33077 or equivalent, contact ON Semiconductor.
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
Kφ (Phase Detector Gain) = VDD / 4π volts per radian for PDout
Kφ (Phase Detector Gain) = VDD / 2π volts per radian for φV and φR
KVCO (VCO Gain) =
2π∆fVCO
∆VVCO
For a nominal design starting point, the user might consider a damping factor ζ ≈ 0.7 anda natural loop frequency ωn ≈ (2πfR/50) where
fR is the frequency at the phase detector input. Larger ωn values result in faster loop lock times and, for similar sideband filtering,higher
fR–related VCO sidebands.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design, New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock, New York, Wiley–Interscience, 1981
Rohde, Ulrich, L., Digital PLL Frequency Synthesizers Theory and Design, Englewood Cliffs, NJ, Prentice–Hall 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits with Experiments, Indianapolis, Howard W. Sams and Co. 1978.
Kinley, Harold., The PLL Synthesizer Cookbook, Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538-586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1207, The MC145170 in Basic HF and VHF Oscillators, Motorola Semiconductor Products, Inc., 1992.
AN1671, MC145170 PSpice Modeling Kit, Motorola Semiconductor Products, Inc., 1998.
Page 16 of 26
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Issue A
LANSDALE Semiconductor, Inc.
ML145170
Figure 21. Example Application
φ
ML145170
φ
NOTES:
1. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked
Loop—Low–Pass Filter Design page for additional information. The φR and φV outputs swing
rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range
of the op amp used in the combiner/loop filter.
2. For optimum performance, bypass the VDD pin to VSS (GND) with one or more low–inductance
capacitors.
3. The R counter is programmed for a divide value = OSCin/fR. Typically, fR is the tuning resolution
required for the VCO. Also, the VCO frequency divided by fR = N, where N is the divide value of
the N counter.
4. May be an R–C low–pass filter.
5. May be a bipolar transistor.
Page 17 of 26
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Issue A
LANSDALE Semiconductor, Inc.
ML145170
Figure 22. Low Frequency Operation Using DC Coupling
ML145170
NOTE: The signals at Points A and B may be low–frequency sinusoidal
or square waves with slow edge rates or noisy signal edges. At
Points C and D, the signals are cleaned up, have sharp edge
rates, and rail–to–rail signal swings. With signals as described at
Points C and D, the ML145170 is guaranteed to operate down
to a frequency as low as DC.
Refer to the MC74HC14A data sheet for input switching levels
and hysteresis voltage range.
Page 18 of 26
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Issue A
LANSDALE Semiconductor, Inc.
ML145170
Figure 23. Input Impedance at fin — Series Format (R + jX)
(5.0 MHz to 185 MHz)
Ω
Ω
Figure 24. Cascading Two ML145170 Devices
ML145170
ML145170
Ω
NOTES:
1. The 33 kΩ resistor is needed to prevent the Din pin from floating. (The Dout pin is a three–state output.)
2. See related Figures 25, 26, and 27.
Page 19 of 26
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?????? ???
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NOTE: At this point, the new data is transferred to the R reigisters of both devices and stored. No other registers are affected.
Figure 26. Accessing the R Registers of Two Cascading ML145170 Devices
NOTE: At this point, the new data is transferred to the C registers of both devices and stored. No other registers are affected.
Figure 25. Accessing the C Registers of Two Cascading ML145170 Devices
ML145170
LANSDALE Semiconductor, Inc.
?????? ???
Issue A
Page 21 of 26
NOTE: At this point, the new data is transferred to the N registers of both devices and stored. No other registers are affected.
Figure 27. Accessing the N Registers of Two Cascaded ML145170 Devices
ML145170
LANSDALE Semiconductor, Inc.
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Issue A
LANSDALE Semiconductor, Inc.
ML145170
Figure 28. Cascading Two Different Device Types
ML145170
Ω
NOTES:
1. The 33 kΩ resistor is needed to prevent the D in pin from floating (The Dout pin is a three–state output.)
2. This PLL Frequency Synthesizer may be a ML12210, ML12202, etc.,…
3. See related Figures 29, 30, and 31.
Page 22 of 26
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Issue A
Page 23 of 26
?????? ???
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NOTE: At this point, the new data is transferred to the A register of Device #2 and R register of Device #1 and stored. No other registers are affected
Figure 30. Accessing the A and R Registers of Two Different Device Types
NOTE: At this point, the new data is transferred to the C registers of both devices and stored. No other registers are affected.
Figure 29. Accessing the C Registers of Two Different Device Types
ML145170
LANSDALE Semiconductor, Inc.
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Issue A
Page 24 of 26
NOTE: At this point, the new data is transferred to the R register of Device #2 and N register of Device #1 and stored. No other registers are affected.
Figure 31. Accessing the R and N Registers of Two Different Device Types
ML145170
LANSDALE Semiconductor, Inc.
?????? ???
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Issue A
LANSDALE Semiconductor, Inc.
ML145170
OUTLINE DIMENSIONS
TSSOP 16 = -7P
PLASTIC PACKAGE
CASE 948C-03
(ML145170-7P)
ISSUE B
A
-P-
16
16x K
REF
9
B
L
PIN 1
IDENTIFICATION
1
8
-U-
C
D
-T-
H
G
A
K
J1
K1
M
°
°
°
°
J
A
SECTION A–A
Page 25 of 26
F
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Issue A
LANSDALE Semiconductor, Inc.
ML145170
OUTLINE DIMENSIONS
P DIP 16 = EP
PLASTIC PACKAGE
CASE 648-08
(ML145170EP)
ISSUE R
-A-
B
F
C
L
S
-TK
H
G
D
M
J
16 PL
SO 16 = -5P
PLASTIC PACKAGE
CASE 751B-05
(ML145170-5P)
(SOG-16)
ISSUE J
-A-
-B-
P
8 PL
G
R
K
F
X 45
C
-TM
D
J
16 PL
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. T
Ò ypical ” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 26 of 26
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Issue A