MC100LVEL51 3.3V ECL Differential Clock D Flip‐Flop Description Features • • • • • • • 8 8 1 1 SOIC−8 NB D SUFFIX CASE 751 TSSOP−8 DT SUFFIX CASE 948R 8 KVL51 ALYW G > 200 V Machine Model The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level ♦ Level 1 for SOIC−8 NB ♦ Level 3 for TSSOP−8 ♦ Level 1 for DFN−8 ♦ For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 114 devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant DFN−8 MN SUFFIX CASE 506AA MARKING DIAGRAMS* 8 • 475 ps Propagation Delay • 2.8 GHz Toggle Frequency • ESD Protection: > 4 kV Human Body Model, • • www.onsemi.com 1 1 SOIC−8 4G M G G The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3 V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3 V VCC. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2. KV51 ALYWG G 1 TSSOP−8 A L Y W M G 4 DFN−8 = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Package Shipping† MC100LVEL51DG SOIC−8 NB (Pb-Free) 98 Units/Tube MC100LVEL51DR2G SOIC−8 NB (Pb-Free) 2500/Tape & Reel MC100LVEL51DTG TSSOP−8 (Pb-Free) 100 Units/Tube MC100LVEL51DTR2G TSSOP−8 (Pb-Free) 2500/Tape & Reel MC100LVEL51MNR4G DFN−8 (Pb-Free) 1000/Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 7 1 Publication Order Number: MC100LVEL51/D MC100LVEL51 R 1 D 2 8 VCC 7 Q R D Flip-Flop CLK 3 6 Q CLK 4 5 VEE Figure 1. Logic Diagram and Pinout Assignment Table 1. PIN DESCRIPTION Table 2. TRUTH TABLE PIN FUNCTION D R CLK Q CLK, CLK Q, Q D R VCC VEE ECL Differential Clock Input ECL Differential Output ECL D Input ECL Reset Input Positive Supp;y Negative Supply L H X L L H Z Z X L H L EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Z = LOW to HIGH Transition X = Don’t Care www.onsemi.com 2 MC100LVEL51 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V Iout Output Current Continuous Surge 50 100 mA VI ≤ VCC VI ≥ VEE TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−8 NB 190 130 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm TSSOP−8 185 140 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm DFN−8 129 84 °C/W Tsol Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C qJC Thermal Resistance (Junction-to-Case) (Note 1) 35 to 40 °C/W DFN−8 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) www.onsemi.com 3 MC100LVEL51 Table 4. LVPECL DC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 30 35 Min 85°C Typ Max 30 35 Min Typ Max Unit 32 37 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV VOL Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV VIH Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single-Ended) 1490 1825 1490 1825 1490 1825 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3) VPP < 500 mV VPP ≥ 500 mV IIH Input HIGH Current IIL Input LOW Current Others CLK V 1.2 1.4 3.0 3.0 1.1 1.3 3.0 3.0 150 0.5 −600 1.1 1.3 3.0 3.0 150 0.5 −600 150 mA mA 0.5 −600 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 2. Outputs are terminated through a 50ĂW resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 5. LVNECL DC CHARACTERISTICS (VCC = 0.0 V; VEE = −3.3 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 30 35 Min 85°C Typ Max 30 35 Min Typ Max Unit 32 37 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 2) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single-Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single-Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3) VPP < 500 mV VPP ≥ 500 mV IIH Input HIGH Current IIL Input LOW Current Others CLK V −2.1 −1.9 −0.3 −0.3 −2.2 −2.0 150 0.5 −600 −0.3 −0.3 −2.2 −2.0 150 0.5 −600 −0.3 −0.3 150 0.5 −600 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 2. Outputs are terminated through a 50ĂW resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. www.onsemi.com 4 MC100LVEL51 Table 6. AC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ fmax Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output CLK R 330 340 465 455 tS Setup Time 150 Max 2.7 Min 85°C Typ Max Min 2.8 Typ Max 2.9 Unit GHz ps 510 540 340 350 475 465 0 150 520 550 370 390 530 510 550 590 0 150 0 ps tH Hold Time 200 100 200 100 200 100 ps tRR Reset Recovery 350 200 350 200 350 200 ps tPW Minimum Pulse CLK Width Reset 400 400 400 500 500 500 tJITTER Cycle-to-Cycle Jitter VPP Input Swing (Note 2) 150 1000 150 1000 150 1000 mV Output Rise/Fall Times Q (20% − 80%) 120 320 120 320 120 320 ps tr tf TBD TBD ps TBD ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. VEE can vary ±0.3 V. 2. VPP (min) is minimum input swing for which AC parameters are guaranteed. Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 3.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) www.onsemi.com 5 MC100LVEL51 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices www.onsemi.com 6 MC100LVEL51 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 7 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC100LVEL51 PACKAGE DIMENSIONS TSSOP−8 CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF M T U V S 0.25 (0.010) B −U− 4 M A −V− S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E www.onsemi.com 8 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC100LVEL51 PACKAGE DIMENSIONS DFN8 2x2, 0.5P CASE 506AA ISSUE F D PIN ONE REFERENCE 2X 0.10 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 ÇÇ ÇÇ ÇÇ 0.10 C 0.10 C A B DETAIL A E OPTIONAL CONSTRUCTIONS ÉÉ ÉÉ ÇÇ EXPOSED Cu TOP VIEW A DETAIL B DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉ ÉÉ ÇÇ A3 MOLD CMPD A1 DETAIL B 0.08 C NOTE 4 (A3) SIDE VIEW DETAIL A ALTERNATE CONSTRUCTIONS A1 SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* D2 1 C MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 4 8X L 1.30 PACKAGE OUTLINE 8X 0.50 E2 K 8 5 e/2 e 0.90 8X 2.30 b 0.10 C A B 0.05 C 1 NOTE 3 8X 0.30 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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