OKI MSM7503 Multi-function pcm codec Datasheet

E2U0024-16-X2
¡ Semiconductor
MSM7503
¡ Semiconductor
This version: Jan.
1998
MSM7503
Previous version: Nov. 1996
Multi-Function PCM CODEC
GENERAL DESCRIPTION
The MSM7503 is a high performance, low power CODEC LSI device integrating a 2-wire time
division transmission (ping-pong transmission) interface function and has a basic function of
man-machine interface to that of the MSM7502.
The MSM7503 operates from single 5 V power supply and is ideal for digital telephone terminals
such as pushbutton telephone sets and digital PBXs.
The MSM7503 ping-pong transmission interface supports a bidirectional communication of up
to 800 m long on the 2-wire twisted pair line, and can send and receive voice data at 64 kbps and
control data at 16 kbps.
The man-machine interface consists of analog speech path, key-scanner, tone generators,
CODEC meeting the m/A companding law, and processor interface, which are controlled via 8bit data buses.
FEATURES
• Single +5 V Power Supply
• Low Power Dissipation
Power ON Mode
Power Down Mode
• Pin-Pong Transmission
: 50 mW Typ. 100 mW Max.
: 15 mW Typ. 30 mW Max.
: Burst of 8 kHz, Transmission of 256 kbps,
AMI coding, 2-wire time division transmission
• Transmission data configuration
: Transmit Start bit (1 bit), K-bit (1 bit),
Control bit (2 bits), Voice bit (8 bits),
DC balance bit (1 bit), totalling 13 bits
Receive Sync bit (4 bits), K-bit (1 bit),
Control bit (2 bits), Voice bit (8 bits),
DC balance bit (1 bit), totalling 16 bits
• Control Data Interface supports synchronous and asynchronous communications
• Built-in Power-on Reset by the power supply voltage monitoring
• Output of the ping-pong transmission monitoring signal
• CODEC complied by the ITU-T companding law
• Calling Tone Interval
: Controlled by processor
• Calling Tone Combination
: Controlled by processor, 6 modes
• Calling Tone Volume
: Controlled by processor, 4 modes
• Ringing Tone Interval
: Controlled by processor
• Ringing Tone Frequency
: Controlled by processor, 6 modes
• Ringing Tone Level
: Controlled by processor, 4 levels
• Built-in PB Tone Generator
• Built-in Speech path Control Switches
• General Latch Output for External Control : 2 bits
• Watch-dog Timer
: 500 ms
1/41
¡ Semiconductor
MSM7503
• Scanning I/O
Output
: 8 bits
Input
: 8 bits
• Direct Connection to Handset
: 1.2 kW driving available
• Built-in Pre-amplifier for Loud-speaker
• Hand-free Interface
• m-law/A-law Switchable CODEC
• LCD Deflection Angle Voltage
: Controlled by processor, 8 levels
• Package:
80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM7503GS-BK)
2/41
¡ Semiconductor
MSM7503
BLOCK DIAGRAM
Communication Suppervisor
I/O CLK
Start bit
Detector
Start-Stop
Sampling
R • Mix
Transmit Polarity Definition
T1N
T2N
I/O INTF
R1N
R2N
PS
SYNC
CLK1
CLK2
CLK3
CLC
FHW
FD
FK
BHW
BD
BDS
CTEST
T • Counter
T • Mix
XOUT
X1
X2
Crystal Oscillator
TEST
Reset
Voltage Detect
LRSTN
WDT Output
1024 kHz
VOL9
+
VOL8
TPBI
VOL10
SW9
0 dB
-
SPI
0 dB
SW10
VOL1
VOL2
-8.7 dB
0 dB
VOL7
SW3
SW4
SW17
SW14
SW13
SW5
SW5
-
VOL6
-
-
SPO
SA0
0 dB
-3 dB
-6.8 dB
SW6
SW8
SW18
VOL5
0 dB
VOL11
VOL12
SW21
SW15
SW11
SW20
VOL13
SW19
SG GEN.
VA
VD
AG
DG
SGT SGC
CAI
SW12
m/A
CODEC
AOUT
PCMIN
DIV
RMI
RMO0
RMO1
+
-
RPO
0 dB
5.7 dB
VOL3
VOL4
SW1
SW2
SW7
SW16
-
MLDYI
CAO
R1I
AIN
PCMOUT
20 dB
MPBI
R2I
TO
+
-
MPAO
MPAI
TPAO
TPAI
MPBO
64 kHz
8 kHz
PB GEN.
R Tone GEN.
400
425
440
450
400 ¥ 16
400 ¥ 20
WRN
RDN
CEN
Processor
INTF
F Tone GEN.
1 kHz
DB0
to
DB7
S Tone GEN.
AD0
Latch
AD1
LA
LB
VLCD GEN.
VLCD
Man-machine INTF
Scanning Output
Scanning Input
PO0~PO7
PI0~PI7
3/41
¡ Semiconductor
MSM7503
65 VD
66 X1
67 X2
68 TEST
69 XOUT
70 BDS
71 R1N
72 R2N
73 T1N
74 T2N
75 PS
76 BD
77 CLK3
78 CLC
79 FK
80 FD
PIN CONFIGURATION (TOP VIEW)
CLK2 1
64 CEN
CLK1 2
63 RDN
SYNC 3
62 WRN
FHW 4
61 AD1
BHW 5
60 AD0
CTEST 6
59 DB7
LRSTN 7
58 DB6
LB 8
57 DB5
LA 9
56 DB4
SAO 10
55 DB3
VLCD 11
54 DB2
DG 12
53 DB1
AG 13
52 DB0
RMO1 14
51 PI7
RMO0 15
50 PI6
RMI 16
49 PI5
SPI 17
48 PI4
SPO 18
47 PI3
RPO 19
46 PI2
R2I 20
45 PI1
R1I 21
44 PI0
PO3 40
PO4 39
PO5 38
PO6 37
PO7 36
CAO 35
SGC 34
CAI 33
VA 32
TO 31
SGT 30
41 PO2
TPAI 29
MPBI 24
TPAO 28
42 PO1
TPBI 27
MPBO 23
MPAI 26
43 PO0
MPAO 25
MLDYI 22
80-Pin Plastic QFP
4/41
¡ Semiconductor
MSM7503
PIN AND FUNCTIONAL DESCRIPTIONS
LA, LB
General latch outputs for external control.
Statuses of these outputs are controlled via the processor interface. Refer to the description of the
control data for details. These outputs provide the capability to drive one TTL.
DG
Digital Ground.
DG is separated from the analog ground AG inside the device. But, DG should be connected as
close to the AG pin on PCB as possible.
AG
Analog Ground.
SA0
Sounder (calling tone) driving outputs.
Through processor control, the calling tone volume is selectable from 4 levels and one of six tone
combinations is selectable. Initially, the calling tone volume is set at a maximum and the tone
combination is set at a 16 Hz Wamble tone by a combination of 1 kHz and 1.3 kHz.
The SA0 outputs pulse waveforms using DG as a reference potential.
5/41
¡ Semiconductor
MSM7503
RMI, RMO0, RMO1
Receive main amplifier input and outputs.
RMI is the inverted input and RMO0 and RMO1 are the outputs of the receive main amplifier.
The output signal on RMO1 is inverted against RMO0 by a gain 1 (0 dB), so the earphone of a
handset is directly connected between RMO0 and RMO1. During the system power down, the
RMO0 and RMO1 outputs are in a high impedance state. The receive main amplifier gain is
determined by a resistor connected between RPO and RMI, and a resistor connected between
RMI and RMO0. The receive main amplifier gain varies between 0 and +20 dB in effect. A piezoreceiver with an impedance greater than 1.2 kW is available.
If the adjusting of receive path frequency characteristics is required, insert the following circuit
for adjustment. During the whole system Power ON, the speech path from RMI to RMO0 and
RMO1 is disconnected and the output of RMO0 and RMO1 is at the SG level (VA/2). The speech
path is provided by processor control.
A circuit example for adjustment of frequency characteristics
RPO
RMI
R1
C1
RMO0
R2
C2
Main amplifier gain without capacitors
G=
R2
R1
SPI
Addition input of speaker amplifier.
The typical gain between SPI and SPO is 0 dB. But, the 2-stage gain amplifier allows to set up a
gain between 0 dB and –18 dB in a 6 dB step, or a gain between 0 dB and –28 dB in a 4 dB step
through processor control. The input resistance of SPI is typically 20 kW to 150 kW (it varies by
gain setting).
6/41
¡ Semiconductor
MSM7503
SPO
Output of pre-amplifier for speaker.
Since the driving capability is 2.4 VPP for the load of 20 kW, SPO can not directly drive a speaker.
During the whole system power down mode, SPO is at an analog ground level. During the whole
system power on mode, SPO is in a non-signal state (SG level), and a receive voice signal, R-tone,
F-tone, hold acknowledge tone, PB signal acknowledge tone, and sounder tone are output from
the speaker by processor control.
When the speaker is used as a sounder, the sounder tone is output via the SPO pin by connecting
the SPI input with the sounder output (SA0 or SA1). In addition, when the AD-converted
sounder tone is sent from the main device, the sounder tone is output via the SPO pin since the
CAO pin for CODEC output is internally connected.
R1I, R2I, RPO
R1I and R2I are for the inputs and RPO is for the output of the receive pre-amplifier.
Normally, R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO),
and R2I is used as the mixing signal input pin.
The typical gain between R1I and PRO is –6 dB. Through processor control, gains are variable
from –14 dB to 0 dB in 2 dB steps. In addition, the receive pad can control the gain of –9, –6, –3,
or 0 dB. The gain between R2I and RPO is fixed to 0 dB.
During the whole system power-on mode, the RPO output is in non-signal state, and speech
signal, R-tone, F-tone, PB acknowledge tone, side tone signal are output by processor control.
During the whole system power-down mode, the RPO output is the analog ground level.
The input resistance of R1I is typically between 20 kW and 100 kW (it varies by gain setting). The
input resistance of R2I is typically 20 kW.
MLDYI
Hold tone signal input.
For example, the output of external melody IC is connected to this pin. Through processor
control, the signal applied to MLDYI is output from the TO output pin as a hold tone on the
transmit path, and from the SPO output pin as a hold acknowledge tone on the receive path. The
typical gain between MLDYI and TO is –2 dB. Through processor control, a gain between –2 dB
and –11 dB is also settable at 3 dB steps. The typical gain between MLDYI and SPO is –3 dB.
Through processor control, a gain between –3 dB to –31 dB is also settable at 4 dB steps. MLDYI
is a high impedance input, so insert an about 100 kW bias resistor between MLDYI and SGT.
7/41
¡ Semiconductor
MSM7503
TPBI, TO
TPBI is the input and TO is the output of the transmit pre-amplifier (B).
When the handset is used, TPBI is connected to the transmit pre-amplifier (A) output pin (TPAO).
If adjustment of frequency characteristics on the transmit path is required, insert a circuit for
adjustment of characteristic between TPAO and TPBI. Through processor control, the signal
applied to this pin is output via the TO pin on the transmit path and its side tone via the RPO pin.
During the whole system power down mode, TO is at an analog ground level. The typical gain
between TPBI and TO is +17.7 dB. Through processor control, a gain between +17.7 dB and +8.7
dB is also settable at 3 dB steps.
The typical gain between TPBI and RPO is +3.0 dB. Through processor control, a gain between
–9 dB and +9 dB is variable in 3 dB steps. Changing the gain between TPBI and TO may change
the gain between TPBI and RPO. TPBI is a high impedance input, so insert an about 100 kW
resistor between TPBI and SGT.
A circuit example for adjustment of frequency characteristics
TPAO
TPBI
R3
C3
SGT
R4
C4
MPAI, MPAO
Handfree microphone pre-amplifier (A) input and output.
MPAI is the input and MPAO is the output. The speech path between MPAI and MPAO is always
active regardless of processor control. During the whole system power saving mode, MPAO is
at an analog ground level. The gain between MPAI and MPAO is typically +20 dB. Through
processor control, gains between +14 dB and +11 dB are also settable. MPAI is a high impedance
input, so insert an about 100 kW between MPAI and SGT.
MPBI, MPBO
The handfree microphone (B) input and output.
MPBI is the inverted input and MPBO is the output. With an external resistor, the amplifier gain
is adjusted in the range between –25 dB and +25 dB. A signal on the MPBO is output via the TO
pin through processor control. During the whole system power down mode, MPBO is at an
analog ground level. The gain between MPBO and TO is fixed to 0 dB.
8/41
¡ Semiconductor
MSM7503
TPAI, TPAO
The transmit pre-amplifier (A) input and output.
TPAI is the input and TPAO is the output. TPAI should be connected to the microphone of
handset via an AC-coupling capacitor if the DC offset appears at a transmit signal (offset from
SGT). The transmit path from TPAI to TPAO is always active regardless of processor control.
During the whole system power down mode, TPAO is at an analog ground level. The gain
between TPAI and TPAO is fixed to 20 dB.
SGT
Transmit path signal ground.
SGT outputs half the supply voltage. During the whole power down mode, SGT output is in a
high impedance state.
SGC
Bypass capacitor connecting pin for a signal ground level.
Insert a 0.1 mF high performance capacitor between SGC and AG.
VA, VD
+5 V power supply.
VA is for an analog circuit and VD is for a digital circuit. Both VA and VD should be connected
to the +5 V analog path of the system.
CAI, CAO
CODEC analog input and output.
CAI is the analog input of CODEC to be connected to the TO pin. If the DC offset voltage on the
TO signal is great, CAI should be connected via AC-coupling capacitor. At this time, insert an
about 100 kW bias resistor between CAI and SGT.
CAO is the analog output of CODEC. CAO should be connected to R1I via AC-coupling
capacitor.
A bias resistor is not required to R1I. During the whole system or CODEC power down mode,
CAO is at the SG voltage level.
9/41
¡ Semiconductor
MSM7503
PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7
Scanning outputs.
These output pins need external pull-up resistors because of their open- drain circuits. But, when
these are used in combination with PI0 to PI7, pull-up resistors are not required. Through
processor control, these outputs can be set open or to digital "0". Initially, these outputs are set
at an opened state.
PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7
Scanning inputs. In the READ mode, data on PI0 to PI7 can be read out of the processor via data
bus (DB0 to DB7).
Since these inputs are pulled up inside the IC, external resistors are not required.
DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7
Data bus I/O pins.
These pins are configured as an output during the READ mode only and as an input during other
modes.
T1N, T2N
Line transmit signal output.
Signals which consist of a total of 13 bits configured by the start bit (fixed at "1"), the K bit (fixed
at "1"), the D bits (control data of two bits), the transmit B bits (eight for voice and data) and the
DC bit (1 bit for the DC balance) at the bit rate of 256 kHz are output in burst mode from the T1N
pin and the T2N pin in turn at intervals of 125 msec. These output signals become the AMI code
with a duty of 50% in the line coding configuration by connecting to the line via a transformer
etc. In the output timing of the T1N and T2N pins, the top bit of the signal is output after receiving
a 16-bit signal.
R1N, R2N
Line receive signal input.
Line signals (50% duty AMI code) which consist of a total of 16 bits configured by the frame
synchronous bits (four bits with "1"), the K bit (one bit for polling), the D bits (control data of two
bits), the receive B bits (eight bits for voice and data), and the DC bit (bit for DC balance) have
been transmitted in burst mode at the bit rate of 256 kHz at interval of 125 msec. These signals
should be input in the R1N pin and the R2N pin after separating then into the polarity of "+" and
"–".
10/41
¡ Semiconductor
MSM7503
SYNC
Synchronous signal (8 kHz) output.
This synchronous signal is generated by dividing the oscillator output of 8.192 MHz, applying
the frame synchronous bit included in the line signal as a reference phase. This signal also sent
to the tone generator and the CODEC inside the device. All timing signals of the CODEC are
synchronized by this signal.
CLK1
64 kHz CLK signal output synchronized to the SYNC signal output.
This signal is connected to the CODEC inside the device and is used as a bit clock for receiving
and sending the PCM I/O data from and to the ping-pong transmission interface. When an
external signal is input to the BHW pin, or when the FHW pin outputs signals for the external
circuit, the timing should be set by the CLK1 signal. This signal is always output in the power ON
mode.
CLK2
16 kHz CLK signal output synchronized to the SYNC signal output.
This signal can be used for the input or output of the control signal (BD input or FD output) of
16 kbps. This signal is always output in the power ON mode.
CLK3
CLK signal output of 256 kHz synchronized to the SYNC signal.
This signal can be used when the control signal of 16 kHz is input or output from or to the external
device by the start-stop synchronization. This signal is always output in the power ON mode.
CLC
Control signal input for phase-inverting the 256 kHz CLK signal which is output form the CLK3
pin.
If the reference phase is set by setting CLC to "0", the CLK signal of 256 kHz is phase-inverted
against the reference phase by setting CLC to "1".
11/41
¡ Semiconductor
MSM7503
FHW
The output of the extracted B-bit (8-bit sequence) from receive signals which are input to R1N and
R2N.
This signal is output synchronizing to the rising edge of a CLK1 (64 kHz) output signal beginning
with the rising edge of a SYNC output signal.
Since this pin is connected to the D/A converter of the CODEC inside device, the B bits of receive
signals are decoded to analog signals.
BHW
Input to the B bit slot of line signals transmitted from the T1N and T2N pins.
The input signal to this pin must be synchronized to the CLK1 output signal (64 kHz) beginning
with the rising edge of the SYNC output signal. The input signal is shifted at the falling edge of
CLK1.
In the case of inserting the voice data into the transmit B bit, the PCM output of the CODEC is
connected to this input pin, and inserting the voice data into the B bit slot is enabled by setting
SW12 to ON through processor control. In this case the BHW pin is used as an output pin, so
external signals can not be input to this pin. This is an input and output pin of an open drain type
with a pulled-up resistance of 5 kW.
FD
The signal output of the extracted Control bit (2-bit sequence at 16 kbps) from line signals which
are input to the R1N and R2N pins.
This signal is output synchronizing to the rising edge of a CLK2 output signal beginning with the
rising edge of the SYNC output signal.
FD is an output pin of an open drain type with a pulled-up resistance of about 10 kW.
FK
The signal output of the extracted K bit (8 kbps) from the line receive signals which are input to
the R1N and R2N pins.
This signal is output synchronizing to the rising edge of a SYNC output signal. FK is an output
pin of an open drain type with a pulled-up resistance of about 10 kW.
12/41
¡ Semiconductor
MSM7503
BD
Input to the D bit (2-bit sequence at 16 kbps) of line signals transmitted from the T1N and T2N
pins. When the BDS control pin is in "0", this pin enters the synchronous mode and data must be
input to this pin synchronizing with CLK2 (16 kHz).
When the BDS control pin is set to "1", this pin enters the asynchronous data input mode and the
asynchronous data of 11 bits including the start bit and stop bit can be input at data rate of 16 kbps.
BDS
Control signal input for selection of the synchronous mode or asynchronous mode for control
data (D-bit) input.
When being at "0" level, this pin enters the synchronous data input mode, when being at "1" level,
this pin enters the asynchronous data input mode.
PS
Monitoring signal output for the state of the ping-pong transmission. When frames are
synchronized (in normal operation) after receiving more than three consecutive frame synchronous
signals which are included in the line receive signal sequence, this pin outputs "1".
Otherwise, this pin outputs "0". PS is an output of an open drain type with pulled-up resistance
of about 10 kW.
X1, X2
CLK oscillator circuit input and output. X1 is input and X2 is output. A crystal oscillator of 8.192
MHz should be connected between X1 and X2. If the frequency deviation in CLK oscillation is
great with respect to the receive data rate, the noise of the CODEC increases. The oscillation
frequency deviation in CLK should be kept in ±20 ppm or less.
13/41
¡ Semiconductor
MSM7503
XOUT
8.192 MHz CLK signal output.
If capacitance load is given to the output, the current consumption will increase. About 0.03 mA/
pF.
AD0, AD1
Address data inputs for the internal control registers.
Addressing of the internal control registers is executed by AD0 and AD1 and sub address data,
DB7 and DB6.
AD1 AD0 DB7 DB6
0
WRITE
READ
0
0
1
Function
0
0
ON/OFF controls of sounder, R-Tone, F-Tone
0
1
Level/Frequency controls of sounder, R-Tone
1
0
PB tone control
1
1
Controls of internal speech path switch and general latch
Watchdog timer reset
0
0
Controls of receive gain and side tone gain
0
1
Controls of transmit hold tone, PB tone, handfree input, handset inputs gain
1
0
Controls of speaker pre-amplifier gain and additional speaker gain
1
1
Controls of receive PAD and incoming tone input gain
1
0
—
—
Scanning output control
1
1
0
0
Scanning interrupt reset
1
1
0
1
LCD deflection angle control voltage setting
1
1
1
0
Power ON/OFF control
1
1
1
1
CODEC control (Controls of companding law and digital loop)
1
0
—
—
Scanning data read-out
WRN
Write signal for internal control registers.
Data on the data bus is written into the registers at the rising edge of WRN under the condition
of digital "0" of CEN (Chip Enable). While CEN is in digital "1" state, WRN becomes invalid. The
Write cycle is a minimum of 2 ms regardless of the presence or absence of clock signals.
14/41
¡ Semiconductor
MSM7503
RDN
Read signal input to read PI0 to PI7 out of the processor.
When CEN and RDN are in digital "0" state, the digital values on PI0 to PI7 are output onto the
data buses DB0 to DB7. While CEN is in digital "1" state, the RDN signal becomes invalid.
CEN
Chip Enable signal input.
When CEN is in digital "0" state, WRN and RDN are valid.
VLCD
By processor control, VLCD outputs a DC voltage between 0 and 1.4 V is about 0.2 V step.
This is used to control the deflection angle of the LCD display. VLCD has the internal resistance
value of about 1 kW, so the external load of over 100 kW should be used. During initialized state,
VLCD outputs the voltage of 0 V.
LRSTN
Reset signal output for external circuit.
This reset signal output pin goes to "0" level when the power supply is approximately more than
4.0 V or when the TEST pin is at digital "0" level and the watchdog timer (WDT) outputs a signal.
The WDT output does not affect the LSRTN output when TEST pin is at digital "1" level.
The LRSTN signal is also used as a reset signal for internal registers.
When LRSTN is at "0" level, all internal control registers are initialized.
The internal WDT outputs a 500 ms cycle signal when the LRSTN is at digital "1" and the
processor does not send a timer reset signal.
Refer to the figure 1 for the output timing of this output.
TEST
Control signal input for deciding valid/invalid of reset control from the internal WDT output.
When this input pin is at digital "0" level, the LRSTN output goes to "0" level. When this input
pin is at "1" level, the internal WDT does not affect the LSRTN output.
CTEST
Test pin for shipment testing.
This pin should be set to "0" level.
15/41
¡ Semiconductor
MSM7503
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
VDD
AG, DG = 0 V
0 to 7
V
Analog Input Voltage
VAIN
AG, DG = 0 V
–0.3 to VDD + 0.3
V
Digital Input Voltage
VDIN
AG, DG = 0 V
–0.3 to VDD + 0.3
V
Storage Temperature
TSTG
—
-55 to 150
°C
Power Supply Voltage
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Power Supply Voltage
VD
VA, VD (Voltage must be fixed)
4.75
5.0
5.25
V
Operating Temperature Range
Ta
—
–10
25
70
°C
Input High Voltage
VIH
All Digital Input Pins
2.2
—
VDD
V
Input Low Voltage
VIL
All Digital Input Pins
0
—
0.8
V
Digital Input Rise Time
tIr
All Digital Input Pins
—
—
50
ns
Digital Input Fall Time
tIf
All Digital Input Pins
—
—
50
ns
kW
RDL
PO0 to PO7
10
—
—
PO0 to PO7
—
—
100
Other digital output pins except PO0 to PO7
—
—
10
—
8.192
—
MHz
–50
—
50
ppm
Temperature Characteristics
–50
—
50
ppm
Equivalent Series Resistance
—
—
80
W
Production Load Capacitance
—
16
—
pF
Min.
Typ.
Max.
Unit
20
—
—
Crystal Oscillator
Digital Output Load
CDL
Oscillating Frequency
Allowable Frequency Deviation
25°C ±3°C
pF
Recommend Operating Conditions (Analog Interface)
Parameter
Symbol
Condition
TPAO, MPAO, MPBO, TO,
Analog Load Resistance
RAL
RPO, SPO, CAO
RMO0, RMO1 with respected to
0.6
—
—
TPAO, MPAO, MPBO, TO,
RPO, SPO, CAO
—
—
30
pF
RMO0, RMO1
—
—
70
nF
TPAI, TPBI, MPAI
–10
—
10
MLDY
–50
—
50
–25
—
25
–100
—
100
SG Level
Analog Load Capacitance
Allowable Analog
Input Offset Voltage
CAL
Voff
kW
R1I, R2I, SPI
CAI
With respect
to SG
mV
16/41
¡ Semiconductor
MSM7503
Recommended Operating Conditions (Processor Digital Interface)
Min.
Typ.
Max.
Unit
Write Pulse Period
Parameter
PW
WRN
2000
—
—
ns
Write Pulse Width
TW
WRN
100
—
—
ns
Read Pulse Width
TR
RDN
200
—
—
ns
Address Data
Setup Time
tAW1
AD0, AD1ÆWRN
80
—
—
ns
tAR1
AD0, AD1ÆRDN
80
—
—
ns
Address Data
Hold Time
tAW2
WRNÆAD0, AD1
tAR2
RDNÆAD0, AD1
tCW1
CENÆWRN
80
—
—
ns
tCR1
CENÆRDN
80
—
—
ns
tCW2
WRNÆCEN
50
—
—
ns
tCR2
RDNÆCEN
50
—
—
ns
Data Setup Time
tDW1
DB0 to 7ÆWRN
110
—
—
ns
Data Hold Time
tDW2
WRNÆDB0 to 7
20
—
—
ns
CEN Setup Time
CEN Hold Time
Symbol
Condition
See Fig.2
50
—
—
ns
50
—
—
ns
Recommended Operating Conditions (Ping-Pong transmission Interface)
Min.
Typ.
Max.
Unit
B Signal Set-up Time
Parameter
Symbol
TSBHW
BHW Input
Condition
See Fig. 3
50
—
—
ns
B Signal Hold Time
THBHW
BHW Input
See Fig. 3
50
—
—
ns
D Signal Set-up Time
TSBD
BD Input
See Fig. 4
50
—
—
ns
D Signal Hold Time
THBD
BD Input
See Fig. 4
50
—
—
ns
Receive Data Cycle Time
TCB
R1N, R2N
See Fig. 5
—
3.906
—
ms
Receive Data Width
TWB
Width of "L" at R1N and R2N
See Fig. 5
1.35
1.953
2.5
ms
Receive Flame Cycle Time
TFM
—
See Fig. 5
—
125
—
ms
17/41
¡ Semiconductor
MSM7503
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 5 V ±5%, Ta = –10°C to 70°C)
Parameter
Power Supply Current
Symbol
Condition
Min.
Typ.
Max.
Unit
IDD1
Operating Mode (No Signal, Sounder OFF)
—
10
20
mA
IDD2
Whole system Power Down
—
3
6
mA
IDD3
CODEC Power Down
—
7
14
mA
Vth
Power Supply Voltage at LRSTN = 1, See Fig. 1
3.9
—
—
V
Power Supply Voltage Non-Detection
Vtl
Power Supply Voltage at LRSTN = 0, See Fig. 1
—
—
3.8
V
Input High Voltage
VIH
—
2.2
—
VDD
V
Input Low Voltage
VIL
Power Supply Voltage Detection
High Input Leakage
Current
Low Input Leakage
Current
IIH
IIL
—
0.0
—
0.8
V
Digital Pins except for PI0 to PI7
—
—
2.0
mA
PI0 to PI7 (Internal Pull-up Pins)
—
—
2.0
mA
Digital Pins except for PI0 to PI7
—
—
0.5
mA
PI0 to PI7 (Internal Pull-up Pins)
10
—
25
mA
Output Pins 1 *1 IOH = 0.1 mA
2.4
—
VDD
Output Pins 2 *2 IOH = 1.6 mA
2.4
—
VDD
All Output Pins IOH = 1 mA
3.8
—
VPP
Digital Output High
Voltage
VOH
Digital Output Low
Voltage
VOL
IOL = –1.6 mA
0.0
—
0.4
V
IO
DB0 to DB7
(Write Mode)
—
—
10
mA
–200
—
200
–100
—
—
5
100
—
TPAI, TPBI, MLDYI, RMI, MPAI,
MPBI
—
10
—
Digital Output Leakage
Current
Analog Output Offset
Voltage
Voff
Input Capacitance
CIN
Analog Input Resistance
SG Voltage
SG Drive Current
Equivalent Pull-up Resistance
Notes:
RIN
TPAO, MPAO
MPBO, TO, CAO, RPO, RMO0, RMO1, SPO
—
V
mV
pF
MW
R1I, R2I, SPI
10
—
—
kW
CAI (fin : < 4 kHz)
—
1
—
MW
—
—
VA/2
–0.05
VA/2
VA/2
+0.05
V
ISGF
FORCE Current
1.0
1.5
—
ISGS
SINK Current
0.3
0.5
—
RPULL
PI0 to PI7, VI = 0 V
200
370
500
mA
kW
*1 BHW, FK, FD, PS
*2 SYNC, CLK1, CLK2, CLK3, T1N, T2N, XOUT, LA, LB, LRSTN, DB0 TO DB7
18/41
¡ Semiconductor
MSM7503
Digital Interface Characteristics
(VDD = 5 V ±5%, Ta = –10°C to 70°C)
Parameter
Symbol
Digital Output (Latch) Delay Time
tpd LA
Key Scanning
Output Delay Time
tpd scn
Digital Output (Data) Delay Time
tpd data
RDÆDB0~DB7
Delay Time of Power
Supply Voltage Detect
tdRST1
LRSTN 0Æ1
tdRST2
LRSTN 1Æ0
Delay Time of LRSTN
due to WDT
CLK Output Delay Time
B Signal Delay Time
Condition
WRÆLA, LB
See Fig. 2
WRÆPO0 to PO7
Pull-up resistance 10 kW
See
Fig. 2
See Fig. 2
See Fig. 1
TWDT
See Fig. 1
tdRST3
tWRST
tdSCK1
SYNCÆCLK1
tsSCK2
SYNCÆCLK2
tdSCK3
SYNCÆCLK3
tdFHW
CLK1ÆFHW
D Signal Output Delay Time
tdFD
K Signal Output Delay Time
tdFK
CLK2ÆFD
See Fig. 3
See Fig. 4
Min.
Typ.
Max.
Unit
0.2
—
1.5
ms
0.2
—
1.5
ms
10
20
100
ns
—
128
—
ms
—
0.01
—
ms
ms
—
500
—
—
0.85
—
—
1.7
—
366
—
488
366
—
488
366
—
488
See Fig. 3
—
10
—
LÆH
—
340
—
HÆL
—
10
—
LÆH
—
740
—
HÆL
—
500
—
See Fig. 4
See Fig. 4
ms
ns
ns
ns
ns
fSYNC
—
8
—
kHz
TWSYNC
—
16.6
—
ms
CLK1 Output Frequency
fCLK1
—
64
—
kHz
CLK2 Output Frequency
fCLK2
—
16
—
kHz
SYNC Output Frequency
SYNC Output Width
CLK3 Output Frequency
fCLK3
CLK Output Duty Ratio
—
Line Output Signal Width
tWF
Clock Output Jitter Width
CLK1, CLK2, CLK3
T1N, T2N "L" Width
See Fig. 5
SYNC, CLK1, CLK2
CLK3 When use Xtal
—
256
—
kHz
—
50
—
%
—
1.953
—
ms
—
250
—
ns
19/41
¡ Semiconductor
MSM7503
AC Characteristics 1 (CODEC)
(VDD = 5 V ±5%, Ta = –10°C to 70°C)
Parameter
Transmit Frequency
Response
Receive Frequency
Response
Transmit Signal to
Distortion Ratio
Receive Signal to
Distortion Ratio
Transmit Gain
Tracking
Receive Gain
Tracking
Symbol Freq. Level
(Hz) (dBm0)
Loss T1
60
Loss T2 300
Loss T3 1020
0
Loss T4 2020
Loss T5 3000
Loss T6 3400
Loss R1 300
Loss R2 1020
0
Loss R3 2020
Loss R4 3000
Loss R5 3400
SD T1
3
SD T2
0
SD T3
1020
–30
SD T4
–40
SD T5
–45
SD R1
3
SD R2
0
1020
SD R3
–30
–40
SD R4
–45
SD R5
3
GT T1
–10
GT T2
1020
–40
GT T3
–50
GT T4
–55
GT T5
3
GT R1
–10
GT R2
1020
–40
GT R3
–50
GT R4
–55
GT R5
Absolute Delay Time
Notes:
*1
AIN = SG
*1
Nidle R
—
—
*1
*2
1020
0
1020
0
Td
Max.
20
–0.20
—
0.20
–0.3
–0.5
–1.2
27
0.07
Reference
–0.03
0.06
0.38
–0.03
Reference
–0.02
0.15
0.56
43.0
41.0
38.0
31.0
26.5
43.0
41.0
40.0
34.0
31.0
0.01
Reference
–0.05
0.05
0.30
0.0
Reference
–0.10
–0.30
–0.40
—
—
–73.5
–71
–70
–68
—
–78.0
–75
–0.3
–0.5
–1.2
–0.3
—
AV T
Typ.
–0.15
–0.15
0.0
35
35
35
29
24
37
37
37
30
25
–0.3
*1
—
AV R
Min.
–0.15
–0.15
0.0
–0.15
Nidle T
Idle Channel Noise
Absolute Amplitude
Condition
m
A
Unit
0.20
0.20
0.80
0.20
dB
0.20
0.20
0.80
—
—
—
—
—
—
—
—
—
—
0.3
dB
0.3
0.4
1.2
0.3
dB
0.3
0.5
1.2
dB
CAI Æ BHW
0.5671
0.6007
0.6363
FHW Æ CAO
0.5671
0.6007
0.6363
CAI Æ CAO
BCLOCK = 64 kHz
—
0.58
0.60
dB
dB
dBmOp
Vrms
ms
*1 The Psophometric weighted filter is used
*2 PCMIN input: idle CODE
20/41
¡ Semiconductor
MSM7503
AC Characteristics 1 (CODEC) (Continued)
(VDD = 5 V ±5%, Ta = –10°C to 70°C)
Parameter
Transmit Group Delay
Receive Group Delay
Crosstalk Attenuation
Symbol Freq. Level
(Hz) (dBm0)
tgd T1
tgd T2
tgd T3
tgd T4
tgd T5
tgd R1
tgd R2
tgd R3
tgd R4
tgd R5
CR T
CR R
500
600
1000
2600
2800
500
600
1000
2600
2800
Condition
Min.
Typ.
Max.
CAI Æ CAO
—
—
—
—
—
—
—
—
—
—
70
0.19
0.12
0.02
0.05
0.08
0.0
0.0
0.0
0.09
0.12
78
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
—
FHW Æ BHW CAO left open
75
86
—
0
*3
0
*3
1020
0
Unit
ms
ms
dB
Discrimination
Out-of-band Signal
DIS
4.6 kHz to
72 kHz
–25
0 to 4000 Hz
30
32.0
—
dB
Out-of-band Signal
Spurious
S
300 to
3400
0
4.6 kHz to 100 kHz
—
–37.5
–35
dBmO
IMD
fa = 470
fb = 320
–4
2fa–fb
—
–52
–35
dBmO
0 to 50
kHz
50
mVpp
*4
25
30
—
dB
Intermodulation Distortion
Power Supply Noise
Rejection Ratio
Notes:
PSR T
PSR R
*3 The minimum value of group delay only is defined as the reference value
*4 Measurement at the idle channel noise
21/41
¡ Semiconductor
MSM7503
AC Characteristics 2 (Transmit Path)
(VDD = 5 V ±5%, Ta = –10°C to 70°C)
Parameter
Symbol Freq.
(Hz)
Pre-Amp Gain
GTPA
Transmit Path Gain
GTPB1
Transmit Path Gain
Setting (VOL8)
RG1TPB
RG2TPB
RG3TPB
Microphone Pre-Amp
Gain
Microphone Pre-Amp
Gain Setting
(VOL9)
Additional Transmit
Signal Gain
1020
Level
(dBV)
–24.0
GMPA
RG1MPA
1020
–24.0
RG2MPA
GTMX
Cross Talk Attennation
TMX OFF
at Microphone Signal Path
Max.
Unit
TPAI-TPAO
18.0
20.0
22.0
dB
TPBI-TO
Set at typical gain
15.7
17.7
19.7
dB
Setting,
–3 dB
than
–6 dB
typical gain –9 dB
MPAI-MPAO
Set at typical gain
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
dB
18.0
20.0
22.0
dB
Setting,
than
typical gain
–6 dB
–8.0
–6.0
–4.0
–9 dB
–11.0
–9.0
–7.0
dB
MPBO-TO
–2.0
0.0
2.0
dB
1020
–24
MPAI-TO
50
60
—
dB
—
—
–19.4
–17.4
–15.4
dBV
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
dB
–1.0
—
1.0
%
In-band Distortion
—
–35
–30
dB
MLDYI-TO
Set at typical gain
–4.0
–2.0
0.0
dB
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
dB
—
–70
—
dBV
2.4
—
—
Vpp
In-Channel PB Signal
Output Level Setting
(VOL4)
GPBT1
GPBT2
GPBT3
—
—
In-Channel PB Signal
Frequency Deviation
DfPBT
—
—
In-Channel PB Signal
Distortion
THDPBT
—
—
Hold Tone Path Gain
GPAT
Hold Tone Path Gain
Setting
(VOL3)
RG1PAT
RG2PAT
RG3PAT
1020
NiTPA
—
—
VOT
1020
—
Note:
Typ.
–4.0
VPBT1
Maximum Output Voltage
Swing
Min.
1020
In-Channel PB Signal
Output Level
Idle Channel Noise
Condition
–4.0
TO per wave
set at typical gain
Setting,
–3 dB
than
–6 dB
typical gain –9 dB
Setting,
–3 dB
than
–6 dB
typical gain –9 dB
TPAI:Terminated in 510 W
Measured at TO
TPAO-TPBI Directly
connected Set at
typical gain *5
TPAO, TO,
MPAO, MPBO
RL = 20 kW
*5 Noise band width: 0.3 to 3.4 kHz, non weighted
22/41
¡ Semiconductor
MSM7503
AC Characteristics 3 (Receive Path)
(VDD = 5 V ±5%, Ta = –10 to 70°C)
Parameter
Receive Signal Path Gain
Receive Signal
Path Gain Setting
(VOL1)
Receive PAD
Gain Setting
(VOL10)
Symbol Freq.
(Hz)
GRPA
RGRPA1
RGRPA2
RGRPA3
RGRPA4
RGRPA5
RGRPA6
RGRPA7
RGPAD1
RGPAD2
RGPAD3
Additional Receive
Signal Path Gain
GRMX
Side Tone Path Gain
GSIDE
Side Tone Path Gain
Setting
(VOL2)
Level
(dBV)
1020
GSP
Speaker Pre-Amp
Gain Setting
(VOL5)
RGSP1
RGSP2
RGSP3
RGSP4
RGSP5
RGSP6
RGSP7
Additional Speaker
Input Path Gain
GSPI
Min.
Typ.
Max.
Unit
Typical gain is set
between R1I and RPO
–8.0
–6.0
–4.0
dB
–8 dB
–6 dB
–4 dB
–2 dB
2 dB
4 dB
6 dB
–3 dB
–6 dB
–9 dB
–10.0
–8.0
–6.0
–4.0
0.0
2.0
4.0
–5.0
–8.0
–11.0
–8.0
–6.0
–4.0
–2.0
2.0
4.0
6.0
–3.0
–6.0
–9.0
–6.0
–4.0
–2.0
0.0
4.0
6.0
8.0
–1.0
–4.0
–7.0
R2I and RPO
–2.0
0.0
2.0
dB
Typical gain is set
betweenTPBI and RPO
1.0
3.0
5.0
dB
4.0
1.0
–5.0
–8.0
–11.0
–14.0
6.0
3.0
–3.0
–6.0
–9.0
–12.0
8.0
5.0
–1.0
–4.0
–7.0
–10.0
dB
–2.0
0.0
2.0
dB
–6.0
–10.0
–14.0
–18.0
–22.0
–26.0
–30.0
–4.0
–8.0
–12.0
–16.0
–20.0
–24.0
–28.0
–2.0
–6.0
–10.0
–14.0
–18.0
–22.0
–26.0
dB
–2.0
0.0
2.0
dB
Setting,
than
typical gain
Setting,
than
typical gain
1020
RGSIDE1
RGSIDE2
RGSIDE3 1020
RGSIDE4
RGSIDE5
RGSIDE6
Speaker Pre-Amp
Gain
–4.0
Condition
1020
1020
–4.0
6 dB
3 dB
Setting,
–3 dB
–14.0
than
–6 dB
typical gain
–9 dB
–12 dB
Typical gain is set
between RPO and SPO
–4 dB
–8 dB
Setting,
–12 dB
–4.0
than
–16 dB
typical gain –20 dB
–24 dB
–28 dB
Typical gain is set
–4.0
between SPI and SPO
dB
dB
23/41
¡ Semiconductor
MSM7503
AC Characteristics 3 (Receive Path) (Continued)
(VDD = 5 V ±5%, Ta = –10°C to 70°C)
Parameter
Additional Speaker
Input Path Gain Setting
(VOL6)
Hold Acknowledge Tone
Path Gain
PB Acknowledge Tone
Output Level
Symbol Freq.
(Hz)
RGSPI1
RGSPI2 1020
RGSPI3
GPAR
1020
Level
(dBV)
–4.0
Min.
Typ.
Max.
Unit
–8.0
–14.0
–20.0
–6.0
–12.0
–18.0
–4.0
–10.0
–16.0
dB
–5.0
–3.0
–1.0
dB
RPO per wave
–32.1
–30.1
–28.1
dBV
Setting,
–6 dB
–12 dB
than
typical gain –18 dB
Typical gain is set
–4.0 between MLDYI and SPO
VPBRP
VPBSP
Condition
—
—
SPO per wave
Set at typical gain
–30.2
–28.2
–26.2
dBV
PB Acknowledge Tone
Frequency Difference
DfPBR
—
—
RPO, SPO
–1.0
—
1.0
%
PB Acknowledge Tone
Distortion
THDPBR
—
—
RPO, SPO
—
–35
–30
dB
Incoming Tone Speaker
Output Path Gain
GCAO
Typical gain is set
between CAO and SPO
–2.0
0.0
2.0
dB
–12.0
–10.0
–8.0
–22.0
–20.0
–18.0
—
–86.0
—
dBV
—
–89.0
—
dBV
—
–86.0
—
dBV
Incoming Tone Speaker
Output Path Gain
Setting (VOL11)
RGCAO1
1020
–20
RGCAO2
Setting,
–10 dB
than
typical gain –20 dB
R1I:SG,
Measured at RPO
Set at typical gain.
R1I:SG,
Measured at SPO
Set at typical gain.
R1I:SG, Gain
0 dB
RMO0, RMOB *5
dB
NiRPO
—
—
NiSPO
—
—
NiRMO
—
—
Maximum Output Amplitude
VOR
—
—
RPO, SPO
RL = 20 kW
2.4
—
—
Vpp
Maximum Output
Amplitude
VOR
1020
—
Resister of 1.2 kW
between RMO0 and RMO1
Measurement at each output
3.6
—
—
Vpp
RX to TX
1020
–4
Between R1I and TO
4.5
55
—
dBV
Idle Channel Noise
Cross Talk Attennation
between Transmit Path
and Receive Path
Note:
*5 Noise band width : 0.3 kHz to 3.4 kHz, non weighted
24/41
¡ Semiconductor
MSM7503
AC Characteristics 4 (Ringing Tone)
(VDD = 5 V ±5%, Ta = –10°C to 70°C)
Parameter
R-Tone Output
Amplitude (VOL7)
F-Tone Output Amplitude
Symbol
Condition
Level Setting 1
Level Setting 2
RPO
Level Setting 3
Level Setting 4
RPO
VRTO
VFTRP
VFTSP
S-Tone Output
Amplitude (VOL12)
VSTSP
Frequency Deviation
DfT
SPO
Gain
Setting
SPO
0 dB
–10 dB
–20 dB
—
Min.
63
84
105
126
112
Typ.
90
120
150
180
160
Max.
117
156
195
234
208
7.5
154
49
12
–0.5
11.0
220
70
17
—
14.5
286
91
22
–0.5
Unit
mVpp
mVpp
mVpp
%
AC Characteristics 4 (Sounder Output Circuit)
(VDD = 5 V ±5%, Ta = –10°C to 70°C)
Parameter
Symbol Freq.
(Hz)
Output Resistance
VST1
VST2
VST3
VST4
ROSAO
Output Load
RLSAO
Sounder Tone Output
Amplitude (VOL13)
—
Level
(dBV)
—
Condition
Reference level
of DG RLSA0
is 40 kW or
more.
—
With respect to DG
Vol.1
Vol.2
Vol.3
Vol.4
Min.
Typ.
Max.
Unit
3.5
1
0.25
0.2
—
4
1.2
0.44
0.27
2
—
1.5
0.6
0.35
—
kW
40
—
—
kW
V
LCD Defelection Angle Control Voltage Output
(VDD = 5 V ±5%, Ta = –10°C to 70°C)
Parameter
Output Resistance
ROLCD
Condition
DB2 DB1 DB0
1
1
1
1
0
1
1
1
0
1
0
0
0
1
1
0
0
1
0
1
0
0
0
0
—
Output Load
RLLCD
To GND
Output Voltage
Symbol
VLCD
Min.
Typ.
Max.
Unit
1.1
0.9
0.7
0.5
0.3
0.2
0.15
0.0
—
1.4
1.2
1.0
0.8
0.8
0.4
0.2
0.0
1.0
1.7
1.5
1.3
1.1
0.9
0.6
0.4
0.05
—
kW
100
—
—
kW
V
25/41
¡ Semiconductor
MSM7503
TIMING DIAGRAM
Reset Signal Output Timing
VD
(VA)
Vth
Vtl
tdRST1
Vth
tdRST2
tdRST1
LRSTN
(a) LRSTN output timing by the power supply voltage charging
Writing the reset
data of WDT
TWDT
Internal WDT output
tdRST3
TWDT
LRSTN
tWRST
(b) LRSTN output timing by the internal WDT
Figure 1
Processor Interface Timing
AD0, AD1
tAW1
tAW2
tAR1
tAR2
tCW1
tCW2
tCR1
tCR2
CEN
WRN
RDN
tR
tW
tDW1 tDW2
tPDDATA
tPDDATA
DB0 to DB7
tPDSCN
PO0 to PO7
tPDLA
Latch Output
Figure 2
26/41
¡ Semiconductor
MSM7503
B-bit signal I/O Timing
1/fSYNC
TWSYNC
SYNC
1/fCLK1
tdSCK1
CLK1
tdFHW
FHW Output
F0
F1
B0
B1
F2
B2
F3
B3
F4
B4
F5
B5
F6
B6
F7
B7
F0
B0
F1
B1
BHW Input
TSBHW
THBHW
Figure 3
D-, K-bit Signal I/O Timing
SYNC
1/fCLK2
tdSCK2
CLK2
1/fCLK3
tdSCK3
CLK3
(CLC=1)
CLK3
(CLC=0)
tdFD
tdFD
FD Output
BD Output
TSBD
tdFK
THBD
FK Output
Figure 4
27/41
¡ Semiconductor
Ping-Pong Transmission Signal Timing
1 Frame (TFM 125 ms)
Receive (62.4 ms)
Wave Shape
of Line Signal
R1N
TWB
,
,
,
Receive
Transmit (50.78 ms)
R2N TCB
Receive Data
1
1
1
1
K
D
B
DC
FP
K
D
B
125 ms
SYNC
CLK1
FHW
BHW
RB1
RB2
TB8
CLK2
CLK3
FD
BD
RD1
TD1
TD2
FK
RK
T1N
Transmit
T2N
1
1
D
28/41
Figure 5
B
DC
MSM7503
tWF
Transmit Data
¡ Semiconductor
FUNCTIONAL DESCRIPTION
Control Data Description
Sounder Calling Tone and tone ON/OFF control
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
Sounder output ON
SW19 ON
0
0
0
Sounder output OFF
SW19 OFF
0
1
Sounder output ON
SW20 ON
0
1
Sounder output OFF
SW20 OFF
1
0
R-Tone
ON
SW13 ON
1
0
R-Tone
OFF
SW13 OFF
1
1
F-Tone
ON(1 kHz)
SW14 ON,
SW15 OFF,
1
1
F-Tone
OFF
SW14 OFF,
SW15 OFF,
1
1
F-Tone
ON(1 kHz)
SW14 OFF,
SW15 ON,
1
1
F-Tone
OFF
SW14 OFF,
SW15 OFF,
1
0
0
0
0
Remarks
1
0
0
1
0
0
0
1
1
0
Tone Output: SA0
Tone Output: SPO *1
Tone Output: RPO
Tone Output: SPO
*1: This Sounder Output is sent at the timing shown below.
ON
OFF
ON
0.625 s
2s
29/41
MSM7503
0.25 s 0.125 s
OFF
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
—
—
—
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
—
1
Description for Control
0
0
SA0 output sounder volume 1 (Large)
0
1
SA0 output sounder volume 2 (Middle)
1
0
SA0 output sounder volume 3 (Small 1)
1
1
—
Remarks
Sounder volume and tone
are defind at a time.
¡ Semiconductor
Level and frequency control of sounder and R-tone
At the initial setting, sounder
volume 1 and sounder
SA0 output sounder volume 4 (Small 2)
combination tone 1 are set.
Sounder combination tone 1 (16 Hz wamble tone with 1000 Hz/1333 Hz)
SA0 sounder volume:
Sounder combination tone 2 (16 Hz wamble tone with 667 Hz/800 Hz) VOL 13
Sounder combination tone 3 (8 Hz wamble tone with 800 Hz/1000 Hz)
Sounder combination tone 4 (Single tone of 1000 Hz)
Sounder combination tone 5 (Single tone of 800 Hz)
Sounder combination tone 6 (Single tone of 400 Hz)
0
0
R-Tone output level 1 (90 mVPP at RPO output)
0
1
R-Tone output level 2 (120 mVPP at RPO output)
1
0
R-Tone output level 3 (150 mVPP at RPO output)
1
1
R-Tone output level 4 (180 mVPP at RPO output)
0
0
0
R-Tone 400 Hz single tone
0
0
1
R-Tone 425 Hz single tone
0
1
0
0
1
1
1
0
0
R-Tone 400 Hz ON/OFF by 16 Hz
1
0
1
R-Tone 400 Hz ON/OFF by 20 Hz
—
R-Tone 440 Hz single tone
R-Tone output level = VOL 7
R-Tone output level and
frequency are defined at a
time.
At the initial setting, output
level 1 and a single 400 Hz
tone are set.
R-Tone 450 Hz single tone
MSM7503
30/41
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
Output PB Frequency
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PB
Low
High
0
0
0
0
1
697 Hz
1209 Hz
0
0
0
1
2
697
1336
0
0
1
0
3
697
1477
When PBTC = 0
SW16: ON
SW17: ON
SW18: OFF
0
0
1
1
A
697
1633
PB tone is sent to the transmit path T0 and the receive path RPO.
0
1
0
0
4
770
1209
0
1
0
1
5
770
1336
0
1
1
0
6
770
1477
0
1
1
1
B
770
1633
When PBTC = 1
SW16: OFF
SW17: OFF
SW18: ON
1
0
0
0
7
852
1209
PB tone is sent to the receive path SPO only.
1
0
1
0
PBTC
0
1
0
0
1
8
852
1336
1
0
1
0
9
852
1477
1
0
1
1
C
852
1633
1
1
0
0
*
941
1209
1
1
0
1
0
941
1336
1
1
1
0
#
941
1477
941
1633
1
1
1
1
D
X
X
X
X
PB tone stop
¡ Semiconductor
PB tone control
SW16, SW17, SW18: OFF
MSM7503
31/41
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
1
1
0
1
1
0
0
0
1
SW1
ON
Transmit handfree input
0
0
1
0
SW2
ON
Transmit handset input
0
0
1
1
SW3
ON
Receive input
0
1
0
1
SW4
ON
Side tone input
0
1
1
0
SW5
ON
Receive main amplifier input
0
1
1
1
SW6
ON
Receive speaker input
1
0
0
0
SW7
ON
Transmit path hold tone input
1
0
0
1
SW8
ON
Receive path hold tone Acknowledge input
1
0
1
0
SW9
ON
Additional receive input
1
0
1
1
SW10
ON
Additional speaker input
1
1
0
0
SW11
ON
Speaker DEC input
1
1
0
1
SW12
ON
PCM output enable
1
1
1
0
LA = 1
1
1
1
1
LB = 1
Remarks
When hold tone or PB tone transmit is
selected, these inputs are muted.
¡ Semiconductor
SW control and timer reset
—
When Handfree input is selected, side
tone is muted.
—
—
—
Speaker DEC input = CODEC AOUT
—
General Latch output for external control
0
0
0
0
0
0
0
0
Above corresponding SW or latch is set to OFF or "0".
All of above SWs or latches are set to OFF or "0" at the initial setting stage.
1
1
0
0
0
0
Watchdog timer is reset.
Above codes
MSM7503
32/41
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
—
0
—
—
0
Description for Control
0
0
0
0
0
1
–8 dB than the typical gain
0
1
0
–6 dB than the typical gain
Typical receive gain (–6dB)
0
1
1
–4 dB than the typical gain
1
0
0
–2 dB than the typical gain
1
0
1
+2 dB than the typical gain
1
1
0
+4 dB than the typical gain
1
1
1
Remarks
Receive gain = VOL1
Side tone gain = VOL2
¡ Semiconductor
Gain setting (receive gain, side tone gain)
Receive gain and side tone gain are set at a time.
At the initial setting, the typical gain is set.
+6 dB than the typical gain
Typical side tone gain (–9 dB)
0
0
0
0
0
1
–12 dB than the typical gain
0
1
0
–9 dB than the typical gain
0
1
1
1
0
0
1
0
1
+3 dB than the typical gain
1
1
0
+6 dB than the typical gain
1
1
1
—
–6 dB than the typical gain
–3 dB than the typical gain
Side tone OFF (VOL2 max loss)
MSM7503
33/41
WRITE Mode
Address Data
AD1 = 0, AD0 = 1
Control Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
—
—
0
0
1
0
0
0
0
1
1
0
1
1
—
—
1
0
0
0
1
1
0
1
1
Description for Control
0
0
0
1
–3 dB with respect to the typical gain
1
0
–6 dB with respect to the typical gain
1
1
–9 dB with respect to the typical gain
Typical transmit hold tone gain (–2 dB)
Typical transmit PB tone gain (+4 dB)
–3 dB with respect to the typical gain
—
Remarks
Transmit hold tone gain = VOL3
Transmit PB tone gain = VOL4
¡ Semiconductor
Gain control (transmit hold tone, PB tone, microphone input, handset input)
Hold tone gain and PB tone
gain are set at a time.
At the initial setting, the typical gain is set.
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
0
0
0
1
–6 dB with respect to the typical gain
1
0
1
1
–9 dB with respect to the typical gain
—
Typical handfree input gain (+20 dB)
Typical handset input gain (+12 dB)
—
–3 dB with respect to the typical gain
Handfree input gain = VOL9
Handset input gain = VOL8
Handfree input gain and handset Input
gain are set at a time.
At the initial setting, the typical gain is set.
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
MSM7503
34/41
WRITE Mode
Address Data
AD1 = 0, AD0 = 1
Control Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
—
—
1
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
1
-4 dB with respect to the typical gain
0
1
0
-8 dB with respect to the typical gain
0
1
1
-12 dB with respect to the typical gain
1
0
0
-16 dB with respect to the typical gain
1
0
1
-20 dB with respect to the typical gain
1
1
0
-24 dB with respect to the typical gain
1
1
1
1
0
Speaker pre-amp. gain = VOL5
Additional speaker gain = VOL6
Speaker pre-amp. gain and additional
speaker gain are set at a time.
At the initial setting, SW21-OFF and the
typical gain are set.
-28 dB with respect to the typical gain
-6 dB with respect to the typical gain
—
-12 dB with respect to the typical gain
-18 dB with respect to the typical gain
0
0
0
0
Typical speaker pre-amp. gain (0 dB)
Remarks
Typical additional speaker input path gain (0 dB)
—
1
Description for Control
¡ Semiconductor
Gain control (receive PAD, speaker)
0
1
Speaker receive ON (SW21 ON)
0
Typical receive PAD gain (0 dB)
0
1
-3 dB with respect to the typical gain
1
1
0
1
-6 dB with respect to the typical gain
1
0
-9 dB with respect to the typical gain
Typical incoming tone gain (0 dB)
—
-10 dB with respect to the typical gain
-20 dB with respect to the typical gain
Receive PAD = VOL10
Incoming tone gain = VOL11, VOL12
Receive PAD and incoming tone gain are
set at a time.
At the initial setting, the typical gain is set.
35/41
MSM7503
1
Speaker receive OFF(SW21 OFF)
0
0
0
0
WRITE Mode
Address Data
AD1 = 1, AD0 = 0
Controlo Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description for Control
The data set on DB7 to DB0 are output on PO7 to PO0 respectively.
Output data is held until next data is written.
When the set data is set to "0", output data goes to "0", when set to "1", output pin is left open.
At the initial setting, PO7 to PO0 are in open state.
Output Data
¡ Semiconductor
Key scanning signal output control
Key scanning data read out
Read Mode
Address Data
AD1 = 1, AD0 = 0
Contorol Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
Data input onto PI7 to PI0 are output onto DB7 to DB0.
MSM7503
36/41
WRITE Mode
Address Data
AD1 = 1, AD0 = 1
Contorol Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description for Control
Remarks
LCD Deflection Angle Control Voltage Output
0
1
0
0
0
0
0
0
0
0
1
VLCD pin output voltage: 0.0 V
: 0.20 V
0
1
0
: 0.40 V
0
1
1
: 0.60 V
1
0
0
: 0.8 V
1
0
1
: 1.0 V
1
1
0
: 1.2 V
1
1
1
: 1.4 V
0
0
Analog, CODEC power down mode
0
1
Analog, CODEC power ON mode
1
0
CODEC power down mode
1
1
CODEC power ON mode
0
CODEC operates in m-law
1
CODEC operates in A-law
¡ Semiconductor
Special functions
At the initial setting stage,
set to 0 V.
Power Down Mode Control
1
0
0
0
0
0
At the initial setting stage, set to
analog and CODEC power down
mode. CODEC power ON/OFF
control is valid in the analog and
CODEC power ON mode.
CODEC Control
—
1
1
0
0
0
0
0
1
*2:
—
FHW and BHW are normally connected
BHW is connected to FHW
37/41
MSM7503
Even during the analog and CODEC power down mode, following functions are available,
Key scanning data I/O, sounder outputs (SA0), WDT, and general latch output (LA, LB)
At the initial setting stage, set to
m-law, and FHW and BHW
are normally connected.
The componding law and the
connection control are set at a
time.
Handset
+5 V
*2
100 kW
100 kW
*1
*2 Insert a resistor if necessary
SAO
SPI
SPO
RMO1
TPAO
TPBI
PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7
MPAI
RMO0
RMI
R1I
RPO
TPAI
CAO
SGT
SW Matrix
*1 Inserting a capacitor (1 to 22 mF)
between SGT and AG will inprove
the transmit path noise
characteristics
Speaker
MIC Input
MPBO
P P P P P P P P
I I I I I I I I
0 1 2 3 4 5 6 7
MPAO MPBI
0.1 mF
S
G
C
+
FD
0-10 W
10 mF
X2
100 kW
MLDYI
T
E
S V V
T D A X1
0.1 mF to 1 mF
C
T
E
A D S
G G T
0.1 mF
TO
CAI
100 kW
T2N
T1N
R2N
R1N
0V
+5 V
PS
LRSTN
WRN
RDN
CEN
DB0 to DB7
AD0
AD1
CLK2
CLK3
BD
BDS
CLC
FK
0.1 mF
+5 V
+5 V
+5 V
+5 V
Controller
Hold Tone
Generator
Line
¡ Semiconductor
MSM7503
APPLICATION CIRCUIT
38/41
TPAI
VOL 9
+
20 dB
MPBI
–
–20 dB to +25 dB
+
VOL 8
+
CAO
CAI
SW1
0 dB
SW2
5.7 dB
SW7
VOL 3
SW16
VOL 4
AIN
–
CODEC
AOUT
R1I
R2I
VOL 10
–
RPO
RMI
–
SW5
–
RMO0
SW5
0 dB
RMO1
SW9
VOL 1
SW3
R-Tone GEN.
90 mVPP Pulse (–27.8 dBV Equivalent)
VOL 2
SW4
F-Tone GEN.
0.16 VPP Pulse (–22.8 dBV Equivalent)
VOL 7
SW13
–8.7 dB
SW17
0 dB
SW14
–
SPO
–
VOL 5
SW21
VOL 12
SW20
VOL 11
SW11
–22 dB
SW15
–
PB GEN.
Per Wave
0.24 VPP(–21.4 dBV Equivalent)
0 dB
0 dB
SW6
–3 dB
SW8
–6.8 dB
SW18
VOL 6
SW10
SPI
39/41
+
: The output signal is input with the same phase as
–
: The output signal is with inverted phase.
CODEC I/O Level
Overload Point: 1.2 Vop
0 dBmO
: 0.6007 Vrms
(–4.4 dBV)
S-Tone GEN.
0.22 VPP Pulse (–20.0 dBV Equivalent)
VOL No. Typical Level Variable Range
Step Width
VOL 1
VOL 2
VOL 3
VOL 4
VOL 5
VOL 6
VOL 7
VOL 8
VOL 9
VOL 10
–6 dB
–9 dB
–2 dB
+4 dB
0 dB
–14 dB to 0 dB
–21 dB to –3 dB
–11 dB to –2 dB
–5 dB to +4 dB
–28 dB to 0 dB
0 dB
0 dB
+12 dB
+20 dB
0 dB
–18 dB to 0 dB
90 mV to 180 mV
+3 dB to +12 dB
+11 dB to +20 dB
–9 dB to 0 dB
2 dB
3 dB
3 dB
3 dB
4 dB
6 dB
30 mV
3 dB
3,6 dB
3 dB
VOL 11
VOL 12
0 dB
0 dB
–20 dB to 0 dB
–20 dB to 0 dB
10 dB
10 dB
MSM7503
Note :
TO
MPBO
¡ Semiconductor
MPAO
MSM7503 Speech Path Level Setting
MLDYI
TPAO TPBI MPAI
¡ Semiconductor
MSM7503
RECOMMENDATIONS FOR ACTUAL DESIGN
• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the VA and AG pins.
• Connect the AG pin and the DG pin each other as close as possible. Connected to the system
ground with low impedance. If the AG and DG of the device are connected to different ground
lines, the device may be latched up.
• Connect the VA pin and the VD pin as close together as possible and routed them to the analog
5 V power supply. If the VA and VD of the device are connected to different power supplies,
the device may be latched up.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, the short lead type socket is recommended.
• When mounted on a frame, electro-magnetic shielding should be recommended, if any electromagnetic wave source such as power supply transformers is surrounding the device.
• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-up
phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power
supply should be used to avoid the erroneous operation and the degradation of the characteristics
of these devices.
• Connect analog input pins and digital input pins that are not used to the SG pin and to GND,
respectively.
• When the data is written differently from the data defined in the section, Control Data
Description in Functional Description, the device is not guaranteed in normal operation.
40/41
¡ Semiconductor
MSM7503
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
41/41