K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM 18Mb NtRAMTM Specification 100TQFP/165FBGA with Pb/Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM Document Title 512Kx36 & 1Mx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. Mar. 23, 2004 Advance 0.1 1. Update the current spec(Icc, ISB) May. 13. 2004 Preliminary 0.2 1. Change the ISB,ISB1,ISB2 - ISB ; from 120mA to 170mA - ISB1 ; from 80mA to 150mA - ISB2 ; from 80mA to 130mA Sep. 21. 2004 Preliminary 0.3 1. Remove the 1.8V Vdd voltage level Oct. 18. 2004 Preliminary 0.4 1. Remove the -20 and -13 speed bin Jan. 04. 2005 Preliminary 1.0 1. Finalize the datasheet July 18. 2005 Final 2.0 1. Add the overshoot timing Feb. 16. 2006 Final 3.0 1. Change ordering information Apr. 04. 2006 Final Rev. No. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -2- Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM 18Mb NtRAM (Pipelined) Ordering Information Org. 1Mx18 512Kx36 VDD (V) Speed (ns) Access Time (ns) Part Number RoHS Avail. 3.3/2.5 4.0 2.6 K7N161831B-P(Q,E,F)1C(I)225 √ 3.3/2.5 6.0 3.5 K7N161831B-P(Q,E,F) C(I) 16 √ 3.3/2.5 4.0 2.6 K7N163631B-P(Q,E,F)1C(I)225 √ 3.3/2.5 6.0 3.5 K7N163631B-P(Q,E,F)1C(I)216 √ 1 2 Note 1. P(Q,E,F) [Package type] : 100TQFP ; P-Pb Free, Q-Pb, 165FBGA ; E-Pb Free, F-Pb 2. C(I) [Operating Temperature] : C-Commercial, I-Industrial -3- Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM 512Kx36 & 1Mx18-Bit Pipelined NtRAMTM FEATURES GENERAL DESCRIPTION • VDD= 2.5 or 3.3V +/- 5% Power Supply. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no datacontention . • A interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • 100-TQFP-1420A (Lead and Lead free package) • 165FBGA(11x15 ball aray) with body size of 13mmx15mm. (Lead and Lead free package) • Operating in commeical and industrial temperature range. The K7N163631B and K7N161831B are 18,874,368-bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N163631B and K7N161803B are implemented with SAMSUNG′s high performance CMOS technology and is available in 100pin TQFP and 165FBGA packages. Multiple power and ground pins minimize ground bounce. FAST ACCESS TIMES PARAMETER Symbol -25 -16 Unit tCYC 4.0 6.0 ns Clock Access Time tCD 2.6 3.5 ns Output Enable Access Time tOE 2.6 3.5 ns Cycle Time LOGIC BLOCK DIAGRAM LBO A [0:18]or A [0:19] CKE ADDRESS REGISTER A2~A18 or A2~A19 CONTROL LOGIC CLK BURST ADDRESS COUNTER A0~A1 ADV WE BWx (x=a,b,c,d or a,b) CONTROL REGISTER CS1 CS2 CS2 WRITE ADDRESS REGISTER K A′0~A′1 WRITE ADDRESS REGISTER 512Kx36, 1Mx18 MEMORY ARRAY K DATA-IN REGISTER K DATA-IN REGISTER CONTROL LOGIC K OUTPUT REGISTER BUFFER OE ZZ 36 or 18 DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung. -4- Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM CLK WE CKE OE ADV A18 A17 A8 A9 88 87 86 85 84 83 82 81 BWa VSS BWb 93 89 BWc 94 90 BWd 95 CS2 CS2 96 VDD CS1 97 91 A7 98 92 A6 99 100 Pin TQFP (20mm x 14mm) 41 42 43 44 45 46 47 48 49 50 N.C. A10 A11 A12 A13 A14 A15 A16 40 VSS VDD 39 N.C. N.C. 38 N.C. 35 A2 37 34 A3 A0 33 A4 36 32 A1 31 K7N163631B(512Kx36) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO NC/DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 VDD VDD VDD VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 NC/DQPd 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS VDD VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC PIN NAME SYMBOL PIN NAME A0 - A18 Address Inputs ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b,c,d) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,44 45,46,47,48,49,50,81 82,83,84,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 PIN NAME TQFP PIN NO. VDD VSS Power Supply(+3.3V) 14,15,16,41,65,66,91 17,40,67,90 Ground N.C. No Connect 38,39,42,43 DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd or NC Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 VDDQ Output Power Supply 4,11,20,27,54,61,70,77 (3.3V or 2.5V) 5,10,21,26,55,60,71,76 Output Ground VSSQ Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -5- Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM VSS CLK WE CKE OE ADV A19 A18 A8 A9 89 88 87 86 85 84 83 82 81 BWa 93 90 BWb 94 CS2 N.C. 95 VDD CS2 N.C. 91 CS1 97 92 A7 98 96 A6 99 100 Pin TQFP (20mm x 14mm) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A4 A3 A2 A1 A0 N.C. N.C. VSS VDD N.C. N.C. A11 A12 A13 A14 A15 A16 A17 K7N161831B(1Mx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb8 DQb7 VSSQ VDDQ DQb6 DQb5 VDD VDD VDD VSS DQb4 DQb3 VDDQ VSSQ DQb2 DQb1 DQb0 N.C. VSSQ VDDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 N.C. N.C. VDDQ VSSQ N.C. DQa0 DQa1 DQa2 VSSQ VDDQ DQa3 DQa4 VSS VDD VDD ZZ DQa5 DQa6 VDDQ VSSQ DQa7 DQa8 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A0 - A19 Address Inputs ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,44 45,46,47,48,49,50,80 81,82,83,84,99,100 85 88 89 87 98 97 92 93,94 86 64 31 PIN NAME TQFP PIN NO. VDD VSS Power Supply(+3.3V) 14,15,16,41,65,66,91 17,40,67,90 Ground N.C. No Connect 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,95,96 DQa0~a8 DQb0~b8 Data Inputs/Outputs Data Inputs/Outputs 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 VDDQ Output Power Supply 4,11,20,27,54,61,70,77 (3.3V or 2.5V) Output Ground 5,10,21,26,55,60,71,76 VSSQ NOTE : A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -6- Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM 165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW) K7N163631B(512Kx36) 1 2 3 4 5 6 7 8 9 10 11 A NC A CS1 BWc BWb CS2 CKE ADV A A NC B NC A CS2 BWd BWa CLK WE OE A A NC C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb H NC VDD NC VDD VSS VSS VSS VDD NC NC ZZ J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa N DQPd NC VDDQ VSS NC NC NC VSS VDDQ NC DQPa P NC NC A A TDI A1* TDO A A A NC R LBO NC A A TMS A0* TCK A A A A Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME A Address Inputs A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b,c,d) Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output SYMBOL PIN NAME VDD VSS Power Supply Ground N.C. No Connect DQa DQb DQc DQd DQPa~Pd Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs VDDQ Output Power Supply -7- Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM 165-PIN FBGA PACKAGE CONFIGURATIONS(TOP VIEW) K7N161831B(1Mx18) 1 2 3 4 5 6 7 8 9 10 11 A NC A CS1 BWb NC CS2 CKE ADV A A A B NC A CS2 NC BWa CLK WE OE A A NC C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa D NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa E NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa F NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa G NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa H NC VDD NC VDD VSS VSS VSS VDD NC NC ZZ J DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC K DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC L DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC M DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC N DQPb NC VDDQ VSS NC NC NC VSS VDDQ NC NC P NC NC A A TDI A1* TDO A A A NC R LBO NC A A TMS A0* TCK A A A A Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME A Address Inputs A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b) Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control TCK TMS TDI TDO JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output SYMBOL PIN NAME VDD VSS Power Supply Ground N.C. No Connect DQa DQb DQPa, Pb Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs VDDQ Output Power Supply -8- Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM FUNCTION DESCRIPTION The K7N163631B and K7N161831B are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2) are active . Output Enable(OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipelined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst, LBO=High) Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 BQ TABLE LBO PIN Case 4 A0 0 1 0 1 A1 1 1 0 0 A0 1 0 1 0 (Linear Burst, LBO=Low) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. -9- Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM STATE DIAGRAM FOR NtRAMTM WRITE READ READ BEGIN READ BEGIN WRITE ITE WR DS RE A D DS ST BUR ST D EA W R IT E R BURST DS BURST READ BURST WRITE COMMAND READ WRI TE DESELECT DS DS BUR D REA DS BURST WRITE BURST ACTION DESELECT BEGIN READ WRITE BEGIN WRITE BURST BEGIN READ BEGIN WRITE CONTINUE DESELECT Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) - 10 - Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS1 CS2 CS2 ADV WE BWx OE CKE CLK ADDRESS ACCESSED Operation H X X L X X X L ↑ N/A Not Selected X L X L X X X L ↑ N/A Not Selected X X H L X X X L ↑ N/A Not Selected X X X H X X X L ↑ N/A Not Selected Continue L H L L H X L L ↑ External Address Begin Burst Read Cycle X X X H X X L L ↑ Next Address Continue Burst Read Cycle L H L L H X H L ↑ External Address NOP/Dummy Read X X X H X X H L ↑ Next Address Dummy Read L H L L L L X L ↑ External Address Begin Burst Write Cycle X X X H X L X L ↑ Next Address Continue Burst Write Cycle L H L L L H X L ↑ N/A NOP/Write Abort X X X H X H X L ↑ Next Address Write Abort X X X X X X X H ↑ Current Address Ignore Clock Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by (↑). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE(x36) WE BWa BWb BWc BWd OPERATION H X X X X READ L L H H H WRITE BYTE a L H L H H WRITE BYTE b L H H L H WRITE BYTE c L H H H L WRITE BYTE d L L L L L WRITE ALL BYTEs L H H H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). WRITE TRUTH TABLE(x18) WE BWa BWb OPERATION H X X READ L L H WRITE BYTE a L H L WRITE BYTE b L L L WRITE ALL BYTEs L H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). - 11 - Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z Read L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Notes 1. X means "Don′t Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time. ABSOLUTE MAXIMUM RATINGS* SYMBOL RATING UNIT Voltage on VDD Supply Relative to VSS PARAMETER VDD -0.3 to 4.6 V Voltage on Any Other Pin Relative to VSS VIN -0.3 to VDD+0.3 V Power Dissipation PD 1.6 W TSTG -65 to 150 °C Commercial TOPR 0 to 70 °C Industrial TOPR -40 to 85 °C TBIAS -10 to 85 °C Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage SYMBOL MIN Typ. MAX UNIT VDD1 2.375 2.5 2.625 V VDDQ1 2.375 2.5 2.625 V VDD2 3.135 3.3 3.465 V VDDQ2 3.135 3.3 3.465 V VSS 0 0 0 V Ground Notes: 1. The above parameters are also guaranteed at industrial temperature range. 2. It should be VDDQ ≤ VDD CAPACITANCE*(TA=25°C, f=1MHz) PARAMETER SYMBOL Input Capacitance Output Capacitance TEST CONDITION MIN MAX UNIT CIN VIN=0V - 5 pF COUT VOUT=0V - 6 pF *Note : Sampled not 100% tested. Overshoot Timing Undershoot Timing 20% tCYC(MIN) VIH VDDQ+1.0V VDDQ+0.5V VSS VDDQ VSS-0.5V VSS-1.0V 20% tCYC(MIN) VIL - 12 - Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT Input Leakage Current(except ZZ) IIL VDD=Max ; VIN=VSS to VDD -2 +2 µA Output Leakage Current IOL Output Disabled, Vout=VSS to VDDQ -2 +2 µA Operating Current ICC ISB Standby Current ISB1 ISB2 Device Selected, IOUT=0mA, -25 - 360 ZZ≤VIL , Cycle Time ≥ tCYC Min -16 - 300 - 170 mA - 150 mA - 130 mA Device deselected, IOUT=0mA, ZZ≤VIL, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V Device deselected, IOUT=0mA, ZZ≤0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZ≥VDD-0.2V, f=Max, All Inputs≤VIL or ≥VIH mA Output Low Voltage(3.3V I/O) VOL IOL=8.0mA - 0.4 V Output High Voltage(3.3V I/O) VOH IOH=-4.0mA 2.4 - V Output Low Voltage(2.5V I/O) VOL IOL=1.0mA - 0.4 V Output High Voltage(2.5V I/O) VOH IOH=-1.0mA 2.0 - V Input Low Voltage(3.3V I/O) VIL -0.3* 0.8 V Input High Voltage(3.3V I/O) VIH 2.0 VDD+0.3** V Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.3** V NOTES 1,2 3 3 Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. Data states are all zero. 4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V TEST CONDITIONS PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 3.3/2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load VALUE 0 to 3.0V 0 to 2.5V 1.0V/ns 1.5V VDDQ/2 See Fig. 1 * The above parameters are also guaranteed at industrial temperature range. - 13 - Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O Output Load(A) RL=50Ω Dout VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O Zo=50Ω 319Ω / 1667Ω Dout 353Ω / 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS PARAMETER SYMBOL -25 -16 MIN MAX MIN MAX UNIT Cycle Time tCYC 4.0 - 6.0 - ns Clock Access Time tCD - 2.6 - 3.5 ns Output Enable to Data Valid tOE - 2.6 - 3.5 ns Clock High to Output Low-Z tLZC 1.5 - 1.5 - ns Output Hold from Clock High tOH 1.5 - 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 2.6 - 3.0 ns Clock High to Output High-Z tHZC - 2.6 - 3.0 ns Clock High Pulse Width tCH 1.7 - 2.2 - ns Clock Low Pulse Width tCL 1.7 - 2.2 - ns Address Setup to Clock High tAS 1.2 - 1.5 - ns CKE Setup to Clock High tCES 1.2 - 1.5 - ns Data Setup to Clock High tDS 1.2 - 1.5 - ns Write Setup to Clock High (WE, BWX) tWS 1.2 - 1.5 - ns Address Advance Setup to Clock High tADVS 1.2 - 1.5 - ns Chip Select Setup to Clock High tCSS 1.2 - 1.5 - ns Address Hold from Clock High tAH 0.3 - 0.5 - ns CKE Hold from Clock High tCEH 0.3 - 0.5 - ns Data Hold from Clock High tDH 0.3 - 0.5 - ns Write Hold from Clock High (WE, BWX) tWH 0.3 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.3 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.3 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - cycle Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC. The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions (0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. - 14 - Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS DESCRIPTION CONDITIONS SYMBOL ZZ ≥ VIH Current during SLEEP MODE MIN ISB2 MAX 130 UNITS mA ZZ active to input ignored tPDS 2 cycle ZZ inactive to input sampled tPUS 2 cycle ZZ active to SLEEP current tZZI ZZ inactive to exit SLEEP current tRZZI 2 cycle 0 SLEEP MODE WAVEFORM K tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z DON′T CARE - 15 - Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Block Diagram JTAG Instruction Coding IR2 IR1 IR0 SRAM CORE TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. Control Signals TMS TCK TAP Controller Instruction TDO Output Notes 0 0 0 EXTEST Boundary Scan Register 1 0 0 1 IDCODE Identification Register 3 0 1 0 SAMPLE-Z Boundary Scan Register 2 0 1 1 BYPASS Bypass Register 4 1 0 0 SAMPLE Boundary Scan Register 5 1 0 1 RESERVED Do Not Use 6 1 1 0 BYPASS Bypass Register 4 1 1 1 BYPASS Bypass Register 4 NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 1 1 Select DR 0 1 Capture DR 0 Shift DR 1 Exit2 DR 1 Update DR 0 - 16 - Select IR 0 1 Capture IR 0 0 1 Exit1 DR 0 Pause DR 1 1 1 0 0 Shift IR 1 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register 512Kx36 3 bits 1 bits 32 bits Boundary Scan 75 bits 1Mx18 3 bits 1 bits 32 bits 75 bits ID REGISTER DEFINITION Part Revision Number (31:28) Part Configuration (27:18) Vendor Definition (17:12) Samsung JEDEC Code (11: 1) Start Bit(0) 512Kx36 0000 00111 00100 XXXXXX 00001001110 1 1Mx18 0000 01000 00011 XXXXXX 00001001110 1 165FBGA BOUNDARY SCAN EXIT ORDER(x36) 165FBGA BOUNDARY SCAN EXIT ORDER(x18) 1 1R LBO CLK 6B 39 1 1R LBO CLK 6B 39 2 6N NC NC 11B 40 2 6N NC NC 11B 40 3 11P NC NC 1A 41 3 11P NC NC 1A 41 4 8P A CS2 6A 42 4 8P A CS2 6A 42 5 8R A BWa 5B 43 5 8R A BWa 5B 43 6 9R A BWb 5A 44 6 9R A NC 5A 44 7 9P A BWc 4A 45 7 9P A BWb 4A 45 8 10P A BWd 4B 46 8 10P A NC 4B 46 9 10R A CS2 3B 47 9 10R A CS2 3B 47 10 11R A CS1 3A 48 10 11R A CS1 3A 48 11 11H ZZ A 2A 49 11 11H ZZ A 2A 49 12 11N DQa A 2B 50 12 11N NC A 2B 50 13 11M DQa NC 1B 51 13 11M NC NC 1B 51 14 11L DQa DQc 1C 52 14 11L NC NC 1C 52 15 11K DQa DQc 1D 53 15 11K NC NC 1D 53 16 11J DQa DQc 1E 54 16 11J NC NC 1E 54 17 10M DQa DQc 1F 55 17 10M DQa NC 1F 55 18 10L DQa DQc 1G 56 18 10L DQa NC 1G 56 19 10K DQa DQc 2D 57 19 10K DQa DQb 2D 57 20 10J DQa DQc 2E 58 20 10J DQa DQb 2E 58 21 11G DQb DQc 2F 59 21 11G DQa DQb 2F 59 22 11F DQb DQc 2G 60 22 11F DQa DQb 2G 60 23 11E DQb DQd 1J 61 23 11E DQa DQb 1J 61 24 11D DQb DQd 1K 62 24 11D DQa DQb 1K 62 25 10G DQb DQd 1L 63 25 11C DQa DQb 1L 63 26 10F DQb DQd 1M 64 26 10F NC DQb 1M 64 27 10E DQb DQd 2J 65 27 10E NC DQb 1N 65 28 10D DQb DQd 2K 66 28 10D NC NC 2K 66 29 11C DQb DQd 2L 67 29 10G NC NC 2L 67 30 11A NC DQd 2M 68 30 11A A NC 2M 68 31 10A A DQd 1N 69 31 10A A NC 2J 69 32 10B A A 3P 70 32 10B A A 3P 70 33 9A A A 3R 71 33 9A A A 3R 71 34 9B A A 4R 72 34 9B A A 4R 72 35 8A ADV A 4P 73 35 8A ADV A 4P 73 36 8B OE A1 6P 74 36 8B OE A1 6P 74 37 7A CKE A0 6R 75 37 7A CKE A0 6R 75 38 7B WE 38 7B WE NOTE, NC ; Don′t Care - 17 - Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM JTAG DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power Supply Voltage VDD 3.135/2.375 3.3/2.5 3.465/2.625 V Input High Level VIH 2.0/1.7 - VDD+0.3 V Input Low Level VIL -0.3 - 0.8/0.7 V Output High Voltage VOH 2.4/2.0 - - V Output Low Voltage VOL - - 0.4/0.4 V Note NOTE : The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Symbol Min Unit Input High/Low Level Parameter VIH/VIL 3.0/0 , 2.5/0 V Input Rise/Fall Time TR/TF 1.0/1.0 , 1.0/1.0 ns VDDQ/2 V Input and Output Timing Reference Level Note JTAG AC Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tCHCH tCHCL tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLCH TMS TDI PI (SRAM) tCLQV TDO - 18 - Rev. 3.0 April 2006 - 19 - Data Out OE ADV CS WRITE Address CKE Clock A1 tADVH tCSH tWH tAH tLZOE tOE Q1-1 A2 tHZOE tCEH Q2-1 tCD tOH tCYC Q2-2 tCL NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tADVS tCSS tWS tAS tCES tCH Q2-3 A3 TIMING WAVEFORM OF READ CYCLE Q2-4 Q3-1 Q3-2 Q3-3 Undefined Don′t Care Q3-4 tHZC K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM Rev. 3.0 April 2006 - 20 - Data Out Data In OE ADV CS WRITE Address CKE Clock Q0-4 tHZOE D1-1 A2 tCYC tCL D2-1 D2-2 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Q0-3 A1 tCES tCEH tCH D2-3 A3 TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 tDS D3-2 tDH D3-3 Undefined Don′t Care D3-4 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM Rev. 3.0 April 2006 - 21 - Data In Data Out OE ADV CS WRITE Address CKE Clock tOE tLZOE A2 Q1 A3 tDS D2 tDH Q3 A4 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L A1 tCES tCEH A5 Q4 A6 D5 A7 TIMING WAVEFORM OF SINGLE READ/WRITE tCH Q6 tCYC tCL A8 Q7 A9 Undefined Don′t Care K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM Rev. 3.0 April 2006 - 22 - Data In A1 tCES tCEH tCD tLZC A2 Q1 tHZC A3 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Data Out OE ADV CS WRITE Address CKE Clock tDS A4 D2 TIMING WAVEFORM OF CKE OPERATION tDH tCH Q3 tCYC tCL A5 Q4 A6 Undefined Don′t Care K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM Rev. 3.0 April 2006 - 23 - Data In Data Out OE ADV CS WRITE Address CKE Clock A1 tCEH tOE tLZOE A2 Q1 Q2 tHZC A3 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tCES D3 tDS tDH A4 tCD tLZC TIMING WAVEFORM OF CS OPERATION Q4 A5 tCH tCYC tCL D5 Undefined Don′t Care K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM PACKAGE DIMENSIONS 100-TQFP-1420A (Lead and Lead free package) Units ; millimeters/Inches 0~8° 22.00 ±0.30 0.10 0.127 +- 0.05 20.00 ±0.20 16.00 ±0.30 14.00 ±0.20 0.10 MAX (0.83) 0.50 ±0.10 #1 0.65 (0.58) 0.30 ±0.10 0.10 MAX 1.40 ±0.10 1.60 MAX 0.50 ±0.10 - 24 - 0.05 MIN Rev. 3.0 April 2006 K7N163631B K7N161831B 512Kx36 & 1Mx18 Pipelined NtRAMTM 165 FBGA PACKAGE DIMENSIONS (Lead and Lead free package) 13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array A B Top View C D Side View A F E G B Bottom View ∅H E Symbol Value Units A 15 ± 0.1 mm B 13 ± 0.1 mm C 1.3 ± 0.1 mm D 0.35 ± 0.05 mm Note Symbol - 25 - Value Units E 1.0 mm F 14.0 mm G 10.0 mm H 0.5 ± 0.05 mm Note Rev. 3.0 April 2006