3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V124SA Description 128K x 8 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/GND) for reduced noise Equal access and cycle times – Commercial: 10/12/15/20ns – Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Inputs and outputs are LVTTL-compatible Single 3.3V supply Low power consumption via chip deselect Available in a 32-pin 300- and 400-mil Plastic SOJ, and 32-pin Type II TSOP packages. The IDT71V124 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The JEDEC center power/GND pinout reduces noise generation and improves system performance. The IDT71V124 has an output enable pin which operates as fast as 5ns, with address access times as fast as 9ns available. All bidirectional inputs and outputs of the IDT71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. Functional Block Diagram A0 • • • ADDRESS • • • 1,048,576-BIT MEMORY ARRAY DECODER A16 8 8 I/O0 - I/O7 I/O CONTROL . 8 WE OE CS CONTROL LOGIC 3873 drw 01 AUGUST 2000 1 ©2000- Integrated Device Technology, Inc. DSC-3873/05 IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Pin Configuration Absolute Maximum Ratings(1) Symbol A0 A1 A2 A3 CS I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7 A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8 1 32 2 31 3 30 4 29 5 28 6 SO32-2 27 7 SO32-3 26 8 SO32-4 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Rating Value Unit VDD Supply Voltage Relative to GND -0.5 to +4.6 V VIN, VOUT Terminal Voltage Relative to GND -0.5 to VDD+0.5 V Commercial Operating Temperature -0 to +70 o C -55 to +125 o C -55 to +125 o C TA . TBIAS TSTG Industrial Operating Temperature -40 to +85 Temperature Under Bias Storage Temperature PT Power Dissipation 1.25 W IOUT DC Output Current 50 mA 3873 drw 02 3873 tbl 02 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. SOJ and TSOP Top View Truth Table(1) CS OE WE I/O L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Output Disabled H X X High-Z Deselected – Standby Recommended Operating Temperature and Supply Voltage Function Grade Temperature GND VDD Commercial 0°C to +70°C 0V See Below Industrial -40°C to +85°C 0V See Below 3873 tb l 02a 3873 tbl 01 NOTE: 1. H = VIH, L = VIL, X = Don't care. Recommended DC Operating Conditions Symbol Capacitance (TA = +25°C, f = 1.0MHz, SOJ package) Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance 3.6 V Supply Voltage 3.0 3.3 3.6 V 0 0 0 VIN = 3dV 6 pF VSS 3873 tbl 03 Unit 3.3 VDD(2) NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested. Max. 3.15 Unit pF Typ. Supply Voltage Max. 7 Min. VDD(1) Conditions VOUT = 3dV Parameter Ground VIH Input High Voltage 2.0 ____ VIL Input Low Voltage –0.5(1) ____ VDD+0.3 0.8 NOTES: 1. For 71V124SA10 only. 2. For all speed grades except 71V124SA10. 3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 4. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. DC Electrical Characteristics V (3) V V 3873 tbl 04 (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) Symbol Parameter Test Conditions Min. Max. Unit 5 µA |ILI| Input Leakage Current VDD = Max., VIN = GND to VDD ___ |ILO| Output Leakage Current VDD = Max.,CS = VIH, VOUT = GND to VDD ___ 5 µA VOL Output Low Voltage IOL = 8mA, V DD = Min. ___ 0.4 V 2.4 ___ V VOH Output High Voltage IOH = –4mA, V DD = Min. 3873 tbl 05 2 IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges DC Electrical Characteristics(1, 2) (VDD = Min. to Max., V LC = 0.2V, VHC = VDD 0.2V) 71V124SA10 Symbol Parameter 71V124SA12 71V124SA15 71V124SA20 Com'l Only Com'l Ind Com'l Ind Com'l Ind Unit ICC Dynamic Operating Current CS < VLC, Outputs Open, VDD = Max., f = fMAX(3) 145 130 140 100 120 95 115 mA ISB Dynamic Standby Power Supply Current CS > VHC, Outputs Open, VDD = Max., f = fMAX(3) 45 40 40 35 40 30 35 mA ISB1 Full Standby Power Supply Current (static) CS > VHC, Outputs Open, VDD = Max., f = 0(3) 10 10 10 10 10 10 10 mA 3873 tbl 06 NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD–0.2V (High). 3. fMAX = 1/t RC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. AC Test Conditions GND to 3.0V Input Pulse Levels Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V 1.5V Output Reference Levels See Figure 1 and 2 AC Test Load 3873 tbl 07 3.3V 320Ω +1.5V DATAOUT 50Ω I/O 5pF* Z0 = 50Ω 350Ω 30pF 3873 drw 03 . 3873 drw 04 Figure 1. AC Test Load *Including jig and scope capacitance. Figure 2. AC Test Load (for t CLZ, t OLZ, tCHZ, tOHZ , tOW, and tWHZ) 3 6.42 IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) 71V124SA10(1) 71V124SA12 71V124SA15 71V124SA20 Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle Time 10 ____ 12 ____ 15 ____ 20 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ____ 20 ns tACS Chip Select Access Time ____ 10 ____ 12 ____ 15 ____ 20 ns tCLZ(2) Chip Select to Output in Low-Z 4 ____ 4 ____ 4 ____ 4 ____ ns 0 Symbol Parameter READ CYCLE tRC (2) tCHZ tOE Chip Deselect to Output in High-Z Output Enable to Output Valid (2) 5 0 6 0 7 0 8 ns ____ 5 ____ 6 ____ 7 ____ 8 ns 0 ____ 0 ____ 0 ____ ns tOLZ Output Enable to Output in Low-Z 0 ____ tOHZ(2) Output Disable to Output in High-Z 0 5 0 5 0 5 0 7 ns tOH Output Hold from Address Change 4 ____ 4 ____ 4 ____ 4 ____ ns 10 ____ 12 ____ 15 ____ 20 ____ ns 8 ____ 10 ____ 12 ____ ns WRITE CYCLE tWC Write Cycle Time tAW Address Valid to End-of-Write 7 ____ tCW Chip Select to End-of-Write 7 ____ 8 ____ 10 ____ 12 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns 7 ____ 8 ____ 10 ____ 12 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns 6 ____ 7 ____ 9 ____ ns tWP Write Pulse Width tWR Write Recovery Time tDW Data Valid to End-of-Write 5 ____ tDH Data Hold Time 0 ____ 0 ____ 0 ____ 0 ____ ns tOW(2) Output Active from End-of-Write 3 ____ 3 ____ 3 ____ 4 ____ ns Write Enable to Output in High-Z 0 5 0 5 0 5 0 8 ns (2) tWHZ NOTES: 1. 0°C to +70°C temperature range only. 2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 4 3873 tbl 08 IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE tOLZ (5) CS tACS(3) tCLZ tOHZ (5) (5) tCHZ (5) HIGH IMPEDANCE DATAOUT . DATAOUT VALID 3873 drw 05 Timing Waveform of Read Cycle No. 2(1, 2, 4) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATAOUT VALID DATAOUT VALID 3873 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 5 6.42 . IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tWP (2) tAS tWR WE tCHZ (5) tOW (5) tWHZ (5) HIGH IMPEDANCE (3) DATAOUT (3) tDW DATAIN tDH . DATAIN VALID 3873 drw 07 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4) tWC ADDRESS tAW CS tAS (3) tWR tCW WE tDW DATAIN tDH DATAIN VALID 3873 drw 08 . NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW . If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t WP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured ±200mV from steady state. 6 IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Ordering Information IDT 71V124 Device Type SA XX X X Power Speed Package Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) TY Y PH 300-mil SOJ (SO32-2) 400-mil SOJ (SO32-3) TSOP Type II (SO32-4) 10* 12 15 20 Speed in nanoseconds . 3873 drw 09 * Commercial temperature range only. ** 400-mil SOJ (SO32-3) package only offered in 10ns and 12ns speed grades 7 6.42 IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Datasheet Document History 11/22/99 08/30/00 Pg. 1–4, 7 Pg. 2 Pg. 6 Pg. 8 Pg. 3 Pg. 4 Updated to new format Added Industrial Temperature range offerings Added Recommended Operating Temperature and Supply Voltage table Revised footnotes on Write Cycle No. 1 diagram Added Datasheet Document History Tighten ICC and ISB Tighten AC Characteristics tOHZ, tOW and tWHZ CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 8 for Tech Support: [email protected] 800-544-7726, x4033