PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS84330-01 is a general purpose, single output high frequency synthesizer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The VCO operates at a frequency range of 200MHz to 700MHz. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps from 250KHz to 2MHz can be achieved using a 16MHz crystal depending on the output divider setting. • • • • • • ICS • • • • Fully integrated PLL, no external loop filter requirements 1 differential 3.3V LVPECL output Crystal oscillator interface range: 10MHz to 25MHz Output frequency range: 25MHz to 700MHz VCO range: 200MHz to 700MHz Parallel or serial interface for programming M and N dividers during power-up RMS Period jitter: TBD Cycle-to-cycle jitter: 15ps (typical) 3.3V supply voltage 0°C to 70°C ambient operating temperature • Pin compatible with the SY89430V BLOCK DIAGRAM PIN ASSIGNMENT M0 M1 M2 M3 M4 M5 M6 M7 M8 N0 N1 VEE TEST VCC XTAL1 OSC XTAL2 ÷ 16 PLL PHASE DETECTOR 1 VCO ÷M 1 2 4 8 FOUT nFOUT 0 nP_LOAD VCC XTAL2 XTAL1 nc nc VCCA S_LOAD S_DATA S_CLOCK VCCO FOUT nFOUT VEE ICS84330-01 28-Lead SOIC 7.5mm x 18.05mm x 2.25mm body package M Package Top View TEST VEE TEST VCC VEE FOUT nFOUT CONFIGURATION INTERFACE LOGIC VCCO S_LOAD S_DATA S_CLOCK nP_LOAD ÷2 ÷ ÷ ÷ ÷ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M0:M8 25 24 23 22 21 20 19 N0:N1 S_CLOCK 26 S_DATA 27 S_LOAD 28 VCCA nc nc XTAL1 18 N1 17 N0 16 M8 28-Lead PLCC 15 V Package 2 14 11.6mm x 11.4mm x 4.1mm 3 13 Top View M7 4 M4 ICS84330-01 1 12 7 8 9 10 11 M5 XTAL2 VCC nP_LOAD M0 M1 M3 6 M2 5 M6 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 84330CV-01 www.icst.com/products/hiperclocks.html 1 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1. N0 through N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. The TEST output is Mode 000 (shift register out) when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x 2M 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 100 ≤ M ≤ 350. The frequency out is defined as follows: fout = fVCO = fxtal x 2M N N 16 Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T2:T0. The internal registers T2:T0 determine the state of the TEST output as follows: The ICS84330-01 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A quartz crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency divided by 16 by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84330-01 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode the nP_LOAD input is LOW. The data on inputs M0 through M8 and T2 T1 T0 TEST Output 0 0 0 Shift Register Out 0 0 1 High 0 1 0 PLL Reference Xtal ÷ 16 0 1 1 (VCO ÷ M) /2 (non 50% Duty M divider) 1 0 0 fOUT LVCMOS Output Frequency < 200MHz 1 0 1 Low 1 1 0 (S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider) 1 1 1 fOUT ÷ 4 fOUT fOUT fOUT fOUT fOUT fOUT fOUT S_CLOCK ÷ N divider fOUT SERIAL LOADING S_CLOCK S_DATA T2 t S S_LOAD t T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 H t nP_LOAD S PARALLEL LOADING M0:M8, N0:N1 M, N nP_LOAD t S t H Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS 84330CV-01 www.icst.com/products/hiperclocks.html 2 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Name Type Description VCC Power VCCA Power Analog supply pin for the PLL. VEE Power Negative supply pins. VCCO Power Output supply pin. Core supply pins. nc Unused XTAL1, XTAL2 Input Do not connect. nP_LOAD Input S_CLOCK Input S_DATA Input S_LOAD Input M0, M1, M2 M3, M4, M5 M6, M7, M8 Input Pullup N0, N1 Input Pullup TEST Output nFOUT, FOUT Output Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divide value. Pullup LVCMOS / LVTTL interface levels. Clocks the serial data present at S_DATA input into the shift register on the Pulldown rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. Pulldown LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the M divider. Pulldown LVCMOS / LVTTL interface levels. M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. Test output which is used in the serial mode of operation. LVCMOS / LVTTL interface levels. Differential output for the synthesizer. 3.3V LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 84330CV-01 www.icst.com/products/hiperclocks.html 3 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. TABLE 3A. PARALLEL AND ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER SERIAL MODE FUNCTION TABLE Inputs nP_LOAD M N S_LOAD S_CLOCK S_DATA X X X X X X L Data Data X X X ↑ Data Data X X X H X X L ↑ Data H X X ↑ L Data H X X ↓ L Data H X X L X X H X X H NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition ↑ Data Conditions Reset. M and N bits are all set HIGH. Data on M and N inputs passed directly to M divider and N output divider. TEST mode 000. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divide and N output divide values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M Divider as it is clocked. TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 0 0 1 1 0 0 1 0 0 101 0 0 1 1 0 0 1 0 1 204 102 0 0 1 1 0 0 1 1 0 206 103 0 0 1 1 0 0 1 1 1 • • • • • • • • • • • • • • • • • • • • • • 696 348 1 0 1 0 1 1 1 0 0 698 349 1 0 1 0 1 1 1 0 1 700 350 1 0 1 0 1 1 1 1 0 VCO Frequency (MHz) M Divide 200 100 202 NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs 84330CV-01 N1 N0 N Divider Value Output Frequency (MHz) Minimum Maximum 0 0 2 100 350 0 1 4 50 175 1 0 8 25 87.5 1 1 1 200 700 www.icst.com/products/hiperclocks.html 4 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 37.8°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 115 mA ICCA Analog Supply Current 15 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V VCC = VIN = 3.465V 5 µA VCC = VIN = 3.465V 150 µA VOH M0:M8, N0, N1, nP_LOAD, XTAL_SEL Input High Current S_LOAD, S_DATA, S_CLOCK M0:M8, N0, N1, nP_LOAD, XTAL_SEL Input Low Current S_LOAD, S_DATA, S_CLOCK Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 IIH IIL VCC = 3.465V, VIN = 0V -150 µA VCC = 3.465V, VIN = 0V -5 µA 2.6 V 0.5 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCCO/2. TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 0.95 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. 84330CV-01 www.icst.com/products/hiperclocks.html 5 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 25 MHz Equivalent Series Resistance (ESR) Frequency 10 50 Ω Shunt Capacitance 7 pF TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions fIN Input Frequency Minimum XTAL; NOTE 1 Typical 10 Maximum Units 25 MHz S_CLOCK 50 MHz NOTE 1: For the cr ystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency range of 200MHz or 700MHz. Using the minimum frequency of 10MHz, valid values of M are 160 ≤ M ≤ 511. Using the maximum frequency of 25MHz, valid values of M are 64 ≤ M ≤ 224. TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency tjit(per) Period Jitter, RMS; NOTE 1, 2 tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 tR, tF Output Rise/Fall Time tS Setup Time tH Hold Time tL PLL Lock Time Test Conditions 20% to 80% Typical Maximum Units 700 MHz TBD ps 15 ps 500 ps S_DATA to S_CLOCK 20 ns S_CLOCK to S_LOAD 20 ns M, N to nP_LOAD 20 ns S_DATA to S_CLOCK 20 ns M, N to nP_LOAD 20 ns 10 odc Output Duty Cycle See Parameter Measurement Information section. Characterized using a 16MHz XTAL. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65 NOTE 2: See Applications section. 84330CV-01 Minimum www.icst.com/products/hiperclocks.html 6 50 ms % REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V V CC , VCCA, VCCO Qx SCOPE nFOUT FOUT tcycle ➤ LVPECL ➤ n tcycle n+1 ➤ ➤ nQx VEE t jit(cc) = tcycle n –tcycle n+1 1000 Cycles -1.3V ± 0.165V CYCLE-TO-CYCLE JITTER 3.3V OUTPUT LOAD AC TEST CIRCUIT VOH nFOUT VREF FOUT Pulse Width VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements t odc = Histogram Reference Point t PW t PERIOD Mean Period (Trigger Edge) PERIOD (First edge after trigger) PERIOD JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 84330CV-01 www.icst.com/products/hiperclocks.html 7 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84330-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA pin. TERMINATION FOR 3.3V VCC .01µF 10Ω .01µF 10 µF V CCA FIGURE 2. POWER SUPPLY FILTERING LVPECL OUTPUTS drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 84330CV-01 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 8 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER CRYSTAL INTERFACE The ICS84330-01 has been characterized with 18pF parallel resonant crystals. The external tuning capacitors C1 and C2 are not required if an 18pF parallel resonant crystal is used. If there is space available, it is recommended to provide spare footprints C1 and C2 (size 0603 or 0402) while laying out the P.C. Board. These footprints provide option of optimizing frequency accuracy if needed. XTAL2 C1 SPARE X1 18pF Parallel Cry stal XTAL1 C2 SPARE FIGURE 4. CRYSTAL OSCILLATOR INTERFACE 84330CV-01 www.icst.com/products/hiperclocks.html 9 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84330-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84330-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 115mA = 398.5mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 1 * 30mW = 30mW Total Power_MAX (3.465V, with all outputs switching) = 398.5mW + 30mW = 428.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.429W * 31.1°C/W = 83.3°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8A. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 37.8°C/W 31.1°C/W 28.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 8B. THERMAL RESISTANCE θJA FOR 28-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 76.2°C/W 46.2°C/W 60.8°C/W 39.7°C/W 53.2°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 84330CV-01 www.icst.com/products/hiperclocks.html 10 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V CCO_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V )= OH_MAX [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V )= OL_MAX [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 84330CV-01 www.icst.com/products/hiperclocks.html 11 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 9A. θJAVS. AIR FLOW FOR 28 LEAD PLCC TABLE θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 37.8°C/W 31.1°C/W 28.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 9B. θJAVS. AIR FLOW FOR 28 LEAD SOIC TABLE θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 76.2°C/W 46.2°C/W 60.8°C/W 39.7°C/W 53.2°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84330-01 is: 4442 84330CV-01 www.icst.com/products/hiperclocks.html 12 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - V SUFFIX FOR ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 28 LEAD PLCC TABLE 10A. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 28 N A 4.19 4.57 A1 2.29 3.05 A2 1.57 2.11 b 0.33 0.53 c 0.19 0.32 D 12.32 12.57 D1 11.43 11.58 D2 4.85 5.56 E 12.32 12.57 E1 11.43 11.58 E2 4.85 5.56 Reference Document: JEDEC Publication 95, MS-018 84330CV-01 www.icst.com/products/hiperclocks.html 13 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FOR 28 LEAD SOIC TABLE 10B. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUM N A MAXIMUM 28 -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 17.70 18.40 E 7.40 e 7.60 1.27 BASIC H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 84330CV-01 www.icst.com/products/hiperclocks.html 14 REV. B MARCH 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS84330-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS84330CV-01 ICS84330CV-01 28 Lead PLCC 38 per Tube 0°C to 70°C ICS84330CVT-01 ICS84330CV-01 28 Lead PLCC on Tape and Reel 500 0°C to 70°C ICS84330CM-01 ICS84330CM-01 28 Lead SOIC 26 per Tube 0°C to 70°C ICS84330CM-01T ICS84330CM-01 28 Lead SOIC on Tape and Reel 1000 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84330CV-01 www.icst.com/products/hiperclocks.html 15 REV. B MARCH 22, 2004