LMH6521 LMH6521 High Performance Dual DVGA Literature Number: SNOSB47C LMH6521 High Performance Dual DVGA General Description Features The LMH6521 contains two high performance, digitally controlled variable gain amplifiers (DVGA). Both channels of the LMH6521 have an independent, digitally controlled attenuator followed by a high linearity, differential output amplifier. Each block has been optimized for low distortion and maximum system design flexibility. Each channel has a high speed power down mode. The internal digitally controlled attenuator provides precise 0.5dB gain steps over a 31.5dB range. Serial and parallel programming options are provided. Serial mode programming utilizes the SPI™ interface. A Pulse mode is also offered where simple up or down commands can change the gain one step at a time. The output amplifier has a differential output allowing 10VPPD signal swings on a single 5V supply. The low impedance output provides maximum flexibility when driving filters or analog to digital converters. ■ ■ ■ ■ ■ ■ ■ ■ ■ OIP3 of 48.5 dBm at 200 MHz Maximum voltage gain of 26 dB Gain range of 31.5 dB with 0.5dB step size Channel Gain Matching of ±0.04 dB Noise figure of 7.3 dB at maximum gain -3 dB bandwidth of 1200 MHz Low power dissipation Independent channel power down Three gain control modes: •Parallel interface •Serial interface (SPI) •Pulse mode interface ■ Temperature Range –40°C to +85°C ■ Thermally enhanced, 32–Pin LLP package Applications ■ ■ ■ ■ ■ Cellular base stations Wideband and narrowband IF sampling receivers Wideband direct conversion Digital pre-distortion ADC driver 0.20 2.0 0.15 1.5 0.10 1.0 Gain Matching Error 0.05 0.5 0.00 0.0 -0.05 -0.5 -0.10 Phase Matching Error -1.0 -0.15 -1.5 -0.20 -2.0 0 4 PHASE MATCHING ERROR (degrees) GAIN MATCHING ERROR (dB) Channel Matching Error (Ch A — Ch B) 8 12 16 20 24 28 32 ATTENUATION (dB) 30120180 30120102 LMH6521 Block Diagram SPI™ is a trademark of Motorola, Inc. TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation 301201 www.national.com LMH6521 High Performance Dual DVGA September 14, 2011 LMH6521 Table of Contents General Description .............................................................................................................................. 1 Features .............................................................................................................................................. 1 Applications ......................................................................................................................................... 1 Absolute Maximum Ratings .................................................................................................................... 3 Operating Ratings (Note 1) .................................................................................................................... 3 Connection Diagram ............................................................................................................................. 5 Ordering Information ............................................................................................................................. 5 Typical Performance Characteristics ....................................................................................................... 8 Application Information ........................................................................................................................ 12 INTRODUCTION ......................................................................................................................... 12 BASIC CONNECTIONS ............................................................................................................... 12 INPUT CHARACTERISTICS ......................................................................................................... 13 OUTPUT CHARACTERISTICS ..................................................................................................... 13 OUTPUT CONNECTIONS ............................................................................................................ 13 DIGITAL CONTROL .................................................................................................................... 14 PARALLEL MODE (MOD1= 1, MOD0 = 1) ...................................................................................... 14 SERIAL MODE — SPI™ COMPATIBLE INTERFACE (MOD1= 1, MOD0 = 0) ..................................... 15 PULSE MODE (MOD1= 0, MOD0 = 1) ........................................................................................... 17 THERMAL MANAGEMENT .......................................................................................................... 18 INTERFACE TO ADC .................................................................................................................. 18 POWER SUPPLIES ..................................................................................................................... 19 Physical Dimensions ........................................................................................................................... 21 www.national.com 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Machine Model Charged Device Model Positive Supply Voltage (Pin 14, 27) Differential Voltage between Any Two Grounds Analog Input Voltage Range Digital Input Voltage Range Junction Temperature Infrared or Convection (30 sec) Operating Ratings 260°C (Note 1) Supply Voltage (Pin 14 & 27) Differential Voltage Between Any Two Grounds Analog Input Voltage Range, AC Coupled Ambient Temperature Range (Note 3) 2 kV 200V 750V −0.6V to 5.5V <200 mV −0.6V to V+ −0.6V to 5.5V +150°C 5V Electrical Characteristics −65°C to +150°C 4.75V to 5.25V <10 mV 0V to V+ −40°C to +85°C Package Thermal Resistance (θJA) 45°C/W (Note 4) The following specifications apply for single supply with V+ = 5V, Differential VOUT = 4VPP, RL= 200Ω, TA=25°C, fin = 200 MHz, and Maximum Gain (0 attenuation). Boldface limits apply at temperature extremes. Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units Dynamic Performance SSBW 3 dB Small Signal Bandwidth OIP2 MHz At amplifier output with RSOURCE=200Ω 33 nV/√Hz Noise Figure Source = 200Ω 7.3 dB Output 3rd-Order Intercept Point f=100MHz, PO= +4dBm per tone 56 dBm f=200MHz, PO= +4dBm per tone 48.5 f=250MHz, PO= +4dBm per tone 46.5 f=100MHz, PO= +4dBm per tone 92 f=200MHz, PO= +4dBm per tone 80 f=250MHz, PO= +4dBm per tone 73 Output Noise Voltage OIP3 1200 Output 2nd-Order Intercept Point dBm HD2 2nd Harmonic Distortion f=200MHz, PO= +6dBm –84 dBc HD3 3rd Harmonic Distortion f=200MHz, PO= +6dBm –83 dBc P1dB 1dB Compression Point 17 dBm Analog I/O Input Resistance Differential 200 Input Common Mode Voltage Self Biased (AC coupled) 2.5 Ω V Input Common Mode Voltage Range Externally Driven (DC coupled) 2–3 V Maximum Input Voltage Swing Differential 11 VPPD Output Resistance Differential 20 Maximum Differential Output Voltage Swing Differential 10 Ω VPPD CMRR Common Mode Rejection Ratio At DC, VID = 0V, VCM = 2.5 ± 0.5V 80 dB PSRR Power Supply Rejection Ratio At DC, V+ = 5 ± 0.5V, VIN = 2.5V 77 dB Channel to Channel Isolation f = 200 MHz, min. attenuation setting 73 dB Maximum Voltage Gain Gain Code 000000 (min. attenuation), Av = VO / VIN 26 dB Minimum Voltage Gain Gain Code 111111 (max. attenuation), Av = VO / VIN –5.5 dB Gain Parameters 3 www.national.com LMH6521 Storage Temperature Range Soldering Information Absolute Maximum Ratings (Note 1) LMH6521 Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units Gain Accuracy 1 % Gain Step Size 0.5 dB Channel Gain Matching ChA - ChB, any gain setting ±0.04 dB ±0.45 degrees 0 to 12 dB attenuation setting ±0.1 dB 0 to 24 dB attenuation setting ±0.3 dB 0 to 31 dB attenuation setting ±0.5 dB 0 to 12 dB attenuation setting ±0.6 degrees 0 to 24 dB attenuation setting ±5.3 degrees 0 to 31 dB attenuation setting ±16.5 degrees Channel Phase Matching Cumulative Gain Error Cumulative Phase Shift Gain Step Switching Time Gain Temperature Sensitivity 0 attenuation setting 15 ns 2.7 mdB/°C Power Requirements VCC Supply Voltage 5.0 5.25 V ICC Supply Current Both Channels Enabled 4.75 225 245 mA ICC Disabled Supply Current Both Channels 35 mA All Digital Inputs Logic Compatibility TTL, 2.5V CMOS, 3.3V CMOS VIL Logic Input Low Voltage 0.5 V VIH Logic Input High Voltage 1.8 V IIH Logic Input High Input Current Digital Input Voltage = 5V 200 μA IIL Logic Input Low Input Current Digital Input Voltage = 0V –60 μA Parallel and Pulse Mode Timing tGS Setup Time 3 ns tGH Hold Time 3 ns tLP Latch Low Pulse Width 7 ns tPG Pulse Gap between Pulses 20 ns tPW Minimum Pulse Width 15 ns tRW Reset Width 10 ns Pulse Mode Serial Mode Timing and AC Characteristics SPI Compatible fSCLK Max Serial Clock Frequency 50 MHz tPH SCLK High State Duty Cycle % of SCLK Period 50 % tPL SCLK Low State Duty Cycle % of SCLK Period 50 % tSU Serial Data In Setup Time 2 ns tH Serial Data In Hold Time 2 ns tOZD Serial Data Out TRI-STATE-toDriven Time Referenced to Negative edge of SCLK 10 ns tOD Serial Data Out Output Delay Time Referenced to Negative edge of SCLK 10 ns tCSS Serial Chip Select Setup Time 5 ns www.national.com Referenced to Positive edge of SCLK 4 Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the electrical tables under conditions different than those tested Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 6: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Note 7: Negative input current implies current flowing out of the device. Note 8: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Connection Diagram 32-Pin LLP Package 30120103 Top View Ordering Information Package Part Number 32-Pin LLP LMH6521SQE Package Marking Transport Media L6521SQ 250 Units Tape and Reel LMH6521SQ NSC Drawing 1k Units Tape and Reel LMH6521SQX SQA32A 4.5k Units Tape and Reel 5 www.national.com LMH6521 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. LMH6521 Pin Descriptions Pin Number Symbol Description 30, 11 INA+, INB+ Amplifier non—inverting input. Internally biased to mid supply. Input voltage should not exceed V+ or go below GND by more than 0.5V. 29, 12 INA−, INB− Amplifier inverting input. Internally biased to mid supply. Input voltage should not exceed V+ or go below GND by more than 0.5V. 24, 17 OUTA+, OUTB+ Amplifier non—inverting output. Externally biased to 0V. 23, 18 OUTA−, OUTB− Amplifier inverting output. Externally biased to 0V. 13, 15, 26, 28, center pad GND Ground pins. Connect to low impedance ground plane. All pin voltages are specified with respect to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins. 14, 27 +5V Power supply pins. Valid power supply range is 4.75V to 5.25V. Analog I/O Power Common Control Pins 4, 5 MOD0, MOD1 Digital Mode control pins. These pins float to the logic hi state if left unconnected. See applications section for Mode settings. 22, 19 ENA, ENB Enable pins. Logic 1 = enabled state. See application section for operation in serial mode. Digital Inputs Parallel Mode (MOD1 = 1, MOD0 = 1) 25, 16 A0, B0 Attenuation bit zero = 0.5dB step. Gain steps down from maximum gain (000000 = Maximum Gain). 31, 10 A1, B1 Attenuation bit one = 1dB step. 32, 9 A2, B2 Attenuation bit two = 2dB step. 1, 8 A3, B3 Attenuation bit three = 4dB step. 2, 7 A4, B4 Attenuation bit four = 8dB step. 3, 6 A5, B5 Attenuation bit five = 16dB step. 21, 20 LATA, LATB Latch pins. Logic zero = active, logic 1 = latched. Gain will not change once latch is high. Connect to ground if the latch function is not desired. Digital Inputs Serial Mode (MOD1 =1 , MOD0 = 0) SPI compatible 2 CLK Serial Clock 1 SDI Serial Data In. See application section for more details. 32 CSb Serial Chip Select (Active Low). 31 SDO Serial Data Out. 3, 4, 6, 7, 8, 9, 10, GND 16, 20, 21, 25 Pins unused in Serial Mode, connect to DC ground. Digital Inputs Pulse Mode (MOD1 = 0 , MOD0 = 1) 2, 7 UPA, UPB Up pulse pin. A logic 0 pulse will increase gain one step. 1, 8 DNA, DNB Down pulse pin. A logic 0 pulse will decrease gain one step. 1 & 2 or 7 & 8 Pulsing both pins together will reset the gain to maximum gain. 31, 32 S0A, S1A Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB. 10, 9 S0B, S1B Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB. 3, 5, 6, 16, 25 GND Pins unused in Pulse Mode, connect to DC ground. www.national.com 6 Pin Number Parallel Mode Serial Mode Pulse Mode 1 A3 SDI DNA 2 A4 CLK UPA 3 A5 NC GND 4 (MOD0) LOGIC HIGH (MOD0=1) LOGIC LOW (MOD0=0) LOGIC HIGH (MOD0=1) 5 (MOD1) LOGIC HIGH (MOD1=1) LOGIC HIGH (MOD1=1) LOGIC LOW (MOD1=0) 6 B5 GND GND 7 B4 NC UPB 8 B3 NC DNB 9 B2 NC S1B 10 B1 NC S0B 11 INB+ 12 INB- 13 GND 14 +5V 15 16 GND B0 GND 17 OUTB+ 18 OUTB- 19 GND ENB 20 LATB GND GND 21 LATA GND GND 22 ENA 23 OUTA- 24 OUTA+ 25 A0 NC 26 GND 27 +5V 28 GND 29 INA- 30 INA+ GND 31 A1 SDO S0A 32 A2 CS S1A 7 www.national.com LMH6521 Digital Control Mode Pin Functions V+ = 5V, Differential VOUT = 4VPP, RL = 200Ω, TA=25 °C, fin = 200 MHz, and Maximum Gain (0 Attenuation) Frequency Response 2dB Gain Steps Gain Flatness vs. Temperature 27.0 26.8 26.6 GAIN (dB) 26.4 26.2 26.0 25.8 25.6 100 MHz 200 MHz 300 MHz 400 MHz 25.4 25.2 25.0 -45 -30 -15 0 15 30 45 60 75 90 TEMPERATURE (degrees) 30120174 30120197 OIP3 vs. Frequency 60 Vsupply = 4.5V Vsupply = 5.0V Vsupply = 5.5V 51 50 OIP3 (dBm) 50 OIP3 (dBm) OIP3 vs. Temperature 52 ATT = 0 dB ATT = 8 dB ATT = 16 dB ATT = 24 dB 55 45 40 35 49 48 47 46 30 45 POUT = 4 dBm / tone 25 0 100 200 300 400 500 FREQUENCY (MHz) POUT = 4 dBm / tone 44 600 -45 -30 -15 0 15 30 45 60 75 90 TEMPERATURE (degrees) 30120179 30120176 OIP3 vs. Pout 60 Third Order Intermodulation Products vs. Frequency -40 ATT = 0 dB ATT = 8 dB ATT = 16 dB ATT = 24 dB 55 -60 50 45 40 -70 -80 -90 35 -100 30 -110 -2 0 2 4 6 8 OUTPUT POWER (dBm/tone) 10 POUT = 4 dBm / tone 0 30120177 www.national.com ATT = 0 dB ATT = 8 dB ATT = 16 dB ATT = 24 dB -50 IMD3 (dBc) OIP3 (dBm) LMH6521 Typical Performance Characteristics 100 200 300 400 500 FREQUENCY (MHz) 600 30120183 8 Second Order Harmonic Distortion vs. Attenuation -60 -60 T = - 40 °C T = 25 °C T = 85 °C -70 HD2 (dBc) HD3 (dBc) -70 Channel A Channel B -65 -80 -90 -75 -80 -85 -90 -95 -100 -100 POUT = 6 dBm -110 POUT = 6 dBm -105 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 0 4 8 12 16 20 24 28 32 ATTENUATION (dB, 0 = MAX GAIN) 30120190 30120181 Third Order Harmonic Distortion vs. Attenuation -50 Second Order Harmonic Distortion vs. Frequency -50 Channel A Channel B -55 -60 -60 -65 HD2 (dBc) HD3 (dBc) T = - 40 °C T = 25 °C T = 85 °C -70 -75 -80 -70 -80 -90 -85 POUT = 6 dBm -90 POUT = 6 dBm -100 0 4 8 12 16 20 24 28 32 ATTENUATION (dB, 0 = MAX GAIN) 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 30120195 30120189 Second Order Harmonic Distortion at 100 MHz -50 -20 ATT = 0 dB ATT = 8 dB ATT = 16 dB ATT = 24 dB -55 -60 ATT = 0 dB ATT = 8 dB ATT = 16 dB ATT = 24 dB -30 -40 -50 -65 HD3 (dBc) HD2 (dBc) Third Order Harmonic Distortion at 100 MHz -70 -75 -60 -70 -80 -90 -80 -100 -85 -110 f = 100 MHz -90 -4 0 4 8 12 16 OUTPUT POWER (dBm) f = 100 MHz -120 20 -4 30120193 0 4 8 12 16 OUTPUT POWER (dBm) 20 30120194 9 www.national.com LMH6521 Third Order Harmonic Distortion vs. Frequency -40 -10 ATT = 0 dB ATT = 8 dB ATT = 16 dB ATT = 24 dB -20 -30 -40 -60 HD3 (dBc) HD2 (dBc) Third Order Harmonic Distortion at 200 MHz ATT = 0 dB ATT = 8 dB ATT = 16 dB ATT = 24 dB -50 -70 -80 -50 -60 -70 -80 -90 -90 -100 f = 200 MHz -100 -4 0 4 8 12 16 OUTPUT POWER (dBm) f = 200 MHz -110 20 -4 0 4 8 12 16 OUTPUT POWER (dBm) 30120191 1.0 Cumulative Phase Shift 20 Channel A Channel B 0.8 15 PHASE ERROR (degrees) GAIN ERROR (dB) 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 0.5 dB steps f = 200 MHz -0.8 -1.0 Channel A Channel B 10 5 0 -5 -10 -15 -20 0 4 8 12 16 20 24 28 32 ATTENUATION (dB, 0 = MAX GAIN) 0.5 dB steps f = 200 MHz 0 4 8 12 16 20 24 28 32 ATTENUATION (dB, 0 = MAX GAIN) 30120173 30120175 Noise Figure vs. Frequency 11 Noise Figure vs. Attenuation 40 T = - 40 °C T = 25 °C T = 85 °C 35 NOISE FIGURE (dB) 10 9 8 7 6 100 MHz 200 MHz 300 MHz 400 MHz 30 25 20 15 10 5 5 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 0 4 8 12 16 20 24 28 32 ATTENUATION (0 = MAX GAIN) (dB) 30120171 www.national.com 20 30120192 Cumulative Gain Error NOISE FIGURE (dB) LMH6521 Second Order Harmonic Distortion at 200 MHz 30120184 10 Channel To Channel Isolation 250 -30 Both Channels Enabled -40 240 ISOLATION (dB) SUPPLY CURRENT (mA) LMH6521 Supply Current vs. Temperature 230 220 210 Vs = 4.5V Vs = 5.0V Vs = 5.5V -50 Ch A to Ch B -60 -70 -80 -90 200 Ch B to Ch A -100 -40 -20 0 20 40 60 80 100 TEMPERATURE (degrees) 0 100 200 300 400 500 FREQUENCY (MHz) 30120188 30120196 Output Impedance 250 80 200 60 OUTPUT IMEDANCE (Ω) INPUT IMPEDANCE (Ω) Input Impedance |Z| 150 100 R 50 0 600 jX -50 -100 |Z| 40 R 20 0 -20 jX -40 0 100 200 300 400 FREQUENCY (MHz) 500 0 30120199 100 200 300 400 FREQUENCY (MHz) 500 301201100 11 www.national.com LMH6521 Application Information 30120101 FIGURE 1. LMH6521 Typical Application The outputs of the LMH6521 are low impedance devices that need to be connected to ground with 1uH RF chokes and require ac-coupling capacitors of 0.01uF. The input pins are self biased to 2.5V and should be ac-coupled with 0.01uF capacitors as well. The output RF inductors and ac-coupling capacitors are the main limitations for operating at low frequencies. Each channel of the LMH6521 consists of a digital step attenuator followed by a low distortion 26 dB fixed gain amplifier and a low impedance output stage. The gain is digitally controlled over a 31.5 dB range from +26dB to −5.5dB. The LMH6521 has a 200Ω differential input impedance and a low 20Ω differential output impedance. To enable each channel of the LMH6521, the ENA and ENB pins can be left to float, which internally is connected high with a weak pull-up resistor. Externally connecting ENA and ENB to ground will disable the channels of the LMH6521 and reduce the current consumption to 17.5mA per channel. INTRODUCTION The LMH6521 is a dual, digitally controlled variable gain amplifier designed for narrowband and wideband intermediate frequency sampling applications. The LMH6521 is optimized for accurate 0.5 dB gain steps with exceptional gain and phase matching between channels combined with low distortion products. Gain matching error is less than ±0.05 dB and phase matching error less than ±0.5 degrees over the entire attenuation range. This makes the LMH6521 ideal for driving analog-to-digital converters where high linearity is necessary. shows a typical application circuit. The LMH6521 has been designed for AC coupled applications and has been optimized to operate at frequencies greater than 3 MHz. BASIC CONNECTIONS A voltage between 4.75 V and 5.25 V should be applied to the supply pin labeled +5V. Each supply pin should be decoupled with a additional capacitance along with some low inductance, surface-mount ceramic capacitor of 0.01uF as close to the device as possible where space allows. 30120124 FIGURE 2. Basic Operating Connection www.national.com 12 OUTPUT CHARACTERISTICS The LMH6521 has a low output impedance very similar to a traditional operational amplifier output. This means that a wide range of load impedance can be driven with minimal gain loss. Matching load impedance for proper termination of filters is as easy as inserting the proper value of resistor between the filter and the amplifier. This flexibility makes system design and gain calculations very easy. The LMH6521 was designed to run from a single 5V supply. In spite of this low supply voltage the LMH6521 is still able to deliver very high power gains when driving low impedance loads. OUTPUT CONNECTIONS The LMH6521, like most high frequency amplifiers, is sensitive to loading conditions on the output. Load conditions that include small amounts of capacitance connected directly to the output can cause stability problems. An example of this is shown inFigure 5. A more sophisticated filter may require better impedance matching. Refer to Figure 17 for an example filter configuration and table IF Frequency Bandpass Filter Component Values for some IF filter components values. 30120102 FIGURE 3. LMH6521 Block Diagram INPUT CHARACTERISTICS The LMH6521 input impedance is set by internal resistors to a nominal 200Ω. At higher frequencies device parasitic reactances will start to impact the input impedances. Refer to the input impedance graph in the typical characteristics section for more details For many AC coupled applications the impedance can be easily changed using LC circuits to transform the actual impedance to the desired impedance. 30120169 FIGURE 4. Differential 200Ω LC Conversion Circuit 13 www.national.com LMH6521 In Figure 4 a circuit is shown that matches the amplifier 200Ω input with a source impedance of 100Ω. To avoid undesirable signal transients the LMH6521 should not be powered on with large inputs signals present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs. LMH6521 30120168 FIGURE 5. Example Output Configuration to 5V to configure the LMH6521 into one of the three digital control modes. Some pins on the LMH6521 have different functions depending on the digital control mode. These functions are shown in the Digital Control Mode Pin Functions table. The outputs of the LMH6521 need to be biased to near ground potential. On the evaluation board, 1µH inductors are installed to provide proper output biasing. The bias current is approximately 36mA per output pin and is not a function of the load condition, which makes the LMH6521 robust to handle various output load conditions while maintaining superior linearity as shown in Figure 6. With large inductors and high operating frequencies the inductor will present a very high impedance and will have minimal AC current. If the inductor is chosen to have a smaller value, or if the operating frequency is very low there could be enough AC current flowing in the inductor to become significant. Make sure to check the inductor datasheet to not exceed the maximum current limit. OIP3 (dBm) 50 40 VOUT = 4 VPP 40 36 32 30 28 Power Gain 20 10 0 24 Maximum Gain f = 200 MHz POWER GAIN (dB) 60 PARALLEL MODE (MOD1= 1, MOD0 = 1) When designing a system that requires very fast gain changes parallel mode is the best selection. Refer to Digital Control Mode Pin Functions table for pin definitions of the LMH6521 in parallel mode. The LMH6521 has a 6-bit gain control bus as well as latch pins LATA and LATB for channels A and B. When the latch pin is low, data from the gain control pins is immediately sent to the gain circuit (i.e. gain is changed immediately). When the latch pin transitions high the current gain state is held and subsequent changes to the gain set pins are ignored. To minimize gain change glitches multiple gain control pins should not change while the latch pin is low. Gain glitches could result from timing skew between the gain set bits. This is especially the case when a small gain change requires a change in state of three or more gain control pins. If continuous gain control is desired the latch pin can be tied to ground. This state is called transparent mode and the gain pins are always active. In this state the timing of the gain pin logic transitions should be planned carefully to avoid undesirable transients ENA and ENB pins are provided to reduce power consumption by disabling the highest power portions of the LMH6521. The gain register will preserve the last active gain setting during the disabled state. These pins will float high and can be left disconnected if they won't be used. If the pins are left disconnected a 0.01uF capacitor to ground will help prevent external noise from coupling into these pins. Figure 7, Figure 8, and Figure 9 show the various connections in parallel mode with respect to the latch pin. 20 16 50 100 150 200 250 300 FILTER DIFFERENTIAL INPUT RESISTANCE (Ω) 30120120 FIGURE 6. OIP3 vs Amplifier Load Resistance DIGITAL CONTROL The LMH6521 will support three modes of gain control, parallel mode, serial mode (SPI compatible) and pulse mode. Parallel mode is fastest and requires the most board space for logic line routing. Serial mode is compatible with existing SPI compatible systems. The pulse mode is both fast and compact, but must step through intermediate gain steps when making large gain changes. Pins MOD0 and MOD1 are used to configure the LMH6521 for the three gain control modes. MOD0 and MOD1 have weak pull-up resistors to an internal 2.5V reference but is designed for 2.5V-5V CMOS logic levels. MOD0 and MOD1 can be externally driven (LOGIC HIGH) to voltages between 2.5V www.national.com 30120117 FIGURE 7. Parallel Mode Connection for Fastest Response 14 30120118 FIGURE 8. Parallel Mode Connection Not Using Latch Pins (Latch pins tied to logic low state) 30120119 FIGURE 9. Parallel Mode Connection Using Latch Pins to Mulitplex Digital Data SERIAL MODE — SPI™ COMPATIBLE INTERFACE (MOD1= 1, MOD0 = 0) Serial interface allows a great deal of flexibility in gain programming and reduced board complexity. Using only 4 wires for both channels allows for significant board space savings. The trade off for this reduced board complexity is slower response time in gain state changes. For systems where gain is changed only infrequently or where only slow gain changes are required serial mode is the best choice. Refer to Digital Control Mode Pin Functions table for pin definitions of the LMH6521 in serial mode. The serial interface is a generic 4-wire synchronous interface that is compatible with SPI standard interfaces and used on many microcontrollers and DSP controllers. The serial mode is active when the two mode pins are set as follows: MOD1=1, MOD0=0). In this configuration the pins function as shown in the Pin Descriptions table. The SPI interface uses the following signals: clock input (CLK), serial data in (SDI), serial data out, and serial chip select (CS) ENA and ENB pins are active in serial mode. For fast disable capability these pins can be used and the serial register will 15 www.national.com LMH6521 hold the last active gain state. These pins will float high and can be left disconnected for serial mode. The serial control bus can also disable the DVGA channels, but at a much slower speed. The serial enable function is an AND function. For a channel to be active both the enable pin and the serial control register must be in the enabled state. To disable a channel either method will suffice. See the Typical Performance section for disable and enable timing information. LATA and LATB pins are not active during serial mode. The serial clock pin CLK is used to register the input data that is presented on the SDI pin on the rising edge; and to source the output data on the SDO pin on the falling edge. User may disable clock and hold it in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled or disabled. The chip select pin CS starts a new register access with each assertion - i.e., the SDATA field protocol is required. The user is required to deassert this signal after the 16th clock. If the SCSb is deasserted before the 16th clock, no address or data write will occur. The rising edge captures the address just shifted-in and, in the case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the deasserted pulse - which is specified in the Electrical Specifications section. SDI is an input pin for the serial data. It must observe setup/ hold requirements with respect to the SCLK. Each cycle is 16bits long SDO is the data output pin and is normally at TRI-STATE® and is driven only when SCSb is asserted. Upon SCSb assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges. Upon power-up, the default register address is 00h The SDO internal driver circuit is an open collector device with a weak pull-up resistor to an internal 2.5V reference. It is 5V tolerant so an external pull-up resistor can connect to 2.5V, 3.3V or 5V as shown in Figure 11. However, the external pullup resistor should be chosen to limit the current to 11mA or less. Otherwise the SDO logic low output level (VOL may not achieve close to ground and in extreme case could cause problem for FPGA input gate. Using minimum values for external pull-up resistor is a good to maximize speed for SDO signal. So if high SPI clock frequency is needed then minimum value external pull-up resistor is the best choice as shown in Figure 11. Each serial interface access cycle is exactly 16 bits long as shown in Figure 10. Each signal's function is described below. The read timing is shown in Figure 12, while the write timing is shown in figure Figure 13. LMH6521 30120112 FIGURE 10. Serial Interface Protocol (SPI compatible) R/Wb Serial Word Format for LMH6521 Read / Write bit. A value of 1 indicates a read operation, while a value of 0 indicates a write operation. Reserved Not used. Must be set to 0. ADDR: Address of register to be read or written. DATA In a write operation the value of this field will be written to the addressed register when the chip select pin is deasserted. In a read operation this field is ignored. C7 C6 C5 C4 C3 C2 C1 C0 0= write 1=read 0 0 0 0 0 0 0=Ch A 1=Ch B Serial Word Format for LMH6521 (cont) Enable Gb5 0=Off 1=On Gb4 FIGURE 11. Serial Mode 4–wire Connection 16 Gb2 Gb1 Gb0 RES 1= 1= 1= 1= 1= 1= 0 +16dB +8dB +4dB +2dB +1dB +0.5dB 30120182 www.national.com Gb3 LMH6521 30120111 FIGURE 12. Read Timing Read Timing Data Output on SDO Pin Parameter Description tCSH Chip select hold time tCSS Chip select setup time tOZD Initial output data delay tODZ High impedance delay tOD Output data delay 30120110 FIGURE 13. Write Timing Data Written to SDI Pin Write Timing Data Input on SDI Pin Parameter Description tPL Minimum clock low time (clock duty dycle) tPH Minimum clock high time (clock duty cycle) tSU Input data setup time tH Input data hold time board space is limited this mode may be the best choice. The ENA and ENB pins are fully active during pulse mode, and the channel gain state is preserved during the disabled state. Refer to Digital Control Mode Pin Functions table for pin definitions of the LMH6521 in pulse mode. In this mode the gain step size can be selected from a choice of 0.5, 1, 2 or 6dB steps. During operation the gain can be PULSE MODE (MOD1= 0, MOD0 = 1) Pulse mode is a simple yet fast way to adjust gain settings. Using only two control lines per channel the LMH6521 gain can be changed by simple up and down signals. Gain step sizes is selectable either by hard wiring the board or using two additional logic inputs. For a system where gain changes can be stepped sequentially from one gain to the next and where 17 www.national.com LMH6521 quickly adjusted either up or down one step at a time by a negative pulse on the UP or DN pins. As shown in Figure 15 each gain step pulse must have a logic high state of at least tPW= 20 ns and a logic low state of at least tPG= 20 ns for the pulse to register as a gain change signal. design techniques assisted with the heat dissipation of the LMH6521 to optimize distortion performance. Please refer to the LMH6521EVAL evaluation board application note AN– 2045 for suggested layout techniques. Package information is available on the National web site. http://www.national.com/packaging/folders/SQA32A.html INTERFACE TO ADC The LMH6521 was designed to be used with National Semiconductor's high speed ADC's. As shown in Figure 1, AC coupling provides the best flexibility especially for IF subsampling applications. The inputs of the LMH6521 will self bias to the optimum voltage for normal operation. The internal bias voltage for the inputs is approximately mid rail which is 2.5V with the typical 5V power supply condition. In most applications the LMH6521 input will need to be AC coupled. The LMH6521 output common mode voltage is biased to 0V and has a maximum differential output voltage swing of 10VPPD as shown in Figure 16. This means that for driving most ADCs AC coupling is required. Since most often a band pass filter is desired between the amplifier and ADC the bandpass filter can be configured to block the DC voltage of the amplifier output from the ADC input. Figure 17 shows a wideband bandpass filter configuration that could be designed for a 200Ω impedance system for various IF frequencies. 30120122 FIGURE 14. To provide a known gain state there is a reset feature in pulse mode. To reset the gain to maximum gain both the UP and DN pins must be strobed low together as shown in Figure 15. There must be an overlap of at least tRW= 20 ns for the reset to register. 30120123 FIGURE 15. Pulse Mode Timing THERMAL MANAGEMENT The LMH6521 is packaged in a thermally enhanced LLP package and features an exposed pad that is connected to the GND pins. It is recommended that the exposed pad be attached directly to a large power supply ground plane for maximum heat dissipation. The thermal advantage of the LLP package is fully realized only when the exposed die attach pad is soldered down to a thermal land on the PCB board with the through vias planted underneath the thermal land. The thermal land can be connected to any ground plane within the PCB. However, it is also very important to maintain good high speed layout practices when designing a system board. The LMH6521EVAL evaluation board implemented an eight metal layer pcb with (a) 4 oz. copper inner ground planes (b) additonal through vias and (c) maximum bottom layer metal coverage to assist with device heat dissipation. These pcb 30120121 FIGURE 16. Output Voltage with Respect to Output Common Mode 30120113 FIGURE 17. Wideband Bandpass Filter www.national.com 18 lost at the input. Figure 18 shows the LMH6521 driving the ADC16DV160 (16–bit ADC). The band-pass filter is a 3rd order 100Ω matched tapped-L configured for a center frequency of 192MHz with a 20MHz bandwidth across the differential inputs of the ADC16DV160. The ADC16DV160 is a dual channel 16–bit ADC with maximum sampling rate of 160 MSPS. Using a 2–tone large input signal with the LMH6521 set to maximum gain (26dB) to drive an input signal level at the ADC of –1dBFS, the SNR and SFDR results are shown in table below. IF Frequency Bandpass Filter Component Values Center Frequency 75 MHz 150 MHz 180 MHz 250 MHz Bandwidth 40 MHz 60 MHz 75 MHz 100 MHz LMH6521+BPF+ADC16DV160 vs Typical ADC16DV160 Specifications R1, R2 L1, L2 90 Ω 90 Ω 390 nH 370 nH 90 Ω 300 nH 90 Ω 225 nH Configuraton C1, C2 10 pF 3 pF 2.7 pF 1.9 pF C3 22 pF 19 pF 15 pF 11 pF L5 220 nH 62 nH 54 nH 36 nH R3, R4 100 Ω 100 Ω 100 Ω 100 Ω ADC Input SNR (dBFS) SFDR (dBFS) LMH6521+BPF +ADC16DV160 –1dBFS 75.5 82 ADC16DV160 only –1dBFS 76 89 POWER SUPPLIES The LMH6521 was designed primarily to be operated on 5V power supplies. The voltage range for VCC is 4.75V to 5.25V. When operated on a board with high speed digital signals it is important to provide isolation between digital signal noise and the LMH6521 inputs. The SP16160CH1RB reference board provides an example of good board layout. An alternate narrowband filter approach is presented in Figure 18. The narrow band-pass antialiasing filter between the LMH6521 and ADC16DV160 attenuates the output noise of the LMH6521 outside the Nyquist zone helping to preserve the available SNR of the ADC. Figure 18 shows a 1:4 input transformer used to match the 200Ω balanced input of the LMH6521 to the 50 unbalanced source to minimize insertion 30120125 FIGURE 18. Narrowband Tapped-L Bandpass Filter Center Frequency is 192MHz with a 20MHz Bandwidth Designed for 200Ω Impedance 19 www.national.com LMH6521 Table IF Frequency Bandpass Filter Component Values show values for some common IF frequencies for Figure 17. The filter shown in Figure 17 offers a good compromise between bandwidth, noise rejection and cost. This filter topology works best with the 12 to 16 bit analog to digital converters shown in the COMPATIBLE HIGH SPEED ANALOG TO DIGITAL CONVERTERS table. LMH6521 COMPATIBLE HIGH SPEED ANALOG TO DIGITAL CONVERTERS Product Number Max Sampling Rate (MSPS) Resolution Channels ADC12L063 62 12 SINGLE ADC12DL065 65 12 DUAL ADC12L066 66 12 SINGLE ADC12DL066 66 12 DUAL CLC5957 70 12 SINGLE ADC12L080 80 12 SINGLE ADC12DL080 80 12 DUAL ADC12C080 80 12 SINGLE ADC12C105 105 12 SINGLE ADC12C170 170 12 SINGLE ADC12V170 170 12 SINGLE ADC14C080 80 14 SINGLE ADC14C105 105 14 SINGLE ADC14DS105 105 14 DUAL ADC14155 155 14 SINGLE ADC14V155 155 14 SINGLE ADC16V130 130 16 SINGLE ADC16DV160 160 16 DUAL ADC08D500 500 8 DUAL ADC08500 500 8 SINGLE ADC08D1000 1000 8 DUAL ADC081000 1000 8 SINGLE ADC08D1500 1500 8 DUAL ADC081500 1500 8 SINGLE ADC08(B)3000 3000 8 SINGLE ADC08L060 60 8 SINGLE ADC08060 60 8 SINGLE ADC10DL065 65 10 DUAL ADC10065 65 10 SINGLE ADC10080 80 10 SINGLE ADC08100 100 8 SINGLE ADCS9888 170 8 SINGLE ADC08(B)200 200 8 SINGLE ADC11C125 125 11 SINGLE ADC11C170 170 11 SINGLE www.national.com 20 LMH6521 Physical Dimensions inches (millimeters) unless otherwise noted 32-Pin Package NS Package Number SQA32A 21 www.national.com LMH6521 High Performance Dual DVGA Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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