AD AD8345-EVAL 250 mhz.1000 mhz quadrature modulator Datasheet

a
FEATURES
250 MHz–1000 MHz Operating Frequency
+2.5 dBm P1 dB @ 800 MHz
–155 dBm/Hz Noise Floor
0.5 Degree RMS Phase Error (IS95)
0.2 dB Amplitude Balance
Single 2.7 V–5.5 V Supply
Pin-Compatible with AD8346
16-Lead Exposed Paddle TSSOP Package
APPLICATIONS
Cellular Communication Systems
W-CDMA/CDMA/GSM/PCS/ISM Transceivers
Fixed Broadband Access Systems LMDS/MMDS
Wireless LAN
Wireless Local Loop
Digital TV/CATV Modulators
Single Sideband Upconverter
250 MHz–1000 MHz
Quadrature Modulator
AD8345
FUNCTIONAL BLOCK DIAGRAM
IBBP 1
AD8345
IBBN 2
COM3 3
LOIN 5
LOIP
QBBP
15
QBBN
14
COM3
13
COM3
12
VPS2
11
VOUT
10
COM2
9
COM3
+
COM1 4
6
16
PHASE
SPLITTER
VPS1 7
BIAS
ENBL 8
PRODUCT DESCRIPTION
APPLICATIONS
The AD8345 is a silicon RFIC quadrature modulator, designed
for use from 250 MHz to 1000 MHz. Its excellent phase accuracy and amplitude balance enable the high performance direct
modulation of an IF carrier.
The AD8345 Modulator can be used as the IF transmit modulator in digital communication systems such as GSM and PCS
transceivers. It can also directly modulate an LO signal to
produce QPSK and various QAM formats for 900 MHz communication systems as well as digital TV and CATV systems.
The AD8345 accurately splits the external LO signal into two
quadrature components through the polyphase phase-splitter
network. The two I and Q LO components are mixed with the
baseband I and Q differential input signals. Finally, the outputs
of the two mixers are combined in the output stage to provide a
single-ended 50 Ω drive at VOUT.
Additionally, this quadrature modulator can be used with direct
digital synthesizers in hybrid phase-locked loops to generate
signals over a wide frequency range with millihertz resolution.
The AD8345 Modulator is supplied in a 16-lead TSSOP package with exposed paddle. Its performance is specified over a
–40°C to +85°C temperature range. This device is fabricated on
Analog Devices’ advanced silicon bipolar process.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD8345–SPECIFICATIONS (V = 5 V; LO= –2 dBm @ 800 MHz, 50 ⍀ source and load impedances, I and Q inputs
S
0.7 V ⴞ 0.3 V on each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz Baseband Frequency.
TA = 25ⴗC, unless otherwise noted.)
Parameters
RF OUTPUT
Operating Frequency1
Output Power
Output P1 dB
Noise Floor
Quadrature Error
I/Q Amplitude Balance
LO Leakage
Sideband Rejection
Third Order Distortion
Second Order Distortion
Equivalent Output IP3
Equivalent Output IP2
Output Return Loss (S22)
RESPONSE TO CDMA IS95
BASEBAND SIGNALS
ACPR
EVM
Rho
Conditions
Min
250
–3
20 MHz Offset from LO, All BB
Inputs at 0.7 V
(CDMA IS95 Setup, Refer to Figure 13)
(CDMA IS95 Setup, Refer to Figure 13)
0.5
0.2
–42
–42
–52
–60
25
59
–20
Turn-Off
Unit
1000
+2
MHz
dBm
dBm
dBm/Hz
–33
–34
–72
1.3
0.9995
–10
No Termination on LOIP, LOIN at
AC Ground
50 Ω Terminating Resistor, Differential
Drive via Balun
ENABLE
Turn-On
–1
2.5
–155
Max
Degree rms
dB
dBm
dBc
dBc
dBc
dBm
dBm
dB
(Refer to Figure 13)
LO INPUT
LO Drive level
LOIP Input Return Loss (S11)2
BASEBAND INPUTS
Input Bias Current
Input Capacitance
DC Common Level
Bandwidth (3 dB)
Typ
0.6
Full Power (0.7 V ± 0.3 V on Each
Input, Refer to TPC 2)
Enable High to Output within 0.5 dB of
Final Value
Enable Low to Supply Current Dropping
below 2 mA
ENBL High Threshold (Logic 1)
ENBL Low Threshold (Logic 0)
POWER SUPPLIES
Voltage
Current Active
Current Standby
2.7
50
–2
dBc
%
0
dBm
–5
dB
–9
dB
10
2
0.7
80
µA
pF
V
MHz
0.8
2.5
µs
1.5
µs
+VS/2
+VS/2
V
V
65
70
5.5
78
V
mA
µA
NOTES
1
For information on operation below 250 MHz, see Figure 4.
2
See LO Drive section for more details on input matching.
Specifications subject to change without notice.
–2–
REV. 0
AD8345
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Supply Voltage VPS1, VPS2 . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Power LOIP, LOIN (re 50 Ω) . . . . . . . . . . . . . 10 dBm
IBBP, IBBN, QBBP, QBBN . . . . . . . . . . . . . . . . . 0 V, 2.5 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 500 mW
θJA (Exposed Paddle Soldered Down) . . . . . . . . . . . . 30°C/W
θJA (Exposed Paddle not Soldered Down) . . . . . . . . . 95°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C
IBBP 1
16 QBBP
IBBN 2
15 QBBN
14 COM3
COM3 3
COM1 4
LOIN 5
AD8345
TOP VIEW
(Not to Scale)
13 COM3
12 VPS2
LOIP 6
11 VOUT
VPS1 7
10 COM2
ENBL 8
9
COM3
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8345 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8345ARE
AD8345ARE-REEL
AD8345ARE-REEL7
AD8345-EVAL
–40°C to +85°C
Tube (16-Lead TSSOP with Exposed Pad)
13" Tape and Reel
7" Tape and Reel
Evaluation Board
RE-16
REV. 0
–3–
AD8345
PIN FUNCTION DESCRIPTIONS
Equivalent
Circuit
Pin No.
Mnemonic
Function
1, 2
IBBP, IBBN
3, 9, 13, 14
4
5, 6
COM3
COM1
LOIN, LOIP
7
VPS1
8
ENBL
I Channel Baseband Differential Input Pins. These high impedance inputs should
Circuit A
be dc biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p
on each pin (0.4 V to 1 V). This gives a differential drive of 1.2 V p-p. Inputs are
not self-biasing so external biasing circuitry must be used in ac-coupled applications.
Ground Pin for Input V-to-I Converters and Mixer Core.
Ground Pin for the LO Phase-Splitter and LO Buffers.
Differential LO Drive Pins. Internal dc bias (approximately 1.8 V @ VS = 5 V)
Circuit B
is supplied. Pins must be ac-coupled. Single-ended or differential drive is permissible.
Power Supply Pin for the Bias Cell and LO Buffers. This pin should be decoupled
using local 1000 pF and 0.01 µF capacitors.
Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Circuit C
10
COM2
Ground Pin for the Output Stage of Output Amplifier.
11
12
VOUT
VPS2
15, 16
QBBN, QBBP
50 Ω DC-Coupled RF Output. Pin should be ac-coupled.
Power supply pin for baseband input voltage to current converters and mixer core.
This pin should be decoupled using local 1000 pF and 0.01 µF capacitors.
Q Channel Baseband Differential Input Pins. Inputs should be dc biased to
approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin
(0.4 V to 1 V). This gives a differential drive level of 1.2 V p-p. Inputs are not
self-biasing so external biasing circuitry must be used in ac-coupled applications.
Circuit D
Circuit A
EQUIVALENT CIRCUITS
VPS2
VPS2
BUFFER
TO MIXER
CORE
100k⍀
100k⍀
ENBL
INPUT
CURRENT
MIRROR
100k⍀
Circuit A
TO BIAS FOR
STARTUP/
SHUTDOWN
Circuit C
VPS2
VPS1
LOIN
PHASE
SPLITTER
CONTINUES
LOIP
40⍀
VOUT
40⍀
Circuit B
Circuit D
Figure 1. Equivalent Circuits
–4–
REV. 0
Typical Performance Characteristics– AD8345
0
0
–2
TA = –40ⴗC
–2
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
SSB OUTPUT P1dB – dBm
SSB POWER – dBm
–4
–6
–8
–10
–12
–14
–16
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–20
250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
LO FREQUENCY – MHz
TPC 1. Single Sideband (SSB) Output Power (POUT) vs. LO
Frequency (FLO). (I and Q Inputs Driven in Quadrature at
Baseband Frequency (FBB) = 1 MHz; TA = 25 °C)
TA = +25ⴗC
–8
–10
–12
TA = +85ⴗC
–16
250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
LO FREQUENCY – MHz
TPC 4. SSB Output 1 dB Compression Point (OP 1 dB) vs.
FLO. (VS = 2.7 V, LO Level = –2 dBm, I and Q Inputs Driven
in Quadrature, FBB = 1 MHz)
1.0
4.0
0.5
3.5
0.0
–0.5
–1.0
SSB OUTPUT P1dB – dBm
OUTPUT POWER VARIATION – dB
–6
–14
–18
VS = 2.7V, 5V DIFFERENTIAL INPUT = 200mV p-p
–1.5
–2.0
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–2.5
–3.0
–3.5
–4.0
TA = +85ⴗC
3.0
TA = +25ⴗC
2.5
2.0
TA = –40ⴗC
1.5
1.0
0.5
–4.5
0.0
–5.0
–5.5
0.1
1
10
BASEBAND FREQUENCY – MHz
–0.5
250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
LO FREQUENCY – MHz
100
TPC 2. I and Q Input Bandwidth. (TA = 25 °C, FLO = 800 MHz,
LO Level = –2 dBm, I and Q Inputs Driven in Quadrature)
TPC 5. SSB Output 1 dB Compression Point (OP 1 dB) vs.
FLO. (VS = 5 V, LO Level = –2 dBm, I and Q Inputs Driven in
Quadrature, FBB = 1 MHz)
0
–40
–2
–41
CARRIER FEEDTHROUGH – dBm
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–4
–6
SSB POWER – dBm
–4
–8
–10
–12
–14
–16
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–18
–20
–22
–20
20
0
40
TEMPERATURE – ⴗC
60
–44
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–45
–46
–47
–48
–50
250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
LO FREQUENCY – MHz
80
TPC 6. Carrier Feedthrough vs. FLO. (LO Level = –2 dBm,
TA = 25 °C)
TPC 3. SSB POUT vs. Temperature. (FLO = 800 MHz, LO
Level = –2 dBm, FBB = 1 MHz, I and Q Inputs Driven in
Quadrature)
REV. 0
–43
–49
–24
–26
–40
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–42
–5–
–30
–26
–32
–28
SIDEBAND SUPPRESSION – dBc
CARRIER FEEDTHROUGH – dBm
AD8345
–34
–36
–38
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–40
–42
–44
–46
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–30
–32
–34
–36
–38
–40
–42
–48
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–50
–40
–20
0
20
40
TEMPERATURE – ⴗC
60
–44
80
0
T = +85
26
T = –40
45
50
–36
SIDEBAND SUPPRESSION – dBc
28
24
22
20
PERCENTAGE
15
20
25
30
35
40
BASEBAND FREQUENCY – MHz
–35
30
18
16
14
12
10
8
6
4
–37
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–38
–39
–40
–41
–42
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–43
–44
2
–82
–78
–74
–70
–66
–62
–58
CARRIER FEEDTHROUGH – dBm
AFTER NULLING TO ⬍–65dBm AT +25ⴗC
–54
–45
–40
–50
TPC 8. Carrier Feedthrough Distribution at Temperature
Extremes. After Feedthrough Nulled to <–65 dBm at TA =
25 °C. (FLO = 800 MHz, LO Level = –2 dBm)
–20
0
20
40
TEMPERATURE – ⴗC
60
80
TPC 11. Sideband Suppression vs. Temperature.
(FLO = 800 MHz, LO Level = –2 dBm, FBB =1 MHz,
I and Q Inputs Driven in Quadrature)
–30
–20
–32
–25
THIRD ORDER DISTORTION – dBc
SIDEBAND SUPPRESSION – dBc
10
TPC 10. Sideband Suppression vs. FBB. (TA = 25 °C,
FLO = 800 MHz, LO Level = –2 dBm, I and Q Inputs
Driven in Quadrature)
TPC 7. Carrier Feedthrough vs. Temperature.
(FLO = 800 MHz, LO Level = –2 dBm)
0
–86
5
–34
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–36
–38
–40
–42
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–44
–46
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–30
–35
–40
–45
–50
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–55
–48
–60
–50
250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
LO FREQUENCY – MHz
–65
0
5
10
15
20
25
30
35
40
BASEBAND FREQUENCY – MHz
45
50
TPC 12. Third Order Distortion vs. FBB. (TA = 25 °C,
FLO = 800 MHz, LO Level = –2 dBm, I and Q Inputs
Driven in Quadrature)
TPC 9. Sideband Suppression vs. FLO. (TA = 25 °C,
LO Level = –2 dBm, FBB = 1 MHz, I and Q Inputs
Driven in Quadrature)
–6–
REV. 0
–45
80
–50
75
SUPPLY CURRENT – mA
THIRD ORDER DISTORTION – dBc
AD8345
–55
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
–60
–65
–70
–75
–20
0
20
40
TEMPERATURE – ⴗC
60
VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p
65
60
55
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
50
45
VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p
–80
–40
70
40
–40
80
TPC 13. Third Order Distortion vs. Temperature.
(FLO = 800 MHz, LO Level = –2 dBm, FBB =1 MHz,
I and Q Inputs Driven in Quadrature)
–20
0
20
40
TEMPERATURE – ⴗC
60
80
TPC 16. Power Supply Current vs. Temperature
1GHz
–10
–2
–15
–4
–20
–6
–25
SSB POUT
–8
–30
–10
–35
–12
–14
–40
–45
THIRD ORDER DISTORTION
–16
–18
–50
–55
–20
–60
–22
–65
–24
–70
0.0
0.5
1.0
1.5
2.0
2.5
BASEBAND DIFFERENTIAL INPUT VOLTAGE – V p-p
WITH 50⍀
SSB OUTPUT POWER – dBm
THIRD ORDER DISTORTION – dBc
SMITH CHART
NORMALIZED
TO 50⍀
250MHz
–26
3.0
WITH 100⍀
4
2
–15
0
–20
–2
–25
SSB POUT
–4
–30
–6
–35
–8
–40
–10
–45
–12
–14
–50
–55
THIRD ORDER DISTORTION
–16
–60
–18
–65
–20
–70
0.0
0.5
1.0
1.5
2.0
2.5
BASEBAND DIFFERENTIAL INPUT VOLTAGE – V p-p
0
–5
RETURN LOSS – dB
–5
–10
–10
–15
–20
VS = 2.7V
–25
VS = 5V
–30
250 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
FREQUENCY – MHz
–22
3.0
TPC 18. Return Loss (S22) of VOUT Output (TA = 25 °C)
TPC 15. Third Order Distortion and SSB POUT vs. Baseband Differential Input Level. (TA = 25 °C, FLO = 800 MHz,
LO level = –2 dBm, FBB = 1 MHz, VS = 5 V)
REV. 0
LOIN NO BALUN
OR TERMINATION
TPC 17. Smith Chart of LOIN Port S11 (LOIP Pin ACCoupled to Ground). Curves with Balun and External
Termination Resistors Also Shown. (VS = 5 V,
TA = 25 °C)
SSB OUTPUT POWER – dBm
THIRD ORDER DISTORTION – dBc
TPC 14. Third Order Distortion and SSB POUT vs. Baseband Differential Input Level. (TA = 25 °C, FLO = 800 MHz,
LO Level = –2 dBm, FBB = 1 MHz, VS = 2.7 V)
1GHz
–7–
AD8345
–150
The LO Interface generates two LO signals at 90 degrees of
phase difference with each other, to drive two mixers in quadrature. Baseband signals are converted into current form in the
Differential V-to-I Converters, feeding into the two mixers. The
outputs of the mixers are combined to feed the Differential-toSingle-Ended Converter, which provides a 50 Ω output interface.
Bias currents to each section are controlled by the Enable
(ENBL) signal. Detailed description of each section follows.
–151
NOISE FLOOR – dBm/Hz
–152
–153
–154
VS = 5V
–155
–156
LO Interface
–157
The LO Interface consists of interleaved stages of polyphase
phase-splitters and buffer amplifiers. The polyphase phase-splitter
contains resistors and capacitors connected in a circular manner
to split the LO signal into I and Q paths in precise quadrature with each other. The signal on each path goes through a
buffer amplifier to make up for the loss and high frequency
roll-off. The two signals then go through another polyphase
network to enhance the quadrature accuracy. The broad operating frequency range (250 MHz to 1000 MHz) is achieved
by staggering the RC time constants of each stage of the phasesplitters. The outputs of the second phase-splitter are fed into
the driver amplifiers for the mixers’ LO inputs.
–158
–159
–160
–10
–9
–8
–7
–6
–5 –4 –3 –2
LO LEVEL – dBm
–1
0
1
2
TPC 19. Noise Floor vs. LO Input Power. (TA = 25 °C, FLO =
800 MHz, VS = 5 V, All I and Q Inputs are DC-Biased to
0.7 V) Noise Measured at 20 MHz Offset from Carrier
–36
Differential V-to-I Converter
CARRIER FEEDTHROUGH – dBm
–38
In this circuit, each baseband input pin is connected to an op amp
driving a transistor connected as an emitter follower. A resistor
between the two emitters maintains a varying current proportional to the differential input voltage through the transistor. These
currents are fed to the two mixers in differential form.
–40
–42
VS = 5.5V
Mixers
–44
There are two double-balanced mixers, one for the In-phase
Channel (I-Channel) and one for the Quadrature Channel (QChannel). Each mixer uses the Gilbert-cell design with four
cross-connected transistors. The bases of the transistors are
driven by the LO signal of the corresponding channel. The
output currents from the two mixers are summed together in
two load resistors. The signal developed across the load resistors
is sent to the D-to-S stage.
–46
–48
–50
–10
–9
–8
–7
–6
–5 –4 –3 –2
LO LEVEL – dBm
–1
0
1
2
TPC 20. LO Feedthrough vs. LO Input Power. (TA = 25 °C,
LO = 800 MHz, VS = 5.5 V)
Differential to Single-Ended Converter
The differential-to-single-ended converter consists of two emitter followers driving a totem-pole output stage whose output
impedance is established by the emitter resistors in the output
transistors. The output of this stage is connected to the output
(VOUT) pin.
CIRCUIT DESCRIPTION
Overview
The AD8345 can be divided into the following sections: Local
Oscillator (LO) Interface, Mixer, Differential Voltage-to-Current (V-to-I) Converter, Differential-to-Single-Ended (D-to-S)
Converter, and Bias. A block diagram of the part is shown in
Figure 2.
LOIP
LOIN
Bias
A bandgap reference circuit based on the ∆-VBE principle generates the Proportional-To-Absolute-Temperature (PTAT) as
well as temperature-stable currents used by the different sections as references. When the bandgap reference is disabled by
pulling down the voltage at the ENBL pin, all other sections are
shut off accordingly.
PHASE
SPLITTER
IBBP
IBBN
⌺
OUT
QBBP
QBBN
Figure 2. AD8345 Block Diagram
–8–
REV. 0
AD8345
IP
AD8345
IN
C6
1000pF
5
LO
4
+VS
IBBP
QBBP 16
2
IBBN
QBBN 15
3
COM3
COM3 14
4
COM1
COM3 13
5
LOIN
VPS2 12
6
LOIP
VOUT 11
7
VPS1
COM2 10
8
ENBL
COM3 9
1
T1
ETC1-1-13
R1
50⍀
1
2
C7
1000pF
QP
QN
C1
1000pF
+VS
VOUT
3
C4
0.01␮F
C2
0.01␮F
C5
1000pF
C3
1000pF
Figure 3. Basic Connections
–5
BASIC CONNECTIONS
The basic connections for operating the AD8345 are shown in
Figure 3. A single power supply of between 2.7 V and 5.5 V is
applied to pins VPS1 and VPS2. A pair of ESD protection diodes
are connected internally between VPS1 and VPS2 so these must
be tied to the same potential. Both pins should be individually
decoupled using 1000 pF and 0.01 µF capacitors, located as
close as possible to the device. For normal operation, the enable
pin, ENBL, must be pulled high. The turn-on threshold for
ENBL is VS/2. Pins COM1 to COM3 should all be tied to the
same low impedance ground plane.
SIDEBAND SUPPRESSION – dBc
–10
LO Drive
In Figure 3, a 50 Ω resistor to ground combines with the device’s
high input impedance to provide an overall input impedance of
approximately 50 Ω (see TPC 17 for a plot of LO port input
impedance). For maximum LO suppression at the output, a
differential LO drive is recommended. In Figure 3, this is
achieved using a balun (M/A-COM Part Number ETC1-1-13).
The output of the balun is ac coupled to the LO inputs which
have a bias level about 1.8 V dc. An LO drive level of –2 dBm is
recommended for lowest output noise. Higher levels will degrade
linearity while lower levels will tend to increase the noise floor
slightly. For example, reducing the LO power from –2 dBm to
–10 dBm will increase the noise floor by approximately 0.3 dB
(see TPC 19).
The LO terminal can be driven single-ended at the expense of
slightly higher LO leakage. LOIN is ac coupled to ground using
a capacitor and LOIP is driven through a coupling capacitor
from a (single-ended) 50 Ω source (this scheme could also be
reversed with the drive signal being applied to LOIN).
LO Frequency Range
The frequency range on the LO input is limited by the internal
quadrature phase splitter. The phase splitter generates drive
signals for the internal mixers which are 90° out of phase relative
to one another. Outside of the specified LO frequency range of
250 MHz to 1 GHz, this quadrature accuracy degrades, resulting in decreased sideband suppression. See TPC 9 for a plot of
sideband suppression vs. LO frequency from 250 MHz to 1 GHz.
Figure 4 shows the sideband suppression of a typical device
from 50 MHz to 300 MHz. The level of sideband suppression
degradation below 250 MHz will be subject to manufacturing
process variations.
REV. 0
–15
VS = 5V, DIFFERENTIAL INPUT = 1.2V
–20
–25
–30
–35
–40
–45
–50
–55
–60
40
60
80 100 120 140 160 180 200 220 240 260 280 300
LO FREQUENCY – MHz
Figure 4. Typical Lower Frequency Sideband Suppression
Performance
Baseband I and Q Channel Drive
The I and Q channel baseband inputs should be driven differentially. This is convenient as most modern high-speed DACs
have differential outputs. For optimal performance at VS = 5 V,
the drive signal should be a 1.2 V p-p differential signal with a
bias level of 0.7 V; that is, each input should swing from 0.4 V
to 1 V. If the AD8345 is being run on a lower supply voltage,
the peak-to-peak voltage on the I and Q channel inputs must be
reduced to avoid input clipping. For example, at a supply voltage of 2.7 V, a 200 mV p-p differential drive is recommended.
This will result in a corresponding reduction in output power
(see TPC 1). The I and Q inputs have a large input bandwidth
of approximately 80 MHz. At lower baseband input levels, the
input bandwidth increases (see TPC 2).
If the baseband signal has a high peak-to-average ratio (e.g.,
CDMA or WCDMA), the rms signal strength will have to be
backed off from this peak level in order to prevent clipping of
the signal peaks. Clipping of signal peaks will tend to increase
signal leakage into adjacent channels. Backing off the I and Q
signal strength in the manner recommended will reduce the output
power by a corresponding amount. This also applies to multicarrier
applications where the per-carrier output power will be lower by
3 dB for each doubling of the number of output carriers.
–9–
AD8345
+5V
10k⍀
0.1␮F
1.5k⍀
10␮F
0.01␮F
348⍀
1000pF
1000pF
0.01␮F
348⍀
IIN
49.9⍀
0.1␮F
VPS1 VPS2
AD8132
IBBP
348⍀
IBBN
24.9⍀
⌺
348⍀
0.1␮F
10␮F
VOUT
LOIP
–5V
QBBP
PHASE
SPLITTER
LOIN
+5V
QBBN
0.1␮F
10␮F
348⍀
AD8345
COM1 COM2 COM3
348⍀
QIN
49.9⍀
0.1␮F
AD8132
348⍀
24.9⍀
348⍀
10␮F
0.1␮F
–5V
Figure 5. Single-Ended IQ Drive Circuit
Compensated LO leakage will degrade somewhat as the frequency
is moved away from the frequency at which the compensation
was performed. This is due to the effects of LO to RF output
leakage which are not a result of offsets on the I and Q inputs.
The I and Q inputs have high input impedances because they
connect directly to the bases of pnp transistors. If a (dc-coupled)
filter is being used between a DAC and the modulator inputs,
this filter will need to be terminated with the appropriate resistance. If the filter is differential, the termination resistor should
be connected across the I and Q differential inputs.
Single-Ended I and Q Drive
Reduction of LO Leakage
Because the I and Q signals are being effectively multiplied with
the LO, any internal offset voltages on these inputs will result in
leakage of the LO. The nominal LO leakage of –42 dBm which
results from these internal offset voltages, can be reduced further
by applying offset compensation voltages on the I and Q inputs.
(Note that LO feedthrough is reduced by varying the differential
offset voltages on the I and Q inputs, not by varying the nominal
bias level of 0.7 V.) This is easily accomplished by programming
(and then storing) the appropriate DAC offset code to reduce
the LO leakage. This does, however, require the path from the
DAC to the I and Q inputs to be dc-coupled. (DC-coupling is
also advantageous from the perspective of I and Q input biasing if the DAC is capable of delivering a bias level of 0.7 V).
The procedure for reducing the LO feedthrough is simple. In
order to isolate the LO in the output spectrum, a single sideband configuration is recommended (set I and Q signals to sine
and cosine waves at, say, 100 kHz, set LO to FRF – 100 kHz).
An offset voltage is applied from the I DAC until the LO leakage
reaches a trough. With this offset level held, an offset voltage is
applied to the Q DAC until a (lower) trough is reached.
LO leakage compensation holds up well over temperature. TPC
8 shows the effect of temperature on LO leakage after compensation at ambient.
Where only single-ended I and Q signals are available, a differential amplifier such as the AD8132 or AD8138 can be used to
generate the required differential drive signal for the AD8345.
Even though most DACs have differential outputs, using a
single-ended low-pass filter between the dual DAC and the I
and Q inputs, may be more desirable from the perspective of
component count and cost. As a result, the output signal from
the filter must be converted back to differential mode and possibly be rebiased to 0.7 V common mode.
Figure 5 shows a circuit which converts a ground-referenced,
single-ended signal to a differential signal and adds the required
0.7 V bias voltage. Two AD8132 differential op amps, configured for a gain of unity, are used. With a 50 Ω input impedance,
this circuit is configured to accept a signal from a 50 Ω source
(e.g., a low-pass filter). The input impedance can be easily changed
by replacing the 49.9 Ω shunt resistor (and the corresponding
24.9 Ω resistor on the inverting input) with the appropriate value.
The required dc-bias level is conveniently added to the signal by
applying 0.7 V to the VOCM pins of the differential amplifiers.
Differential amplifiers such as the AD8132 and AD8138 can
also be used to implement active filters. For more information
on this topic, consult the data sheets of these devices.
–10–
REV. 0
AD8345
DVDD
DCOM
AVDD
LATCH
“I”
“I”
DAC
2ⴛ
33pF
IOUTB
DAC
DATA
INPUTS
51⍀
AD9761
51⍀
SELECT
WRITE
QOUTB
SLEEP
FS ADJ
33pF
310nH
33pF
MUX
CONTROL
CLOCK
100⍀
⌺
IBBN
51⍀
51⍀
VOUT
LOIP
310nH
“Q”
DAC
2ⴛ
VPS2
IBBP
10⍀
QOUTA
LATCH
“Q”
VPS1
310nH
IOUTA
QBBP
100⍀
310nH
PHASE
SPLITTER
LOIN
33pF
QBBN
AD8345
REFIO
10⍀
RSET
2k⍀
0.1␮F
Figure 6. AD8345/TxDAC Interface
Note that this circuit assumes that the single-ended I and Q signals
are ground referenced. Any differential dc-offsets will result
in increased LO Leakage at the output of the AD8345.
positive full scale, IBBP will be equal to 0.96 V. With IOUTB
at 0 mA, the voltage at IBBN will be equal to 0.456 V. This
results in a full-scale differential signal of approximately 1 V p-p
which will have a common-mode level of 0.7 V.
It is possible to drive the baseband inputs with a single-ended
signal biased to 0.7 V, with the unused inputs being biased to a
dc level of 0.7 V. However, this mode of operation is not recommended because any dc level difference between the bias level of
the drive signal and the dc level on the unused input (including
the effect of temperature drift) will result in increased LO
leakage. In addition, the maximum output power will be reduced
by 6 dB.
The AD8345 is packaged in a 16-lead TSSOP package with
exposed pad. For optimum thermal conductivity, the exposed
pad can be soldered to the exposed metal of a ground plane.
This results in a junction-to-air thermal impedance (θJA) of
30°C/W. However, soldering is not necessary for safe operation.
If exposed pad is not soldered down, the θJA is equal to 95°C/W.
RF Output
Evaluation Board
The RF output is designed to drive a 50 Ω load but should be ac
coupled as shown in Figure 3. If the I and Q inputs are driven in
quadrature by 1.2 V p-p signals, the resulting output power will
be approximately –1 dBm (see TPC 1).
Figure 7. Shows the schematic of the AD8345 evaluation board.
Note that uninstalled components are marked as open. This is a
4-layer board, with the two center layers used as ground plane
and top and bottom layers used as signal and power planes.
The RF output impedance is very close to 50 Ω. As a result, no
additional matching circuitry is required if the output is driving
a 50 Ω load.
The board is powered by a single supply (VS) in the range, 2.7 V to
5.5 V. The power supply is decoupled by a 0.01 µF and 1000 pF
capacitors. The circuit closely follows the basic connection
schematic with SW1 in B Position. If SW1 is in Position A, the
Enable pin will be pulled to ground by a 10 kΩ resistor and the
device will be in its power-down mode.
Application with TxDAC
Figure 6 shows the AD8345 driven by the AD9761 TxDAC
(any of the devices in ADI’s TxDAC family can also be used in
this application). The signal from the DAC is being filtered by a
differential 51 MHz low-pass filter.
The I and Q DACs generate differential output currents of 0 mA
to 20 mA and 20 mA to 0 mA, respectively. When loaded with
50 Ω ground-referenced resistors, this would produce a 2 V p-p
differential signal (i.e., 1 V p-p on each output) with a commonmode level of 0.5 V. In the configuration shown, each DAC output
sees a composite load of 48 Ω (10 Ω + 51 Ω储(100 Ω + 51 Ω)) in
the passband. So, for example, when IOUTA is driven to its
REV. 0
Soldering Information
All connectors are SMA-type. The I and Q inputs are dc-coupled
to allow a direct connection to a dual DAC with differential
outputs. Resistor pads are provided in case termination at the
I and Q inputs is required. The local oscillator input (LO) is
terminated to approximately 50 Ω with an external 50 Ω resistor
to ground. A 1:1 wide-band transformer (ETC1-1-13) provides
a differential drive to the AD8345’s differential LO input. The
device can also be driven single-ended by shorting out T1.
–11–
AD8345
R1
(OPEN)
IP
IN
R9
(OPEN)
AD8345
1 IBBP
QBBP 16
2 IBBN
QBBN 15
QP
QN
R10
(OPEN)
R2
(OPEN)
3 COM3
COM3 14
4 COM1
COM3 13
5 LOIN
VPS2 12
6 LOIP
VOUT 11
R11
0⍀
C1
1000pF
5
LO
1
T1
ETC1-1-13
R6
50⍀
C2
1000pF
2
4
3
R7
0⍀
C3
0.01␮F
VPOS
R12
0⍀
C7
1000pF
VPOS
C6
0.01␮F
C5
1000pF
7 VPS1
COM2 10
8 ENBL
COM3 9
R14
(OPEN)
R15
(OPEN)
VOUT
C4
1000pF
A
ENBL
R8
10k⍀
B
SW1
VPOS
Figure 7. Evaluation Board Schematic
IP
QP
COMPONENT
SIDE
QN
TP 4
R6
R9
DUT
C7
C4
A
R 10
C5
R 12
TP 2
R 15
R1
R2
T1 C1
C2
R 14
IN
-
R8
L0
SW 1
ENBL
TP 1
B
TP 3
08-007084
REV A
VOUT
a
AD8345 EVAL BOARD
Figure 10. Layout of Evaluation Board, Bottom Layer
Figure 8. Evaluation Board Silkscreen
Figure 9. Layout of Evaluation Board, Top Layer
–12–
REV. 0
AD8345
IEEE
+15V MAX
D2
34901
34907
34907
D1
D2
D3
TEKAFG2020
INTERFACE
BOARD
+25V MAX
VN
–25V MAX
GND
VP
P1
HP3631
RFOUT
IEEE
IN
I_IN
OUTPUT_1
Q_IN
OUTPUT_2
IEEE
ARB FUNCTION GEN
IN
IP
HP8648C
D3
VPS1
COM
IEEE
HP34970A
D1
IP
QP QN
QP
QN
AD8345
CHARACTERIZATION
BOARD
LO
VOUT
ENBL
P1
HP8593E
SWEEP OUT
28V
RF I/P
SPECTRUM
ANALYZER
IEEE
IEEE
PC CONTROLLER
Figure 11. Characterization Board SSB Test Setup
CHARACTERIZATION SETUPS
SSB Setup
Modulated Waveform Setup
Essentially, two primary setups were used to characterize the
AD8345. These setups are shown in Figures 11 and 13. Figure
11 shows the setup used to evaluate the product as a Single
Sideband modulator. The interface board converts the singleended I and Q inputs from the arbitrary function generator to
differential inputs with a dc bias of approximately 0.7 V. The
interface board also provides connections for power supply
routing. The HP34970A and its associated plug-in 34901 were
used to monitor power supply currents and voltages being
supplied to the AD8345 characterization board. Two HP34907
plug-ins were used to provide additional miscellaneous dc and
control signals to the interface board. The LO input was driven
directly by an RF signal generator and the output was measured
directly with a spectrum analyzer. With the I Channel driven
with a sine wave and the Q Channel driven with a cosine wave,
the lower sideband is the single sideband output. The typical
SSB output spectrum is shown in Figure 12.
For evaluating the AD8345 with modulated waveforms, the
setup shown in Figure 13 was used. A Rohde & Schwarz
AMIQ signal generator with differential outputs was used to
generate the baseband signals. For all measurements the input
level on each baseband input pin was 0.7 V ± 0.3 V peak. The
output was measured with a Rohde & Schwarz FSIQ spectrum/vector analyzer.
PC CONTROL
AMIQ
IN
IP
QP
IP
QP
QN
IEEE
PC CONTROLLER
HP8648C
IEEE
IN
AD8345
QN
CHARACTERIZATION
BOARD
LO
ENBL
VOUT
RFOUT
P1
FSIQ
RF I/P
IEEE
SPECTRUM
ANALYZER
0
+15V MAX
–10
COM
AMPLITUDE – dBm
–20
IEEE
–25V MAX
–30
HP3631
–40
Figure 13. Test Setup for Evaluating AD8345 with Modulated
Waveforms
–50
–60
–70
–80
–90
–100
CENTER = 900MHz
SPAN = 1MHz
Figure 12. Typical SSB Output Spectrum
REV. 0
+25V MAX
–13–
AD8345
CDMA IS95
–10
For measuring ACPR, the I and Q input signals used were
generated with Pilot (Walsh Code 00), Sync (WC 32), Paging
(WC 01), and 6 Traffic (WC 08, 09, 10, 11, 12, 13) channels
active. Figure 14 shows the typical output spectrum for this
configuration.
AMPLITUDE – dBm
–30
For performing EVM, Rho, phase, and amplitude balance measurements, the I and Q input signals used were generated with
only the Pilot Channel (Walsh Code 00) active.
–10
–40
–50
–60
–70
–80
–90
–20
CH PWR = –12.41dBm
ACP UP = –72.8dB
ACP LOW = –72.8dB
–30
AMPLITUDE – dBm
CH PWR = –10.95dBm
ACP UP = –52.51dB
ACP LOW = –52.41dB
–20
–100
–110
CENTER = 380MHz
–40
SPAN = 14.7MHz
–50
Figure 15. Typical AD8345 WCDMA 3GPP Output Spectrum
–60
GSM
–70
–80
–90
–100
–110
CENTER = 880MHz
SPAN = 7.5MHz
For comparing the AD8345 output to the GSM transmit mask I
and Q signals were generated using MSK modulation, GSM
differential coding, a Gaussian filter and a symbol rate of
270.833 kHz. The transmit mask was manually generated on
the FSIQ using the GSM BTS specification for reference. The
plot in Figure 16 shows that the AD8345 meets the GSM transmit mask requirements.
Figure 14. Typical IS95 Output Spectrum
0
WCDMA 3GPP
–10
For evaluating the AD8345 for WCDMA, the 3GPP standard
was used with a Chip Rate of 3.84 MHz. The plot in Figure 15
is an ACPR plot of the AD8345 using “Test Model 1” from the
3GPP specification with 64 channels active.
AMPLITUDE – dBm
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER = 900MHz
SPAN = 1MHz
Figure 16. Typical AD8345 GSM Output Spectrum
–14–
REV. 0
AD8345
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead HTSSOP with Exposed Pad
(RE-16)
0.201 (5.10)
0.193 (4.90)
16
0.118 (3.0)
SQ
9
0.177 (4.50)
0.169 (4.30)
EXPOSED
PAD
1
0.256 (6.50)
0.246 (6.25)
8
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. 0
0.0433 (1.10)
MAX
8ⴗ
0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0ⴗ
BSC
0.0075 (0.19) 0.0035 (0.090)
–15–
0.028 (0.70)
0.020 (0.50)
–16–
PRINTED IN U.S.A.
C00932–1.5–7/01(0)