Mitsubishi M64893GP Serial input pll frequency synthesizer for tv/vcr Datasheet

MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M64893 is a semiconductor integrated circuit consisting of
PLL frequency synthesizer for TV/VCR using Bip process. It
contains the prescaler with operating up to 1.3GHz, 4 band drivers
PRESCALER
INPUT
and Op. Amp for direct tuning.
•
4 integrated PNP band drivers
(Io=40mA,Vsat=0.2V typ@Vcc1 to 13.2V)
•
•
•
•
Built-in Op. Amp for direct tuning voltage output (33V)
Low power dissipation (Icc=20mA, Vcc1=5V)
Built-in prescaler with input amplifier (Fmax=1.3GHz)
PLL lock/unlock status display out put
(Built-in pull up resistor )
X’tal 4MHz is used to realize 1 type of tuning steps
(Division ratio 1/640)
Serial data input. (3 wire bus )
Built-in Power on reset system
Small package (SOP/SSOP)
•
•
•
•
14 DATA
13 CLK
CLOCK INPUT
1
16 Xin
GND
GND
2
15 ENA
SUPPLY
VOLTAGE 1
SUPPLY
VOLTAGE 2
VCC1
3
VCC2
4
BS4
5
BS3
6
BS2
7
BS1
8
BAND
SWITCHING
OUTPUTS
M64893FP/GP
FEATURES
CRYSTAL
OSCILLATOR
ENABLE
INPUT
DATA INPUT
fin
12 LD/ftest LD/ftest
OUTPUT
SUPPLY
11 VCC3
VOLTAGE 3
TUNING
10 Vtu
OUTPUT
9 Vin
FILTER INPUT
Outline 16P2S-A (FP)
16P2Z-A (GP)
APPLICATION
TV, VCR tuners
FUNCTION
RECOMMENDED OPERATING CONDITION
Supply voltage range..............................................V CC1=4.5 to 5.5V
VCC2=VCC1 to 13.2V
VCC3=28 to 35V
Rated supply voltage...........................................................V CC1=5V
VCC2=12V
VCC3=33V
1
•
•
•
•
•
•
•
2-modulus prescaler (1/32 and 1/33)
Built-in 4MHz crystal oscillator and reference divider
Programmable divider (10-bit M counter, 5-bit S counter)
Tri-state phase comparator
Lock detector
Band switch driver
Op. Amp for direct tuning
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
BLOCK DIAGRAM
CRYSTAL
OSCILLATOR
ENABLE
INPUT
DATA INPUT
CLOCK
INPUT
LD/ftest
OUTPUT
X in
ENA
DATA
CLK
LD/ftest
16
15
14
13
12
19-BIT SHIFT
REGISTER LATCH
OSC
SUPPLY
VOLTAGE 3
TUNING
OUTPUT
FILTER
INPUT
VCC3
Vtu
Vin
11
10
9
VCC1
DIVIDER
10
10-BIT M COUNTER
LOCK
DETECTOR
AMP
PHASE
DETECTOR
CHARGE
PUMP
1/32,1/33
5
5-BIT S COUNTER
4
P.O
RESET
1/8
BAND DRIVER
BIAS
AMP
1
2
3
4
5
6
7
8
f in
GND
VCC1
VCC2
BS4
BS3
BS2
BS1
SUPPLY
VOLTAGE 1
SUPPLY
VOLTAGE 2
PRESCALER
INPUT
BAND SWITCHING
OUTPUTS
2
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
DESCRIPTION OF PIN
Pin No.
1
2
3
4
5
6
7
8
Symbol
fin
GND
VCC1
VCC2
BS4
BS3
BS2
BS1
Pin name
Prescaler input
GND
Input for the VCO frequency.
Ground to 0V.
Function
Power supply voltage 1
Power supply voltage 2
Power supply voltage terminal. 5.0V ±0.5V
Power supply for band switching, Vcc 1 to 13.2V
Band switching outputs
PNP open collector method is used.
When the band switching data is "H", the output is ON.
When it is "L", the output is OFF.
9
Vin
Filter input
(Charge pump output)
10
11
Vtu
VCC3
Tuning output
Power supply voltage 3
12
LD/ftest
Lock detect/Test port
13
14
CLK
DATA
Clock input
Data input
15
ENA
Enable input
This is the output terminal for the LPF input and charge pump output. When the
phase of the programmable divider output (f 1/N) is ahead compared to the
reference frequency (fref), the "source" current state becomes active.
If it is behind, the "sink" current becomes active.
If the phases are the same, the high impedance state becomes active.
This supplies the tuning voltage.
Power supply voltage for tuning voltage 28 to 35V
When 19 bit data is input,lock detector is output.
When 27 bit data is input, lock detector is output, the programmable freq.
Divider output and reference freq.
Output is selected by the test mode.
Data is read into the shift register when the clock signal falls.
Input for band SW and programmable freq. divider set up.
This is normally at a "L". When this is at "H", data and clock signals are received.
Data is read into the latch when the 19th pulse of the clock signal falls.
16
Xin
This is connected to the
crystal oscillator
4.0MHz crystal oscillator is connected.
ABSOLUTE MAXIMUM RATINGS (Ta=-20°C to +75°C, unless otherwise noted)
Symbol
VCC1
VCC2
VCC3
VI
VO
VBSOFF
IBSON
Parameter
Supply voltage 1
Supply voltage 2
Supply voltage 3
Input voltage
Output voltage
Voltage applied when the band output is
OFF
Band output current
tBSON
ON the time when the band output is ON
Pd
Topr
Tstg
Power dissipation
Operating temperature
Storage temperature
Conditions
Pin3
Pin4
Pin11
Not to exceed VCC1
LD output
Per 1 band output circuit
50mA per 1 band output circuit
3circuit are pn at same time
Ta=+75°C
Ratings
6.0
14.4
36.0
6.0
6.0
Unit
V
V
V
V
V
14.4
V
50.0
mA
10
sec
470
-20 to +75
-40 to +125
mW
°C
°C
Ratings
4.5 to 5.5
VCC1 to 13.2
28 to 35
4.0
80 to 1,300
Unit
V
V
V
MHz
MHz
0 to 40
mA
RECOMMENDED OPERATING CONDITIONS (Ta=-20°C to +75°C, unless otherwise noted)
3
Symbol
VCC1
VCC2
VCC3
fopr1
fopr2
Parameter
Supply voltage 1
Supply voltage 2
Supply voltage 3
Operating frequency (1)
Operating frequency (2)
IBDL
Band output current 5 to 8
Conditions
Pin3
Pin4
Pin11
Crystal oscillation circuit
Normally 1 circuit is on. 2 circuits on at the
same time is max. It is prohibited to have
3 or more circuits turned on at the same time.
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
ELECTRICAL CHARACTERISTICS (Ta=-20°C to +75°C, Vcc1=5.0V, Vcc2=12V, Vcc3=33V, unless otherwise noted)
Symbol
VIH
VIL
IIH
IIL
IIL
VOH
VOL
VBS
IOLK2
VTOH
VTOL
ICPH
ICPL
ICPLK
ICC1
ICC2A
ICC2B
ICC2C
ICC3
Input pin
Lock
output
Band
SW
Tuning
output
Charge
pump
Limits
Typ.
3.0
−
−
−
−
5.0
−
11.6
−
32.5
−
−
−
−
VCC1+0.3
−
−
1.5
−
10
-6
-10
-18
-30
−
−
0.3
0.5
11.8
−
−
-10
−
−
0.2
0.4
±270
±370
±70
±110
−
±50
Test pin
“H” input voltage
“L” input voltage
“H” input current
“L” input current
“L” input current
“H” output voltage
13 to 15
13 to 15
13 to 15
13, 15
14
12
“L” output voltage
Output voltage
Leak current
12
5 to 8
5 to 8
Output voltage “H”
Output voltage “L”
“H” output current
10
10
9
“L” output current
Leak current
9
9
VCC1=5.5V, Vi=4.0V
VCC1=5.5V, Vi=0.4V
VCC1=5.5V, Vi=0.4V
VCC1=5.5V
VCC1=5.5V
VCC2=12V, Io=-40mA
VCC2=12V band SW is OFF
VCC3=33V
VCC3=33V
VCC1=5.0V, Vo=1V
VCC1=5.0V, Vo=1V
VCC1=5.0V, Vo=2.5V
3
4
VCC1=5.5V
VCC2=12V
−
−
20
−
30
0.3
mA
mA
4
VCC2=12V
−
6.0
8.0
mA
4
11
VCC2=12V Io=-40mA
VCC3=33V Output ON
−
−
46.0
3.0
48.0
4.0
mA
mA
Supply current 1
4 circuits: OFF
Supply
1 circuits: ON,
current 2 Output: OPEN
Output current 40mA
Supply current 3
Test conditions
Min.
Parameter
Max.
Unit
V
V
µA
µA
µA
V
V
V
µA
V
V
µA
µA
nA
Note. Typical values are measured at VCC1=5.0V, VCC2=12V, VCC3=33V, Ta=+25°C.
SWITCHING CHARACTERISTICS (Ta=-20°C to +75°C, VCC1=5.0V, VCC2=12V, VCC3=33V, unless otherwise noted)
Symbol
fopr2
Parameter
Prescaler operating frequency
Vin
Operating input voltage
tPWC
Clock pulse width
Data setup time
Data hold time
Enable setup time
Enable hold time
Enable data interval time
Rise time
Fall time
Next enable prohibit time
Next clock prohibit time
tSU (D)
tH (D)
tSU (E)
tH (E)
tINT
tr
tf
tbt
tbcl
Test pin
1
1
13
14
14
15
15
15, 14
Test conditions
VCC1=4.5 to 5.5V
Vin=Vinmin to Vinmax
80 to 100MHz
100 to 200MHz
VCC1=4.5
200 to 800MHz
to 5.5V
800 to 1000MHz
1000 to 1300MHz
VCC1=4.5 to 5.5V
VCC1=4.5 to 5.5V
VCC1=4.5 to 5.5V
VCC1=4.5 to 5.5V
VCC1=4.5 to 5.5V
VCC1=4.5 to 5.5V
13, 14, 15 VCC1=4.5 to 5.5V
13, 14, 15 VCC1=4.5 to 5.5V
15
VCC1=4.5 to 5.5V
13, 15 VCC1=4.5 to 5.5V
Min.
Limits
Typ.
Max.
80
−
1300
MHz
-24
-27
-30
-27
-18
−
−
−
−
−
4
4
4
4
4
dBm
1
2
1
3
3
1
−
−
5
5
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
−
−
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
4
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
METHOD OF SETTING DATA
The frequency demultiplying ratio uses 15bits. Setting up the band
the 19th pulse of the clock signal. When the enable signal goes to
switching output uses 4bits.
"L" before the 19th pulse of the enable signal, only the band SW
The test mode data uses 8bits. The total bits used is 27bits. Data is
data is updated and other data is ignored.
read in when the enable signal is "H" and the clock signal falls.
The data is latched at the 19th pulse of the clock signal. At this time,
The band switching data is read in at the 4th pulse of the clock
1/640 frequency division ratio is used. Clock signals after the above
signal. The program counter data is read into the latch by the fall of
are invalid.
ENA
BS4
BS3
BS2
BS1
DATA
29
28
27
26
25
24
23
22
21
20
24
23
22
21
20
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
S4
S3
S2
S1
S0
CLK
BAND SW
DATA
M COUNTER DIVISION
RATIO SETTING
S COUNTER DIVISION
RATIO SETTING
READ INTO LATCH
READ INTO LATCH
HOW TO SET THE DIVIDING RATIO OF THE
PROGRAMMABLE DIVIDER
Total division N is given by the following formulas in addition to the
Therefore, the range of division N is 8,192 to 262,136.
prescaler used in the previous stage.
The tuning frequency fVCO is given in the following equations.
N=8 (32M+S) M: 10 bit main counter division
fVCO =fREF×N
S: 5 bit swallow counter division
The M and S counters are binary the possible ranges of division
=6.25×8×(32M+S)
=50.0×(32M+S)
[kHz]
are as follows.
But, the tuning frequency range is 51.2MHz to 1300MHz from the
32≤M≤1023
maximum prescaler operating frequency.
0≤S≤31
TEST MODE DATA SET UP METHOD
The data for the test mode uses 20 to 27bits. Data is latched when
the 27th clock signal falls.
(1) When transferring 3-wire 27 bit data
ENA
1
19
20
27
SI
CP T2 T1 T0 RSa RSb OS
TEST DATA SETTING
CLK
BAND SW
DATA
M COUNTER DIVISION
RATIO SETTING
S COUNTER
DIVISION
RATIO SETTING
READ INTO LATCH
5
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
(2) Test-mode bit setting
Set up for the reference frequency division ratio
X
:Random, 0 or 1.normal "0"
CP
:Set up the charge pump current value
RSa
1
0
X
T0, T1, and T2 :Set up test modes
RSa, RSb
:Set the frequency division of the standard
RSb
1
1
0
Division ratio
1/512
1/1024
1/640
frequency
OS
:Set up the tuning amplifier
SI
:1 Only (It is prohibit to "0 ")
Set up the tuning amplifier
OS
0
1
Setting up the charge pump current of the phase comparator
CP
0
1
Charge pump current
70µA
270µA
Mode
Test
Normal
0
1
1
1
1
Mode
Normal
Test
POWER ON RESET OPERATION
(Initial state the power is turned ON)
Setting up for the test mode
T2 T1 T0 Charge pump
0 0 X Normal operation
Tuning voltage output
ON
OFF
12 pin output
LD
LD
LD
LD
fREF
f1/N
1 X High impedance
1 0 Sink
1 1 Source
0 0 High impedance
0 1 High impedance
Mode
Normal operation
Test mode
Test mode
Test mode
Test mode
Test mode
BS4 to BS1
: OFF
Charge pump
: High impedance
Tuning amplifier
: OFF
Charge pump current
: 270µA
Frequency divider ratio
: 1/640
Lock detect
: “H”
TIMING DIAGRAM
tr
tf
90%
1.5V
ENABLE
10%
10%
tINT
tINT
90%
1.5V
DATA
VIH
90%
10%
VIL
tBT
VIH
90%
10%
VIL
tr
1.5V
VIH
90%
90%
CLOCK
tf
10%
10%
VIL
tPWC
tSU(D)
tr
tH(D)
tf
tH(E)
tBCL
tSU(E)
CRYSTAL OSCILLATOR CONNECTION DIAGRAM
16
18pF
4MHz
Crystal oscillator characteristics
Actual resistance: less than 300Ω
Load capacitance : 20pF
6
MITSUBISHI ICS (TV)
M64893FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
APPLICATION EXAMPLE
BUILT-IN PLL TUNER
+5V
1000p
-
10µ
Vcc1 to 12V
3
5
18
SW
Vcc2
M64893FP/GP
UHF
VHF
-
+B
4
47k
BS4 11
BS4
5
47k
BS3 12
IF
BS3
IF
6
1 TEST
47k
BS2 13
BS2
M5493X
series
3 DATA
7
47k
BS1 14
14
BS1
8
1000p
fIN 17
MCU
4-BAND
TUNER
4 CLK
GND 16
13
Lo
AGC
15
2 EN
0.1µ
10
15
VT
9
XIN
XOUT
GND
6
7
8
+5V
16
2.2n
100p ∗
11
18p
4MHz
56k
10
9
12
56k
AFT
PD
20 LD/f1/N
AGC
1.5n
1000pF
-
+33V
Note) Filter constant is
for reference.
∗ Add a capacitor to stabilize
the circuit.
BT
Units Resistance : Ω
Capacitance : F
7
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