CY62167DV30 MoBL® 16-Mbit (1M x 16) Static RAM Features also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH and WE LOW). • TSOP I Configurable as 1M x 16 or as 2M x 8 SRAM • Very high speed: 45 ns • Wide voltage range: 2.2V – 3.6V • Ultra-low active power — Typical active current: 2 mA @ f = 1 MHz — Typical active current: 18.5 mA @ f = fMax (45 ns speed) Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). • Ultra-low standby power • Easy memory expansion with CE1, CE2 and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in Pb-free and non Pb-free 48-ball VFBGA and 48-pin TSOP I package Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. Functional Description[1] The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device Logic Block Diagram 1M × 16 / 2M x 8 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BYTE A11 A12 A13 A14 A15 A16 A17 A18 A19 BHE WE CE2 CE1 OE BLE Power-Down Circuit BHE BLE CE2 CE1 Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05328 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 27, 2006 [+] Feedback CY62167DV30 MoBL® Product Portfolio Power Dissipation Operating ICC(mA) VCC Range (V) Product CY62167DV30LL Min. Typ.[2] Max. Speed (ns) 2.2 3.0 3.6 45 f = 1MHz f = fMax Standby ISB2(µA) Typ.[2] Max. Typ.[2] Max. Typ.[2] Max. 2 4 18.5 37 2.5 22 55 15 30 70 12 25 Pin Configuration[3, 4, 5] 48-ball VFBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 DNU H 48-Pin TSOP I (Forward) (1M x 16/ 2M x 8)[6] Top View A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 DNU BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss I/O15/A20 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0 Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 3. NC pins are not connected on the die. 4. DNU pins have to be left floating. 5. Ball H6 for the FBGA package can be used to upgrade to a 32M density. 6. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOPI package can also be used as a 2M X 8 SRAM by tying the BYTE signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used (DNU). Document #: 38-05328 Rev. *G Page 2 of 12 [+] Feedback CY62167DV30 MoBL® Maximum Ratings Output Current into Outputs (LOW) .............................20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................–65°C to +150°C Ambient Temperature with Power Applied .............................................–55°C to +125°C Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .....................................................> 200 mA Operating Range Supply Voltage to Ground Potential ...... –0.2V to VCC + 0.3V Device DC Voltage Applied to Outputs in High-Z State[7, 8] ................................ –0.2V to VCC + 0.3V Ambient Temperature Range CY62167DV30LL Industrial –40°C to +85°C VCC[9] 2.20V to 3.60V DC Input Voltage[7, 8] ............................. –0.2V to VCC + 0.3V Electrical Characteristics Over the Operating Range CY62167DV30-45 CY62167DV30-55 CY62167DV30-70 Parameter Description VOH VOL VIH VIL Output HIGH Voltage Output LOW Voltage Test Conditions Min. Typ.[2] Max. Min. Typ.[2] Max. Min. Typ.[2] Max. Unit IOH = –0.1 mA VCC = 2.20V 2.0 2.0 2.0 IOH = –1.0 mA VCC = 2.70V 2.4 2.4 2.4 IOL = 0.1 mA VCC = 2.20V IOL = 2.1mA VCC = 2.70V 0.4 Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC= 2.7V to 3.6V 2.2 Input LOW Voltage VCC = 2.2V to 2.7V –0.3 0.4 VCC 1.8 +0.3V 2.2 0.6 VCC= 2.7V to 3.6V V VCC 1.8 +0.3V 2.2 –0.3 0.6 0.8 –0.3 0.8 0.4 V VCC +0.3V V 0.6 V 0.8 –1 +1 –1 +1 –1 +1 µA GND < VO < VCC, Output Disabled –1 +1 –1 +1 –1 +1 µA mA IIX Input Leakage GND < VI < VCC Current IOZ Output Leakage Current ICC VCC Operating VCC = VCC(max) IOUT = 0 mA Supply CMOS levels Current f = fMax = 1/tRC f = 1 MHz 18.5 37 15 30 12 25 2 4 2 4 2 4 ISB1 Automatic CE Power-down Current — CMOS Inputs CE1 > VCC − 0.2V or CE2 < 0.2V VIN > VCC – 0.2V, VIN < 0.2V, f = fMax (Address and Data Only), f = 0 (OE, WE, BHE, BLE), VCC = 3.60V 2.5 22 2.5 22 2.5 22 µA ISB2 Automatic CE Power-down Current — CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V 2.5 22 2.5 22 2.5 22 µA Notes: 7. VIL(min.) = –2.0V for pulse durations less than 20 ns. 8. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 9. Full Device AC operation requires linear VCC ramp from 0 to VCC(min.) and VCC must be stable at VCC(min) for 500 µs. Document #: 38-05328 Rev. *G Page 3 of 12 [+] Feedback CY62167DV30 MoBL® Capacitance[10, 11] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 8 pF 10 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance[10] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, 2-layer printed circuit board VFBGA TSOP I Unit 55 60 °C/W 16 4.3 °C/W AC Test Loads and Waveforms[12] R1 VCC OUTPUT ALL INPUT PULSES VCC 90% 10% 50 pF[12] GND Rise Time = 1 V/ns R2 90% 10% Fall Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters 2.5V 3.0V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[10] Chip Deselect to Data Retention Time tR[13] Operation Recovery Time Conditions Min. Typ.[2] Max. 1.5 VCC= 1.5V CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Unit V 10 µA 0 ns tRC ns Notes: 10. Tested initially and after any design or process changes that may affect these parameters. 11. This applies for all packages. 12. Test condition for the 45 ns part is with a load capacitance of 30 pF. 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. Document #: 38-05328 Rev. *G Page 4 of 12 [+] Feedback CY62167DV30 MoBL® Data Retention Waveform[14] VCC DATA RETENTION MODE VDR > 1.5 V VCC, min. tCDR CE1 or VCC, min. tR BHE,BLE or CE2 Switching Characteristics Over the Operating Range[15] 45 ns [12] Parameter Description Min. Max. 55 ns Min. Max. 70 ns Min. Max. Unit Read Cycle tRC Read Cycle Time 45 tAA Address to Data Valid tOHA Data Hold from Address Change 55 45 10 70 55 10 ns 70 10 ns ns tACE CE1 LOW and CE2 HIGH to Data Valid 45 55 70 ns tDOE OE LOW to Data Valid 25 25 35 ns tLZOE OE LOW to LOW Z[16] OE HIGH to High tHZOE 5 Z[16, 17] 15 Z[16] tLZCE CE1 LOW and CE2 HIGH to Low tHZCE CE1 HIGH and CE2 LOW to High Z[16, 17] tPU CE1 LOW and CE2 HIGH to Power-up tPD CE1 HIGH and CE2 LOW to Power-down tDBE BLE/BHE LOW to Data Valid tLZBE BLE/BHE LOW to Low Z[16] tHZBE BLE/BHE HIGH to HIGH Z[16, 17] Write Cycle 5 10 5 20 10 20 0 0 25 ns ns ns 70 55 10 15 ns 0 55 45 10 25 10 20 45 ns 70 10 20 ns ns ns 25 ns [18] tWC Write Cycle Time 45 55 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 40 40 60 ns tAW Address Set-Up to Write End 40 40 60 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 35 40 45 ns tBW BLE/BHE LOW to Write End 40 40 60 ns tSD Data Set-Up to Write End 25 25 30 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High-Z[16, 17] tLZWE WE HIGH to Low-Z[16] 0 15 10 0 20 10 ns 25 10 ns ns Notes: 14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 15. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 18. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write. Document #: 38-05328 Rev. *G Page 5 of 12 [+] Feedback CY62167DV30 MoBL® Switching Waveforms Read Cycle 1 (Address Transition Controlled)[19, 20] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle 2 (OE Controlled)[20, 21] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tLZBE OE tDBE tHZBE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes: 19. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 20. WE is HIGH for read cycle. 21. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05328 Rev. *G Page 6 of 12 [+] Feedback CY62167DV30 MoBL® Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[18, 22, 23, 24] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA See Note 23 tHZOE Notes: 22. Data I/O is high-impedance if OE = VIH. 23. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 24. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05328 Rev. *G Page 7 of 12 [+] Feedback CY62167DV30 MoBL® Switching Waveforms (continued) Write Cycle 2 (CE1 or CE2 Controlled)[18, 22, 23, 24] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA See Note 23 tHZOE Write Cycle 3 (WE Controlled, OE LOW)[23, 24] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW WE tSA tHA tPWE tSD DATA I/O See Note 23 VALID DATA tHZWE Document #: 38-05328 Rev. *G tHD tLZWE Page 8 of 12 [+] Feedback CY62167DV30 MoBL® Switching Waveforms (continued) Write Cycle 4 (BHE/BLE Controlled, OE LOW)[23, 24] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD See Note 23 DATA I/O tHD VALID DATA Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X X X X X L H H L H L Mode Power High Z Deselect/Power-Down Standby (ISB) X High Z Deselect/Power-Down Standby (ISB) H H High Z Deselect/Power-Down Standby (ISB) L L L Data Out (I/O0–I/O15) Read Active (ICC) H L H L High Z (I/O8–I/O15); Data Out (I/O0–I/O7) Read Active (ICC) H H L L H Data Out (I/O8–I/O15); High Z (I/O0–I/O7) Read Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L High Z (I/O8–I/O15); Data In (I/O0–I/O7) Write Active (ICC) L H L X L H Data In (I/O8–I/O15); High Z (I/O0–I/O7) Write Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) Document #: 38-05328 Rev. *G Inputs/Outputs Page 9 of 12 [+] Feedback CY62167DV30 MoBL® Ordering Information Speed (ns) 45 55 Ordering Code CY62167DV30LL-45ZXI CY62167DV30LL-55BVI CY62167DV30LL-55BVXI CY62167DV30LL-55ZI CY62167DV30LL-55ZXI CY62167DV30LL-70BVI 70 Package Package Type Diagram 51-85183 48-pin TSOP I (12 x 18.4 x 1 mm) (Pb-free) 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) (Pb-free) 51-85183 48-pin TSOP I (12 x 18.4 x 1 mm) 48-pin TSOP I (12 x 18.4 x 1 mm) (Pb-free) 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts Package Diagrams 48-ball VFBGA (8 x 9.5 x 1 mm) (51-85178) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 9.50±0.10 9.50±0.10 1 F G H H A 1.875 A B 0.75 8.00±0.10 B 0.10 C 0.21±0.05 0.25 C 0.55 MAX. 3.75 8.00±0.10 0.15(4X) 1.00 MAX 0.26 MAX. SEATING PLANE C 51-85178-** Document #: 38-05328 Rev. *G Page 10 of 12 [+] Feedback CY62167DV30 MoBL® Package Diagrams (continued) 48-pin TSOP I (12 x 18.4 x 1mm) (51-85183) DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] N 1 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.002[0.05] 0.006[0.15] 0.724 [18.40] 0.047[1.20] MAX. SEATING PLANE 0.004[0.10] 0.787[20.00] 0.004[0.10] 0.008[0.21] 0.010[0.25] GAUGE PLANE 0°-5° 0.020[0.50] 0.028[0.70] 51-85183-*A MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05328 Rev. *G Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62167DV30 MoBL® Document History Page Document Title: CY62167DV30 MoBL®, 16-Mbit (1M x 16) Static RAM Document Number: 38-05328 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 118408 09/30/02 GUG New Data Sheet *A 123692 02/11/03 DPM Changed Advanced to Preliminary Added package diagram *B 126555 04/25/03 DPM Minor change: Changed Sunset Owner from DPM to HRT *C 127841 09/10/03 XRJ Added 48 TSOP I package *D 205701 AJU Changed BYTE pin usage description for 48 TSOPI package *E 238050 See ECN *F 304054 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #12 on page #4 Added Pb-free packages on page # 10 *G 492895 See ECN VKN Modified datasheet to explain x8 configurability Removed L power bin from the product offering Updated Ordering Information Table Document #: 38-05328 Rev. *G KKV/AJU Replaced 48-ball VFBGA package diagram; Modified Package Name in Ordering Information table from BV48A to BV48B Page 12 of 12 [+] Feedback