Cypress CY7C1364C-250AXI 9-mbit (256k x 32) pipelined sync sram Datasheet

CY7C1364C
9-Mbit (256K x 32) Pipelined Sync SRAM
Functional Description[1]
Features
• Registered inputs and outputs for pipelined operation
• 256K × 32 common I/O architecture
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
The CY7C1364C SRAM integrates 256K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• “ZZ” Sleep Mode Option
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1364C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram-CY7C1364C (256K x 32)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
Q0
LOGIC
ADSC
ADSP
BWD
DQD
BYTE
WRITE REGISTER
DQD
BYTE
WRITE DRIVER
BWC
DQC
BYTE
WRITE REGISTER
DQC
BYTE
WRITE DRIVER
DQB
BYTE
WRITE REGISTER
DQB
BYTE
WRITE DRIVER
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQA
BYTE
WRITE DRIVER
DQA
BYTE
WRITE REGISTER
ENABLE
REGISTER
MEMORY
ARRAY
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE3 is not available on 2 Chip Enable TQFP package.
Cypress Semiconductor Corporation
Document #: 38-05689 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 14, 2006
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CY7C1364C
Selection Guide
250 MHz
200 MHz
166 MHz
Unit
Maximum Access Time
2.8
3.0
3.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
40
40
40
mA
Pin Configuration
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
A
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP Pinout (2 Chip Enables) (AJ version)
BYTE C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1364C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
BYTE B
BYTE A
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE D
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
Document #: 38-05689 Rev. *E
Page 2 of 18
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CY7C1364C
Pin Configuration (continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP Pinout (3 Chip Enables) (A version)
BYTE C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1364C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
BYTE B
BYTE A
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE D
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
Document #: 38-05689 Rev. *E
Page 3 of 18
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CY7C1364C
Pin Definitions
Name
TQFP
I/O
Description
37, 36, 32, 33, 34, 35, 43,
44, 45, 46, 47, 48, 49, 50,
81, 82, 99, 100
InputAddress Inputs used to select one of the 256K address locations.
Synchronous Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW,
and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
93, 94, 95, 96
InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct
Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK.
GW
88
InputGlobal Write Enable Input, active LOW. When asserted LOW on the
Synchronous rising edge of CLK, a global Write is conducted (ALL bytes are written,
regardless of the values on BW[A:D] and BWE).
BWE
87
InputByte Write Enable Input, active LOW. Sampled on the rising edge of
Synchronous CLK. This signal must be asserted LOW to conduct a Byte Write.
CLK
89
CE1
98
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE2 and CE3 to select/deselect the device.
ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new
external address is loaded.
CE2
97
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE1 and CE3 to select/deselect the device.
CE2 is sampled only when a new external address is loaded.
A0, A1, A
BWA, BWB
BWC, BWD
CE3
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV is asserted LOW, during
a burst operation.
92
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
(for 3 Chip Enable Version) Synchronous Used in conjunction with CE1 and CE2 to select/deselect the
device.CE3 is assumed active throughout this document for BGA. CE3
is sampled only when a new external address is loaded.
OE
86
InputOutput Enable, asynchronous input, active LOW. Controls the
Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a Read cycle when emerging
from a deselected state.
ADV
83
InputAdvance Input signal, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted, it automatically increments the address in a burst
cycle.
ADSP
84
InputAddress Strobe from Processor, sampled on the rising edge of
Synchronous CLK, active LOW. When asserted LOW, A is captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored
when CE1 is deasserted HIGH.
ADSC
85
InputAddress Strobe from Controller, sampled on the rising edge of
Synchronous CLK, active LOW. When asserted LOW, A is captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
64
InputZZ “sleep” Input, active HIGH. This input, when High places the
Asynchronous device in a non-time-critical “sleep” condition with data integrity
preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
DQs
52, 53, 56, 57, 58, 59, 62,
63, 68, 69, 72, 73, 74, 75,
78, 79, 2, 3, 6, 7, 8, 9, 12,
13, 18, 19, 22, 23, 24, 25,
28, 29
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data
Synchronous register that is triggered by the rising edge of CLK. As outputs, they
deliver the data contained in the memory location specified by “A”
during the previous clock rise of the Read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQ are placed in a tri-state condition.
VDD
15, 41, 65, 91
Power Supply Power supply inputs to the core of the device.
VSS
17, 40, 67, 90
Document #: 38-05689 Rev. *E
Ground
Ground for the core of the device.
Page 4 of 18
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CY7C1364C
Pin Definitions (continued)
Name
TQFP
I/O
VDDQ
4, 11, 20, 27, 54, 61, 70, 77
I/O Power
Supply
Power supply for the I/O circuitry.
VSSQ
5, 10, 21, 26, 55, 60, 71, 76
I/O Ground
Ground for the I/O circuitry.
31
InputStatic
MODE
NC
1, 14, 16, 30, 38, 39, 42,
51, 66, 80
Description
Selects Burst Order. When tied to GND selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
No Connects. Not internally connected to the die
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1364C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within tCO if OE is active LOW. The only
exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single Read cycles are supported. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will tri-state immediately.
Document #: 38-05689 Rev. *E
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the RAM
array. The Write signals (GW, BWE, and BW[A:D]) and ADV
inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corresponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW[A:D]
signals. The CY7C1364C provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW[A:D]) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1364C is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BW[A:D]) are asserted active to conduct a Write to
the desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQ is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1364C is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Page 5 of 18
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CY7C1364C
Burst Sequences
The CY7C1364C provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A[1:0]
Second
Address
A[1:0]
Third
Address
A[1:0]
Fourth
Address
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
First
Address
A[1:0]
Second
Address
A[1:0]
Third
Address
A[1:0]
Fourth
Address
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
Sleep mode standby current
Test Conditions
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ Active to Sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit Sleep current
This parameter is sampled
Document #: 38-05689 Rev. *E
Min.
ZZ > VDD – 0.2V
Max.
Unit
50
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Page 6 of 18
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CY7C1364C
Truth Table[3, 4, 5, 6, 7, 8]
Address
Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
L
X
X
H
X
L
X
X
Tri-State
X
Unselected
None
L
H
X
L
L
X
X
X
Tri-State
X
Unselected
None
L
X
L
L
L
X
X
X
Tri-State
X
Unselected
None
L
H
X
L
H
L
X
X
Tri-State
X
Unselected
None
L
X
L
L
H
L
X
X
Tri-State
X
Next Cycle
Begin Read
External
L
L
H
L
L
X
X
X
Tri-State
X
Begin Read
External
L
L
H
L
H
L
X
X
Tri-State
Read
Continue Read
Next
L
X
X
X
H
H
L
H
Tri-State
Read
Continue Read
Next
L
X
X
X
H
H
L
L
DQ
Read
Continue Read
Next
L
X
X
H
X
H
L
H
Tri-State
Read
Continue Read
Next
L
X
X
H
X
H
L
L
DQ
Read
Suspend Read
Current
L
X
X
X
H
H
H
H
Tri-State
Read
Suspend Read
Current
L
X
X
X
H
H
H
L
DQ
Read
Suspend Read
Current
L
X
X
H
X
H
H
H
Tri-State
Read
Suspend Read
Current
L
X
X
H
X
H
H
L
DQ
Read
Begin Write
Current
L
X
X
X
H
H
H
X
Tri-State
Write
Begin Write
Current
L
X
X
H
X
H
H
X
Tri-State
Write
Begin Write
External
L
L
H
L
H
H
X
X
Tri-State
Write
Next
L
X
X
X
H
H
H
X
Tri-State
Write
Continue Write
Continue Write
Next
L
X
X
H
X
H
H
X
Tri-State
Write
Suspend Write
Current
L
X
X
X
H
H
H
X
Tri-State
Write
Suspend Write
Current
L
X
X
H
X
H
H
X
Tri-State
Write
None
H
X
X
X
X
X
X
X
Tri-State
X
ZZ “Sleep”
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA,BWB,BWC,BWD), BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE1, CE2, and CE3 are available only in the TQFP package.
7. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05689 Rev. *E
Page 7 of 18
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CY7C1364C
Truth Table for Read/Write[3, 4]
GW
BWE
BWD
BWC
BWB
BWA
Read
Function
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – DQA
H
L
H
H
H
L
Write Byte B – DQB
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – DQC
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – DQD
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Document #: 38-05689 Rev. *E
Page 8 of 18
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CY7C1364C
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ..................................................... >200 mA
Operating Range
Supply Voltage on VDD Relative to GND ........–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND...... –0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state.............................................–0.5V to VDDQ + 0.5V
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VDD
3.3V –
5%/+10%
VDDQ
2.5V – 5% to
VDD
Electrical Characteristics Over the Operating Range [9, 10]
Parameter
Description
VDD
Power Supply Voltage
Test Conditions
Min.
3.135
Max.
3.6
Unit
V
for 3.3 V I/O
3.135
VDD
V
for 2.5V I/O
2.375
2.625
V
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
for 3.3 V I/O, IOL = 8.0 mA
VIH
Input HIGH Voltage[9]
for 3.3 V I/O
VIL
Input LOW Voltage[9]
for 2.5V I/O
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
for 3.3 V I/O, IOH = –4.0 mA
2.4
for 2.5V I/O, IOH = –1.0 mA
2.0
for 2.5V I/O, IOL = 1.0 mA
V
0.4
V
VDD + 0.3V
V
for 2.5V I/O
1.7
VDD + 0.3V
V
for 3.3 V I/O
–0.3
0.8
V
–0.3
0.7
V
–5
5
µA
µA
–30
Input = VDD
5
Input = VSS
Input = VDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Automatic CE
Power-down
Current—TTL Inputs
–5
µA
µA
–5
IOZ
ISB1
V
0.4
2.0
Input Current of MODE Input = VSS
Input Current of ZZ
V
30
µA
5
µA
4-ns cycle, 250 MHz
250
mA
5-ns cycle, 200 MHz
220
mA
6-ns cycle, 166 MHz
180
mA
VDD = Max., Device Deselected, 4-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL,
5-ns cycle, 200 MHz
f = fMAX = 1/tCYC
6-ns cycle, 166 MHz
130
mA
120
110
ISB2
Automatic CE
VDD = Max., Device Deselected, All speeds
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
40
mA
ISB3
Automatic CE
VDD = Max., Device Deselected, 4-ns cycle, 250 MHz
Power-down
or VIN ≤ 0.3V or VIN > VDDQ – 0.3V, 5-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6-ns cycle, 166 MHz
120
mA
Automatic CE
Power-down
Current—TTL Inputs
40
ISB4
VDD = Max., Device Deselected, All speeds
VIN ≥ VIH or VIN ≤ VIL,
f=0
110
100
mA
Notes:
9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0Vv to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05689 Rev. *E
Page 9 of 18
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CY7C1364C
Capacitance[11]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
100 TQFP
Max.
Unit
5
pF
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 2.5V
5
pF
5
pF
Thermal Resistance[11]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
100 TQFP Package
Unit
29.41
°C/W
6.13
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
Z0 = 50Ω
10%
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
R = 351Ω
(b)
(c)
10%
(a)
90%
10%
90%
GND
5 pF
VT = 1.25V
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
≤ 1 ns
≤ 1 ns
R = 1667Ω
2.5V
OUTPUT
90%
10%
90%
GND
5 pF
VT = 1.5V
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
R =1538Ω
INCLUDING
JIG AND
SCOPE
(b)
≤ 1 ns
≤ 1 ns
(c)
Note:
11. Tested initially and after any design or process change that may affect these parameters
Document #: 38-05689 Rev. *E
Page 10 of 18
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CY7C1364C
Switching Characteristics Over the Operating Range[12,13]
–250
Parameter
tPOWER
Description
VDD(Typical) to the First Access[14]
Min.
–200
Max.
Min.
–166
Max.
Min.
Max.
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
5.0
6.0
ns
tCH
Clock HIGH
1.8
2.0
2.4
ns
tCL
Clock LOW
1.8
2.0
2.4
ns
Output Times
tCO
Data Output Valid after CLK Rise
tDOH
Data Output Hold after CLK Rise
1.25
1.25
1.25
ns
tCLZ
Clock to Low-Z[15, 16, 17]
1.25
1.25
1.25
ns
tCHZ
[15, 16, 17]
Clock to High-Z
1.25
tOEV
OE LOW to Output Valid
Low-Z[15, 16, 17]
tOELZ
OE LOW to Output
tOEHZ
OE HIGH to Output High-Z[15, 16, 17]
2.8
2.8
3.0
1.25
2.8
0
3.0
3.5
1.25
3.0
0
2.8
3.5
ns
3.5
ns
0
3.0
ns
ns
3.5
ns
Set-up Times
tAS
Address Set-up before CLK Rise
1.25
1.5
1.5
ns
tADS
ADSC, ADSP Set-up before CLK Rise
1.25
1.5
1.5
ns
tADVS
ADV Set-up before CLK Rise
1.25
1.5
1.5
ns
tWES
GW, BWE, BW[A:D] Set-up before CLK Rise
1.25
1.5
1.5
ns
tDS
Data Input Set-up before CLK Rise
1.25
1.5
1.5
ns
tCES
Chip Enable Set-up before CLK Rise
1.25
1.5
1.5
ns
tAH
Address Hold after CLK Rise
0.4
0.5
0.5
ns
tADH
ADSP, ADSC Hold after CLK Rise
0.4
0.5
0.5
ns
tADVH
ADV Hold after CLK Rise
0.4
0.5
0.5
ns
tWEH
GW, BWE, BW[A:D] Hold after CLK Rise
0.4
0.5
0.5
ns
tDH
Data Input Hold after CLK Rise
0.4
0.5
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.4
0.5
0.5
ns
Hold Times
Notes:
12. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
13. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
14. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
15. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
16. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document #: 38-05689 Rev. *E
Page 11 of 18
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CY7C1364C
Switching Waveforms
Read Cycle Timing[18]
t CYC
CLK
t
CH
t
CL
t
t
ADS ADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
A3
Burst continued with
new base address
tWES tWEH
GW, BWE,
BW[A:D]
Deselect
cycle
tCES tCEH
CE
tADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
Note:
to its initial state
18. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05689 Rev. *E
Page 12 of 18
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CY7C1364C
Switching Waveforms (continued)
Write Cycle Timing[18,19]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BW[A :D]
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
19. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
Document #: 38-05689 Rev. *E
Page 13 of 18
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CY7C1364C
Switching Waveforms (continued)
Read/Write Cycle Timing[18,20, 21]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BW[A:D]
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
Q(A1)
High-Z
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
20. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
21. GW is HIGH.
Document #: 38-05689 Rev. *E
Page 14 of 18
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CY7C1364C
Switching Waveforms (continued)
ZZ Mode Timing[22, 23]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
23. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05689 Rev. *E
Page 15 of 18
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CY7C1364C
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
166
200
250
Ordering Code
CY7C1364C-166AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
CY7C1364C-166AJXC
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
CY7C1364C-166AXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
CY7C1364C-166AJXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
CY7C1364C-200AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
CY7C1364C-200AJXC
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
CY7C1364C-200AXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
CY7C1364C-200AJXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
CY7C1364C-250AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
CY7C1364C-250AJXC
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
CY7C1364C-250AXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
CY7C1364C-250AJXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
Document #: 38-05689 Rev. *E
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 16 of 18
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CY7C1364C
Package Diagram
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05689 Rev. *E
Page 17 of 18
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1364C
Document History Page
Document Title: CY7C1364C 9-Mbit (256K x 32) Pipelined Sync SRAM
Document Number: 38-05689
REV.
ECN NO.
Issue Date
Orig. of
Change
**
286269
See ECN
PCI
New data sheet
*A
320834
See ECN
PCI
Changed 225 MHz into 250 MHz
Changed ΘJA and ΘJC for TQFP from 25 and 9 °C/W to 29.41 and 6.13 °C/W
respectively
Modified VOL, VOH test conditions
Added Industrial Operating Range
Changed Snooze to Sleep in the ZZ Mode Electrical Characteristics
Shaded 250 MHz speed bin in the AC/DC table and Selection Guide
Added AJXC package in the Ordering Information
Updated Ordering Information Table
*B
377095
See ECN
PCI
Changed ISB2 from 30 to 40 mA
Modified test condition in note# 9 from VIH < VDD to VIH < VDD
*C
408725
See ECN
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed three-state to tri-state
Converted from Preliminary to Final
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the ordering information
*D
429278
See ECN
NXR
Added 2.5 V I/O option
Included 2 Chip Enable Pinout
Updated Ordering Information Table
*E
501828
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Updated the Ordering Information table.
Document #: 38-05689 Rev. *E
Description of Change
Page 18 of 18
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