Allegro A1211 Continuous-time latch family Datasheet

A1210, A1211, A1212, A1213, and A1214
Continuous-Time Latch Family
Features and Benefits
Description
▪ Continuous-time operation
▫ Fast power-on time
▫ Low noise
▪ Stable operation over full operating temperature range
▪ Reverse battery protection
▪ Solid-state reliability
▪ Factory-programmed at end-of-line for optimum
performance
▪ Robust EMC performance
▪ High ESD rating
▪ Regulator stability without a bypass capacitor
The Allegro™ A1210-A1214 Hall-effect latches are next
generation replacements for the popular Allegro 317x and
318x lines of latching switches. The A121x family, produced with BiCMOS technology, consists of devices that
feature fast power-on time and low-noise operation. Device
programming is performed after packaging, to ensure
increased switchpoint accuracy by eliminating offsets that
can be induced by package stress. Unique Hall element
geometries and low-offset amplifiers help to minimize noise
and to reduce the residual offset voltage normally caused by
device overmolding, temperature excursions, and thermal
stress.
The A1210-A1214 Hall-effect latches include the following
on a single silicon chip: voltage regulator, Hall-voltage generator, small-signal amplifier, Schmitt trigger, and NMOS
output transistor. The integrated voltage regulator permits
operation from 3.8 to 24 V. The extensive on-board protection circuitry makes possible a ±30 V absolute maximum
voltage rating for superior protection in automotive and
industrial motor commutation applications, without adding
external components. All devices in the family are identical
except for magnetic switchpoint levels.
Packages: 3 pin SOT23W (suffix LH), and
3 pin SIP (suffix UA)
1
3
2
1
2
The small geometries of the BiCMOS process allow these
devices to be provided in ultrasmall packages. The package
styles available provide magnetically optimized solutions
for most applications. Package LH is an SOT23W, a miniature low-profile surface-mount package, while package
UA is a three-lead ultramini SIP for through-hole mounting.
Each package is lead (Pb) free, with 100% matte tin plated
leadframes.
3
Not to scale
Functional Block Diagram
VCC
To all subcircuits
Regulator
VOUT
Amp
Gain
Offset
Trim
Control
GND
A1210-DS, Rev. 10
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Selection Guide
Part Number
Packing*
Mounting
Ambient, TA
A1210ELHLT-T
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A1210LLHLT-T
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A1210LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1211LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1212LLHLT-T
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A1212LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1213LLHLT-T
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A1213LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
A1214LLHLT-T
7-in. reel, 3000 pieces/reel
3-pin SOT23W surface mount
A1214LUA-T
Bulk, 500 pieces/bag
3-pin SIP through hole
BRP (Min)
BOP (Max)
–150
150
–180
180
–40ºC to 150ºC
–200
200
–40ºC to 150ºC
–300
300
–40ºC to 85ºC
–40ºC to 150ºC
–40ºC to 150ºC
–40ºC to 150ºC
*Contact Allegro for additional packing options.
Absolute Maximum Ratings
Rating
Unit
Supply Voltage
Characteristic
VCC
30
V
Reverse Supply Voltage
VRCC
–30
V
Output Off Voltage
VOUT
30
V
VROUT
–0.5
V
IOUTSINK
25
mA
Reverse Output Voltage
Output Current
Magnetic Flux Density
Symbol
B
Notes
1 G = 0.1 mT (millitesla)
Unlimited
G
Range E
–40 to 85
ºC
Range L
–40 to 150
ºC
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(max)
165
ºC
Tstg
–65 to 170
ºC
Storage Temperature
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Pin-out Diagrams
Package UA, 3-pin SIP
GND
Package LH, 3-pin Surface Mount
2
3
VOUT
VOUT
1
GND
2
VCC
1
VCC
3
Terminal List
Name
VCC
VOUT
GND
Description
Connects power supply to chip
Output from circuit
Ground
Number
Package LH Package UA
1
1
2
3
3
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
OPERATING CHARACTERISTICS over full operating voltage and ambient temperature ranges, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Electrical Characteristics
Supply Voltage1
Output Leakage Current
Output On Voltage
Power-On Time2
Output Rise Time3
Output Fall
Time3
Supply Current
Reverse Battery Current
VCC
Operating, TJ < 165°C
3.8
–
24
V
IOUTOFF
VOUT = 24 V, B < BRP
–
–
10
μA
VOUT(SAT)
IOUT = 20 mA, B > BOP
–
215
400
mV
Slew rate (dVCC/dt) < 2.5 V/μs, B > BOP + 5 G or
B < BRP – 5 G
–
–
4
μs
tr
VCC = 12 V, RLOAD = 820 Ω, CS = 12 pF
–
–
400
ns
tf
tPO
VCC = 12 V, RLOAD = 820 Ω, CS = 12 pF
–
–
400
ns
ICCON
B > BOP
–
4.1
7.5
mA
ICCOFF
B < BRP
–
3.8
7.5
mA
VRCC = –30 V
–
–
–10
mA
IRCC
Supply Zener Clamp Voltage
VZ
ICC = 10.5 mA; TA = 25°C
32
–
–
V
Supply Zener Current4
IZ
VZ = 32 V; TA = 25°C
–
–
10.5
mA
25
78
150
G
15
87
180
G
50
107
175
G
80
–
200
G
140
–
300
G
Magnetic
Characteristics5
A1210
A1211
Operate Point
BOP
A1212
A1213
South pole adjacent to branded face
of device
A1214
Release Point
BRP
A1210
–150
–78
–25
G
A1211
–180
–95
–15
G
–175
–117
–50
G
A1212
A1213
Hysteresis
BHYS
North pole adjacent to branded face
of device
–200
–
–80
G
A1214
–300
–
–140
G
A1210
50
155
–
G
A1211
80
180
–
G
100
225
350
G
A1213
160
–
400
G
A1214
280
–
600
G
A1212
BOP – BRP
1
Maximum voltage must be adjusted for power dissipation and junction temperature, see Power Derating section.
2 For V
CC slew rates greater than 250 V/μs, and TA = 150°C, the Power-On Time can reach its maximum value.
3 C =oscilloscope probe capacitance.
S
4 Maximum current limit is equal to the maximum I
CC(max) + 3 mA.
5 Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and as a positive value for south-polarity magnetic fields.
This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the field is indicated
by the absolute value of B, and the sign indicates the polarity of the field (for example, a –100 G field and a 100 G field have equivalent strength, but
opposite polarity).
DEVICE QUALIFICATION PROGRAM
Contact Allegro for information.
EMC (Electromagnetic Compatibility) REQUIREMENTS
Contact Allegro for information.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions
Package LH, on single layer, single-sided PCB with copper
limited to solder pads
Package LH, on single layer, double-sided PCB with 0.926 in2
copper area
Package UA on single layer, single-sided PCB with copper
limited to solder
110 pads
RθJA
Maximum Allowable VCC (V)
Package Thermal Resistance
Value Units
228
ºC/W
110
ºC/W
165
ºC/W
Power Derating Curve
TJ(max) = 165ºC; ICC = ICC(max)
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
VCC(max)
Low-K PCB, Package LH
(RθJA = 110 ºC/W)
Minimum-K PCB, Package UA
(RθJA = 165 ºC/W)
Minimum-K PCB, Package LH
(RθJA = 228 ºC/W)
20
40
60
80
100
120
VCC(min)
140
160
180
Power Dissipation, PD (m W)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Lo
(R w-K
PC
θJ
A =
11 B, P
0 º ac
Min
C/ ka
W ge
(R imum
)
LH
-K
θJA =
165 PCB
ºC/ , Pac
W)
kag
eU
A
Min
imu
m-K
(R
P
θJA =
228 CB, Pa
ºC/W
ckag
e LH
)
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Characteristic Data
Supply Current (On) versus Ambient Temperature
Supply Current (On) versus Supply Voltage
(A1210/11/12/13/14)
(A1210/11/12/13/14)
8.0
7.0
7.0
ICCON (mA)
6.0
VCC (V)
5.0
24
3.8
4.0
3.0
ICCON (mA)
8.0
6.0
TA (°C)
5.0
–40
25
150
4.0
3.0
2.0
2.0
1.0
1.0
0
0
–50
0
50
TA (°C)
100
150
0
5
20
25
Supply Current (Off) versus Supply Voltage
(A1210/11/12/13/14)
(A1210/11/12/13/14)
8.0
7.0
7.0
VCC (V)
5.0
24
3.8
4.0
3.0
ICCOFF (mA)
8.0
6.0
ICCOFF (mA)
15
VCC (V)
Supply Current (Off) versus Ambient Temperature
6.0
TA (°C)
5.0
–40
25
150
4.0
3.0
2.0
2.0
1.0
1.0
0
0
–50
0
50
TA (°C)
100
0
150
10
15
20
25
Output Voltage (On) versus Supply Voltage
(A1210/11/12/13/14)
400
5
VCC (V)
Output Voltage (On) versus Ambient Temperature
(A1210/11/12/13/14)
400
350
350
300
300
250
VCC (V)
200
24
3.8
150
100
50
VOUT(SAT) (mV)
VOUT(SAT) (mV)
10
TA (°C)
250
–40
25
150
200
150
100
50
0
0
–50
0
50
TA (°C)
100
150
0
5
10
15
20
25
VCC (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Operate Point versus Ambient Temperature
Operate Point versus Supply Voltage
(A1210)
(A1210)
150
150
125
125
TA (°C)
100
24
3.8
75
BOP (G)
BOP (G)
VCC (V)
–40
25
150
100
75
50
50
25
–50
25
0
50
TA (°C)
100
150
0
5
10
15
20
25
VCC (V)
Release Point versus Ambient Temperature
Release Point versus Supply Voltage
(A1210)
(A1210)
-25
-25
-50
-50
TA (°C)
-75
24
3.8
BRP (G)
BRP (G)
VCC (V)
–40
25
150
-75
-100
-100
-125
-125
-150
-150
–50
0
50
TA (°C)
100
0
150
5
10
Hysteresis versus Ambient Temperature
20
25
Hysteresis versus Supply Voltage
(A1210)
(A1210)
225
225
200
200
175
VCC (V)
150
24
3.8
125
TA (°C)
BHYS (G)
175
BHYS (G)
15
VCC (V)
150
–40
25
150
125
100
100
75
75
50
50
–50
0
50
TA (°C)
100
150
0
5
10
15
20
25
VCC (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Operate Point versus Ambient Temperature
Operate Point versus Ambient Temperature
(A1211)
(A1212)
175
165
150
125
VCC (V)
115
24
3.8
90
BOP (G)
BOP (G)
140
VCC (V)
75
24
3.8
50
25
65
0
40
-25
15
–50
-50
0
50
TA (°C)
100
–50
150
0
50
TA (°C)
100
150
Release Point versus Ambient Temperature
Release Point versus Ambient Temperature
(A1211)
(A1212)
-50
-30
-55
-75
VCC (V)
-80
24
3.8
-105
VCC (V)
BRP (G)
BRP (G)
100
-130
-100
24
3.8
-125
-150
-155
-175
-180
–50
0
50
TA (°C)
100
–50
150
Hysteresis versus Ambient Temperature
0
100
150
Hysteresis versus Ambient Temperature
(A1211)
240
50
TA (°C)
(A1212)
350
220
300
180
VCC (V)
160
24
3.8
140
120
BHYS (G)
BHYS (G)
200
VCC (V)
250
24
3.8
200
150
100
100
80
–50
0
50
TA (°C)
100
150
–50
0
50
100
150
TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Functional Description
OPERATION
The output of these devices switches low (turns on) when a
magnetic field perpendicular to the Hall element exceeds the
operate point threshold, BOP. After turn-on, the output is capable
of sinking 25 mA and the output voltage is VOUT(SAT). Notice
that the device latches; that is, a south pole of sufficient strength
towards the branded surface of the device turns the device on,
and the device remains on with removal of the south pole. When
the magnetic field is reduced below the release point, BRP ,
the device output goes high (turns off). The difference in the
magnetic operate and release points is the hysteresis, Bhys, of
the device. This built-in hysteresis allows clean switching of the
output, even in the presence of external mechanical vibration and
electrical noise.
Powering-on the device in the hysteresis range, less than BOP
and higher than BRP, allows an indeterminate output state. The
correct state is attained after the first excursion beyond BOP or
BRP.
Due to offsets generated during the IC packaging process,
continuous-time devices typically require programming after
packaging to tighten magnetic parameter distributions. In contrast, chopper-stabilized switches employ an offset cancellation
technique on the chip that eliminates these offsets without the
need for after-packaging programming. The tradeoff is a longer
settling time and reduced frequency response as a result of the
chopper-stabilization offset cancellation algorithm.
The choice between continuous-time and chopper-stabilized
designs is solely determined by the application. Battery management is an example where continuous-time is often required. In
these applications, VCC is chopped with a very small duty cycle
in order to conserve power (refer to figure 2). The duty cycle
is controlled by the power-on time, tPO, of the device. Because
continuous-time devices have the shorter power-on time, they
are the clear choice for such applications.
Continuous-time devices, such as the A121x family, offer the
fastest available power-on settling time and frequency response.
For more information on the chopper stabilization technique,
refer to Technical Paper STP 97-10, Monolithic Magnetic Hall
Sensing Using Dynamic Quadrature Offset Cancellation and
Technical Paper STP 99-1, Chopper-Stabilized Amplifiers with a
Track-and-Hold Signal Demodulator.
(A)
(B)
CONTINUOUS-TIME BENEFITS
VS
V+
VOUT
VCC
Switch to Low
Switch to High
VCC
A121x
VOUT(SAT)
0
BOP
B–
BRP
0
RL
VOUT
Output
GND
B+
BHYS
Figure 1. Switching Behavior of Latches. On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the
B– direction indicates decreasing south polarity field strength (including the case of increasing north polarity). This behavior can be exhibited when
using a circuit such as that shown in Panel B.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
ADDITIONAL APPLICATIONS INFORMATION
Extensive applications information for Hall-effect devices is
available in:
• Hall-Effect IC Applications Guide, Application Note 27701
• Hall-Effect Devices: Gluing, Potting, Encapsulating, Lead
Welding and Lead Forming, Application Note 27703.1
• Soldering Methods for Allegro’s Products – SMT and ThroughHole, Application Note 26009
All are provided in Allegro Electronic Data Book, AMS-702,
and the Allegro Web site, www.allegromicro.com.
1
2
3
4
5
VCC
t
VOUT
t
tPO(max)
Output Sampled
Figure 2. Continuous-Time Application, B < BRP.. This figure illustrates the use of a quick cycle for chopping VCC in order to conserve battery power.
Position 1, power is applied to the device. Position 2, the output assumes the correct state at a time prior to the maximum Power-On Time, tPO(max).
The case shown is where the correct output state is HIGH . Position 3, tPO(max) has elapsed. The device output is valid. Position 4, after the output is
valid, a control unit reads the output. Position 5, power is removed from the device.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Power Derating
Power Derating
The device must be operated below the maximum junction
temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, RJA, is a figure of merit summarizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RJC, is
relatively small component of RJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN

(1)
T = PD × RJA (2)
TJ = TA + ΔT
Example: Reliability for VCC at TA = 150°C, package UA, using
minimum-K PCB.
Observe the worst-case ratings for the device, specifically:
RJA = 165°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
ICC(max) = 7.5 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = Tmax ÷ RJA = 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 7.5 mA = 12.1 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced
RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
VCC(max) is reliable under these conditions.
(3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 4 mA, and RJA = 140 °C/W, then:
PD = VCC × ICC = 12 V × 4 mA = 48 mW

T = PD × RJA = 48 mW × 140 °C/W = 7°C
TJ = TA + T = 25°C + 7°C = 32°C
A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max),
at a selected RJA and TA.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Package LH, 3-Pin (SOT-23W)
+0.12
2.98 –0.08
1.49 D
4°±4°
3
A
+0.020
0.180–0.053
0.96 D
+0.10
2.90 –0.20
+0.19
1.91 –0.06
2.40
0.70
D
0.25 MIN
1.00
2
1
0.55 REF
0.25 BSC
0.95
Seating Plane
Gauge Plane
8X 10° REF
B
PCB Layout Reference View
Branded Face
1.00 ±0.13
+0.10
0.05 –0.05
0.95 BSC
0.40 ±0.10
For Reference Only; not for tooling use (reference dwg. 802840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Active Area Depth, 0.28 mm REF
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
Branding scale and appearance at supplier discretion
D
Hall element, not to scale
NNT
1
C
Standard Branding Reference View
N = Last two digits of device part number
T = Temperature code
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Package UA, 3-Pin SIP
+0.08
4.09 –0.05
45°
B
C
E
2.04
1.52 ±0.05
10°
1.44
+0.08
3.02 –0.05
E
Mold Ejector
Pin Indent
E
Branded
Face
45°
0.79 REF
A
1.02
MAX
NNT
1
1
2
D Standard Branding Reference View
3
= Supplier emblem
N = Last two digits of device part number
T = Temperature code
+0.03
0.41 –0.06
14.99 ±0.25
For Reference Only; not for tooling use (reference DWG-9065)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.05
0.43 –0.07
A
Dambar removal protrusion (6X)
B
Gate and tie bar burr area
C
Active Area Depth, 0.50 mm REF
D
Branding scale and appearance at supplier discretion
E
Hall element (not to scale)
1.27 NOM
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
A1210, A1211,
A1212, A1213,
and A1214
Continuous-Time Latch Family
Revision History
Revision
Revision Date
Rev. 10
May 29, 2012
Description of Revision
Update UA package drawing
Copyright ©2005-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14