AD AD6657ABBCZRL Quad if receiver Datasheet

Quad IF Receiver
AD6657A
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
DRGND
AD6657A
VIN+A
PIPELINE
ADC
VIN–A
14
NOISE SHAPING
REQUANTIZER
DO±AB
VCMA
VIN+B
PIPELINE
ADC
VIN–B
14
NOISE SHAPING
REQUANTIZER
11
VCMB
VIN+C
PIPELINE
ADC
VIN–C
14
NOISE SHAPING
REQUANTIZER
DCO±AB
11
11
DATA MULTIPLEXER
AND LVDS DRIVERS
PORT A
D10±AB
DCO±CD
DO±CD
PORT B
VCMC
VIN+D
PIPELINE
ADC
VIN–D
14
NOISE SHAPING
REQUANTIZER
11
D10±CD
VCMD
MODE
REFERENCE
CLOCK
DIVIDER
PDWN
SERIAL PORT
SCLK
SDIO
SYNC
CSB
CLK+ CLK–
09684-001
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer
Performance with NSR enabled
SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS
SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS
SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS to 70 MHz at 185 MSPS
SFDR: 88 dBc to 70 MHz at 185 MSPS
Low power: 1.2 W at 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self test (BIST) capability
Energy saving power-down modes
Figure 1.
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate
frequency (IF) receiver specifically designed to support multiple
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of four high performance ADCs and NSR
digital blocks. Each ADC consists of a multistage, differential
pipelined architecture with integrated output error correction
logic. The ADC features a wide bandwidth switched capacitor
sampling network within the first stage of the differential pipeline.
An integrated voltage reference eases design considerations. A
duty cycle stabilizer (DCS) compensates for variations in the
ADC clock duty cycle, allowing the converters to maintain
excellent performance.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the serial port interface (SPI).
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6657A supports enhanced SNR performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution. The NSR block
can be programmed to provide a bandwidth of either 22%, 33%,
or 36% of the sample clock. For example, with a sample clock
rate of 185 MSPS, the AD6657A can achieve up to 76.0 dBFS
SNR for a 40 MHz bandwidth in the 22% mode, up to 73.6 dBFS
SNR for a 60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS
SNR for a 65 MHz bandwidth in the 36% mode.
(General Description continued on Page 3)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD6657A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Channel/Chip Synchronization ................................................ 23
Applications ....................................................................................... 1
Digital Outputs ........................................................................... 24
Functional Block Diagram .............................................................. 1
Timing ......................................................................................... 24
General Description ......................................................................... 1
Noise Shaping Requantizer ........................................................... 25
Revision History ............................................................................... 2
22% BW Mode (>40 MHz at 184.32 MSPS) ........................... 25
Product Highlights ........................................................................... 3
33% BW Mode (>60 MHz at 184.32 MSPS) ........................... 26
Specifications..................................................................................... 4
36% BW Mode (>65 MHz at 184.32 MSPS) ........................... 27
DC Specifications ......................................................................... 4
MODE Pin ................................................................................... 27
AC Specifications.......................................................................... 5
Built-In Self Test (BIST) and Output Test ................................... 28
Digital Specifications ................................................................... 7
BIST .............................................................................................. 28
Switching Specifications .............................................................. 9
Output Test Modes ..................................................................... 28
Timing Specifications ................................................................ 10
Serial Port Interface (SPI) .............................................................. 29
Absolute Maximum Ratings ..................................................... 11
Configuration Using the SPI ..................................................... 29
Thermal Characteristics ............................................................ 11
Hardware Interface..................................................................... 29
ESD Caution ................................................................................ 11
Memory Map .................................................................................. 30
Pin Configuration and Function Descriptions ........................... 12
Reading the Memory Map Register Table............................... 30
Typical Performance Characteristics ........................................... 14
Memory Map Register Table ..................................................... 31
Equivalent Circuits ......................................................................... 18
Memory Map Register Descriptions ........................................ 33
Theory of Operation ...................................................................... 19
Applications Information .............................................................. 35
ADC Architecture ...................................................................... 19
Design Guidelines ...................................................................... 35
Analog Input Considerations.................................................... 19
Packaging and Ordering Information ......................................... 36
Clock Input Considerations ...................................................... 21
Outline Dimensions ................................................................... 36
Power Dissipation and Standby Mode ..................................... 23
Ordering Guide .......................................................................... 36
REVISION HISTORY
10/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
Data Sheet
AD6657A
With the NSR block disabled, the ADC data is provided directly to
the output with a resolution of 11 bits. The AD6657A can achieve
up to 66.5 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6657A to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are used.
(CSP_BGA) that is specified over the industrial temperature
range of −40°C to +85°C.
After digital signal processing, multiplexed output data is
routed into two 11-bit output ports such that the maximum
digital data rate (DDR) is 400 Mbps. These outputs are set at
1.8 V LVDS and support ANSI-644 levels.
2.
PRODUCT HIGHLIGHTS
1.
3.
The AD6657A receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces component
cost and complexity compared with traditional analog techniques
or less integrated digital methods.
4.
5.
6.
Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire SPI-compatible serial interface with numerous
modes to support board level system testing.
7.
The AD6657A is available in a Pb-free, RoHS compliant,
144-ball, 10 mm × 10 mm chip scale package ball grid array
Rev. 0 | Page 3 of 36
Four analog-to-digital converters (ADCs) are contained in
a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball
CSP_BGA package.
Pin selectable noise shaping requantizer (NSR) function
that allows for improved SNR within a reduced bandwidth
of up to 65 MHz at 185 MSPS.
LVDS digital output interface configured for low cost
FPGA families.
230 mW per ADC core power consumption.
Operation from a single 1.8 V supply.
Standard SPI that supports various product features and
functions, such as data formatting (offset binary or twos
complement), NSR, power-down, test modes, and voltage
reference mode.
On-chip integer 1-to-8 input clock divider and multichip
sync function to support a wide range of clocking schemes
and multichannel subsystems.
AD6657A
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUT
Input Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance 2
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1 (1.8 V LVDS)
POWER CONSUMPTION
Sine Wave Input1
Standby Power 3
Power-Down Power
1
2
3
Temperature
Full
Min
11
Typ
Max
Unit
Bits
Full
Full
Full
Full
Full
−0.9
+4
−0.4
−0.55
Guaranteed
+0.1
+11
±0.1
±0.17
+0.9
+18
+0.4
+0.55
mV
% FSR
LSB
LSB
Full
Full
−5
0
+3
+2.1
+11
+8
mV
% FSR
Full
Full
2
40
ppm/°C
ppm/°C
Full
Full
Full
Full
1.4
1.75
0.95
20
5
2.0
V p-p
V
kΩ
pF
Full
Full
1.7
1.7
1.8
1.8
1.9
1.9
V
V
Full
Full
466
170
510
183
mA
mA
Full
Full
Full
1145
129
3.8
1247
mW
mW
mW
Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair.
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).
Rev. 0 | Page 4 of 36
10
Data Sheet
AD6657A
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE-RATIO (SNR)—NSR DISABLED
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
SIGNAL-TO-NOISE-RATIO (SNR)—NSR ENABLED
22% BW Mode
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
33% BW Mode
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
36% BW Mode
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
Temperature
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Rev. 0 | Page 5 of 36
Min
Typ
66.6
66.5
66.5
66.3
65.6
65.9
76.0
75.7
75.7
74.3
72.9
72.8
73.6
73.6
73.3
72.5
71.3
71.2
72.8
72.6
72.6
71.8
70.7
70.8
65.5
65.5
65.5
65.3
Max
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
64.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
10.6
10.6
10.6
10.6
10.5
Bits
Bits
Bits
Bits
Bits
64.6
AD6657A
Parameter 1
WORST SECOND OR THIRD HARMONIC
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH)
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
TWO TONE SFDR (−7 dBFS)
fIN1 = 169 MHz, fIN2 = 172 MHz
CROSSTALK 2
ANALOG INPUT BANDWIDTH
1
2
Data Sheet
Temperature
Min
Typ
25°C
25°C
25°C
25°C
Full
25°C
−94
−91
−88
−90
25°C
25°C
25°C
25°C
Full
25°C
94
91
88
90
Max
−80
−83
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
80
83
25°C
25°C
25°C
25°C
Full
25°C
−94
−95
−94
−94
−90
dBc
dBc
dBc
dBc
dBc
dBc
25°C
Full
25°C
89
95
800
dBc
dB
MHz
−80
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 155 MHz with −1 dBFS on one channel and no input on the alternate channel.
Rev. 0 | Page 6 of 36
Data Sheet
AD6657A
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (CSB) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ
Max
Unit
3.6
AVDD + 0.2
2.0
0.8
+10
+10
12
V
V p-p
V
V
V
µA
µA
kΩ
pF
AVDD
AVDD
0.6
+100
+100
20
V
V
V
V
µA
µA
kΩ
pF
CMOS/LVDS/LVPECL
0.9
0.2
AGND − 0.3
1.2
0
−10
−10
8
10
4
CMOS
0.9
AGND
1.2
AGND
−100
−100
12
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
16
1
2.1
0.6
+10
132
V
V
µA
µA
kΩ
pF
2.1
0.6
−135
+10
V
V
µA
µA
kΩ
pF
2.1
0.6
+10
128
V
V
µA
µA
kΩ
pF
26
2
26
2
26
5
Rev. 0 | Page 7 of 36
AD6657A
Parameter
LOGIC INPUT (MODE)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (LVDS)
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
1
2
Data Sheet
Temperature
Min
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−90
−10
Full
Full
247
1.125
Typ
Max
Unit
2.1
0.6
+10
132
V
V
μA
μA
kΩ
pF
2.1
0.6
−134
+10
V
V
μA
μA
kΩ
pF
454
1.375
mV
V
26
2
26
5
Pull up.
Pull down.
Rev. 0 | Page 8 of 36
Data Sheet
AD6657A
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate 1
CLK Pulse Width High (tCH) 2
Aperture Delay (tA)2
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)2
DCO to Data Skew (tSKEW)2
Pipeline Delay (Latency)
With NSR Enabled
Wake-Up Time (from Standby) 3
Wake-Up Time (from Power Down)3
OUT-OF-RANGE RECOVERY TIME
1
2
3
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ
40
185
2.7
1.3
0.13
3.0
3.1
−41
4.0
4.0
+6.1
9
12
0.5
310
2
Max
Unit
625
200
MHz
MSPS
ns
ns
ps rms
4.9
4.9
+33
ns
ns
ns
Cycles
Cycles
µs
µs
Cycles
Conversion rate is the clock rate after the divider.
See Figure 2 for details.
Wake-up time is dependent on the value of the decoupling capacitors.
Data Output Timing Diagram
tA
N–1
N+4
N+5
N
N+3
VIN
N+1
tCH
tCL
N+2
1/fS
CLK+
CLK–
tDCO
DCO+
DCO–
tSKEW
tPD
D10+AB (MSB)
D10A
D10B
D10A
D10B
D10A
D10B
D10A
D10B
D10A
D10B
D10A
D10B
D10A
D10B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0A
D0B
D0+AB (LSB)
D0–AB (LSB)
Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B)
Rev. 0 | Page 9 of 36
09684-002
D10–AB (MSB)
AD6657A
Data Sheet
TIMING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Description
See Figure 3 for details
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
See Figure 60 for details, except where noted
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to
an output relative to the SCLK falling edge (not pictured in
Figure 60)
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge (not pictured in
Figure 60)
Min
Typ
0.24
0.40
10
ns
09684-003
tHSYNC
Figure 3. SYNC Input Timing Requirements
Rev. 0 | Page 10 of 36
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK+
SYNC
Unit
2
2
40
2
2
10
10
10
Sync Input Timing Diagram
tSSYNC
Max
Data Sheet
AD6657A
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
AVDD to AGND
DRVDD to AGND
VIN+x, VIN−x to AGND
CLK+, CLK− to AGND
SYNC to AGND
VCMx to AGND
CSB to AGND
SCLK to AGND
SDIO to AGND
PDWN to AGND
MODE to AGND
Digital Outputs to AGND
DCO+AB, DCO−AB, DCO+CD,
DCO−CD to AGND
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
The values in Table 7 are per JEDEC JESD51-7 and JEDEC
JESD25-5 for a 2S2P test board. Typical θJA is specified for a
4-layer printed circuit board (PCB) with a solid ground plane.
As shown in Table 7, airflow improves heat dissipation, which
reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces θJA.
Table 7.
Package Type
144-Ball CSP_BGA
Airflow
Velocity
0 m/s
1 m/s
2.5 m/s
θJA1
26.9
24.2
23.0
θJC2
8.9
θJB3
6.6
Unit
°C/W
°C/W
°C/W
1
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-STD 883, Method 1012.1.
3
Per JEDEC JESD51-8 (still air).
2
−40°C to +85°C
The values in Table 8 are from simulations. The PCB is a JEDEC
multilayer board. Thermal performance for actual applications
requires careful inspection of the conditions in the application
to determine whether they are similar to those assumed in these
calculations.
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 8.
Package Type
144-Ball CSP_BGA
ESD CAUTION
Rev. 0 | Page 11 of 36
Airflow
Velocity
0 m/s
1 m/s
2.5 m/s
JB
14.4
14.0
13.9
JT
0.23
0.50
0.53
Unit
°C/W
°C/W
°C/W
AD6657A
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
A
AGND
VIN+C
VIN–C
AGND
AVDD
CLK–
CLK+
AVDD
AGND
VIN–B
VIN+B
AGND
B
AGND
AGND
VCMC
AGND
AVDD
AVDD
AVDD
AVDD
AGND
VCMB
AGND
AGND
C
VIN+D
AGND
AGND
CSB
SDIO
SCLK
PDWN
SYNC
MODE
AGND
AGND
VIN+A
D
VIN–D
VCMD
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AGND
VCMA
VIN–A
E
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AGND
F
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
G
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
H
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
J
D0–CD
D2–CD
D4–CD
D6–CD
D8–CD
D10–CD
D0–AB
D2–AB
D4–AB
D6–AB
D8–AB
D10–AB
K
D0+CD
D2+CD
D4+CD
D6+CD
D8+CD
D10+CD
D0+AB
D2+AB
D4+AB
D6+AB
D8+AB
D10+AB
L
D1–CD
D3–CD
D5–CD
D7–CD
D9–CD
DCO–CD
D1–AB
D3–AB
D5–AB
D7–AB
D9–AB
DCO–AB
M
D1+CD
D3+CD
D5+CD
D7+CD
D9+CD
DCO+CD
D1+AB
D3+AB
D5+AB
D7+AB
D9+AB
DCO+AB
09684-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No.
A5, A8, B5 to B8, D4 to
D9, E2 to E11
A1, A4, A9, A12, B1, B2,
B4, B9, B11, B12, C2, C3,
C10, C11, D3, D10, E1,
E12, F1 to F12
H1 to H12
G1 to G12
A7
A6
C12
D12
D11
A11
A10
B10
A2
A3
B3
C1
D1
D2
K7
J7
M7
L7
K8
J8
M8
L8
K9
J9
Mnemonic
AVDD
Type
Supply
Description
Analog Power Supply. 1.8 V nominal.
AGND
Ground
Analog Ground.
DRVDD
DRGND
CLK+
CLK−
VIN+A
VIN−A
VCMA
VIN+B
VIN−B
VCMB
VIN+C
VIN−C
VCMC
VIN+D
VIN−D
VCMD
D0+AB
D0−AB
D1+AB
D1−AB
D2+AB
D2−AB
D3+AB
D3−AB
D4+AB
D4−AB
Supply
Ground
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Digital Output Driver Supply. 1.8 V nominal.
Digital Output Driver Ground.
ADC Clock Input—True.
ADC Clock Input—Complement.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Common-Mode Level Bias Output for Analog Input Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Common-Mode Level Bias Output for Analog Input Channel B.
Differential Analog Input Pin (+) for Channel C.
Differential Analog Input Pin (−) for Channel C.
Common-Mode Level Bias Output for Analog Input Channel C.
Differential Analog Input Pin (+) for Channel D.
Differential Analog Input Pin (−) for Channel D.
Common-Mode Level Bias Output for Analog Input Channel D.
Channel A and Channel B LVDS Output Data 0—True.
Channel A and Channel B LVDS Output Data 0—Complement.
Channel A and Channel B LVDS Output Data 1—True.
Channel A and Channel B LVDS Output Data 1—Complement.
Channel A and Channel B LVDS Output Data 2—True.
Channel A and Channel B LVDS Output Data 2—Complement.
Channel A and Channel B LVDS Output Data 3—True.
Channel A and Channel B LVDS Output Data 3—Complement.
Channel A and Channel B LVDS Output Data 4—True.
Channel A and Channel B LVDS Output Data 4—Complement.
Rev. 0 | Page 12 of 36
Data Sheet
Pin No.
M9
L9
K10
J10
M10
L10
K11
J11
M11
L11
K12
J12
M12
L12
K1
J1
M1
L1
K2
J2
M2
L2
K3
J3
M3
L3
K4
J4
M4
L4
K5
J5
M5
L5
K6
J6
M6
L6
C9
C8
C7
C6
C5
C4
AD6657A
Mnemonic
D5+AB
D5−AB
D6+AB
D6−AB
D7+AB
D7−AB
D8+AB
D8−AB
D9+AB
D9−AB
D10+AB
D10−AB
DCO+AB
DCO−AB
D0+CD
D0−CD
D1+CD
D1−CD
D2+CD
D2−CD
D3+CD
D3−CD
D4+CD
D4−CD
D5+CD
D5−CD
D6+CD
D6−CD
D7+CD
D7−CD
D8+CD
D8−CD
D9+CD
D9−CD
D10+CD
D10−CD
DCO+CD
DCO−CD
MODE
SYNC
PDWN
SCLK
SDIO
CSB
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input/Output
Input
Description
Channel A and Channel B LVDS Output Data 5—True.
Channel A and Channel B LVDS Output Data 5—Complement.
Channel A and Channel B LVDS Output Data 6—True.
Channel A and Channel B LVDS Output Data 6—Complement.
Channel A and Channel B LVDS Output Data 7—True.
Channel A and Channel B LVDS Output Data 7—Complement.
Channel A and Channel B LVDS Output Data 8—True.
Channel A and Channel B LVDS Output Data 8—Complement.
Channel A and Channel B LVDS Output Data 9—True.
Channel A and Channel B LVDS Output Data 9—Complement.
Channel A and Channel B LVDS Output Data 10—True.
Channel A and Channel B LVDS Output Data 10—Complement.
Data Clock LVDS Output for Channel A and Channel B—True.
Data Clock LVDS Output for Channel A and Channel B—Complement.
Channel C and Channel D LVDS Output Data 0—True.
Channel C and Channel D LVDS Output Data 0—Complement.
Channel C and Channel D LVDS Output Data 1—True.
Channel C and Channel D LVDS Output Data 1—Complement.
Channel C and Channel D LVDS Output Data 2—True.
Channel C and Channel D LVDS Output Data 2—Complement.
Channel C and Channel D LVDS Output Data 3—True.
Channel C and Channel D LVDS Output Data 3—Complement.
Channel C and Channel D LVDS Output Data 4—True.
Channel C and Channel D LVDS Output Data 4—Complement.
Channel C and Channel D LVDS Output Data 5—True.
Channel C and Channel D LVDS Output Data 5—Complement.
Channel C and Channel D LVDS Output Data 6—True.
Channel C and Channel D LVDS Output Data 6—Complement.
Channel C and Channel D LVDS Output Data 7—True.
Channel C and Channel D LVDS Output Data 7—Complement.
Channel C and Channel D LVDS Output Data 8—True.
Channel C and Channel D LVDS Output Data 8—Complement.
Channel C and Channel D LVDS Output Data 9—True.
Channel C and Channel D LVDS Output Data 9—Complement.
Channel C and Channel D LVDS Output Data 10—True.
Channel C and Channel D LVDS Output Data 10—Complement.
Data Clock LVDS Output for Channel C and Channel D—True.
Data Clock LVDS Output for Channel C and Channel D—Complement.
Mode Select Pin. Logic low enables NSR; logic high disables NSR.
Digital Synchronization Pin.
Power-Down Input (Active High).
SPI Clock.
SPI Data.
SPI Chip Select (Active Low).
Rev. 0 | Page 13 of 36
AD6657A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32,000 sample, TA = 25°C,
unless otherwise noted.
0
185MSPS
140.3MHz @ –1dBFS
SNR = 65.4dB (66.4dBFS)
SFDR = 90dBc
–20
AMPLITUDE (dBFS)
–20
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–40
–60
THIRD HARMONIC
SECOND HARMONIC
–80
0
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
–120
09684-005
–120
0
Figure 5. Single Tone FFT, fIN = 10.3 MHz
0
0
–40
–60
THIRD HARMONIC
–80
185MSPS
200.3MHz @ –1dBFS
SNR = 64.9dB (65.9dBFS)
SFDR = 84dBc
–20
AMPLITUDE (dBFS)
SECOND HARMONIC
–100
–40
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–100
0
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
–120
09684-006
–120
0
Figure 6. Single Tone FFT, fIN = 50.3 MHz
Figure 9. Single Tone FFT, fIN = 200.3 MHz
0
0
185MSPS
70.3MHz @ –1dBFS
SNR = 65.5dB (66.5dBFS)
–20 SFDR = 88dBc
185MSPS
230.3MHz @ –1dBFS
SNR = 66.1dB (65.1dBFS)
SFDR = 84dBc
AMPLITUDE (dBFS)
–20
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–100
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–100
–120
0
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
09684-007
AMPLITUDE (dBFS)
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
09684-009
AMPLITUDE (dBFS)
Figure 8. Single Tone FFT, fIN = 140.3 MHz
185MSPS
50.3MHz @ –1dBFS
SNR = 65.6dB (66.6dBFS)
SFDR = 92.0dBc
–20
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
09684-008
–100
–100
Figure 7. Single Tone FFT, fIN = 70.3 MHz
–120
0
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
Figure 10. Single Tone FFT, fIN = 230.3 MHz
Rev. 0 | Page 14 of 36
09684-010
AMPLITUDE (dBFS)
0
185MSPS
10.3MHz @ –1dBFS
SNR = 65.6dB (66.6dBFS)
SFDR = 94.0dBc
Data Sheet
AD6657A
0
0
185MSPS
247.3MHz @ –1dBFS
SNR = 66dB (65dBFS)
–20 SFDR = 83dBc
185MSPS
230.3MHz @ –1dBFS
NSR 33% BW MODE, TW = 17
SNR = 70.8dB (72.5dBFS)
SFDR = 93.7dBc
–20
AMPLITUDE (dBFS)
SECOND HARMONIC
–60
THIRD HARMONIC
–80
–100
SECOND HARMONIC
–60
THIRD HARMONIC
–80
–100
–120
0
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
–140
09684-011
–120
0
Figure 11. Single Tone FFT, fIN = 247.3 MHz
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
09684-014
AMPLITUDE (dBFS)
–40
–40
Figure 14. Single Tone FFT, fIN = 230.3 MHz, NSR Enabled
in 33% BW Mode, Tuning Word = 17
0
0
185MSPS
305.3MHz @ –1dBFS
SNR = 64.9dB (65.9dBFS)
–20 SFDR = 80dBc
185MSPS
230.3MHz @ –1dBFS
NSR 36% BW MODE, TW = 14
SNR = 70.3dB (71.3dBFS)
SFDR = 93.4dBc
–20
AMPLITUDE (dBFS)
THIRD HARMONIC
–60
SECOND HARMONIC
–80
–100
–60
–100
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
–140
0
Figure 12. Single Tone FFT, fIN = 305.3 MHz
0
Figure 15. Single Tone FFT, fIN = 230.3 MHz, NSR Enabled
in 36% BW Mode, Tuning Word = 14
100
185MSPS
140.3MHz @ –1dBFS
NSR 22% BW MODE, TW = 28
SNR = 73.4dB (74.9dBFS)
SFDR = 91dBc
90
SFDR (dBFS)
80
SNR/SFDR (dBc AND dBFS)
–20
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
–40
–60
THIRD HARMONIC
–80
–100
SNR (dBFS)
70
60
50
SFDR (dBc)
40
30
SNR (dBc)
20
–120
INPUT AMPLITUDE (dBFS)
Figure 16. Single Tone SNR/SFDR vs. Input Amplitude (AIN),
fIN = 70.3 MHz
Figure 13. Single Tone FFT, fIN = 140.3 MHz, NSR Enabled
in 22% BW Mode, Tuning Word = 28
Rev. 0 | Page 15 of 36
0
09684-016
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
0
–75
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
–80
0
–85
–140
09684-013
10
09684-015
0
09684-012
–120
–120
AMPLITUDE (dBFS)
THIRD HARMONIC
–80
–90
AMPLITUDE (dBFS)
–40
–40
AD6657A
Data Sheet
100
100
90
95
SFDR (dBFS)
SFDR (dBc)
90
SNR/SFDR (dBFS AND dBc)
SNR (dBFS)
70
60
50
SFDR (dBc)
40
30
SNR (dBc)
20
10
80
75
70
SNR (dBFS)
65
60
0
INPUT AMPLITUDE (dBFS)
50
30.00
09684-017
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
55
–85
–90
0
85
Figure 17. Single Tone SNR/SFDR vs. Input Amplitude (AIN),
fIN = 140.3 MHz
51.25
72.50
93.75 115.00 136.25 157.50 178.75 200.00
SAMPLE RATE (MSPS)
09684-020
SNR/SFDR (dBc AND dBFS)
80
Figure 20. Single Tone SNR/SFDR vs. Sample Rate (fS),
fIN = 70.3 MHz
95
95
SFDR (dBc)
90
SNR/SFDR (dBFS AND dBc)
85
80
75
70
SNR (dBFS)
65
75
70
65
SNR (dBFS)
60
Figure 18. Single Tone SNR/SFDR vs. Input Frequency (fIN),
1.75 V p-p Full Scale
51.25
72.50
93.75 115.00 136.25 157.50 178.75 200.00
SAMPLE RATE (MSPS)
09684-021
50
30.00
09684-018
400
380
360
340
320
300
280
260
240
220
200
180
160
140
120
100
INPUT FREQUENCY (MHz)
Figure 21. Single Tone SNR/SFDR vs. Sample Rate (fS),
fIN = 140.3 MHz
95
0
90
185MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
SFDR = 88.5dBc
–20
SFDR (dBc)
AMPLITUDE (dBFS)
85
80
75
70
–40
–60
–80
SNR (dBFS)
09684-019
INPUT FREQUENCY (MHz)
400
380
360
340
320
300
280
260
240
220
200
180
160
140
–120
120
60
100
–100
80
65
60
SNR/SFDR (dBFS AND dBc)
SFDR (dBc)
80
55
80
60
60
85
0
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
Figure 22. Two Tone FFT, fIN1 = 169.1 MHz and fIN2 = 172.1 MHz
Figure 19. Single Tone SNR/SFDR vs. Input Frequency (fIN),
2.0 V p-p Full Scale
Rev. 0 | Page 16 of 36
09684-122
SNR/SFDR (dBFS AND dBc)
90
Data Sheet
AD6657A
0.20
0
0.15
0.10
SFDR (dBc)
–40
DNL ERROR (LSB)
SFDR/IMD3 (dBc AND dBFS)
–20
IMD3 (dBc)
–60
–80
0.05
0
–0.05
SFDR (dBFS)
–0.10
–100
–0.15
–78
–66
–54
–42
–30
INPUT AMPLITUDE (dBFS)
–18
–6
–0.20
09684-123
–120
–90
0
500
Figure 23. Two Tone SFDR/IMD3 vs. Input Amplitude (AIN),
fIN1 = 169.1 MHz and fIN2 = 172.1 MHz
1000
OUTPUT CODE
1500
2000
09684-126
IMD3 (dBFS)
Figure 26. DNL, fIN = 30.3 MHz
69
2,500,000
68
67
66
1,500,000
SNR (dBFS)
NUMBER OF HITS
2,000,000
1,000,000
65
64
63
62
500,000
N–3
N–2
N–1
N
N+1
OUTPUT CODE
N+2
09684-124
0
N+3
Figure 24. Grounded Input Histogram
0.8
0.6
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
1000
OUTPUT CODE
1500
2000
09684-125
INL ERROR (LSB)
0.4
500
35
40
45
50
55
DUTY CYCLE (%)
60
65
Figure 27. SNR vs. Duty Cycle, fIN = 10.3 MHz
1.0
0
60
30
Figure 25. INL, fIN = 30.3 MHz
Rev. 0 | Page 17 of 36
70
09684-127
61
AD6657A
Data Sheet
EQUIVALENT CIRCUITS
AVDD
350Ω
SCLK
OR
PDWN
30kΩ
09684-022
09684-026
VIN
Figure 28. Equivalent Analog Input Circuit
Figure 32. Equivalent SCLK and PDWN Input Circuit
AVDD
AVDD
AVDD
30kΩ
AVDD
0.9V
15kΩ
CLK–
09684-023
09684-027
15kΩ
CLK+
350Ω
CSB
OR
MODE
Figure 33. Equivalent CSB and MODE Input Circuit
Figure 29. Equivalent Clock Input Circuit
DRVDD
DRVDD
V+
V–
DATAOUT+
V–
SDIO
V+
350Ω
09684-024
30kΩ
Figure 34. Equivalent SDIO Circuit
Figure 30. Equivalent LVDS Output Circuit
AVDD
AVDD
SYNC
0.9V
08557-025
16kΩ
0.9V
Figure 31. Equivalent SYNC Input Circuit
Rev. 0 | Page 18 of 36
09684-028
DATAOUT–
Data Sheet
AD6657A
THEORY OF OPERATION
The AD6657A architecture consists of a quad front-end sampleand-hold circuit, followed by a pipelined, switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. Alternately,
the 14-bit result can be processed through the NSR block before
it is sent to the digital correction logic.
The pipelined architecture permits the first stage to operate on
a new input sample and the remaining stages to operate on the
preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage
simply consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-ended
modes. The output staging block aligns the data, corrects errors,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the output
drive current. During power-down, the output buffers go into a
high impedance state.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications,
any shunt capacitors should be reduced. In combination with
the driving source impedance, the shunt capacitors limit the
input bandwidth. For more information on this subject, see the
AN-742 Application Note, Frequency Domain Response of
Switched-Capacitor ADCs; AN-827 Application Note, A Resonant
Approach to Interfacing Amplifiers to Switched-Capacitor ADCs;
and the Analog Dialogue article, “Transformer-Coupled Front-End
for Wideband A/D Converters” (see www.analog.com).
BIAS
S
S
CFB
CS
VIN+
CPAR2
CPAR1
H
S
S
CS
VIN–
CPAR1
CPAR2
S
CFB
S
BIAS
09684-029
ADC ARCHITECTURE
Figure 35. Switched Capacitor Input
The AD6657A quad IF receiver can simultaneously digitize four
channels, making it ideal for diversity reception and digital predistortion (DPD) observation paths in telecommunication systems.
For best dynamic performance, match the source impedances
driving the VIN+ and VIN− pins.
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 × VREF.
Programming and control of the AD6657A are accomplished
using a 3-wire SPI-compatible serial interface.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6657A is a differential switched
capacitor circuit that has been designed for optimum performance while processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see Figure 35). When the input is switched
to sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
Input Common Mode
The analog inputs of the AD6657A are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. An on-board common-mode voltage reference is
included in the design and is available from the VCMx pins.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the VCMx pin voltage
(typically 0.5 × AVDD). The VCMx pins must be decoupled
to ground by a 0.1 µF capacitor.
Rev. 0 | Page 19 of 36
AD6657A
Data Sheet
Differential Input Configurations
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
Optimum performance is achieved when driving the AD6657A
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, and ADA4938-2 differential drivers
provide excellent performance and a flexible interface to the ADC.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD6657A. For applications in
which SNR is a key parameter, differential double balun coupling
is the recommended input configuration (see Figure 38). In this
configuration, the input is ac-coupled and the CML is provided to
each input through a 33 Ω resistor. These resistors compensate
for losses in the input baluns to provide a 50 Ω impedance to
the driver.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCMx pin of the AD6657A (see Figure 36), and the
driver can be configured in a Sallen-Key filter topology to provide
band limiting of the input signal.
15pF
200Ω
33Ω
90Ω
15Ω
VIN–
AVDD
5pF
33Ω
15Ω
VCM
VIN+
15pF
200Ω
09684-030
120Ω
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance and may need to be reduced
or removed. Table 10 lists recommended values to set the RC
network. At higher input frequencies, good performance can be
achieved by using a ferrite bead in series with a resistor and
removing the capacitors. However, these values are dependent
on the input signal and should be used as a starting guide only.
ADC
ADA4938-2
0.1µF
Figure 36. Differential Input Configuration Using the ADA4938-2
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 37. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
Table 10. Example RC Network
Frequency
Range
(MHz)
0 to 100
100 to 200
100 to 300
C2
R2
VIN+
R1
ADC
C1
R2
R1
0.1µF
1
VCM
VIN–
C2
C1 Differential
5 pF
5 pF
Remove
Figure 37. Differential Transformer-Coupled Configuration
C2
2V p-p
R1
R2
VIN+
33Ω
PA
S
S
P
ADC
C1
0.1µF
33Ω
0.1µF
R1
R2
VIN–
VCM
C2
Figure 38. Differential Double Balun Input Configuration
VCC
ANALOG INPUT
0.1µF 0Ω
16
1
8, 13
11
0.1µF
0.1µF
RD
RG
3
5
0.1µF 0Ω
VIN+
C
AD8352
10
4
ANALOG INPUT
R
200Ω
2
CD
C2 Shunt
(Each)
15 pF
10 pF
Remove
In this configuration, R1 is a ferrite bead with a value of 10 Ω @ 100 MHz.
0.1µF
0.1µF
R2 Series
(Each)
15 Ω
10 Ω
66 Ω
An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential
driver (see Figure 39). For more information, see the AD8352
data sheet.
09684-032
49.9Ω
09684-031
2V p-p
R1 Series
(Each)
33 Ω
10 Ω
10 Ω1
0.1µF
200Ω
R
14
0.1µF
0.1µF
Figure 39. Differential Input Configuration Using the AD8352
Rev. 0 | Page 20 of 36
ADC
VIN–
VCM
09684-033
76.8Ω
VIN
Data Sheet
AD6657A
ANALOG
INPUT
XFMR 1:4 Z
ETC4-1T-7
33Ω
0.1µF
121Ω
0.1µF
0.1µF
121Ω
0.1µF
3.0kΩ
33Ω
0.1µF
3.0pF
ADC
INTERNAL
INPUT Z
VCM
09684-034
431nH
INPUT
Z = 50Ω
Figure 40. 1:4 Transformer Passive Configuration
1000pF
180nH 220nH
1µH
VPOS
301Ω
AD8376
5.1pF
1nF
1µH
165Ω
15pF
3.9pF
165Ω
VCM
1nF
1000pF
AD6657A
3.0kΩ║3.0pF
68nH
180nH 220nH
09684-035
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
Figure 41. Active Front-End Configuration Using the AD8376
For the popular IF band of 140 MHz, Figure 40 shows an
example of a 1:4 transformer passive configuration where a
differential inductor is used to resonate with the internal input
capacitance of the AD6657A. This configuration realizes excellent
noise and distortion performance. Figure 41 shows an example
of an active front-end configuration using the AD8376 dual variable gain amplifier (VGA). This configuration is recommended
when signal gain is required.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD6657A sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal is
typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require
no external bias (see Figure 42).
Figure 43 and Figure 44 show two preferred methods for clocking
the AD6657A (at clock rates of up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer configuration is recommended for clock frequencies from 10 MHz to
200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD6657A
to approximately 0.8 V p-p differential. This limit helps to prevent
the large voltage swings of the clock from feeding through to
other portions of the AD6657A, yet preserves the fast rise and
fall times of the signal that are critical to a low jitter performance.
AVDD
ADT1-1WT, 1:1Z
0.1µF
XFMR
0.1µF
CLOCK
INPUT
1.2V
ADC
0.1µF
CLK–
CLK–
SCHOTTKY
DIODES:
HSMS2822
0.1µF
2pF
Figure 43. Transformer-Coupled Differential Clock (Up to 200 MHz)
09684-036
2pF
09684-037
CLK+
CLK+
100Ω
50Ω
Figure 42. Equivalent Clock Input Circuit
1nF
CLOCK
INPUT
The AD6657A has a very flexible clock input structure. The
clock input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern (see the Jitter Considerations section).
Rev. 0 | Page 21 of 36
0.1µF
CLK+
50Ω
ADC
0.1µF
1nF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 44. Balun-Coupled Differential Clock (Up to 625 MHz)
09684-038
Clock Input Options
AD6657A
Data Sheet
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 45. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent
jitter performance.
CLK+ can be driven directly from a CMOS gate. Although
the CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.6 V, making the
selection of the drive logic voltage very flexible (see Figure 48).
VCC
0.1µF
0.1µF
CLOCK
INPUT
CLK+
0.1µF
CLOCK
INPUT
50kΩ
AD951x
PECL DRIVER
100Ω
240Ω
0.1µF
100Ω
ADC
0.1µF
Clock Duty Cycle
09684-040
CLK–
50kΩ
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor in
parallel with a 39 kΩ resistor (see Figure 47).
50Ω1
AD951x
CMOS DRIVER
OPTIONAL
0.1µF
100Ω
1kΩ
CLK+
ADC
150Ω
39kΩ
RESISTOR IS OPTIONAL.
Figure 47. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
09684-041
CLK–
0.1µF
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic performance characteristics.
The AD6657A contains a DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD6657A. Noise and distortion performance are nearly flat for
a wide range of duty cycles with the DCS enabled.
VCC
1kΩ
RESISTOR IS OPTIONAL.
The AD6657A clock divider can be synchronized using the
external SYNC input. Bit 1 of Register 0x3A enables the clock
divider to be resynchronized on every SYNC signal. A valid
SYNC causes the clock divider to reset to its initial state. This
synchronization feature allows multiple parts to have their clock
dividers aligned to guarantee simultaneous input sampling.
0.1µF
AD951x
LVDS DRIVER
150Ω
Figure 48. Single-Ended 3.3 V CMOS Input Clock (Up to 200 MHz)
The AD6657A contains an input clock divider with the ability to
divide the input clock by integer values from 1 to 8.
Figure 46. Differential LVDS Sample Clock (Up to 625 MHz)
CLOCK
INPUT
ADC
Input Clock Divider
CLK+
0.1µF
CLK+
CLK–
09684-039
240Ω
CLOCK
INPUT
50kΩ
1kΩ
0.1µF
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 46. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock
drivers offer excellent jitter performance.
0.1µF
OPTIONAL 0.1µF
100Ω
0.1µF
Figure 45. Differential PECL Sample Clock (Up to 625 MHz)
CLOCK
INPUT
AD951x
CMOS DRIVER
ADC
CLK–
50kΩ
50Ω1
1kΩ
09684-042
0.1µF
CLOCK
INPUT
Jitter in the rising edge of the input is of paramount concern and
is not easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates at less than
40 MHz nominally. The loop has a time constant associated with
it that must be considered in applications in which the clock
rate can change dynamically. A wait time of 1.5 µs to 5 µs is
required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal. During the
time period that the loop is not locked, the DCS loop is bypassed,
and internal device timing is dependent on the duty cycle of the
input clock signal.
Rev. 0 | Page 22 of 36
Data Sheet
AD6657A
In the equation, the rms aperture jitter represents the clock
input jitter specification. IF undersampling applications are
particularly sensitive to jitter, as shown in Figure 49.
0.55
1.2
0.50
IAVDD
1.1
0.45
1.0
0.40
0.9
TOTAL POWER
0.8
0.30
0.7
0.6
0.25
0.5
0.20
0.4
0.3
IDRVDD
0.15
0.10
80
0.2
75
0.05
0.1
0
0
30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
0.05ps
SAMPLING FREQUENCY (MSPS)
Figure 50. Power and Current vs. Sampling Frequency
70
SNR (dBc)
0.35
CURRENT (A)
SNRHF = −10log[(2π × fIN × tJRMS)2 + 10(−SNRLF/10) ]
0.60
1.4
1.3
TOTAL POWER (W)
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR from the low frequency
SNR (SNRLF) at a given input frequency (fIN) due to jitter (tJRMS)
can be calculated by
1.5
09684-050
Jitter Considerations
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD6657A is placed in power-down
mode. In this state, the ADC typically dissipates 4.5 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD6657A to its normal operating mode. Note that PDWN is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
0.20ps
65
60
0.50ps
55
1.00ps
1
10
100
INPUT FREQUENCY (MHz)
1k
09684-043
1.50ps
50
Figure 49. SNR vs. Input Frequency and Jitter
In cases where aperture jitter may affect the dynamic range of
the AD6657A, treat the clock input as an analog signal. Separate
power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step. Refer to the AN-501
Application Note and AN-756 Application Note for more information about jitter performance as it relates to ADCs (available at
www.analog.com).
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD6657A is proportional to its clock
rate (see Figure 50). The digital power dissipation does not vary
significantly because it is determined primarily by the DRVDD
supply and the bias current of the LVDS drivers.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 50 was
obtained using the same operating conditions as those used in
the Typical Performance Characteristics section, with a 5 pF
load on each output driver.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and must be recharged when returning to
normal operation. As a result, wake-up time is related to the
time spent in power-down mode; shorter power-down cycles
result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Descriptions section for more details.
CHANNEL/CHIP SYNCHRONIZATION
The AD6657A has a SYNC input that offers the user flexible
synchronization options for synchronizing the clock divider. The
clock divider sync feature is useful for guaranteeing synchronized
sample clocks across multiple ADCs.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, externally synchronize the SYNC input signal to
the input clock signal, meeting the setup and hold times shown
in Table 5. Drive the SYNC input using a single-ended CMOS
type signal.
Rev. 0 | Page 23 of 36
AD6657A
Data Sheet
DIGITAL OUTPUTS
The AD6657A output drivers are configured to interface with
LVDS outputs using a DRVDD supply voltage of 1.8 V. The
output bits are DDR LVDS as shown in Figure 2. Applications
that require the ADC to drive large capacitive loads or large
fanouts may require external buffers or latches.
As described in the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI, the data format can be selected for
offset binary or twos complement when using the SPI control.
TIMING
The AD6657A provides latched data with a latency of
nine clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Minimize the length of the output data lines and minimize the
loads placed on them to reduce transients within the AD6657A
because these transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD6657A is 40 MSPS.
At clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD6657A provides a data clock output (DCO) signal
intended for capturing the data in an external register. The
output data for Channel A and Channel C is valid when DCO
is high; the output data for Channel B and Channel D is valid
when DCO is low (see Figure 2).
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
000 0000 0000
000 0000 0000
100 0000 0000
111 1111 1111
111 1111 1111
Rev. 0 | Page 24 of 36
Twos Complement Mode
100 0000 0000
100 0000 0000
000 0000 0000
011 1111 1111
011 1111 1111
Data Sheet
AD6657A
NOISE SHAPING REQUANTIZER
The NSR feature can be independently controlled per channel
via the SPI or via the MODE pin.
Two different bandwidth modes are provided; the mode can be
selected from the SPI port. In each of the two modes, the center
frequency of the band can be tuned such that IFs can be placed
anywhere in the Nyquist band.
0
–20
–40
–60
THIRD HARMONIC
–80
–100
–120
22% BW MODE (>40 MHZ at 184.32 MSPS)
–140
0
The first bandwidth mode offers excellent noise performance
over 22% of the ADC sample rate (44% of the Nyquist band)
and can be centered by setting the NSR mode bits in the NSR
control register (Address 0x3C) to 000. In this mode, the useful
frequency range can be set using the 6-bit tuning word in the
NSR tuning word register (Address 0x3E).
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
Figure 51. 22% BW Mode, Tuning Word = 13
0
185MSPS
140.3MHz @ –1dBFS
NSR 22% BW MODE, TW = 28
SNR = 73.4dB (75.0dBFS)
SFDR = 91dBc
–20
–40
AMPLITUDE (dBFS)
There are 57 possible tuning words (TW); each step is 0.5% of
the ADC sample rate. The following three equations describe
the left band edge (f0), the channel center (fCENTER), and the right
band edge (f1), respectively.
fCENTER = f0 + 0.11 × fADC
–60
THIRD HARMONIC
–80
–100
–140
0
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
09684-052
–120
f1 = f0 + 0.22 × fADC
Figure 52. 22% BW Mode, Tuning Word = 28 (fS/4 Tuning)
0
185MSPS
140.3MHz @ –1dBFS
NSR 22% BW MODE, TW = 41
SNR = 73.4dB (75.0dBFS)
SFDR = 91dBc
–20
AMPLITUDE (dBFS)
–40
–60
THIRD HARMONIC
–80
–100
–120
–140
0
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
Figure 53. 22% BW Mode, Tuning Word = 41
Rev. 0 | Page 25 of 36
09684-053
f0 = fADC × .005 × TW
185MSPS
140.3MHz @ –1dBFS
NSR 22% BW MODE, TW = 13
SNR = 73.4dB (75.0dBFS)
SFDR = 91dBc
09684-051
When enabled, the NSR contributes an additional 0.6 dB of
loss to the input signal, such that a 0 dBFS input is reduced to
−0.6 dBFS at the output pins.
Figure 51 to Figure 53 show the typical spectrum that can be
expected from the AD6657A in the 22% BW mode for three
different tuning words.
AMPLITUDE (dBFS)
The AD6657A features a noise shaping requantizer (NSR) to allow
higher than an 11-bit SNR to be maintained in a subset of the
Nyquist band. The harmonic performance of the receiver is
unaffected by the NSR feature.
AD6657A
Data Sheet
33% BW MODE (>60 MHZ AT 184.32 MSPS)
0
–40
Figure 54 to Figure 56 show the typical spectrum that can be
expected from the AD6657A in the 33% BW mode for three
different tuning words.
185MSPS
140.3MHz @ –1dBFS
NSR 33% BW MODE, TW = 5
SNR = 70.9dB (72.5dBFS)
SFDR = 91dBc
AMPLITUDE (dBFS)
–40
–60
THIRD HARMONIC
–80
–100
–140
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
09684-154
–120
Figure 54. 33% BW Mode, Tuning Word = 5
0
185MSPS
140.3MHz @ –1dBFS
NSR 33% BW MODE, TW = 17
SNR = 71.1dB (72.7dBFS)
SFDR = 91dBc
–20
–60
THIRD HARMONIC
–80
–100
–120
–140
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
09684-055
AMPLITUDE (dBFS)
–40
0
–120
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
Figure 56. 33% BW Mode, Tuning Word = 17
f1 = f0 + 0.33 × fADC
0
–100
0
fCENTER = f0 + 0.165 × fADC
–20
THIRD HARMONIC
–80
–140
f0 = fADC × .005 × TW
0
–60
Figure 55. 33% BW Mode, Tuning Word = 17 (fS/4 Tuning)
Rev. 0 | Page 26 of 36
09684-056
There are 34 possible tuning words (TW); each step is 0.5% of
the ADC sample rate. The following three equations describe
the left band edge (f0), the channel center (fCENTER), and the right
band edge (f1), respectively.
–20
AMPLITUDE (dBFS)
The second bandwidth mode offers excellent noise performance
over 33% of the ADC sample rate (66% of the Nyquist band)
and can be centered by setting the NSR mode bits in the NSR
control register (Address 0x3C) to 001. In this mode, the useful
frequency range can be set using the 6-bit tuning word in the
NSR tuning word register (Address 0x3E).
185MSPS
140.3MHz @ –1dBFS
NSR 33% BW MODE, TW = 17
SNR = 70.9dB (72.5dBFS)
SFDR = 91dBc
Data Sheet
AD6657A
36% BW MODE (>65 MHZ AT 184.32 MSPS)
0
–40
0
Figure 57 to Figure 59 show the typical spectrum that can be
expected from the AD6657A in the 36% BW mode for three
different tuning words.
0
185MSPS
140.3MHz @ –1dBFS
NSR 36% BW MODE, TW = 0
SNR = 70.4dB (72.0dBFS)
SFDR = 91dBc
AMPLITUDE (dBFS)
MODE PIN
The MODE pin input allows convenient control of the NSR
feature. A logic low enables NSR mode and a logic high sets the
receiver to a straight 11-bit mode with NSR disabled. By default,
the MODE pin is pulled high internally to disable the NSR.
Each channel can be individually configured to ignore the
MODE pin state by writing to Bit 4 of the NSR control register
at Address 0x3C. Use of the NSR control register in conjunction
with the MODE pin allows for very flexible control of the NSR
feature on a per channel basis.
–40
–60
THIRD HARMONIC
–80
–100
–140
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
09684-057
–120
Figure 57. 36% BW Mode, Tuning Word = 0
0
185MSPS
140.3MHz @ –1dBFS
NSR 36% BW MODE, TW = 14
SNR = 70.4dB (72.0dBFS)
SFDR = 91dBc
–60
THIRD HARMONIC
–80
–100
–120
–140
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
09684-058
AMPLITUDE (dBFS)
–40
0
9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50
FREQUENCY (MHz)
Figure 59. 36% BW Mode, Tuning Word = 28
f1 = f0 + 0.36 × fADC
–20
–100
–140
fCENTER = f0 + 0.18 × fADC
0
THIRD HARMONIC
–80
–120
f0 = fADC × .005 × TW
–20
–60
09684-059
There are 28 possible tuning words (TW); each step is 0.5% of
the ADC sample rate. The following three equations describe
the left band edge (f0), the channel center (fCENTER), and the right
band edge (f1), respectively.
–20
AMPLITUDE (dBFS)
The third bandwidth mode offers excellent noise performance
over 36% of the ADC sample rate (72% of the Nyquist band)
and can be centered by setting the NSR mode bits in the NSR
control register (Address 0x3C) to 010. In this mode, the useful
frequency range can be set using the 6-bit tuning word in the
NSR tuning register (Address 0x3E).
185MSPS
140.3MHz @ –1dBFS
NSR 36% BW MODE, TW = 28
SNR = 70.4dB (72.0dBFS)
SFDR = 91dBc
Figure 58. 36% BW Mode, Tuning Word = 14 (fS/4 Tuning)
Rev. 0 | Page 27 of 36
AD6657A
Data Sheet
BUILT-IN SELF TEST (BIST) AND OUTPUT TEST
The AD6657A includes built-in test features designed to verify
the integrity of each channel and to facilitate board-level debugging. A built-in self test (BIST) feature is included that verifies
the integrity of the digital datapath of the AD6657A. Various
output test options are also provided to place predictable values
on the outputs of the AD6657A.
BIST
The BIST is a thorough test of the digital portion of the selected
AD6657A signal path. When enabled, the test runs from an
internal pseudorandom noise (PN) source through the digital
datapath starting at the ADC block output. The BIST sequence
runs for 512 cycles and stops. The BIST signature value for the
selected channel is written to Register 0x24 and Register 0x25.
If more than one channel is BIST enabled, the channel that
is first according to alphabetical order is written to the BIST
signature registers. For example, if Channel B and Channel C
are BIST enabled, the results from Channel B are written to the
BIST signature registers.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in Table 13. When an output
test mode is enabled, the analog section of the receiver is disconnected from the digital back-end blocks, and the test pattern
is run through the output formatting block. Some of the test
patterns are subject to output formatting. The seed value for the
PN sequence tests can be forced if the PN reset bits are used to
hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without an
analog signal (if present, the analog signal is ignored), but they
require an encode clock. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Rev. 0 | Page 28 of 36
Data Sheet
AD6657A
SERIAL PORT INTERFACE (SPI)
During an instruction phase, a 16-bit instruction is transmitted.
The first bit of the first byte in a serial data transfer frame indicates
whether a read command or a write command is issued. Data
follows the instruction phase, and its length is determined by
the W0 and W1 bits. All data is composed of 8-bit words.
The AD6657A serial port interface (SPI) allows the user to configure the receiver for specific functions or operations through a
structured internal register space. The SPI provides added flexibility
and customization, depending on the application. Addresses are
accessed via the serial port and can be written to or read from
via the port. Memory is organized into bytes that can be further
divided into fields, which are documented in the Memory Map
section. For detailed operational information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
The instruction phase determines whether the serial frame is a
read or write operation, allowing the serial port to be used both
to program the chip and to read the contents of the on-chip
memory. If the instruction is a read operation, the serial data
input/output (SDIO) pin changes direction from an input to an
output at the appropriate point in the serial frame.
CONFIGURATION USING THE SPI
Three pins define the SPI of the AD6657A: SCLK, SDIO, and
CSB (see Table 12). SCLK (a serial clock) is used to synchronize
the read and write data presented from and to the AD6657A.
SDIO (serial data input/output) is a bidirectional pin that allows
data to be sent to and read from the internal memory map
registers. CSB (chip select bar) is an active low control that
enables or disables the read and write cycles.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default mode on power-up and can be changed via
the SPI port configuration register. For more information about
this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
Table 12. Serial Port Interface Pins
Pin
SCLK
The pins described in Table 12 constitute the physical interface
between the user’s programming device and the serial port of
the AD6657A. The SCLK pin and the CSB pin function as
inputs when using the SPI interface. The SDIO pin is
bidirectional, functioning as an input during the write phase
and as an output during readback.
Function
Serial clock. Serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
Serial data input/output. Bidirectional pin that serves
as an input or an output, depending on the instruction
being sent and the relative position in the timing frame.
Chip select bar (active low). This control gates the read
and write cycles.
SDIO
CSB
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in Application Note AN-812, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The falling edge of the CSB pin, in conjunction with the rising
edge of the SCLK pin, determines the start of the framing. An
example of the serial timing can be found in Figure 60 (for
symbol definitions, see Table 5).
The SPI port should not be active during periods when the full
dynamic performance of the AD6657A is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade AD6657A performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD6657A to prevent these signals from transitioning at the receiver inputs during critical sampling periods.
CSB can be held low indefinitely, which permanently enables
the device; this is called streaming. CSB can stall high between
bytes to allow for additional external timing. When CSB is tied
high, SPI functions are placed in high impedance mode.
tH
tCLK
tHIGH
tDS
tDH
tS
tLOW
CSB
SCLK DON’T
CARE
DON’T
CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 60. Serial Port Interface Timing Diagram
Rev. 0 | Page 29 of 36
D4
D3
D2
D1
D0
DON’T CARE
09684-054
SDIO
DON’T CARE
AD6657A
Data Sheet
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
Each row in the memory map register table has eight bit locations (see Table 13). The memory map is roughly divided into
four sections: the chip configuration registers (Address 0x00
and Address 0x01); the channel index and transfer registers
(Address 0x05 and Address 0xFF); the ADC function registers,
including setup, control, and test (Address 0x08 to Address 0x25);
and the digital feature control registers (Address 0x3A to
Address 0x3E).
An explanation of logic level terminology follows:
The memory map register table (see Table 13) provides the
default hexadecimal value for each hexadecimal address shown.
The column with the heading (MSB) Bit 7 is the start of the
default hexadecimal value given. The AN-877 Application Note,
Interfacing to High Speed ADCs via SPI, documents the functions
controlled by Register 0x00 to Register 0xFF. The remaining
registers, Register 0x3A to Register 0x3E, are documented in
the Memory Map Register Descriptions section.
Open Locations
All address and bit locations that are not included in Table 13 are
not currently supported for this device. Unused bits of a valid
address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
After the AD6657A is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (see Table 13).


“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x3E are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, thereby setting the
transfer bit. This allows these registers to be updated internally
and simultaneously when the transfer bit is set. The transfer bit
is autoclearing.
Channel Specific Registers
Some channel setup functions, such as the NSR control function, can be programmed differently for each channel. In these
cases, channel address locations are internally duplicated for
each channel. These registers and bits are designated in Table 13
as local. Local registers and bits can be accessed by setting the
appropriate channel bits in Register 0x05.
If multiple channel bits are set, the subsequent write affects the
registers of all selected channels. In a read cycle, select a single
channel only to read one of the registers. If multiple channels are
selected during a SPI read cycle, the device returns the value for
Channel A only. Registers and bits designated as global in Table 13
affect the entire device or the channel features for which there are
no independent per channel settings. The settings in Register 0x05
do not affect the global registers and bits.
Rev. 0 | Page 30 of 36
Data Sheet
AD6657A
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr. Register
(MSB)
(Hex) Name
Bit 7
Chip Configuration Registers
0x00
SPI port
Open
configuration
(global)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
LSB first
Soft reset
1
1
Soft reset
LSB first
Open
0x01
0x18
Chip ID
(global)
Channel Index and Transfer Registers
0x05
Channel
Enable
index
output
port for
Channel C
and
Channel D
Enable
output
port for
Channel A
and
Channel B
Open
Open
Channel D
enable
Channel C
enable
Channel B
enable
Channel A
enable
0xCF
0xFF
Open
Open
Open
Open
Open
Open
Open
SW
transfer
1 = on
0 = off
(default)
0x00
ADC Function Registers
0x08
Power modes
Open
Open
Open
0x0B
Clock divide
(global)
Open
Open
Open
Open
External
powerdown pin
function
(global)
0 = full
powerdown
1=
standby
Clock divide phase
000 = 0 input clock cycles delayed
001 = 1 input clock cycle delayed
010 = 2 input clock cycles delayed
0x0C
Shuffle mode
(local)
Open
Open
Open
Open
Transfer
8-bit chip ID, Bits[7:0]
AD6657A = 0x7B (default)
Default
Value
(Hex)
Open
Open
Rev. 0 | Page 31 of 36
0x7B
Internal power-down
mode (local)
00 = normal operation
(default)
01 = full power-down
10 = standby
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Shuffle mode enable
00 = shuffle disabled
01 = shuffle enabled
0x00
Comments
Nibbles are
mirrored so
that LSB first
or MSB first
mode is set
correctly,
regardless of
shift mode.
To control
this register,
all channel
index bits in
Register 0x05
must be set.
Read only.
Bits are set to
determine
which
channel on
the chip
receives the
next write
command;
applies to
local
registers.
Synchronously
transfers
data from
the master
shift register
to the slave.
Determines
generic
modes of
chip operation.
0x00
0x01
Enables or
disables
shuffle
mode.
AD6657A
Data Sheet
Addr.
(Hex)
0x0D
Register
Name
Test mode
(local)
(MSB)
Bit 7
Open
Bit 6
Open
Bit 5
Reset
long PN
generator
0 = on
1 = off
(default)
0x0E
BIST enable
(local)
Open
Open
Open
0x10
Offset adjust
(local)
Open
Open
0x14
Output mode
(local)
Open
Open
Open
0x15
Output
adjust
(local)
Open
Open
Open
0x16
Clock phase
control
(local)
Open
Open
0x17
DCO output
delay
(local)
Invert
DCO clock
0 = off
1 = on
DCO
delay
enable
0 = off
1 = on
Open
Open
0x18
VREF select
(global)
Open
Open
Open
Bit 4
Reset
short PN
generator
0 = on
1 = off
(default)
Bit 3
Open
Bit 2
(LSB)
Bit 0
Bit 1
Output test mode
000 = off (normal operation)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN sequence long
110 = PN sequence short
111 = 1/0 word toggle
Open
BIST
Open
Open
BIST reset
enable
0 = on
1 = on
1 = off
0 = off
(default)
(default)
Offset adjustment in LSBs from +127 to −128
(twos complement format)
011111 = +31 LSB
011110 = +30 LSB
011101 = +29 LSB
…
000010 = +2 LSB
000001 = +1 LSB
000000 = 0 LSB
…
111111 = −1 LSB
111110 = −2 LSB
111101 = −3 LSB
…
100001 = −31 LSB
100000 = −32 LSB
Output format (local)
Open
Output
Output
00 = offset binary
invert
enable
01 = twos
(local)
bar
complement
1 = on
(local)
0 = off
1 = off
0 = on
Open
Output port LVDS drive current
0000 = 3.72 mA
0001 = 3.5 mA (default)
0010 = 3.3 mA
0011 = 2.96 mA
0100 = 2.82 mA
0101 = 2.57 mA
0110 = 2.27 mA
0111 = 2.0 mA
1000 = 2.0 mA
Open
Open
Open
Open
Open
Output port DCO clock delay
00000 = 100 ps additional delay on the DCO pin
00001 = 200 ps additional delay on the DCO pin
00010 = 300 ps additional delay on the DCO pin
…
11101 = 3.0 ns additional delay on the DCO pin
11110 = 3.1 ns additional delay on the DCO pin
11111 = 3.2 ns additional delay on the DCO pin
Internal VREF full-scale adjustment
Main reference full-scale VREF adjustment
01111: internal 2.087 V p-p
…
00001: internal 1.772 V p-p
00000: internal 1.75 V p-p
…
11111: internal 1.727 V p-p
…
10000: internal 1.383 V p-p
Rev. 0 | Page 32 of 36
Default
Value
(Hex)
0x00
0x00
0x00
Comments
When set,
the test data
is placed on
the output
pins in place
of normal
data.
When Bit 0
is set, the
built-in self
test function
is initiated.
Device offset
trim.
0x00
Configures
the outputs
and the
format of
the data.
0x01
Output
current
adjustments.
0x00
When Bit 7
is set, clock
polarity is
reversed.
Enable DCO
delay and set
the delay
time.
0x00
0x00
Select
adjustments
for VREF.
Data Sheet
AD6657A
Addr.
(Hex)
0x24
Register
(MSB)
Name
Bit 7
BIST
signature LSB
(local)
0x25
BIST signature MSB
(local)
Digital Feature Control Registers
0x3A
Sync control
Open
(global)
Bit 6
Bit 5
Bit 4
Bit 3
BIST Signature[7:0]
Bit 2
Bit 1
Default
Value
(Hex)
0x00
Comments
Read only.
0x00
Read only.
Master
sync
enable
0 = off
1 = on
0x00
Control
register to
synchronize
the clock
divider.
NSR
enable
0 = off
1 = on
(used only
if
Bit 4 = 1;
otherwise
ignored)
0x00
Noise
shaping
requantizer
(NSR)
controls.
0x1C
NSR
frequency
tuning word.
(LSB)
Bit 0
BIST Signature[15:8]
Open
Open
Open
Open
MODE
pin
disable
0=
MODE
pin used
1=
MODE
pin disabled
0x3C
NSR control
(local)
Open
Open
0x3E
NSR tuning
word
(local)
Open
Open
Open
Clock
Clock divider
divider
sync mode
sync
0 = contienable
nuous
0 = off
1 = next sync
1 = on
mode, next
rising edge of
sync resets
clock divider
NSR mode
000 = 22% BW mode
001 = 33% BW mode
010 = 36% BW mode
NSR tuning word
See the Noise Shaping Requantizer section.
Equations for the tuning word are dependent on the NSR mode.
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled
in Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
NSR Control (Register 0x3C)
Bits[7:5]—Reserved
Bit 4—MODE Pin Disable
Sync Control (Register 0x3A)
Bits[7:3]—Reserved
Bit 4 specifies whether the selected channels are to be controlled
by the MODE pin. Local registers act on the channels that are
selected by the channel index register (Address 0x05).
Bit 2—Clock Divider Sync Mode
Bits[3:1]—NSR Mode
Bit 2 selects the mode of the clock divider sync function. When
Bit 2 is low, continuous sync mode is enabled. When Bit 2 is
high, the clock divider is reset on the next rising edge of the
sync signal. Subsequent rising edges of the sync signal are
ignored.
Bits[3:1] determine the bandwidth (BW) mode of the NSR.
When Bits[3:1] are set to 000, the NSR is configured for a 22%
BW mode that provides enhanced SNR performance over 22%
of the sample rate. When Bits[3:1] are set to 001, the NSR is
configured for a 33% BW mode that provides enhanced SNR
performance over 33% of the sample rate. When Bits[3:1] are
set to 010, the NSR is configured for a 36% BW mode that provides enhanced SNR performance over 36% of the sample rate.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions. If
the sync capability is not used, this bit should remain low
to conserve power.
Bit 0—NSR Enable
The NSR is enabled when Bit 0 is high and disabled when Bit 0
is low. Bit 0 is ignored unless the MODE pin disable bit (Bit 4)
is set.
Rev. 0 | Page 33 of 36
AD6657A
Data Sheet
NSR Tuning Word (Register 0x3E)
Bits[7:6]—Reserved
Bits[5:0]—NSR Tuning Word
The NSR tuning word sets the band edges of the NSR band. In
22% BW mode, there are 57 possible tuning words; in 33% BW
mode, there are 34 possible tuning words; in 36% BW mode,
there are 28 possible tuning words. For either mode, each step
represents 0.5% of the ADC sample rate. For the equations used
to calculate the tuning word based on the BW mode of
operation, see the Noise Shaping Requantizer section.
Rev. 0 | Page 34 of 36
Data Sheet
AD6657A
APPLICATIONS INFORMATION
DESIGN GUIDELINES
VCMx Pins
Before starting the design and layout of the AD6657A in a
system, it is recommended that the designer become familiar
with these guidelines, which discuss the special circuit
connections and layout requirements needed for certain pins.
The VCMx pins are provided to set the common-mode level
of the analog inputs. Decouple the VCMx pins to ground with a
0.1 μF capacitor, as shown in Figure 37.
Power and Ground Recommendations
The SPI port should not be active during periods when the full
dynamic performance of the AD6657A is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade AD6657A performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD6657A to prevent these signals from transitioning at the receiver inputs during critical sampling periods.
When connecting power to the AD6657A, it is recommended
that two separate 1.8 V supplies be used. Use one supply for
analog (AVDD); use a separate supply for the digital outputs
(DRVDD). The AVDD and DRVDD supplies should be isolated
with separate decoupling capacitors. Several different decoupling
capacitors can be used to cover both high and low frequencies.
Locate these capacitors close to the point of entry at the PCB
level and close to the pins of the part, with minimal trace length.
SPI Port
A single PCB ground plane is sufficient when using the AD6657A.
With proper decoupling and smart partitioning of the PCB
analog, digital, and clock sections, optimum performance is
easily achieved.
Rev. 0 | Page 35 of 36
AD6657A
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
A1 BALL
CORNER
10.10
10.00 SQ
9.90
A1 BALL
CORNER
12 11 10 9 8
7 6
5
4
3
2
1
A
B
C
D
8.80
BSC SQ
E
F
G
H
0.80
J
K
L
M
0.60
REF
TOP VIEW
BOTTOM VIEW
DETAIL A
*1.40 MAX
DETAIL A
0.65 MIN
0.25 MIN
0.50
COPLANARITY
0.45
0.20
0.40
BALL DIAMETER
10-21-2010-B
SEATING
PLANE
*COMPLIANT WITH JEDEC STANDARDS MO-275-EEAB-1
WITH EXCEPTION TO PACKAGE HEIGHT.
Figure 61. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD6657ABBCZ
AD6657ABBCZRL
AD6657AEBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
Package Option
BC-144-1
BC-144-1
Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09684-0-10/11(0)
www.analog.com/AD6657A
Rev. 0 | Page 36 of 36
Similar pages