ICST MK2049-34SITR 3.3 v communications clock pll Datasheet

MK2049-34
3.3 V Communications Clock PLL
Description
Features
The MK2049-34 is a Phase-Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a
reference, the MK2049-34 generates T1, E1, T3,
E3, ISDN, xDSL, and other communications
frequencies. This allows for the generation of
clocks frequency-locked and phase-locked to an
8 kHz backplane clock, simplifying clock
synchronization in communications systems. The
MK2049-34 can also accept a T1 or E1 input clock
and provide the same output for loop timing. All
outputs are frequency locked together and to the
input.
• Packaged in 20 pin SOIC
• 3.3 V ±5% operation
• Fixed I/O phase relationship on all selections
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock,
Loop Timing frequencies, or 10-36 MHz
• Locks to 8 kHz ±100 ppm (External mode)
• Buffer Mode allows jitter attenuation of
10–36 MHz input and x1/x0.5 or x2/x4 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and OC3 submultiples
• See the MK2049-01, -02, and -03 for more
selections at VDD = 5 V
This part also has a jitter-attenuated Buffer
capability. In this mode, the MK2049-34 is ideal
for filtering jitter from 27 MHz video clocks or
other clocks with high jitter.
ICS/MicroClock can customize these devices for
many other different frequencies. Contact your
ICS/MicroClock representative for more details.
Block Diagram
FS3:0
VDD
3
GND
3
4
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
External/
Loop Timing
Mux
Clock
Input
RES
Reference
X1
Crystal
Output
Buffer
CLK
Output
Buffer
CLK/2
Output
Buffer
Crystal
Oscillator
X2
FCAP
CAP1
8 kHz
(External
Mode only)
CAP2
1
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
Pin Assignment
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8K
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FS0
RES
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
20 pin (300 mil) SOIC
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8K
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RES
FS0
Type
I
XO
XI
P
P
P
O
O
O
I
I
I
P
P
LF
P
LF
I
Description
Frequency Select 1. Determines CLK input/outputs per tables on page 4.
Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.
Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.
Connect to +3.3V.
Filter Capacitor. Connect a 1000 pF ceramic capacitor to ground.
Connect to +3.3V.
Connect to ground.
Clock output determined by status of FS3:0 per tables on page 4.
Clock output determined by status of FS3:0 per tables on page 4. Always 1/2 of CLK.
Recovered 8 kHz clock output.
Frequency Select 2. Determines CLK input/outputs per tables on page 4.
Frequency Select 3. Determines CLK input/outputs per tables on page 4.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Connect to +3.3V.
Connect the loop filter ceramic capacitors and resistor between this pin and CAP2.
Connect to ground.
Connect the loop filter ceramic capacitors and resistor between this pin and CAP1.
Connect a 10-200kΩ resistor to ground. Contact ICS applications dept. at 408-297-1201 for the recommended value for your app.
Frequency Select 0. Determines CLK input/outputs per tables on page 4.
Type: XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter
connections
2
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
7
VDD+0.5
85
250
150
V
V
°C
°C
°C
3.45
V
V
V
V
V
V
mA
mA
pF
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
Referenced to GND
MK2049-34SI
Max of 10 seconds
-0.5
-40
-65
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH, CMOS level
Output High Voltage, VOH
Output Low Voltage
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance, FS3:0
3.15
2
3.3
0.8
IOH=-4 mA
IOH=-8 mA
IOL=8 mA
No Load, VDD=3.3 V
Each output
VDD-0.4
2.4
0.4
7
±50
5
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Frequency, External Mode
Input Clock Pulse Width
Propagation Delay
Output-Output Skew
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, High Time
Actual mean frequency error versus target
ICLK
8.000
10
ICLK to CLK
CLK to CLK/2
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2, except 8K
Any clock selection
0
40
0
6
150
2
2
60
0
kHz
ns
ns
ps
ns
ns
%
ppm
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
3
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
MK2049-34 Output Decoding Table – External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
CLK/2
CLK
8K
Crystal
1.544
2.048
22.368
17.184
19.44
16.384
17.664
18.688
7.68
10.752
10.24
38.88
3.088
4.096
44.736
34.368
38.88
32.768
35.328
37.376
15.36
21.504
20.48
77.76
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
12.352
12.288
11.184
11.456
9.72
8.192
17.664
9.344
15.36
10.752
10.24
9.72
MK2049-34 Output Decoding Table – Loop Timing Mode (MHz)
ICLK
1.544
2.048
FS3 FS2 FS1 FS0
1
1
0
0
0
0
0
1
CLK/2
CLK
8K
Crystal
1.544
2.048
3.088
4.096
N/A
N/A
12.352
12.288
MK2049-34 Output Decoding Table – Buffer Mode (MHz)
ICLK
19 - 36
10 - 18
FS3 FS2 FS1 FS0
1
1
1
1
1
1
0
1
CLK/2
CLK
8K
Crystal
ICLK/2
2*ICLK
ICLK
4*ICLK
N/A
N/A
ICLK/2
ICLK
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
4
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
OPERATING MODES
The MK2049-34 has three operating modes: External, Loop Timing, and Buffer. Although each mode
uses an input clock to generate various output clocks, there are important differences in their input and
crystal requirements.
External Mode
The MK2049-34 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse
as narrow as 10 ns is acceptable. In the MK2049-34, the rising edges of CLK and CLK/2 are both aligned
with the rising edge of the 8 kHz ICLK; refer to Figure 1 for more details.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1
and E1 inputs, the CLK/2 output will be the same as the input frequency, with CLK at twice the input
frequency.
Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a
wider range of input clocks. The input jitter is attenuated, and the outputs on CLK and CLK/2 also
provide the option of getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be
used to remove the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs.
INPUT AND OUTPUT SYNCHRONIZATION
As shown in the tables on page 4, the MK2049-34 offers a Zero Delay feature in all selections. There is an
internal feedback path between ICLK and the output clocks, providing a fixed phase relationship between
the input and output, a requirement in many communications systems.
The rising edge of ICLK will be aligned with the rising edges of CLK and CLK/2. (8 kHz is used in this
illustration, but the same is true for the selections in the Loop Timing and Buffer modes.)
ICLK (8 kHz)
CLK (MHz)
CLK/2(MHz)
Figure 1. MK2049-34 Input and Output Clock Waveforms
5
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
Measuring Zero Delay on the MK2049
The MK2049-34 produces low-jitter output clocks. In addition, this part has a very low bandwidth--on the
order of a few Hertz. Since most 8 kHz input clocks will have high jitter, this can make measuring the
input-to-output skew (zero delay feature) very difficult. The MK2049 is designed to reject the input jitter;
when the input and output clocks are both displayed on an oscilloscope, they may appear not to be locked
because the scope trigger point is constantly changing with the input jitter. In fact, the input and output
clocks probably are locked, and the MK2049 will have zero delay to the average position of the 8 kHz input
clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab frequency sources
are NOT SUITABLE for this since they have high jitter at low frequencies.
Frequency Locking to the Input
In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified
output frequency as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.
6
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
PC BOARD LAYOUT
A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins
are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as
possible and the two capacitors and resistor must be mounted next to the device as shown below. The
capacitor shown between pins 15 and 17, and the one between pins 4 and 7 are the power supply decoupling
capacitors. The high frequency output clocks on pins 8 and 9 should have a series termination of 33 Ω
connected close to the pin. Additional improvements will come from keeping all components on the same
side of the board, minimizing vias through other signal layers, and routing other signals away from the
MK2049. You may also refer to MAN05 for additional suggestions on layout of the crystal section.
The crystal traces should include pads for small capacitors from X1 and X2 to ground; these are used to
adjust the stray capacitance of the board to match the crystal load capacitance. The typical telecom reference
frequency is accurate to much less than 1 ppm, so the MK2049 may lock and run properly even if the board
capacitance is not adjusted with these fixed capacitors. However, ICS MicroClock recommends that the
adjustment capacitors be included to minimize the effects of variation in individual crystals, temperature,
and aging. The value of these capacitors (typically 0-4 pF) is determined once for a given board layout,
using the procedure described in the section titled “Determining the Crystal Frequency Adjustment
Capacitors”.
Optional;
see text
Cutout in ground and power plane.
Route all traces away from this area.
cap
G
cap
V
cap
resist.
resist.
cap
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
resist.
G
resist.
G
cap
cap
cap
V
V =connect to VDD
G =connect to GND
Figure 2. Typical MK2049-34 Layout
7
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
EXTERNAL COMPONENT SELECTION
The MK2049-34 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF must be connected between VDD and GND pins close to the chip (especially pins 4
and 7, 15 and 17), and 33 Ω series terminating resistors should be used on clock outputs with traces longer
than 1 inch (assuming 50 Ω traces). The selection of additional external components is described in the
following sections.
Loop Filter Components
The external loop filter should be connected between CAP1 and CAP2 as shown in Figure 3 below, and as
close to the chip as possible. High quality ceramic capacitors are recommended. DO NOT use any type of
polarized or electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Another
alternative is the Panasonic PPS polymer dielectric series; their part number for the 0.1 µF cap is
ECHU1C104JB5. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have
piezolectric properties allow mechanical vibration in the system to increase the output jitter because the
mechanical energy is converted directly to voltage noise on the VCO input.
CAP2
5.6 nF
CAP1
470 kΩ
0.1 µF
Figure 3. Loop Filter Component Values
(Typical component values are shown. Contact the ICS MicroClock applications
department at (408)297-1201 for the recommended values for your application)
Crystal Operation
The MK2049 operates by phase locking the input signal to a VCXO which consists of the special
recommended crystal and the integrated VCXO oscillator circuit on the MK2049. To achieve the best
performance and reliability, the layout guidelines shown on the previous page must be closely followed.
The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected
to it. The MK2049 has variable load capacitors on-chip which “pull”, or change the frequency of the crystal.
External stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To
achieve this, the layout should use short traces between the MK2049 and the crystal.
8
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
EXTERNAL COMPONENT SELECTION (continued)
Crystal Specifications
Parameter
Operating Temperature Range
Initial Accuracy at 25 C
Temperature stability
Aging, first year
Aging, 10 years
Load Capacitance
Shunt Capacitance, C0
Motional Capacitance, C1
C0/C1 ratio
Equivalent Series Resistance
Minimum
0
-20
-30
-5
-20
Typical
25
Maximum
70
20
30
5
20
Units
°C
ppm
ppm
ppm
ppm
7
none
250
35
pF
pF
none
Ohms
Note 1
none
*This ratio decreases for lower crystal frequencies.
Note 1: Nominal crystal load capacitance specifications varies with frequency. Contact
the ICS MicroClock applications department at (408)297-1201
Note 2: The third overtone mode of the crystal and all spurs must be >200 ppm away
from 3x the fundamental resonance shown in the table below.
For recommended crystal devices, please contact the ICS MicroClock application department
at 408-297-1201.
9
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
EXTERNAL COMPONENT SELECTION (continued)
Determining the Crystal Frequency Adjustment Capacitors
To determine the crystal adjustment capacitor values, you will need a PC board of your final layout, a
frequency counter capable of less than 1 ppm resolution and accuracy, two power supplies, and some samples
of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at
the specified load capacitance, CL .
To determine the value of the crystal capacitors:
1. Connect VDD of the MK2049 to 3.3 V. Connect pin 18 of the MK2049 to the second power supply.
Adjust the voltage on pin 18 to 0.0 V. Measure and record the frequency of the CLK or CLK/2 output .
2. Adjust the voltage on pin 18 to 3.3 V. Measure and record the frequency of the same output.
To calculate the centering error:
 (f3.3V − ftarget) + (f 0.0V - f target) 
Centering error = 106 
 - error xtal


ftarget
Where ftarget = 44.736000 MHz, for example, and errorxtal = actual initial accuracy (in ppm) of the
crystal being measured.
If the centering error is less than ±15 ppm, no adjustment is needed. If the centering error is more than
15 ppm negative, the PC board has too much stray capacitance and will need to be redone with a new layout
to reduce stray capacitance. (The crystal may be re-specified to a lower load capacitance instead. Contact ICS
MicroClock for details.) If the centering error is more than 15 ppm positive, add identical fixed centering
capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by:
External Capacitor = 2*(centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is
acceptably low (less than ±15 ppm).
The MicroClock Applications department can perform this procedure on your board. Call us at
408–295–9800, and we will arrange for you to send us a PC board (stuffed or unstuffed) and one of your
crystals. We will calculate the value of capacitors needed.
10
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MDS 2049-34 C
MK2049-34
3.3 V Communications Clock PLL
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
20 pin SOIC
E
H
INDEX
AREA
1
2
h x 45°
D
A1
e
B
Inches
Symbol Min
Max
A
-0.104
A1
0.0040
-B
0.013 0.020
C
0.007 0.013
D
0.496 0.512
E
0.291 0.299
e
.050 BSC
H
0.394 0.419
h
0.01
0.029
L
0.016 0.050
Millimeters
Min
Max
-2.65
0.10
-0.33
0.51
0.18
0.33
12.60
13.00
7.40
7.60
1.27 BSC
10.01
10.64
0.25
0.74
0.41
1.27
A
C
L
Ordering Information
Part/Order Number
Marking
Package
Temperature
MK2049-34SI
MK2049-34SITR
MK2049-34SI
MK2049-34SI
20 pin SOIC
Add Tape & Reel
-40 to 85 °C
-40 to 85 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any
ICS product for use in life support devices or critical medical instruments.
11
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MDS 2049-34 C