ON MC10H640 Pecl-ttl clock driver Datasheet

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
68030/040
PECL-TTL Clock Driver
MC10H640
MC100H640
The MC10H/100H640 generates the necessary clocks for the 68030,
68040 and similar microprocessors. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of part–to–part
skew, within–part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced to
+5.0V) for the input clock. TTL clocks are typically used in present MPU
systems. However, as clock speeds increase to 50MHz and beyond, the
inherent superiority of ECL (particularly differential ECL) as a means of
clock signal distribution becomes increasingly evident. The H640 also
uses differential PECL internally to achieve its superior skew
characteristic.
The H640 includes divide–by–two and divide–by–four stages, both to
achieve the necessary duty cycle skew and to generate MPU clocks as
required. A typical 50MHz processor application would use an input clock
running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz
(see Logic Symbol).
The 10H version is compatible with MECL 10H ECL logic levels,
while the 100H version is compatible with 100K levels (referenced
to +5.0V).
•
•
•
•
•
•
68030/040
PECL–TTL CLOCK
DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
Generates Clocks for 68030/040
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single +5.0V Supply
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q outputs HIGH.
Power–Up: The device is designed to have the POS edges of the ÷2 and ÷4 outputs synchronized at power up.
Select (SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT).
The H640 also contains circuitry to force a stable state of the ECL input differential pair, should both sides be left open. In this
case, the DE side of the input is pulled LOW, and DE goes HIGH.
VT
VT
Q1
GT
GT
Q0
VT
25
24
23
22
21
20
19
Q2
26
18
VBB
GT
27
17
DE
GT
28
16
DE
15
VE
Pinout: 28–Lead PLCC
(Top View)
Q3
1
VT
2
14
R
VT
3
13
GE
Q0
4
12
DT
5
6
7
8
9
10
11
Q1
GT
GT
Q4
Q5
VT
SEL
11/93
 Motorola, Inc. 1996
2–1
REV 3
MC10H640 MC100H640
LOGIC DIAGRAM
TTL Outputs
Q0
PIN NAMES
Q1
PIN
GT
VT
VE
GE
DE, DE
VBB
DT
Qn, Qn
SEL
R
TTL/ECL Clock Inputs
FUNCTION
VBB
TTL Ground (0 V)
TTL VCC (+5.0 V)
ECL VCC (+5.0 V)
ECL Ground (0 V)
ECL Signal Input (positive ECL)
VBB Reference Output
TTL Signal Input
Signal Outputs (TTL)
Input Select (TTL)
Reset (TTL)
Q2
DE
DE
÷2
MUX
Q3
DT
Q0
SEL
Q1
÷4
Q4
TTL Control Inputs
Q5
R
AC CHARACTERISTICS (VT = VE = 5.0V ±5%)
0°C
Symbol
Characteristic
Q0–Q3
25°C
Min
Max
Min
Max
Min
Max
Unit
4.9
5.9
4.9
5.9
5.2
6.2
ns
CL = 25pF
5.0
6.0
5.0
6.0
5.3
6.3
ns
CL = 25pF
0.5
ns
CL = 25pF
tPLH
Propagation Delay ECL
D to Output
tPLH
Propagation Delay TTL
D to Output
tskwd*
Within–Device Skew
tPLH
Propagation Delay ECL
D to Output
tPLH
Propagation Delay TTL
D to Output
tPLH
Propagation Delay ECL
D to Output
tPLH
Propagation Delay TTL
D to Output
tPD
Propagation Delay
R to Output
All
Outputs
tR
tF
Output Rise/Fall Time
0.8 V – 2.0 V
All
Outputs
fmax
Maximum Input Frequency
135
135
tpw
Minimum Pulse Width
1.50
trr
Reset Recovery Time
1.25
0.5
Q0, Q1
Q4, Q5
85°C
0.5
Condition
4.9
5.9
4.9
5.9
5.2
6.2
ns
CL = 25pF
5.0
6.0
5.0
6.0
5.3
6.3
ns
CL = 25pF
4.9
5.9
4.9
5.9
5.2
6.2
ns
CL = 25pF
5.0
6.0
5.0
6.0
5.3
6.3
ns
CL = 25pF
4.3
6.3
4.3
6.3
5.0
7.0
ns
CL = 25pF
2.5
2.5
ns
CL = 25pF
135
MHz
CL = 25pF
1.50
1.50
ns
1.25
1.25
ns
2.5
2.5
2.5
2.5
* Within–Device Skew defined as identical transitions on similar paths through a device.
MOTOROLA
2–2
MECL Data
DL122 — Rev 6
MC10H640 MC100H640
VCC and CLOAD RANGES TO MEET DUTY CYCLE REQUIREMENTS (0°C ≤ TA ≤ 85°C Output Duty Cycle Measured
Relative to 1.5V)
Symbol
Characteristic
Min
Nom
Max
Unit
Condition
Range of VCC and CL to meet minimum pulse width
(HIGH or LOW) = 11.5 ns at fout ≤ 40 MHz
VCC
CL
4.75
10
5.0
5.25
50
V
pF
Q0–Q3
Q0–Q1
Range of VCC and CL to meet minimum pulse width
(HIGH or LOW) = 9.5 ns at 40 < fout ≤ 50 MHz
VCC
CL
4.875
15
5.0
5.125
27
V
pF
Q0–Q3
Max
Unit
Condition
DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
0°C
Symbol
IEE
Characteristic
Power Supply Current
ICCH
Min
25°C
Max
Min
85°C
Max
Min
ECL
57
57
57
mA
VE Pin
TTL
30
30
30
mA
Total all VT pins
30
30
30
mA
Max
Unit
ICCL
TTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
0°C
Symbol
Characteristic
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
IIH
Min
25°C
Max
Min
2.0
85°C
Max
2.0
Min
2.0
Condition
V
0.8
0.8
0.8
Input HIGH Current
20
100
20
100
20
100
µA
VIN = 2.7V
VIN = 7.0V
IIL
Input LOW Current
–0.6
–0.6
–0.6
mA
VIN = 0.5V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
0.5
0.5
VIK
Input Clamp Voltage
–1.2
–1.2
IOS
Output Short Circuit Current
MECL Data
DL122 — Rev 6
2.5
2.0
–100
2.5
2.0
–225
–100
2–3
2.5
2.0
–225
–100
V
IOH = –3.0mA
IOH = –15mA
0.5
V
IOL = 24mA
–1.2
V
IIN = –18mA
–225
mA
VOUT = 0V
MOTOROLA
MC10H640 MC100H640
10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
0°C
Symbol
Characteristic
Min
25°C
Max
Min
85°C
Max
225
Min
175
Max
Unit
175
µA
IIH
IIL
Input HIGH Current
Input LOW Current
0.5
VIH*
VIL*
Input HIGH Voltage
Input LOW Voltage
3.83
3.05
4.16
3.52
3.87
3.05
4.19
3.52
3.94
3.05
4.28
3.555
V
VBB*
Output Reference Voltage
3.62
3.73
3.65
3.75
3.69
3.81
V
0.5
Condition
0.5
VE = 5.0V
*NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V.
100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
0°C
Symbol
Characteristic
Min
IIH
IIL
Input HIGH Current
Input LOW Current
0.5
VIH*
VIL*
Input HIGH Voltage
Input LOW Voltage
3.835
3.19
25°C
Max
Min
225
85°C
Max
Min
175
0.5
4.12
3.525
3.835
3.19
Max
Unit
175
µA
4.12
3.525
V
Condition
0.5
4.12
3.525
3.835
3.19
VE = 5.0V
VBB*
Output Reference Voltage
3.62
3.74
3.62
3.74
3.62
3.74
V
*NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V.
10/100H640
DUTY CYCLE CONTROL
To maintain a duty cycle of ±5% at 50MHz, limit the load capacitance and/or power supply variation as shown in Figures 1 and 2.
For a ±2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature. Figure 7 shows typical
TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up.
Best duty cycle control is obtained with a single µP load and minimum line length.
MOTOROLA
2–4
MECL Data
DL122 — Rev 6
MC10H640 MC100H640
11
11
NEGATIVE PULSE WIDTH (ns)
5.25 VCC
5 VCC
PW (ns)
4.75 VCC
10
9
0
25
50
75
10
4.75 VCC
5 VCC
5.25 VCC
9
85
0
25
Figure 1. Positive Pulse Width at
25°C Ambient and 50 MHz Out
75
85
Figure 2. Negative Pulse Width @ 50 MHz
Out and 25°C Ambient
11
11
5.125 VCC
5 VCC
4.875 VCC
NEGATIVE PULSE WIDTH (ns)
POSITIVE PULSE WIDTH (ns)
50
LOAD (pF)
LOAD (pF)
10
9
0
25
50
75
10
4.875 VCC
5 VCC
5.125 VCC
9
85
0
25
LOAD (pF)
50
75
85
LOAD (pF)
Figure 3. Positive Pulse Width at
25°C Ambient at 50 MHz Out
Figure 4. Negative Pulse Width @ 50 MHz
Out and 25°C Ambient
11
11
NEGATIVE PULSE WIDTH (ns)
POSITIVE PULSE WIDTH (ns)
10 pF
50 pF
25 pF
10
10 pF
9
0°
25°
50°
TEMPERATURE (°C)
75°
85°
25 pF
9
0°
Figure 5. Temperature versus Positive Pulse Width
for 100H640 at 50 MHz and +5.0 V VCC
MECL Data
DL122 — Rev 6
10
25°
50°
TEMPERATURE (°C)
75°
85°
Figure 6. Temperature versus Negative Pulse Width
for MC100H640 @ 50 MHz and +5.0 V VCC
2–5
MOTOROLA
MC10H640 MC100H640
6.2
4.75 V
6.0
5V
TPD++ (ns)
5.25 V
5.8
5.6
5.4
5.2
25
0
50
75
85
CLOAD (pF)
Figure 7. TP versus Load Typical at TA = 25°C
DT
RESET, R
Rtrec
Rtpw
Q0, Q1, Q2, Q3
Q0, Q1
Q4, Q5
Figure 8. MC10H/100H640 Clock Phase and Reset Recovery Time After Reset Pulse
Din
Q0
Q3
Q1
Q2
Q4 & Q5
AFTER POWER UP
OUTPUTS Q4 & Q5 WILL SYN WITH POSITIVE EDGES OF Din & Q0
Q3 & NEGATIVE EDGES OF Q0 & Q1
Figure 9. Output Timing Diagram
MOTOROLA
2–6
MECL Data
DL122 — Rev 6
MC10H640 MC100H640
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
0.007 (0.180)
B
T L–M
M
N
S
T L–M
S
S
Y BRK
–N–
0.007 (0.180)
U
M
N
S
D
Z
–M–
–L–
W
28
D
X
G1
0.010 (0.250)
T L–M
S
N
S
S
V
1
VIEW D–D
A
0.007 (0.180)
R
0.007 (0.180)
M
T L–M
S
N
S
C
M
T L–M
S
N
0.007 (0.180)
H
Z
M
T L–M
N
S
S
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
–T–
T L–M
S
N
S
M
T L–M
S
N
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
MECL Data
DL122 — Rev 6
0.007 (0.180)
2–7
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10_
0.410
0.430
0.040
–––
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2_
10_
10.42
10.92
1.02
–––
MOTOROLA
MC10H640 MC100H640
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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◊
MOTOROLA
2–8
*MC10H640/D*
MC10H640/D
MECL Data
DL122 — Rev 6