Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter AD9142A Data Sheet FEATURES GENERAL DESCRIPTION Supports input data rate up to 575 MHz Very small inherent latency variation: <2 DAC clock cycles Proprietary low spurious and distortion design 6-carrier GSM ACLR = 79 dBc at 200 MHz IF SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF Flexible 16-bit LVDS interface Supports word and byte load Data interface DLL Sample error detection and parity Multiple chip synchronization Fixed latency and data generator latency compensation Selectable 2×, 4×, 8× interpolation filter Low power architecture fS/4 power saving coarse mixer Input signal power detection Emergency stop for downstream analog circuitry protection FIFO error detection On-chip numeric control oscillator allows carrier placement anywhere in the DAC Nyquist bandwidth Transmit enable function for extra power saving High performance, low noise PLL clock multiplier Digital gain and phase adjustment for sideband suppression Digital inverse sinc filter Low power: 1.8 W at 1.6 GSPS, 1.5 W at 1.25 GSPS, full operating conditions 72-lead LFCSP The AD9142A is a dual, 16-bit, high dynamic range digital-toanalog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142A TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the programming/ readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142A is available in a 72-lead LFCSP. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. APPLICATIONS Wide signal bandwidth (BW) enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. New low power architecture improves power efficiency (mW/MHz/channel) by 30%. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection. Programmable transmit enable function allows easy design balance between power consumption and wakeup time. Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com AD9142A* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Reference Materials View a parametric search of comparable parts Press • Analog Devices Introduces High-Performance RF ICs for Multi-band Base Stations and Microwave Point-to-Point Radios Evaluation Kits • AD9142A Evaluation Board Documentation Application Notes • AN-1342: AD9142 to AD9142A Migration Data Sheet • AD9142A: Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-toAnalog Converter Data Sheet Tools and Simulations • AD9142A IBIS Model Reference Designs • CN0375 Design Resources • • • • AD9142A Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all AD9142A EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. 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AD9142A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Datapath Configuration ............................................................ 35 Applications ....................................................................................... 1 Digital Quadrature Gain and Phase Adjustment ................... 35 General Description ......................................................................... 1 DC Offset Adjustment ............................................................... 35 Product Highlights ........................................................................... 1 Inverse Sinc Filter ....................................................................... 36 Revision History ............................................................................... 4 Input Signal Power Detection and Protection ........................ 36 Functional Block Diagram .............................................................. 5 Transmit Enable Function ......................................................... 37 Specifications..................................................................................... 6 Digital Function Configuration ............................................... 37 DC Specifications ......................................................................... 6 Multidevice Synchronization and Fixed Latency ....................... 38 Digital Specifications ................................................................... 8 Very Small Inherent Latency Variation ................................... 38 DAC Latency Specifications ........................................................ 9 Further Reducing the Latency Variation................................. 38 Latency Variation Specifications ................................................ 9 Synchronization Implementation ............................................ 39 AC Specifications........................................................................ 10 Synchronization Procedures ..................................................... 39 Operating Speed Specifications ................................................ 10 Interrupt Request Operation ........................................................ 40 Absolute Maximum Ratings ..................................................... 11 Interrupt Working Mechanism ................................................ 40 Thermal Resistance .................................................................... 11 Interrupt Service Routine .......................................................... 40 ESD Caution ................................................................................ 11 Temperature Sensor ....................................................................... 41 Pin Configuration and Function Descriptions ........................... 12 DAC Input Clock Configurations ................................................ 42 Typical Performance Characteristics ........................................... 15 Driving the DACCLK and REFCLK Inputs ........................... 42 Terminology .................................................................................... 20 Direct Clocking .......................................................................... 42 Serial Port Operation ..................................................................... 21 Clock Multiplication .................................................................. 42 Data Format ................................................................................ 21 PLL Settings ................................................................................ 43 Serial Port Pin Descriptions ...................................................... 21 Configuring the VCO Tuning Band ........................................ 43 Serial Port Options ..................................................................... 21 Automatic VCO Band Select .................................................... 43 Data Interface .................................................................................. 23 Manual VCO Band Select ......................................................... 43 LVDS Input Data Ports .............................................................. 23 PLL Enable Sequence ................................................................. 43 Word Interface Mode ................................................................. 23 Analog Outputs............................................................................... 44 Byte Interface Mode ................................................................... 23 Transmit DAC Operation.......................................................... 44 Data Interface Configuration Options .................................... 23 Interfacing to Modulators ......................................................... 45 DLL Interface Mode ................................................................... 23 Reducing LO Leakage and Unwanted Sidebands .................. 46 Parity ............................................................................................ 26 Example Start-Up Routine ............................................................ 47 SED Operation ............................................................................ 26 Device Configuration and Start-Up Sequence 1 .................... 47 SED Example ............................................................................... 27 Device Configuration and Start-Up Sequence 2 .................... 47 Delay Line Interface Mode ........................................................ 27 Device Configuration Register Map and Description ............... 49 FIFO Operation .............................................................................. 29 SPI Configure Register .............................................................. 52 Resetting the FIFO ..................................................................... 30 Power-Down Control Register ................................................. 52 Serial Port Initiated FIFO Reset ............................................... 30 Interrupt Enable0 Register ........................................................ 52 Frame Initiated FIFO Reset ....................................................... 30 Interrupt Enable1 Register ........................................................ 53 Digital Datapath.............................................................................. 32 Interrupt Flag0 Register............................................................. 53 Interpolation Filters ................................................................... 32 Interrupt Flag1 Register............................................................. 53 Digital Modulation ..................................................................... 34 Interrupt Select0 Register .......................................................... 54 Rev. A | Page 2 of 72 Data Sheet AD9142A Interrupt Select1 Register...........................................................54 NCO Frequency Tuning Word 3 Register ............................... 64 Frame Mode Register..................................................................54 NCO Phase Offset 0 Register .................................................... 64 Data Control 0 Register ..............................................................55 NCO Phase Offset 1 Register .................................................... 64 Data Control 1 Register ..............................................................55 IQ Phase Adjust 0 Register ........................................................ 64 Data Control 2 Register ..............................................................55 IQ Phase Adjust 1 Register ........................................................ 64 Data Control 3 Register ..............................................................55 Power Down Data Input 0 Register .......................................... 65 Data Status 0 Register .................................................................55 IDAC DC Offset 0 Register ....................................................... 65 DAC Clock Receiver Control Register .....................................56 IDAC DC Offset 1 Register ....................................................... 65 Ref Clock Receiver Control Register ........................................56 QDAC DC Offset 0 Register ...................................................... 65 PLL Control 0 Register ...............................................................56 QDAC DC Offset 1 Register ...................................................... 65 PLL Control 2 Register ...............................................................57 IDAC Gain Adjust Register ....................................................... 65 PLL Control 3 Register ...............................................................57 QDAC Gain Adjust Register...................................................... 66 PLL Status 0 Register ..................................................................57 Gain Step Control 0 Register ..................................................... 66 PLL Status 1 Register ..................................................................58 Gain Step Control 1 Register ..................................................... 66 IDAC FS Adjust LSB Register ....................................................58 Tx Enable Control Register ....................................................... 66 IDAC FS Adjust MSB Register ..................................................58 DAC Output Control Register .................................................. 67 QDAC FS Adjust LSB Register ..................................................58 DLL Cell Enable 0 Register ........................................................ 67 QDAC FS Adjust MSB Register ................................................58 DLL Cell Enable 1 Register ........................................................ 67 Die Temperature Sensor Control Register ...............................59 SED Control Register ................................................................. 67 Die Temperature LSB Register ..................................................59 SED Pattern I0 Low Bits Register.............................................. 68 Die Temperature MSB Register .................................................59 SED Pattern I0 High Bits Register ............................................ 68 Chip ID Register..........................................................................59 SED Pattern Q0 Low Bits Register ............................................ 68 Interrupt Configuation Register ...............................................59 SED Pattern Q0 High Bits Register .......................................... 68 Sync Control Register .................................................................60 SED Pattern I1 Low Bits Register.............................................. 68 Frame Reset Control Register ....................................................60 SED Pattern I1 High Bits Register ............................................ 68 FIFO Level Configuration Register ..........................................60 SED Pattern Q1 Low Bits Register ............................................ 68 FIFO Level Readback Register ..................................................61 SED Pattern Q1 High Bits Register .......................................... 69 FIFO Control Register ................................................................61 Parity Control Register ............................................................... 69 Data Format Select Register.......................................................61 Parity Error Rising Edge Register ............................................. 69 Datapath Control Register .........................................................61 Parity Error Falling Edge Register ............................................ 69 Interpolation Control Register ..................................................62 Version Register .......................................................................... 69 Over Threshold Control 0 Register ..........................................62 DAC Latency and System Skews ................................................... 70 Over Threshold Control 1 Register ..........................................62 DAC Latency Variations............................................................. 70 Over Threshold Control 2 Register ..........................................62 FIFO Latency Variation.............................................................. 70 Input Power Readback LSB Register ........................................62 Clock Generation Latency Variation ........................................ 71 Input Power Readback MSB Register .......................................63 Correcting System Skews ........................................................... 71 NCO Control Register ................................................................63 Packaging and Ordering Information .......................................... 72 NCO Frequency Tuning Word 0 Register ...............................63 Outline Dimensions ................................................................... 72 NCO Frequency Tuning Word 1 Register ...............................63 Ordering Guide ........................................................................... 72 NCO Frequency Tuning Word 2 Register ...............................63 Rev. A | Page 3 of 72 AD9142A Data Sheet REVISION HISTORY 5/14—Rev. 0 to Rev. A Change to Table 25 ......................................................................... 51 Changes to Table 103...................................................................... 69 12/13—Revision 0: Initial Version Rev. A | Page 4 of 72 Data Sheet AD9142A FUNCTIONAL BLOCK DIAGRAM INPUT POWER DETECTION HB2 2× NCO HB3 2× fDAC /4 MOD IOUT1P IOUT1N DAC CLK 16 DAC 2 16-BIT IOUT2P IOUT2N GAIN 1 DAC_CLK INTERP MODE CTRL3 INTERP MODE CTRL2 INTERP MODE CTRL1 FIFO CTRL SED CTRL INTERFACE CTRL FRAMEP/PARITYP FRAMEN/PARITYN DAC 1 16-BIT 10 GAIN 2 HB1 2× 16 OVERTHRESHOLD PROTECTION FIFO 8-SAMPLE SED LVDS DATA RECEIVER D0P/D0N INV SINC COMPLEX MODULATION D15P/D15N DC OFFSET CONTROL AD9142A GAIN AND PHASE CONTROL DLL 13-TAP DCIP/DCIN 10 REF AND BIAS VREF FSADJ INTERNAL CLOCK TIMING AND CONTROL LOGIC SERIAL INPUT/OUTPUT PORT POWER-ON RESET MULTICHIP SYNCHRONIZATION DAC_CLK CLOCK MULTIPLIER CLK RCVR DACCLKP DACCLKN REF RCVR REFP/SYNCP REFN/SYNCN 11901-001 IRQ2 RESET TXEN CS IRQ1 SCLK SYNC SDIO PROGRAMMING REGISTERS Figure 1. Rev. A | Page 5 of 72 AD9142A Data Sheet SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error Full-Scale Output Current Output Compliance Range Output Resistance Gain DAC Monotonicity Settling Time to Within ±0.5 LSB MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD18 DVDD18 Variation over Operating Conditions 1 POWER CONSUMPTION 2× Mode NCO OFF NCO ON 2× Mode NCO OFF NCO ON 4× Mode NCO OFF NCO ON 4× Mode NCO OFF NCO ON 4× Mode NCO OFF NCO ON 4× Mode NCO OFF NCO ON Test Conditions/Comments Min Typ 16 Max ±2.1 ±3.7 With internal reference Based on a 10 kΩ external resistor between FSADJ and AVSS −0.001 −3.2 19.06 −1.0 0 +2 19.8 LSB LSB +0.001 +4.7 20.6 +1.0 10 Guaranteed 20 % FSR % FSR mA V MΩ ns 0.04 100 30 1.17 Unit Bits ppm/°C ppm/°C ppm/°C 1.19 V kΩ 5 3.13 1.7 3.3 1.8 3.47 1.9 V V 1.7 −2.5% 1.8 1.9 +2.5% V V fDAC = 737.28 MSPS 925 1217 mW mW 1135 1520 mW mW 852 1144 mW mW 1040 1425 mW mW 1230 1725 mW mW 1405 1990 mW mW fDAC = 983.04 MSPS fDAC = 737.28 MSPS fDAC = 983.04 MSPS fDAC = 1228.8 MSPS fDAC = 1474.56 MSPS Rev. A | Page 6 of 72 Data Sheet Parameter 8× Mode NCO OFF NCO ON Phase-Lock Loop (PLL) Inverse Sinc Reduced Power Mode (Power-Down) AVDD33 CVDD18 DVDD18 OPERATING RANGE 1 AD9142A Test Conditions/Comments fDAC = 1600 MSPS Min Typ Max Unit 96.6 1.5 42.3 8.6 +85 mW mW mW mW mW mA mA mA °C 1350 1984 70 113 fDAC = 1474.56 MSPS −40 +25 This term specifies the maximum allowable variation of DVDD18 over operating conditions compared with the DVDD18 presented to the device at the time the data interface DLL is enabled. Rev. A | Page 7 of 72 AD9142A Data Sheet DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input Logic High Logic Low CMOS OUTPUT LOGIC LEVEL Output Logic High Logic Low LVDS RECEIVER INPUTS Input Voltage Range Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance DLL SPEED RANGE DAC UPDATE RATE DAC Adjusted Update Rate DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage REFCLK/SYNCCLK INPUT (REFP/SYNCP, REFN/SYNCN) Differential Peak-to-Peak Voltage Common-Mode Voltage Input Clock Frequency SERIAL PORT INTERFACE Maximum Clock Rate Minimum Pulse Width High Low SDIO to SCLK Setup Time SDIO to SCLK Hold Time CS to SCLK Setup Time CS to SCLK Hold Time SDIO to SCLK Delay Symbol Min DVDD18 = 1.8 V DVDD18 = 1.8 V 1.2 DVDD18 = 1.8 V DVDD18 = 1.8 V Data, frame signal, and DCI inputs 1.4 VIA or VIB VIDTH VIDTHH to VIDTHL RIN Typ 825 −175 0.6 V V 0.4 V V 575 1600 575 500 1.25 2000 mV V 100 500 1.25 2000 mV V MHz 1.03 GHz ≤ fVCO ≤ 2.07 GHz SCLK 450 40 MHz 12.5 12.5 Wait time for valid output from SDIO Time for SDIO to relinquish the output bus 1.5 0.68 2.38 9.6 11 Rev. A | Page 8 of 72 1.4 8.5 1.2 With 2 mA loading With 2 mA loading mV mV mV Ω MHz MSPS MSPS 100 Self biased input, ac-coupled VIH VIL IIH IIL Unit 20 100 2× interpolation tPWH tPWL tDS tDH tDCSB tDCSB tDV Max 1675 +175 250 SDIO High-Z to CS SDIO LOGIC LEVEL Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Test Conditions/Comments 1.36 0 ns ns ns ns ns ns ns ns 1.8 0 0.5 2 0.45 V V V V Data Sheet AD9142A DAC LATENCY SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, FIFO level is set to 4 (half of the FIFO depth), unless otherwise noted. Table 3. Parameter WORD INTERFACE MODE 2× Interpolation 4× Interpolation 8× Interpolation BYTE INTERFACE MODE 2× Interpolation 4× Interpolation 8× Interpolation INDIVIDUAL FUNCTION BLOCKS Modulation Fine Coarse Inverse Sinc Phase Compensation Gain Compensation Test Conditions/Comments Fine/coarse modulation, inverse sinc, gain/phase compensation off Min Typ Max 134 244 481 DACCLK cycles DACCLK cycles DACCLK cycles 145 271 506 DACCLK cycles DACCLK cycles DACCLK cycles 17 10 20 12 16 DACCLK cycles DACCLK cycles DACCLK cycles DACCLK cycles DACCLK cycles Fine/coarse modulation, inverse sinc, gain/phase compensation off LATENCY VARIATION SPECIFICATIONS Table 4. Parameter DAC LATENCY VARIATION 1 SYNC Off SYNC On 1 Unit Min Typ Max Unit 1 0 2 1 DACCLK cycles DACCLK cycles DAC latency is defined as the elapsed time from a data sample clocked at the input to the AD9142A until the analog output begins to change. Rev. A | Page 9 of 72 AD9142A Data Sheet AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 5. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 737.28 MSPS BW = 125 MHz BW = 270 MHz fDAC = 983.04 MSPS BW = 360 MHz fDAC = 1228.8 MSPS BW = 200 MHz BW = 500 MHz fDAC = 1474.56 MSPS BW = 737 MHz BW = 400 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 737.28 MSPS fDAC = 983.04 MSPS fDAC = 1228.8 MSPS fDAC = 1474.56 MSPS NOISE SPECTRAL DENSITY (NSD) fDAC = 737.28 MSPS fDAC = 983.04 MSPS fDAC = 1228.8 MSPS fDAC = 1474.56 MSPS W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR) fDAC = 983.04 MSPS fDAC = 1228.8 MSPS fDAC = 1474.56 MSPS W-CDMA SECOND (ACLR) fDAC = 983.04 MSPS fDAC = 1228.8 MSPS fDAC = 1474.56 MSPS Test Conditions/Comments −14 dBFS single tone fOUT = 200 MHz Min Typ Max Unit 85 80 dBc dBc 85 dBc 85 75 dBc dBc 85 80 dBc dBc 80 82 80 85 79 dBc dBc dBc dBc dBc −160 −161.5 −164.5 −166 −162.5 dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz 81 83 80 81 80 dBc dBc dBc dBc dBc 85 86 86 86 85 dBc dBc dBc dBc dBc fOUT = 200 MHz fOUT = 280 MHz fOUT = 10 MHz fOUT = 280 MHz −12 dBFS each tone fOUT = 200 MHz fOUT = 200 MHz fOUT = 280 MHz fOUT = 10 MHz fOUT = 280 MHz Eight-tone, 500 kHz tone spacing fOUT = 200 MHz fOUT = 200 MHz fOUT = 280 MHz fOUT = 10 MHz fOUT = 280 MHz Single carrier fOUT = 200 MHz fOUT = 20 MHz fOUT = 280 MHz fOUT = 20 MHz fOUT = 280 MHz Single carrier fOUT = 200 MHz fOUT = 20 MHz fOUT = 280 MHz fOUT = 20 MHz fOUT = 280 MHz OPERATING SPEED SPECIFICATIONS Table 6. Interpolation Factor 2× 4× 8× DVDD18, CVDD18 = 1.8 V ± 5% fDCI (MSPS) fDAC (MSPS) Maximum Maximum 575 1150 350 1400 175 1400 DVDD18, CVDD18 = 1.9 V ± 5% or 1.8 V ± 2% fDCI (MSPS) fDAC (MSPS) Maximum Maximum 575 1150 375 1500 187.5 1500 Rev. A | Page 10 of 72 DVDD18, CVDD18 = 1.9 V ± 2% fDCI (MSPS) fDAC (MSPS) Maximum Maximum 575 1150 400 1600 200 1600 Data Sheet AD9142A ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter AVDD33 to GND DVDD18, CVDD18 to GND FSADJ, VREF, IOUT1P, IOUT1N, IOUT2P, IOUT2N to GND D15P to D0P, D15N to D0N, FRAMEP/PARITYP, FRAMEN/PARITYN, DCIP, DCIN to GND DACCLKP, DACCLKN, REFP, SYNCP, REFN, SYNCN to GND RESET, IRQ1, IRQ2, CS, SCLK, SDIO to GND Junction Temperature Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +2.1 V −0.3 V to AVDD33 + 0.3 V −0.3 V to DVDD18 + 0.3 V −0.3 V to CVDD18 + 0.3 V The exposed pad (EPAD) must be soldered to the ground plane (AVSS) for the 72-lead LFCSP. The EPAD provides an electrical, thermal, and mechanical connection to the board. Typical θJA, θJB, and θJC values are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA and θJB. Table 8. Thermal Resistance −0.3 V to DVDD18 + 0.3 V Package 72-Lead LFCSP 125°C −65°C to +150°C ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 11 of 72 θJA 20.7 θJB 10.9 θJC 1.1 Unit °C/W Conditions EPAD soldered to ground plane AD9142A Data Sheet 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 CVDD18 CVDD18 VREF FSADJ AVDD33 IOUT1P IOUT1N AVDD33 CVDD18 CVDD18 DACCLKP DACCLKN CVDD18 CVDD18 AVDD33 IOUT2N IOUT2P AVDD33 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 AD9142A TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 CS SCLK SDIO IRQ1 IRQ2 DVDD18 DVDD18 D0N D0P D1N D1P DVDD18 D2N D2P D3N D3P D4N D4P NOTES 1. EXPOSED PAD (EPAD) MUST BE SOLDERED TO THE GROUND PLANE (AVSS, DVSS, CVSS). THE EPAD PROVIDES AN ELECTRICAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD. 11901-002 DVDD18 D11P D11N D10P D10N D9P D9N D8P D8N DCIP DCIN D7P D7N D6P D6N D5P D5N DVDD18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 REFP/SYNCP REFN/SYNCN CVDD18 RESET TXEN DVDD18 FRAMEP/PARITYP FRAMEN/PARITYN D15P D15N DVDD18 D14P D14N D13P D13N D12P D12N Figure 2. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic CVDD18 REFP/SYNCP REFN/SYNCN CVDD18 RESET TXEN 7 DVDD18 8 9 10 11 12 FRAMEP/PARITYP FRAMEN/PARITYN D15P D15N DVDD18 13 14 15 16 17 18 19 D14P D14N D13P D13N D12P D12N DVDD18 20 21 22 23 D11P D11N D10P D10N Description 1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution. PLL Reference Clock/Synchronization Clock Input, Positive. PLL Reference Clock/Synchronization Clock Input, Negative. 1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution. Reset, Active Low. CMOS levels with respect to DVDD18. Recommended reset pulse length is 1 µs. Active High Transmit Path Enable. CMOS levels with respect to DVDD18. A low level on this pin triggers three selectable actions in the DAC. See Table 87 for details. 1.8 V Digital Supply. Pin 7 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. Frame/Parity Input, Positive. Frame/Parity Input, Negative. Data Bit 15 (MSB), Positive. Data Bit 15 (MSB), Negative. 1.8 V Digital Supply. Pin 12 supplies the power to the digital core and digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. Data Bit 14, Positive. Data Bit 14, Negative. Data Bit 13, Positive. Data Bit 13, Negative. Data Bit 12, Positive. Data Bit 12, Negative. 1.8 V Digital Supply. Pin 19 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. Data Bit 11, Positive. Data Bit 11, Negative. Data Bit 10, Positive. Data Bit 10, Negative. Rev. A | Page 12 of 72 Data Sheet Pin No. 24 25 26 27 28 29 30 31 32 33 34 35 36 Mnemonic D9P D9N D8P D8N DCIP DCIN D7P D7N D6P D6N D5P D5N DVDD18 37 38 39 40 41 42 43 D4P D4N D3P D3N D2P D2N DVDD18 44 45 46 47 48 D1P D1N D0P D0N DVDD18 49 DVDD18 50 IRQ2 51 IRQ1 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 SDIO SCLK CS AVDD33 IOUT2P IOUT2N AVDD33 CVDD18 CVDD18 DACCLKN DACCLKP CVDD18 CVDD18 AVDD33 IOUT1N IOUT1P AVDD33 FSADJ VREF AD9142A Description Data Bit 9, Positive. Data Bit 9, Negative. Data Bit 8, Positive. Data Bit 8, Negative. Data Clock Input, Positive. Data Clock Input, Negative. Data Bit 7, Positive. Data Bit 7, Negative. Data Bit 6, Positive. Data Bit 6, Negative. Data Bit 5, Positive. Data Bit 5, Negative. 1.8 V Digital Supply. Pin 36 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. Data Bit 4, Positive. Data Bit 4, Negative. Data Bit 3, Positive. Data Bit 3, Negative. Data Bit 2, Positive. Data Bit 2, Negative. 1.8 V Digital Supply. Pin 43 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. Data Bit 1, Positive. Data Bit 1, Negative. Data Bit 0, Positive. Data Bit 0, Negative. 1.8 V Digital Supply. Pin 48 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. 1.8 V Digital Supply. Pin 49 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. Second Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a 10 kΩ resistor. First Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a 10 kΩ resistor. Serial Port Data Input/Output. CMOS levels with respect to DVDD18. Serial Port Clock Input. CMOS levels with respect to DVDD18. Serial Port Chip Select. Active low (CMOS levels with respect to DVDD18). 3.3 V Analog Supply. QDAC Positive Current Output. QDAC Negative Current Output. 3.3 V Analog Supply. 1.8 V Clock Supply. Supplies clock receivers and clock distribution. 1.8 V Clock Supply. Supplies clock receivers and clock distribution. DAC Clock Input, Negative. DAC Clock Input, Positive. 1.8 V Clock Supply. Supplies clock receivers and clock distribution. 1.8 V Clock Supply. Supplies clock receivers and clock distribution. 3.3 V Analog Supply. IDAC Negative Current Output. IDAC Positive Current Output. 3.3 V Analog Supply. Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to GND. Voltage Reference. Nominally 1.2 V output. Decouple VREF to GND. Rev. A | Page 13 of 72 AD9142A Pin No. 71 72 Mnemonic CVDD18 CVDD18 EPAD Data Sheet Description 1.8 V Clock Supply. Pin 71 supplies the clock receivers, clock multiplier, and clock distribution. 1.8 V Clock Supply. Pin 72 supplies the clock receivers, clock multiplier, and clock distribution. Exposed Pad. The exposed pad (EPAD) must be soldered to the ground plane (AVSS, DVSS, CVSS). The EPAD provides an electrical, thermal, and mechanical connection to the board. Rev. A | Page 14 of 72 Data Sheet AD9142A TYPICAL PERFORMANCE CHARACTERISTICS 0 –60 fDAC = 737.28MHz fDAC = 983.04MHz fDAC = 1228.8MHz fDAC = 1474.56MHz –10 –65 IN-BAND SFDR (dBc) –20 –30 SFDR (dBc) BW BW BW BW –40 –50 –60 = 80MHz, –6dBFS = 80MHz, –12dBFS = 300MHz, –6dBFS = 300MHz, –12dBFS –70 –75 –80 –70 –85 –80 100 200 300 400 500 600 700 800 fOUT (MHz) 11901-003 0 < –85 Figure 3. Single Tone (0 dBFS) SFDR vs. fOUT in the First Nyquist Zone over fDAC 0 –60 IN-BAND SFDR (dBc) –40 –50 –60 –70 –80 100 120 140 160 180 200 = 80MHz, –6dBFS = 80MHz, –12dBFS = 300MHz, –6dBFS = 300MHz, –12dBFS –70 –75 –80 –85 0 100 200 300 400 500 600 700 800 fOUT (MHz) < –85 11901-005 –100 Figure 4. Single Tone Second Harmonic vs. fOUT in the First Nyquist Zone over Digital Back Off, fDAC = 1474.56 MHz 0 –60 BW BW BW BW –65 IN-BAND SFDR (dBc) –30 –40 –50 –60 –70 150 200 250 300 Figure 7. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. fOUT in 80 MHz and 300 MHz BW, fDAC = 983.04 MHz 0dBFS –6dBFS –12dBFS –16dBFS –20 100 fOUT (MHz) 0 –10 50 11901-006 –85 MEANS ≤ –85 –90 THIRD HARMONIC (dBc) 80 –80 = 80MHz, –6dBFS = 80MHz, –12dBFS = 300MHz, –6dBFS = 300MHz, –12dBFS –70 –75 –80 –85 –85 MEANS ≤ –85 –90 0 100 200 300 400 fOUT (MHz) 500 600 700 800 < –85 11901-007 –100 Figure 5. Single Tone Third Harmonic vs. fOUT in the First Nyquist Zone over Digital Back Off, fDAC = 1474.56 MHz 0 50 100 150 200 fOUT (MHz) 250 300 350 11901-008 SECOND HARMONIC (dBc) BW BW BW BW –65 –30 60 Figure 6. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. fOUT in 80 MHz and 300 MHz Bandwidths, fDAC = 737.28 MHz 0dBFS –6dBFS –12dBFS –16dBFS –20 40 fOUT (MHz) 0 –10 20 11901-004 –85 MEANS ≤ –85 –90 Figure 8. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. fOUT in 80 MHz and 300 MHz Bandwidths, fDAC = 1228.8 MHz Rev. A | Page 15 of 72 AD9142A –60 BW BW BW BW –65 0 = 80MHz, –6dBFS = 80MHz, –12dBFS = 300MHz, –6dBFS = 300MHz, –12dBFS 0.6MHz TONE SPACING 16MHz TONE SPACING 35MHz TONE SPACING –20 –70 –40 IMD (dBc) IN-BAND SFDR (dBc) Data Sheet –75 –80 –60 –80 –85 –100 0 50 100 150 200 250 300 350 fOUT (MHz) –120 11901-009 < –85 0 –20 300 400 500 600 700 800 Figure 12. Two Tone, Third IMD vs. fOUT over Tone Spacing, fDAC = 1474.56 MHz –152 fDAC = 737.28MHz fDAC = 983.04MHz fDAC = 1228.8MHz fDAC = 1474.56MHz –10 200 fOUT (MHz) Figure 9. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. fOUT in 80 MHz and 300 MHz Bandwidths, fDAC = 1474.56 MHz 0 100 11901-010 –85 MEANS ≤ –85 fDAC = 737.28MHz fDAC = 983.04MHz fDAC = 1228.8MHz fDAC = 1474.56MHz –154 –156 NSD (dBm/Hz) IMD (dBc) –30 –40 –50 –158 –160 –162 –60 –164 –70 –166 –80 –90 300 400 500 600 700 800 fOUT (MHz) 0 300 400 500 600 700 800 800 Figure 13. Single Tone (0 dBFS) NSD vs. fOUT over fDAC –152 0dBFS –6dBFS –9dBFS –20 200 fOUT (MHz) Figure 10. Two Tone, Third IMD vs. fOUT over fDAC 0 100 11901-012 200 11901-014 100 11901-011 –168 0 0dBFS –6dBFS –12dBFS –16dBFS –154 –156 NSD (dBm/Hz) –60 –158 –160 –162 –80 –164 –100 –166 –168 –120 0 100 200 300 400 500 600 700 800 fOUT (MHz) 11901-013 IMD (dBc) –40 0 100 200 300 400 500 600 700 fOUT (MHz) Figure 14. Single Tone NSD vs. fOUT over Digital Back Off, fDAC = 1474.56 MHz Figure 11. Two Tone, Third IMD vs. fOUT over Digital Back Off, fDAC = 1474.56 MHz Rev. A | Page 16 of 72 Data Sheet –150 AD9142A –60 737.2MHz 983.04MHz 1228.8MHz 1474.56MHz –152 –154 –65 –156 –70 –158 ACLR (dBc) NSD (dBm/Hz) fDAC = 1474.56MHz, PLL OFF, 0dBFS fDAC = 1474.56MHz, PLL ON, 0dBFS fDAC = 1228.8MHz, PLL OFF, 0dBFS fDAC = 1228.8MHz, PLL ON, 0dBFS –160 –162 –75 –80 –164 –166 –85 0 100 200 300 400 500 600 700 800 fOUT (MHz) Figure 15. 1C WCDMA NSD vs. fOUT, over fDAC –150 –90 11901-200 –170 0 100 200 300 400 500 600 700 fOUT (MHz) 800 11901-101 –168 Figure 18. 1C WCDMA, Second Adjacent ACLR vs. fOUT, PLL On and Off PLL OFF PLL ON –152 –154 NSD (dBm/Hz) –156 –158 –160 –162 –164 0 100 200 300 400 500 600 700 800 fOUT (MHz) 11901-015 –168 11901-016 –166 Figure 16. Single Tone NSD vs. fOUT, fDAC = 1474.28 MHz, PLL On and Off –60 fDAC = 1474.56MHz, PLL OFF, 0dBFS fDAC = 1474.56MHz, PLL ON, 0dBFS fDAC = 1228.8MHz, PLL OFF, 0dBFS fDAC = 1228.8MHz, PLL ON, 0dBFS –65 –70 –75 –85 0 100 200 300 400 500 600 700 800 fOUT (MHz) Figure 17. 1C WCDMA, First Adjacent ACLR vs. fOUT, PLL On and Off 11901-017 –80 11901-100 ACLR (dBc) Figure 19. Two Tone, Third IMD Performance, IF = 280 MHz, fDAC = 1474.28 MHz Figure 20. 1C WCDMA ACLR Performance, IF = 280 MHz, fDAC = 1474.28 MHz Rev. A | Page 17 of 72 Data Sheet Figure 21. Single Tone fDAC = 1474.56 MHz, fOUT = 280 MHz, −14 dBFS 1600 1400 2× 4× 8× 1200 1000 800 600 400 200 400 600 800 1000 1200 1400 1600 fDAC (MHz) 11901-021 11901-018 TOTAL BASELINE POWER CONSUMPTION (mW) AD9142A Figure 24. Total Power Baseline Consumption vs. fDAC over Interpolation 600 DVDD SUPPLY CURRENT (mA) 500 2× 4× 8× 400 300 200 11901-019 0 200 400 600 800 1000 1200 1400 1600 fDAC (MHz) 11901-024 100 Figure 25. DVDD18 Supply Current vs. fDAC over Interpolation Figure 22. 4C WCDMA ACLR Performance, IF = 280 MHz, fDAC = 1474.28 MHz 350 DVDD18 SUPPLY CURRENT (mA) 300 NCO INVERSE SINC DIGITAL GAIN AND PHASE fS/4 MODULATION 250 200 150 100 Figure 23. Single Tone SFDR fDAC = 1474.56 MHz, 4× Interpolation, fOUT = 10 MHz, −14 dBFS 0 200 400 600 800 1000 1200 1400 1600 fDAC (MHz) Figure 26. DVDD18 Supply Current vs. fDAC over Digital Functions Rev. A | Page 18 of 72 11901-022 11901-020 50 Data Sheet CVDD18, PLL ON CVDD18, PLL OFF AVDD33 200 150 100 50 200 400 600 800 1000 1200 1400 fDAC (MHz) 1600 11901-023 SUPPLY CURRENT (mA) 250 AD9142A Figure 27. CVDD18, AVDD33 Supply Current vs. fDAC Rev. A | Page 19 of 72 AD9142A Data Sheet TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, the interpolation filters reject energy in this band. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the DAC output. Offset Error Offset error is the deviation of the output current from the ideal of 0 mA. For IOUT1P, 0 mA output is expected when all inputs are set to 0. For IOUT1N, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. A | Page 20 of 72 Data Sheet AD9142A SERIAL PORT OPERATION 54 CS SPI PORT 53 SCLK 52 SDIO 11901-025 The serial port is a flexible, synchronous serial communications port that allows easy interfacing to many industry standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola® SPI and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9142A. MSB-first or LSB-first transfer formats are supported. The serial port interface is a 3-wire only interface. The input and output share a single pin input/output (SDIO). SERIAL PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. Chip Select (CS) Figure 28. Serial Port Interface Pins There are two phases to a communication cycle with the AD9142A. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first 16 SCLK rising edges. The instruction word provides the serial port controller with information regarding the data transfer cycle, Phase 2, of the communication cycle. The Phase 1 instruction word defines whether the upcoming data transfer is a read or write, along with the starting register address for the next data transfer in the cycle. A logic high on the CS pin, followed by a logic low, resets the serial port timing to the initial state of the instruction cycle. From this state, the next 16 rising SCLK edges represent the instruction bits of the current I/O operation. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one data byte. Registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word and NCO phase offsets, which change only when the frequency tuning word (FTW) update bit is set. DATA FORMAT The instruction byte contains the information shown in Table 10. Table 10. Serial Port Instruction Word I15 (MSB) R/W A14 to A0 (Bit 14 to Bit 0 of the instruction word) determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A14 is the starting address; the device generates the remaining register addresses based on the SPI_LSB_FIRST bit. I[14:0] A[14:0] R/W (Bit 15 of the instruction word) determines whether a read or a write data transfer occurs after the instruction word write. Logic 1 indicates a read operation and Logic 0 indicates a write operation. CS is an active low input that starts and gates a communication cycle. It allows more than one device to be used on the same serial communications line. The SDIO pins enter a high impedance state when the CS input is high. During the communication cycle, CS should stay low. Serial Data I/O (SDIO) The SDIO pin is a bidirectional data line. SERIAL PORT OPTIONS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by the SPI_LSB_FIRST bit (Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0). When SPI_LSB_FIRST = 0 (MSB first), the instruction and data bits must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction word that includes the register address of the most significant data byte. Subsequent data bytes must follow from high address to low address. In MSB-first mode, the serial port internal word address generator decrements for each data byte of the multibyte communication cycle. When SPI_LSB_FIRST = 1 (LSB first), the instruction and data bits must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction word that includes the register address of the least significant data byte. Subsequent data bytes must follow from low address to high address. In LSB-first mode, the serial port internal word address generator increments for each data byte of the multibyte communication cycle. If the MSB-first mode is active, the serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations. If the LSB-first mode is active, the serial port controller data address increments from the data address written toward 0xFF for multibyte I/O operations. Rev. A | Page 21 of 72 AD9142A Data Sheet tDCSB INSTRUCTION CYCLE tSCLK DATA TRANSFER CYCLE CS CS tPWH SCLK R/W A14 A13 A3 A2 A1 A0 D7N D6N D5N D30 D20 D10 D00 tDS SDIO INSTRUCTION BIT 14 Figure 31. Timing Diagram for Serial Port Register Write Figure 29. Serial Register Interface Timing, MSB First INSTRUCTION CYCLE tDH INSTRUCTION BIT 15 11901-028 SCLK 11901-026 SDIO tPWL CS DATA TRANSFER CYCLE CS A0 A1 A2 A12 A13 A14 R/W D00 D10 D20 D4N D5N D6N D7N 11901-027 SDIO tDV SDIO DATA BIT n DATA BIT n – 1 Figure 32. Timing Diagram for Serial Port Register Read Figure 30. Serial Register Interface Timing, LSB First Rev. A | Page 22 of 72 11901-029 SCLK SCLK Data Sheet AD9142A DATA INTERFACE LVDS INPUT DATA PORTS Table 12. Data Interface Configuration Options The AD9142A has a 16-bit LVDS bus that accepts 16-bit I and Q data either in word (16-bit) or byte (8-bit) formats. In the word interface mode, the data is sent over the entire 16-bit data bus. In the byte interface mode, the data is sent over the lower 8-bit (D7 to D0) LVDS bus. Table 11 lists the pin assignment of the bus and the SPI register configuration for each mode. Register 0x26 DATA_FORMAT (Bit 7) DATA_PAIRING (Bit 6) DATA_BUS_INVERT (Bit 5) Table 11. LVDS Input Data Modes Interface Mode Word Byte Pin Assignment D15 to D0 D7 to D0 SPI Register Configuration Register 0x26, Bit 0 = 0 Register 0x26, Bit 0 = 1 WORD INTERFACE MODE In word interface mode, the digital clock input (DCI) signal is a reference bit that generates a double data rate (DDR) data sampling clock. Time align the DCI signal with the data. The IDAC data follows the rising edge of the DCI, and the QDAC data follows the falling edge of the DCI, as shown in Figure 33. WORD INTERFACE MODE I0 Q0 I1 Q1 11901-030 INPUT DATA[15:0] DCI Figure 33. Timing Diagram for Word Interface Mode BYTE INTERFACE MODE In byte interface mode, the required sequence of the input data stream is I[15:8], I[7:0], Q[15:8], Q[7:0]. A frame signal is required to align the order of input data bytes properly. Time align both the DCI signal and frame signal with the data. The rising edge of the frame indicates the start of the sequence. The frame can be either a one shot or periodical signal as long as its first rising edge is correctly captured by the device. For a one shot frame, the frame pulse must be held at high for at least one DCI cycle. For a periodical frame, the frequency needs to be fDCI/(2 × n) Figure 34 is an example of signal timing in byte mode. BYTE INTERFACE MODE I0[15:8] I0[7:0] Q0[15:8] Q0[7:0] Figure 34. Timing Diagram for Byte Interface Mode DATA INTERFACE CONFIGURATION OPTIONS To provide more flexibility for the data interface, some additional options are listed in Table 12. 11901-031 DCI FRAME DLL INTERFACE MODE A source synchronous LVDS interface is used between the data host and AD9142A to achieve high data rates while simplifying the interface. The FPGA or ASIC feeds the AD9142A with 16-bit input data. Along with the input data, the FPGA or ASIC provides a DDR (double data rate) data clock input (DCI). A delay locked loop (DLL) circuit designed to operate with DCI clock rates between 250 and 575 MHz is used to generate a phaseshifted version of the DCI, called DSC (data sampling clock), to register the input data on both the rising and falling edges. As shown in Figure 35, the DCI clock edges must be coincident with the data bit transitions with minimum skew and jitter. The nominal sampling point of the input data occurs in the middle of the DCI clock edges because this point corresponds to the center of the data eye. This is also equivalent to a nominal phase shift of 90°of the DCI clock. The data timing requirements are defined by a data valid window (DVW) that is dependent on the data clock input skew, input data jitter, and the variations of the DLL delay line across delay settings. The DVW is defined as DVW = tDATA PERIOD − tDATA SKEW – tDATA JITTER The available margin for data interface timing is given by tMARGIN = DVW − (tS + tH) The difference between the setup and hold times, which is also called the keep out window, or KOW, is the area where data transitions should not happen. The timing margin allows tuning of the DLL delay setting by the user, see Figure 36. where n is a positive integer, that is, 1, 2, 3, … INPUT DATA[7:0] Description Select between binary and twos complement formats. Indicate I/Q data pairing on data input. This allows the I and Q data that is received to be paired in various ways. Swaps the bit order of the data input port. Remaps the input data from D[15:0] to D[0:15]. From the figure, it can be seen that the ideal location for the DSC signal is 90° out of phase from the DCI input. However, due to skew of the DCI relative to the data, it may be necessary to change the DSC phase offset to sample the data at the center of its eye diagram. The sampling instance can be varied in discrete increments by offsetting the nominal DLL phase shift value of 90° via Register 0x0A, Bits[3:0]. This register is a signed value. The MSB is the sign and the LSBs are the magnitude. The following equation defines the phase offset relationship: Phase Offset = 90° ± n × 11.25°, |n| < 7 where n is the DLL phase offset setting. Rev. A | Page 23 of 72 AD9142A Data Sheet Table 13. DLL Phase Setup and Hold Times (Guaranteed) Figure 35 shows the DSC setup and hold times with respect to the DCI signal and data signals. Frequency, fDCI (MHz) 307 DATA DCI 368 11901-135 DSC tS tH 491 Time (ps) tS tH tS tH tS tH Data Port Setup and Hold Times (ps) at DLL Phase −3 0 +3 −125 −385 −695 834 1120 1417 −70 −305 −534 753 967 1207 −81 −245 −402 601 762 928 Figure 35. LVDS Data Port Setup and Hold Times Table 13 lists the values that are guaranteed over the operating conditions. These values were taken with a 50% duty cycle and a DCI swing of 450 mV p-p. For best performance, the duty cycle variation should be kept below ±5%, and the DCI input should be as high as possible, up to 1200 mV p-p. tDATA JITTER tH tS INPUT DATA DATA EYE tDATA PERIOD DCI DATA SAMPLE CLOCK tDATA JITTER tDCI SKEW INPUT DATA DLL PHASE DELAY tH AND tS DATA EYE tDATA PERIOD 11901-037 DCI DATA SAMPLE CLOCK Figure 36. LVDS Data Port Timing Requirements Rev. A | Page 24 of 72 Data Sheet AD9142A Table 14. DLL Phase Setup and Hold Times (Typical) Frequency, fDCI 1 (MHz) 250 275 300 325 350 375 400 425 450 475 500 525 550 575 1 Time (ps) tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH tS tH −6 −93 468 −87 451 −82 422 −46 405 −23 383 −7 401 −46 385 4 358 11 354 −15 355 9 313 −7 311 −5 300 8 312 −5 −196 579 −172 537 −166 500 −114 483 −92 451 −82 466 −98 445 −52 408 −34 406 −51 399 −28 354 −52 356 −39 340 −28 348 −4 −312 707 −264 646 −256 598 −190 563 −180 524 −150 504 −161 503 −110 465 −92 457 −95 451 −77 399 −100 395 −74 378 −66 379 −3 −416 825 −364 757 −341 703 −271 647 −252 607 −225 569 −243 546 −170 524 −147 516 −147 499 −128 445 −147 438 −107 423 −102 414 Data Port Setup and Hold Times (ps) at DLL Phase −2 −1 0 +1 +2 +3 −530 −658 −770 −878 −983 −1093 947 1067 1188 1315 1442 1570 −464 −556 −653 −756 −859 −956 878 977 1092 1218 1311 1423 −426 −515 −622 −715 −809 −900 803 897 1000 1105 1203 1303 −358 −447 −538 −612 −706 −806 740 832 914 1000 1100 1200 −328 −409 −491 −574 −654 −731 682 762 844 930 1011 1097 −315 −391 −461 −526 −595 −661 641 718 783 863 941 1025 −303 −384 −448 −513 −578 −643 604 674 748 826 890 965 −229 −297 −394 −449 −517 −579 595 625 692 762 829 900 −209 −269 −324 −386 −446 −509 573 637 693 731 792 852 −198 −255 −313 −366 −425 −480 556 613 675 727 779 815 −183 −233 −288 −333 −390 −438 500 555 615 668 726 783 −187 −237 −285 −335 −387 −436 489 537 592 645 692 746 −147 −192 −249 −302 −352 −397 468 510 560 610 659 710 −143 −181 −245 −280 −336 −366 453 496 544 599 654 708 +4 −1193 1697 −1053 1537 −1001 1411 −891 1292 −819 1186 −726 1106 −713 1039 −641 966 −564 917 −530 873 −495 825 −483 799 −440 756 −406 759 +5 −1289 1777 −1151 1653 −1097 1522 −966 1380 −889 1277 −786 1187 −771 1110 −704 1032 −622 983 −585 930 −545 881 −530 850 −486 810 −443 806 +6 −1412 1876 −1251 1728 −1184 1612 −1044 1476 −959 1358 −853 1264 −833 1178 −752 1097 −672 1042 −640 988 −594 934 −581 909 −529 865 −488 847 Table 14 shows characterization data for selected fDCI frequencies. Other frequencies are possible, and Table 14 can be used to estimate performance. Table 14 shows the typical times for various DCI clock frequencies that are required to calculate the data valid margin. The amount of margin that is available for tuning of the DSC sampling point can be determined using Table 14. Maximizing the opening of the eye in both the DCI and data signals improves the reliability of the data port interface. Differential controlled impedance traces of equal length (that is, delay) should be used between the host processor and the AD9142A input. To ensure coincident transitions with the data bits, the DCI signal should be implemented as an additional data line with an alternating (010101…) bit sequence from the same output drivers used for the data. The DCI signal is ac-coupled by default; thus, removing the DCI signal may cause DAC output chatter due to randomness on the DCI input. To avoid this, it is recommended that the DAC output is disabled whenever the DCI signal is not present. To do this, program the DAC output current power down bit in Register 0x01, Bit 7 and Bit 6 to 1. When the DCI signal is again present, the DAC output can be enabled by setting Register 0x01, Bit 7 and Bit 6 to 0. Register 0x0D optimizes the DLL stability over the operating frequency range. Table 15 shows the recommended setting. Table 15. DLL Configuration Options DCI Speed ≥350 MHz <350 MHz Register 0x0D 0x06 0x86 The status of the DLL can be polled by reading the data status register at Address 0x0E. Bit 0 indicates that the DLL is running and attempting lock, and Bit 7 is set to when the DLL has locked. Bit 2 is 1 when a valid data clock in is detected. The warning bits in Register 0x0E[6:4] can be used as indicators that the DAC may be operating in a non ideal location in the delay line. Note that these bits are read at the SPI port speed, which is much slower than the actual speed of the DLL. This means they can only show a snapshot of what is happening as opposed to giving real-time feedback. Rev. A | Page 25 of 72 AD9142A Data Sheet In the following DLL configuration example, fDCI = 500 MHz, DLL is enabled, and DLL phase offset = 0. 1. 0x5E → 0xFE /* Turn off LSB delay cell*/ 2. 0x0D → 0x06 /* Select DLL configure options */ 3. 0x0A → 0xC0 /* Enable DLL and duty cycle correction. Set DLL phase offset to 0 */ 4. Read 0x0E[7:4] /* Expect 1000b if the DLL is locked */ DLL Configuration Example 2 In the following DLL configuration example, fDCI = 300 MHz, DLL is enable, and DLL phase offset = 0. 1. 0x5E → 0xFE /* Turn off LSB delay cell*/ 2. 0x0D → 0x86 /* Select DLL configure options */ 3. 0x0A → 0xC0 /* Enable DLL and duty cycle correction. Set DLL phase offset to 0 */ 4. Read 0x0E[7:4] /* Expect 1000b if the DLL is locked */ PARITY The data interface can be continuously monitored by enabling the parity bit feature in Register 0x6A, Bit 7 and configuring the frame/parity bit as parity by setting Register 0x09 to 0x21. In this case, the host sends a parity bit along with each data sample. This bit is set according to the following formulas, where n is the data sample that is being checked. For even parity, XOR[FRM(n), D0(n), D1(n), D2(n), ..., D15(n)] = 0 For odd parity, XOR[FRM(n), D0(n), D1(n), D2(n), ..., D15(n)] = 1 The parity bit is calculated over 17 bits (including the frame/parity bit). If a parity error occurs, the parity error counter (Register 0x6B or Register 0x6C) is incremented. Parity errors on the bits sampled by the rising edge of DCI increments the rising edge parity counter (Register 0x6B) and set the PARERRRIS bit (Register 0x6A, Bit 0). Parity errors on the bits sampled by the falling edge of DCI will increment the falling edge parity counter (Register 0x6C) and set the PARERRFAL bit (Register 0x6A, Bit 1). The parity counter continues to accumulate until it is cleared or until it reaches a maximum value of 255. The count can be cleared by writing a 1 to Register 0x6A, Bit 5. To trigger an IRQ when a parity error occurs, write a 1 to Register 0x04, Bit 7. This IRQ triggers if there is either a rising edge or falling edge parity error. The status of the IRQ can be observed via Register 0x06, Bit 7 or by using the selected IRQx pin. Clear the IRQ by writing a 1 to Register 0x06, Bit 7. Use the parity bit to validate the interface timing. As described previously, the host provides a parity bit with the data samples, as well as configures the AD9142A to generate an IRQ. The user can then sweep the sampling instance of the AD9142A input registers to determine at what point a sampling error occurs. The sampling instance can be varied in discrete increments by offsetting the nominal DLL phase shift value of 90° via Register 0x0A[3:0]. SED OPERATION The AD9142A provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected. Options are available for customizing SED test sequencing and error handling. The SED circuitry allows the application to test a short user defined pattern to confirm that the high speed source synchronous data bus is correctly implemented and meets the timing requirement. Unlike the parity bit, the SED circuitry is expected to be used during initial system calibration, before the AD9142A is in use in the application. The SED circuitry operates on a data set made up of user defined input words, denoted as I0, Q0, I1, and Q1. The user defined pattern consists of sequential data word samples (I0 is sampled on the rising edge of DCI, Q0 is sampled on the following falling edge of DCI, I1 is sampled on the following DCI rising edge, and Q1 is sampled on the following DCI falling edge). The user loads this data pattern in the byte format into Register 0x61 through Register 0x68. The depth of the user defined pattern is selectable via Bit 4 in the SED_CTRL register (0x60), with the default, 0, meaning a depth of two (using I0 and Q0), and a 1 meaning a depth of four (using I0, Q0, I1, and Q1, and requiring the use of frame signal input to define I0 to the SED state machine). To properly align the input samples using a depth of four, I0 is indicated by asserting the frame signal for a minimum of two complete input samples as shown in Figure 37. The frame signal can be issued once at the start of the data transmission, or it can be asserted repeatedly at intervals coinciding with the S0 word. FRAME DATA[15:0] I0 Q0 I1 Q1 I0 Figure 37. Timing Diagram of Extended FRAME Signal Required to Align Input Data for SED The SED has three flag bits (Register 0x60, Bit 0, Bit 1, and Bit 2) that indicate the results of the input sample comparisons. The sample error detected bit (Register 0x60, Bit 0) is set when an error is detected and remains set until cleared. Rev. A | Page 26 of 72 11901-137 DLL Configuration Example 1 Data Sheet AD9142A The autosample error detection (AED) mode is an autoclear mode that has two effects: it activates the compare fail bit and the compare pass bit (Register 0x60, Bit 1 and Bit 2). The compare pass bit sets if the last comparison indicated that the sample was error free. The compare fail bit sets if an error is detected. The compare fail bit is automatically cleared by the reception of eight consecutive error-free comparisons, when autoclear mode is enabled. The sample error flag can be configured to trigger an IRQ when active, if needed. This is done by enabling the appropriate bit in the event flag register (Register 4, Bit 6). SED EXAMPLE Normal Operation The following example illustrates the AD9142A SED configuration sequence for continuously monitoring the input data and assertion of an IRQ when a single error is detected: 2. 3. 4. 5. Write to the following registers to enable the SED and load the comparison values with a 4-deep user pattern. Comparison values can be chosen arbitrarily; however, choosing values that require frequent bit toggling provides the most robust test. a. Register 0x61[7:0] → I0[7:0] b. Register 0x62[7:0] → I0[15:8] c. Register 0x63[7:0] → Q0[7:0] d. Register 0x64[7:0] → Q0[15:8] e. Register 0x65[7:0] → I1[7:0] f. Register 0x66[7:0] → I1[15:8] g. Register 0x67[7:0] → Q1[7:0] h. Register 0x68[7:0] → Q1[15:8] Enable SED. a. Register 0x60 → 0xD0 b. Register 0x60 → 0x90 Enable the SED error detect flag to assert the IRQx pin. a. Register 0x04[6] = 1 Set up frame parity as the frame signal. a. Register 0x09 = 0x12 Begin transmitting the input data pattern (frame signal) is also required because the depth of the pattern is 4). The DLL is designed to help ease the interface timing requirements in very high speed data rate applications. The DLL has a minimum supported interface speed of 250 MHz, as shown in Table 2. For interface rates lower than this speed, use the interface delay line. In this mode, the DLL is powered off and a four-tap delay line is provided for the user to adjust the timing between the data bus and the DCI. Table 16 specifies the setup and hold times for each delay tap. Table 16. Delay Line Setup and Hold Times (Guaranteed) Delay Setting Register 0x5E[7:0] Register 0x5F[2:0] tS (ns)1 tH (ns) |tS + tH| (ns) 1 0 0x00 0x60 −0.81 1.96 1.15 1 0x80 0x67 −0.97 2.20 1.23 2 0xF0 0x67 −1.13 2.53 1.40 3 0xFE 0x67 −1.28 2.79 1.51 The negative sign indicates the direction of the setup time. The setup time is defined as positive when it is on the left side of the clock edge and negative when it is on the right side of the clock edge. There is a fixed 1.38 ns delay on the DCI signal when the delay line is enabled. Each tap adds a nominal delay of 200 ps to the fixed delay. To achieve the best timing margin, that is, to center the setup and hold window in the middle of the data eye, the user may need to add a delay on the data bus with respect to the DCI in the data source. Figure 38 is an example of calculating the optimal external delay. Register 0x0D, Bit 4 configures the DCI signal coupling settings for optimal interface performance over the operating frequency range. It is recommended that this bit be set to 1 (dc-coupled DCI) in the delay line interface mode. tDELAY = 0.63ns tDATA PERIOD = 2.5ns INPUT DATA [15:0] WITH OPTIMIZED DELAY DATA EYE |tS| = 1.25ns |tH| = 2.51ns DCI = 200MHz NO DATA TRANSITION Figure 38. Example of Interfacing Timing in the Delay Line Interface Mode Rev. A | Page 27 of 72 11901-039 1. DELAY LINE INTERFACE MODE AD9142A Data Sheet Interface Timing Requirements SPI Sequence to Enable Delay Line Interface Mode The following example shows how to calculate the optimal delay at the data source to achieve the best sampling timing in the delay line interface mode: Use the following SPI sequence to enable the delay line interface mode: • • fDCI = 200 MHz Delay setting = 0 The shadow area in Figure 38 is the interface setup and hold time window set to 0. To optimize the interface timing, this window must be placed in the middle of the data transitions. Because the input is double data rate, the available data period is 2.5 ns. Therefore, the optimal data bus delay, with respect to the DCI at the data source, can be calculated as t DELAY = (| t S | + | t H |) t DATA PERIOD − = 1.38 − 1.25 = 0.13 ns 2 2 Rev. A | Page 28 of 72 1. 0x5E → 0x00 /* Configure the delay setting */ 2. 0x5F → 0x60 3. 4. 0x0D → 0x16 /* DC couple DCI */ 0x0A → 0x00 /* Turn off DLL and duty cycle correction */ Data Sheet AD9142A FIFO OPERATION As is described in the Data Interface section, the AD9142A adopts source synchronous clocking in the data receiver. The nature of source synchronous clocking is the creation of a separate clock domain at the receiving device. In the DAC, it is the DAC clock domain, that is, the DACCLK. Therefore, there are two clock domains inside of the DAC: the DCI and the DACCLK. Often, these two clock domains are not synchronous, requiring an additional stage to adjust the timing for proper data transfer. In the AD9142A, a FIFO stage is inserted between the DCI and DACCLK domains to transfer the received data into the core clock domain (DACCLK) of the DAC. The AD9142A contains a 2-channel, 16-bit wide, 8-word deep FIFO. The FIFO acts as a buffer that absorbs timing variations between the two clock domains. The timing budget between the two clock domains in the system is significantly relaxed due to the depth of the FIFO. Figure 39 shows the block diagram of the datapath through the FIFO. The input data is latched into the device, formatted, and then written into the FIFO register, which is determined by the FIFO write pointer. The value of the write pointer is incremented every time a new word is loaded into the FIFO. Meanwhile, data is read from the FIFO register, which is determined by the read pointer, and fed into the digital datapath. The value of the read pointer is incremented every time data is read into the datapath from the FIFO. The FIFO pointers are incremented at the data rate, which is the DACCLK rate divided by the interpolation rate. Valid data is transmitted through the FIFO as long as the FIFO does not overflow (full) or underflow (empty). An overflow or underflow condition occurs when the write pointer and read pointer point to the same FIFO slot. This simultaneous access of data leads to unreliable data transfer through the FIFO and must be avoided. Normally, data is written to and read from the FIFO at the same rate to maintain a constant FIFO depth. If data is written to the FIFO faster than data is read, the FIFO depth increases. If data is read from the FIFO faster than data is written to it, the FIFO depth decreases. For optimal timing margin, maintain the FIFO depth near half full (a difference of four between the write pointer and read pointer values). The FIFO depth represents the FIFO pipeline delay and is part of the overall latency of the AD9142A. FIFO WRITE CLOCK FIFO READ CLOCK DACCLK ÷INT FIFO FIFO SLOT 0 FIFO SLOT 2 DATA RECEIVER INPUT DATA[15:0] FIFO SLOT 3 DATA FORMAT LATCHED DATA[15:0] I[15:0] I DATA PATH FIFO SLOT 1 RETIMED DCI DCI I[15:0] I DAC READ POINTER FIFO SLOT 4 I/Q[31:0] WRITE POINTER FIFO SLOT 5 FIFO SLOT 6 Q[15:0] Q[15:0] Q DATA PATH Q DAC FIFO SLOT 7 FRAME RESET LOGIC FIFO LEVEL FIFO LEVEL REQUEST REGISTER 0x23 Figure 39. Block Diagram of FIFO Rev. A | Page 29 of 72 11901-040 SPI FIFO RESET REG 0x25[0] AD9142A Data Sheet RESETTING THE FIFO SERIAL PORT INITIATED FIFO RESET Upon power-on of the device, the read and write pointers start to roll around the FIFO from an arbitrary slot; consequently, the FIFO depth is unknown. To avoid a concurrent read and write to the same FIFO address and to assure a fixed pipeline delay from power-on to power-on, it is important to reset the FIFO pointers to a known state each time the device powers on or wakes up. This state is specified in the requested FIFO level (FIFO depth and FIFO level are used interchangeably in this data sheet), which consists of two sections: the integer FIFO level and the fractional FIFO level. A SPI initiated FIFO reset is the most common method to reset the FIFO. To initialize the FIFO level through the serial port, toggle FIFO_SPI_RESET_REQUEST (Register 0x25[0]) from 0 to 1 and back to 0. When the write to this register is complete, the FIFO level is initialized to the requested FIFO level and the readback of FIFO_SPI_RESET_ACK (Register 0x25[1]) is set to 1. The FIFO level readback, in the same format as the FIFO level request, should be within ±1 DACCLK cycle of the requested level. For example, if the requested value is 0x40 in 4× interpolation, the readback value should be one of the following: 0x33, 0x40, or 0x41. The range of ±1 DACCLK cycle indicates the default DAC latency uncertainty from power-on to power-on without turning on synchronization. The integer FIFO level represents the difference of the states between the read and write points in the unit of an input data period (1/fDATA). The fractional FIFO level represents the difference of the FIFO pointers that is smaller than the input data period. The resolution of the fractional FIFO level is the input data period divided by the interpolation ratio and, thus, it is equal to one DACCLK cycle. The exact FIFO level, that is, the FIFO latency, can be calculated by Because the FIFO has eight data slots, there are eight possible FIFO integer levels. The maximum supported interpolation rate in the AD9142A is 8× interpolation. Therefore, there are eight possible FIFO fractional levels. Two 3-bit registers in Register 0x23 are assigned to represent the two FIFO levels, as follows: Bits[6:4] represent the FIFO integer level Bits[2:0] represent the FIFO fractional level. Table 17. Examples of FIFO Level Configuration Example FIFO Level (1/fDATA) 3 + 1/2 4 + 1/4 4 + 3/8 Integer Level (Reg. 0x23[6:4]) 3 4 4 Fractional Level (Reg. 0x23[2:0]) 1 1 3 By default, the FIFO level is 4.0. It can be programmed to any allowed value from 0.0 to 7.x. The maximum allowed number for x is the interpolation rate minus 1. For example, in 8× interpolation, the maximum value allowed for x is 7. The following two ways are used to reset the FIFO and initialize the FIFO level: • • Serial port (SPI) initiated FIFO reset. Frame initiated FIFO reset. 2. 4. 5. 6. 7. 8. For example, if the interpolation rate is 4× and the total FIFO depth is 4.5 input data periods, set the FIFO_LEVEL_CONFIG (Register 0x23) to 0x42 (4 here means four data cycles and 2 means two DAC cycles, which is half of a data cycle). Note that there are only four possible fractional levels in the case of 4× interpolation. Table 17 shows additional examples of configuring the FIFO level in various interpolation rate modes. Interpolation Rate 2× 4× 8× 1. 3. FIFO Latency = Integer Level + Fractional Level • • The recommended procedure for a serial port FIFO reset is as follows: Configure the DAC in the desired interpolation mode (Register 0x28[1:0]). Ensure that the DACCLK and DCI are running and stable at the clock inputs. Program Register 0x23 to the customized value, if the desired value is not 0x40. Request the FIFO level reset by setting Register 0x25[0] to 1. Verify that the device acknowledges the request by setting Register 0x25[1] to 1. Remove the request by setting Register 0x25[0] to 0. Verify that the device drops the acknowledge signal by setting Register 0x25[1] to 0. Read back Register 0x24 multiple times to verify that the actual FIFO level is set to the requested level and that the readback values are stable. By design, the readback is within ±1 DACCLK around the requested level. FRAME INITIATED FIFO RESET The frame input has two functions. One function is to indicate the beginning of a byte stream in the byte interface mode, as discussed in the Data Interface section. The other function is to initialize the FIFO level by asserting the frame signal high for at least the time interval required to load complete data to the I and Q DACs. This corresponds to one DCI period in word interface mode and two DCI periods in byte interface mode. Note that this requirement of the frame pulse length is longer than that of the frame signal when it serves only to assemble the byte stream. The device accepts either a continuous frame or a one shot frame signal. In the continuous reset mode, the FIFO responds to every valid frame pulse and resets itself. In the one shot reset mode, the FIFO responds only to the first valid frame pulse after the FRAME_RESET_MODE bits (Register 0x22[1:0]) are set. Therefore, even with a continuous frame input, the FIFO resets one time only; this prevents the FIFO from toggling between the two states from periodic resets. The one shot frame reset mode is the default and the recommended mode. Rev. A | Page 30 of 72 Data Sheet AD9142A The recommended procedure for a frame initiated FIFO reset is as follows: 1. 2. 3. 4. 5. 6. 7. Configure the DAC in the desired interpolation mode (Register 0x28[1:0]). Ensure that the DACCLK and DCI are running and stable at the clock inputs. Ensure that the DLL is locked (if using DLL mode) or the DCI clock is being sent properly (if using bypass mode). Program Register 0x23 to the customized value, if the desired value is not 0x40. Configure the FRAME_RESET_MODE bits (Register 0x22, Bits [1:0]) to 00b. Choose whether to use continuous or one shot mode by writing 0 or 1 to EN_CON_FRAME_RESET (Register 0x22, Bit 2). Toggle the frame input from 0 to 1 and back to 0. The pulse width needs to be longer than the minimum requirement. a. If the frame input is a continuous clock, turn on the signal. Read back Register 0x24 multiple times to verify that the actual FIFO level is set to the requested level and the readback values are stable. By design, the readback is within ±1 DACCLK around the requested level. Monitoring the FIFO Status The real-time FIFO status can be monitored from the SPI Register 0x24 and reflects the real-time FIFO depth after a FIFO reset. Without timing drifts in the system, this readback does not change from that which resulted from the FIFO reset. When there is a timing drift or other abnormal clocking situation, the FIFO level readback can change. However, as long as the FIFO does not overflow or underflow, there is no error in data transmission. Three status bits in Register 0x06, Bits[2:0], indicate if there are FIFO underflows, overflows, or similar situations. The status of the three bits can be latched and used to trigger hardware interrupts, IRQ1 and IRQ2. To enable latching and interrupts, configure the corresponding bits in Register 0x03 and Register 0x04. Rev. A | Page 31 of 72 AD9142A Data Sheet DIGITAL DATAPATH HB1 HB2 HB3 COARSE AND FINE MODULATION DIGITAL GAIN AND PHASE AND OFFSET ADJUSTMENT INV SINC 11901-041 INPUT POWER DETECTION AND PROTECTION Figure 40. Block Diagram of Digital Datapath 0.02 The block diagram in Figure 40 shows the functionality of the digital datapath. The digital processing includes The interpolation filters accept I and Q data streams and process them as two independent data streams, whereas the quadrature modulator and phase adjustment block accepts I and Q data streams as a quadrature data stream. Therefore, quadrature input data is required when digital modulation and phase adjustment functions are used. –0.02 –0.04 –0.06 –0.10 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 1.8 2.0 FREQUENCY (Hz) 11901-042 –0.08 Figure 41. Pass-Band Detail of 2× Mode 10 INTERPOLATION FILTERS 0 The AD9142A provides three interpolation modes (see Table 6). Each mode offers a different usable signal bandwidth in an operating mode. Which mode to select depends on the required signal bandwidth and the DAC update rate. Refer to Table 6 for the maximum speed and signal bandwidth of each interpolation mode. –10 –20 MAGNITUDE (dB) The transmit path contains three interpolation filters. Each of the three interpolation filters provides a 2× increase in output data rate and a low-pass function. The half-band (HB) filters are cascaded to provide 4× or 8× interpolation ratios. The usable bandwidth is defined as the frequency band over which the filters have a pass-band ripple of less than ±0.001 dB and a stop band rejection of greater than 85 dB. 2× Interpolation Mode Figure 41 and Figure 42 show the pass-band and all-band filter response for 2× mode. Note that the transition from the transition band to the stop band is much sharper than the transition from the pass band to the transition band. Therefore, when the desired output signal moves out of the defined pass band, the signal image, which is supposed to be suppressed by the stop band, grows faster than the droop of the signal itself due to the degraded pass-band flatness. In cases where the degraded image rejection is acceptable or can be compensated by the analog low-pass filter at the DAC output, it is possible to let the output signal extend beyond the specified usable signal bandwidth. Rev. A | Page 32 of 72 –30 –40 –50 –60 –70 –80 –90 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 FREQUENCY (Hz) Figure 42. All-Band Response of 2× Mode 11901-043 0 An input power detection block Three half-band interpolation filters A quadrature modulator consisting of a fine resolution NCO and an fS/4 coarse modulation block An inverse sinc filter A gain and phase and offset adjustment block MAGNITUDE (dB) Data Sheet AD9142A 4× Interpolation Mode 10 0 Figure 43 and Figure 44 show the pass-band and all-band filter responses for 4× mode. –10 –20 MAGNITUDE (dB) 0.02 –0.02 –40 –50 –60 –70 –0.04 –80 –90 –0.06 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 FREQUENCY (Hz) –0.08 1.8 2.0 11901-049 MAGNITUDE (dB) 0 –30 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 FREQUENCY (Hz) 11901-046 Figure 46. All-Band Response of 8× Mode –0.10 Figure 43. Pass-Band Detail of 4× Mode 10 0 –10 MAGNITUDE (dB) –20 –30 –40 –50 –60 –70 –80 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 FREQUENCY (Hz) 11901-047 –90 Figure 44. All-Band Response of 4× Mode 8× Interpolation Mode Figure 45 and Figure 46 show the pass-band and all-band filter responses for 8× mode. The maximum DAC update rate is 1.6 GHz, and the maximum input data rate that is supported in this mode is 200 MHz (1.6 GHz/8). 0.02 –0.02 Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28) –0.04 –0.06 –0.08 –0.10 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 FREQUENCY (Hz) 0.40 0.45 11901-048 MAGNITUDE (dB) 0 Table 18. Half-Band Filter 1 Coefficient Figure 45. Pass-Band Detail of 8× Mode Rev. A | Page 33 of 72 Upper Coefficient H(55) H(54) H(53) H(52) H(51) H(50) H(49) H(48) H(47) H(46) H(45) H(44) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) Integer Value −4 0 +13 0 −32 0 +69 0 −134 0 +239 0 −401 0 +642 0 −994 0 +1512 0 −2307 0 +3665 0 −6638 0 +20,754 +32,768 AD9142A Data Sheet I DATA OUT I DATA IN Table 19. Half-Band Filter 2 Coefficient Upper Coefficient H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) Integer Value −2 0 +17 0 −75 0 +238 0 −660 0 +2530 +4096 Table 20. Half-Band Filter 3 Coefficient Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) Upper Coefficient H(11) H(10) H(9) H(8) H(7) Integer Value +29 0 −214 0 +1209 +2048 FTW[31:0] COSINE ~ NCO PHASE[15:0] SINE Q DATA IN Figure 47. NCO Modulator Block Diagram The NCO modulator mixes the carrier signal generated by the NCO with the I and Q signals. The NCO produces a quadrature carrier signal to translate the input signal to a new center frequency. A complex carrier signal is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. The frequency of the complex carrier signal is set via NCO_FTW3 to NCO_FTW0 in Register 0x31 through Register 0x34. The NCO operating frequency, fNCO, is always equal to fDAC, the DACCLK frequency. The frequency of the complex carrier signal can be set from dc up to ±0.5 × fNCO. The frequency tuning word (FTW) is in twos complement format. It can be calculated as DIGITAL MODULATION f DAC f f CARRIER DAC 2 2 f CARRIER The AD9142A provides two modes to modulate the baseband quadrature signal to the desired DAC output frequency. FTW FTW (1 Coarse (fS/4) modulation Fine (NCO) modulation fS/4 Modulation The fS/4 modulation is a convenient and low power modulation mode to translate the input baseband frequency to a fixed fS/4 IF frequency, fS being the DAC sampling rate. When modulation frequencies other than this frequency are required, the NCO modulation mode must be used. NCO Modulation The NCO modulation mode makes use of a numerically controlled oscillator (NCO), a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. A block diagram of the digital modulator is shown in Figure 47. The NCO modulation allows the DAC output signal to be placed anywhere in the output spectrum with very fine frequency resolution. Q DATA OUT 11901-050 Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) f DAC f 2 32 f CARRIER f DAC CARRIER 0 ) (2 32 ) f CARRIER 0 The generated quadrature carrier signal is mixed with the I and Q data. The quadrature products are then summed into the I and Q data paths, as shown in Figure 47. Updating the Frequency Tuning Word The frequency tuning word registers are not updated immediately upon writing, as are other configuration registers. Similar to FIFO reset, the NCO update can be triggered in two ways. Rev. A | Page 34 of 72 SPI initiated update Frame initiated update Data Sheet AD9142A SPI Initiated Update Quadrature Gain Adjustment In the SPI initiated update method, the user simply toggles Register 0x30[0] (NCO_SPI_UPDATE_REQ) after configuring the NCO settings. The NCO is updated on the rising edge (from 0 to 1) in this bit. Register 0x30[1] (NCO_SPI_UPDATE_ACK) goes high when the NCO is updated. A falling edge (from 1 to 0) in Register 0x30[0] clears Bit 1 of Register 0x30 and prepares the NCO for the next update operation. This update method is recommended when there is no requirement to align the DAC output from multiple devices because SPI writes to multiple devices are asynchronous. Ordinarily, the I and Q channels have the same gain or signal magnitude. The quadrature gain adjustment is used to balance the gain between the I and Q channels. The digital gain of the I and Q channels can be adjusted independently through two 6-bit registers, IDAC_GAIN_ADJ (Register 0x3F[5:0]) and QDAC_GAIN_ADJ (Register 0x40[5:0]). The range of the adjustment is [0, 2] or [−∞, 6 dB] with a step size of 2−5 (−30 dB). The default setting is 0x20, corresponding to a gain equal to 1 or 0 dB. Configuring the AD9142A datapath starts with the following four parameters: • • • • The application requirements of the input data rate The interpolation ratio The output signal center frequency The output signal bandwidth Given these four parameters, the first step to configure the datapath is to verify that the device supports the desired input data rate, the DAC sampling rate, and the bandwidth requirements. After this verification, the modes of the interpolation filters can be chosen. If the output signal center frequency is different from the baseband input center frequency, additional frequency offset requirements are determined and applied with on-chip digital modulation. DIGITAL QUADRATURE GAIN AND PHASE ADJUSTMENT The digital quadrature gain and phase adjustment function enables compensation of the gain and phase imbalance of the I and Q paths caused by analog mismatches between DAC I/Q outputs, quadrature modulator I/Q baseband inputs, and DAC/modulator interface I/Q paths. The undesired imbalances cause unwanted sideband signal to appear at the quadrature modulator output with significant energy. Tuning the quadrature gain and phase adjust values optimizes image rejection in single sideband radios. The dc value of the I datapath and the Q datapath can be controlled independently by adjusting the values in the two IDAC dc offset 16-bit registers, IDAC_DC_OFFSET_LSB, IDAC_DC_OFFSET_MSB, QDAC_DC_OFFSET_LSB, and QDAC_DC_OFFSET_MSB (Register 0x3B through Register 0x3E). These values are added directly to the datapath values. Take care not to overrange the transmitted values. As shown in Figure 48, the DAC offset current varies as a function of the I/QDAC dc offset values. Figure 48 shows the nominal current of the positive node of the DAC output, IOUTP, when the digital inputs are fixed at midscale (0x0000, twos complement data format) and the DAC offset value is swept from 0x0000 to 0xFFFF. Because IOUTP and IOUTN are complementary current outputs, the sum of IOUTP and IOUTN is always 20 mA. Rev. A | Page 35 of 72 20 0 15 5 10 10 5 15 0 0x0000 0x4000 0x8000 0xC000 20 0xFFFF DAC OFFSET VALUE Figure 48. DAC Output Currents vs. DAC Offset Value IOUTxN (mA) DATAPATH CONFIGURATION DC OFFSET ADJUSTMENT 11901-051 When the DAC output from multiple devices must be well aligned with NCO turned on, the frame initiated update is recommended. In this method, the NCOs from multiple devices are updated at the same time upon the rising edge of the frame signal. To use this update method, the FRAME_RESET_MODE (Register 0x22[1:0]) must be set in NCO only or FIFO and NCO, depending on whether a FIFO reset is needed at the same time. The second step is to ensure that the reset mode is in one shot mode (EN_CON_FRAME_RESET, Register 0x22[2] = 0). When this is completed, the NCO waits for a valid frame pulse and updates the FTW accordingly. The user can verify if the frame pulse is correctly received by reading Register 0x30[6] (NCO_FRAME_ UPDATE_ACK) wherein a 1 indicates a complete update operation. See the FIFO Operation section for information to generate a valid frame pulse. Under normal circumstances, I and Q channels have an angle of precisely 90° between them. The quadrature phase adjustment is used to change the angle between the I and Q channels. IQ_PHASE_ADJ_MSB and IQ_PHASE_ADJ_LSB (Register 0x37, Bits [7:0] and Register 0x38, Bits [4:0]) provide an adjustment range of ±14° with a resolution of 0.0035°. If the original angle is precisely 90°, setting IQ_PHASE_ADJ_MSB and IQ_PHASE_ADJ_LSB to 0x0FFF adds approximately 14° between I and QDAC outputs, creating an angle of 104° between the channels. Likewise, if the original angle is precisely 90°, setting IQ_PHASE_ADJ_MSB and IQ_PHASE_ADJ_LSB to 0x1000 adds approximately −14° between the I and QDAC outputs, creating an angle of 76° between the channels. IOUTxP (mA) Frame Initiated Update Quadrature Phase Adjustment AD9142A Data Sheet INVERSE SINC FILTER INPUT SIGNAL POWER DETECTION AND PROTECTION The AD9142A provides a digital inverse sinc filter to compensate for the DAC roll-off over frequency. The inverse sinc (sinc−1) filter is a seven-tap FIR filter. Figure 49 shows the frequency response of sin(x)/x roll-off, the inverse sinc filter, and their composite response. The composite response has less than ±0.05 dB pass-band ripple up to a frequency of 0.4 × fDAC. The input signal power detection and protection function detects the average power of the DAC input signal and prevents overrange signals from being passed to the next stage. An overrange DAC output signal can cause destructive breakdown on power sensitive devices, such as power amplifiers. The power detection and protection feature of the AD9142A detects overrange signals in the DAC. When an overrange signal is detected, the protection function either attenuates or mutes the signal to protect the downstream devices from abnormal power surges in the signal. To provide the necessary peaking at the upper end of the pass band, the inverse sinc filter has an intrinsic insertion loss of about 3.8 dB. The loss of the digital gain can be offset by increasing the quadrature gain adjustment setting on both the I and Q data paths to minimize the impact on the output signal-to-noise ratio. However, care is needed to ensure that the additional digital gain does not cause signal saturation, especially at high output frequencies. The sinc−1 filter is disabled by default; it can be enabled by setting the INVSINC_ENABLE bit to 1 in Register 0x27[7]). Figure 50 shows the block diagram of the power detection and protection function. The protection block is at the very last stage of the data path and the detection block uses a separate path from the data path. The design of the detection block guarantees that the worst-case latency of power detecting is shorter than that of the data path. This ensures that the protection circuit initiates before the overrange signal reaches the analog DAC core. 1 The sum of I2 and Q2 is calculated as a representation of the input signal power. Only the upper six MSBs, D[15:10], of data samples are used in the calculation; consequently, samples whose power is 36 dB below the full-scale peak power are not detected. –1 –2 The calculated sample power numbers accumulate through a moving average filter. Its output is the average of the input signal power in a certain number of data clock cycles. The length of the filter is configurable through the SAMPLE_WINDOW_LENGTH (Register 0x2B[3:0]). To determine whether the input average power is over range, the device averages the power of the samples in the filter and compares the average power with a user defined threshold, THRESHOLD_LEVEL_REQUEST_LSB and THRESHOLD_LEVEL_REQUEST_MSB (Register 0x29[7:0] and Register 0x2A[4:0]). When the output of the averaging filter is larger than the threshold, the DAC output is either attenuated or muted. –3 –5 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 FREQUENCY (Hz) 0.45 0.50 11901-052 –4 Figure 49. Responses of sin(x)/x Roll Off (Blue), the Sinc−1 Filter (Red), and Composite of Both (Black) Table 21. Inverse Sinc Filter Lower Coefficient H(1) H(2) H(3) H(4) Upper Coefficient H(7) H(6) H(5) Integer Value −1 +4 −16 +192 The appropriate filter length and average power threshold for effective protection are application dependent. It is recommended that experiments be performed with real-world vectors to determine the values of these parameters. POWER PROTECTION (ATTENUATE OR MUTE) SIGNAL PROCESSING ENGINE FIFO DAC CORE POWER DETECTION I2 + Q2 AVERAGING FILTER FILTER LENGTH SETTINGS REG 0x2B[3:0] AVG POWER REG 0x2C[7:0] AND REG 0x2D[4:0] USER DEFINED THRESHOLD REG 0x29[7:0] AND REG 0x2A[4:0] Figure 50. Block Diagram of Input Signal Power Detection and Protection Function Rev. A | Page 36 of 72 11901-053 MAGNITUDE (dB) 0 Data Sheet AD9142A TRANSMIT ENABLE FUNCTION DIGITAL FUNCTION CONFIGURATION The transmit enable (TXEN) function provides the user with a hardware switch of the DAC output. The function accepts a CMOS signal via Pin 6 (TXEN). When this signal is detected high, the transmit path is enabled and the DAC transmits the data normally. When this signal is detected low, one of the three actions related to the DAC output is triggered. This can be configured in Register 0x43. Each of the digital gain and phase adjust functions and the inverse sinc filter can be enabled and adjusted independently. The pipeline latencies these blocks add into the data path are different between enabled and disabled. If fixed DAC pipeline latency is desired during operation, leave these functions always on or always off after initial configuration. 1. 2. 3. The DAC output is gradually attenuated from full scale gain to 0. The attenuation step size is set in Register 0x42[5:0]. The DAC is put in sleep mode and the output current is turned off. Other areas of the DAC are still running in this mode. The DAC is put in power-down mode. In this mode, not only the DAC output current is turned off but the rest of the DAC is powered down. This minimizes the power consumption of the DAC when the data is not transmitting but it takes a bit longer than the first two modes to start to retransmit data due to the device power-up time. The digital dc adjust function is always on. The default value is 0; that is, there is no additional dc offset. The pipeline latency that this block adds is a constant, no matter the value of the dc offset. There is also a latency difference between using and not using the input signal power detection and protection function. Therefore, to keep the overall latency fixed, leave this function always on or always off after the initial configuration. The TXEN function also provides a gain ramp-up function that lets the user turn on the DAC output gradually when the TXEN signal switches from low to high. The ramp-up gain step can be configured using Register 0x41[5:0]. Rev. A | Page 37 of 72 AD9142A Data Sheet MULTIDEVICE SYNCHRONIZATION AND FIXED LATENCY A DAC introduces a variation of pipeline latency to a system. The latency variation causes the phase of a DAC output to vary from power-on to power-on. Therefore, the output from different DAC devices may not be perfectly aligned even with well aligned clocks and digital inputs. The skew between multiple DAC outputs varies from power-on to power-on. In applications such as transmit diversity or digital predistortion, where deterministic latency is desired, the variation of the pipeline latency must be minimized. Deterministic latency in this data sheet is defined as a fixed time delay from the digital input to the analog output in a DAC from power-on to power-on. Multiple DAC devices are considered synchronized to each other when each DAC in this group has the same constant latency from power-on to power-on. Three conditions must be identical in all of the ready-to-sync devices before these devices are considered synchronized: • • • The phase of DAC internal clocks The FIFO level The alignment of the input data VERY SMALL INHERENT LATENCY VARIATION The innovative architecture of the AD9142A minimizes the inherent latency variation. The worst-case variation in the AD9142A is two DAC clock cycles. For example, in the case of a 1.5 GHz sample rate, the variation is less than 1.4 ns in any scenario. Therefore, without turning on the synchronization engine, the DAC outputs from multiple AD9142A devices are guaranteed to be aligned within two DAC clock cycles, regardless of the timing between the DCI and the DACCLK. No additional clocks are required to achieve this accuracy. The user must reset the FIFO in each DAC device through the SPI at startup. Therefore, the AD9142A can decrease the complexity of system design in multitransmit channel applications. Note the alignment of the DCI signals in the design. The DCI is used as a reference in the AD9142A design to align the FIFO and the phase of internal clocks in multiple devices. The achieved DAC output alignment depends on how well the DCI signals are aligned at the input of each device. The following equation is the expression of the worst-case DAC output alignment accuracy in the case of DCI signal mismatches. tSK (OUT) = tSK (DCI) + 2/fDAC where: tSK (OUT) is the worst-case skew between the DAC output from two AD9142A devices. tSK (DCI) is the skew between two DCI signals at the DCI input of the two AD9142A devices. fDAC is the DACCLK frequency. The better the alignment of the DCI signals, the smaller is the overall skew between two DAC outputs. FURTHER REDUCING THE LATENCY VARIATION For applications that require finer synchronization accuracy (DAC latency variation < 2 DAC clock cycles), the AD9142A has a provision for enabling multiple devices to be synchronized to each other within a single DAC clock cycle. To further reduce the latency variation in the DAC, the synchronization machine needs to be turned on and two external clocks (frame and sync) need to be generated in the system and fed to all the DAC devices. Set Up and Hold Timing Requirement The sync clock (fSYNC) serves as a reference clock in the system to reset the clock generation circuitry in multiple AD9142A devices simultaneously. Inside the DAC, the sync clock is sampled by the DACCLK to generate a reference point for aligning the internal clocks, so there is a setup and hold timing requirement between the sync clock and the DAC clock. If the user adopts the continuous frame reset mode, that is, the FIFO and sync engine periodically reset, the timing requirements between the sync clock and the DAC clock must be met. Otherwise, the device can lose lock and corrupt the output. In the one shot frame reset mode, it is still recommended that this timing be met at the time when the sync routine is run because not meeting the timing can degrade the sync alignment accuracy by one DAC cycle, as shown in Table 22. For users who want to synchronize the device in a one-shot manner and continue to monitor the synchronization status, the AD9142A provides a sync monitoring mode. It provides a continuous sync and frame clock to synchronize the part once and ignore the clock cycles after the first valid frame pulse is detected. In this way, the user can monitor the sync status without periodically resynchronizing the device; to engage the sync monitoring mode, set Register 0x22[1:0] (FRAME_RESET_ MODE) to 11b. Table 22. Sync Clock and DAC Clock Setup and Hold Times Falling Edge Sync Timing (default) tS (ns) tH (ns) 1 |tS + tH| (ns) 1 Max (ps) 324 −92 232 The negative sign indicates the direction of the setup time. The setup time is defined as positive when it is on the left side of the clock edge and negative when it is on the right side of the clock edge. Rev. A | Page 38 of 72 Data Sheet AD9142A Synchronization Procedure for PLL Off SYNCHRONIZATION IMPLEMENTATION The AD9142A lets the user choose either the rising or falling edge of the DAC clock to sample the sync clock, which makes it easier to meet the timing requirements. Ensure that the sync clock, fSYNC, is 1/8 × fDATA or slower by a factor of 2n, n being an integer (1, 2, 3…). Note that there is a limit on how slow the sync clock can be received because of the ac coupling nature of the sync clock receiver. Choose an appropriate value of the ac coupling capacitors to ensure that the signal swing meets the data sheet specification, as listed in Table 2. 1. 2. 3. Configure the DAC interpolation mode and, if NCO is used, configure the NCO FTW. Set up the DAC data interface according to the procedure outlined in the Data Interface section and verify that the DLL is locked. Choose the appropriate mode in the FRAME_RESET_MODE bits (Register 0x22[1:0]). a. If NCO is not used, choose FIFO only mode. b. If NCO is used, it must be synchronized. FIFO and NCO mode can then be used. Configure Bit 2 in Register 0x22 for continuous or one shot reset mode. One shot reset mode is recommended. Ensure that the DACCLK, DCI, and sync clock to all of the AD9142A devices are running and stable. Enable the sync engine by writing 1 to Register 0x21[0]. Send a valid frame pulse(s) to all of the AD9142A devices. Verify that the frame pulse is received by each device by reading back Register 0x22[3]. All the readback values are 1. At this point, the devices should be synchronized. The frame clock resets the FIFO in multiple AD9142A devices. The frame can be either a one shot or continuous clock. In either case, the pulse width of the frame must be longer than one DCI cycle in the word interface mode and two DCI cycles in the byte interface mode. When the frame is a continuous clock, fFRAME, ensure that it is 1/8 × fDATA or slower by a factor of 2n, n being an integer (1, 2, 3…). Table 23 lists the requirements of the frame clock in various conditions. Byte interface mode is not supported when the frame signal is used in synchronization. 4. Table 23. Frame Clock Speed and Pulse Width Requirement Synchronization Procedure for PLL On Sync Clock One Shot Continuous 1 Maximum Speed N/A1 fDATA/8 Minimum Pulse Width For both one shot and continuous sync clocks, word interface mode = one DCI cycle and byte interface mode = two DCI cycles. N/A means not applicable. 5. 6. 7. 8. Note that, because the sync clock and PLL reference clock share the same clock and the maximum sync clock rate is fDATA/8, the same limit also applies to the reference clock. Therefore, only 2× interpolation is supported for synchronization with PLL on. 1. 2. SYNCHRONIZATION PROCEDURES When the sync accuracy of an application is less precise than two DAC clock cycles, it is recommended to turn off the synchronization machine because there are no additional steps required, other than the regular start-up procedure sequence. For applications that require more precise sync accuracy than two DAC clock cycles, it is recommended that the procedure in the Synchronization Procedure for PLL Off or Synchronization Procedure for PLL On sections be followed to set up the system and configure the device. For more information about the details of the synchronization scheme in the AD9142A and using the synchronization function to correct system skews and drifts, see the DAC Latency and System Skews section. 3. 4. 5. 6. 7. 8. 9. Rev. A | Page 39 of 72 Set up the PLL according to the procedure in the Clock Multiplication section and ensure that the PLL is locked. Configure the DAC interpolation mode and, if NCO is used, configure the NCO FTW. Set up the DAC data interface according to the procedure in the Data Interface section and verify that the DLL is locked. Choose the appropriate mode in the FRAME_RESET_MODE bits (Register 0x22[1:0]) a. If NCO is not used, choose the FIFO only mode. b. If NCO is used, it must be synchronized. FIFO and NCO mode can then be used. Configure Bit 2 in Register 0x22 for continuous or one shot reset mode. One shot reset mode is recommended. Ensure that DACCLK, DCI, and sync clock to all of the AD9142A devices are running. Enable the sync engine by writing 1 to Register 0x21[0]. Send a valid frame pulse(s) to all of the AD9142A devices. Verify that the frame pulse is received by each device by reading back Register 0x22[3]. All the readback values are 1. At this point, the devices should be synchronized. AD9142A Data Sheet INTERRUPT REQUEST OPERATION method is by writing 1 to the corresponding event flag bit. The second method is to use a hardware or software reset to clear the INTERRUPT_SOURCE signal. The AD9142A provides an interrupt request output signal on Pin 50 and Pin 51 (IRQ2 and IRQ1, respectively) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, query the device to determine the precise event that occurred. The IRQ1 pin is an open-drain, active low output. Pull the IRQ1 pin high external to the device. This pin can be tied to the interrupt pins of other devices with open-drain outputs to wire-OR these pins together. The IRQ2 circuitry works in the same way as the IRQ1 circuitry. Any one or multiple event flags can be enabled to trigger the IRQ1 and IRQ2 pins. The user can select one or both hardware interrupt pins for the enabled event flags. Register 0x07 and Register 0x08 determine the pin to which each event flag is routed. Set Register 0x07 and Register 0x08 to 0 for IRQ1 and set these registers to 1 for IRQ2. Ten event flags provide visibility into the device. These flags are located in the two event flag registers, Register 0x05 and Register 0x06. The behavior of each event flag is independently selected in the interrupt enable registers, Register 0x03 and Register 0x04. When the flag interrupt enable is active, the event flag latches and triggers an external interrupt. When the flag interrupt is disabled, the event flag monitors the source signal, but the IRQ1 and IRQ2 pins remain inactive. INTERRUPT SERVICE ROUTINE Interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. Enable the events that require host action so that the host is notified when they occur. For events requiring host intervention upon IRQx activation, run the following routine to clear an interrupt request: INTERRUPT WORKING MECHANISM Figure 51 shows the interrupt related circuitry and how the event flag signals propagate to the IRQx output. The INTERRUPT_ ENABLE signal represents one bit from the interrupt enable register. The EVENT_FLAG_SOURCE signal represents one bit from the event flag register. The EVENT_FLAG_SOURCE signal represents one of the device signals that can be monitored, such as the PLL_LOCK signal from the PLL phase detector or the FIFO_WARNING_1 signal from the FIFO controller. 1. 2. 3. 4. When an interrupt enable bit is set high, the corresponding event flag bit reflects a positively tripped version of the EVENT_FLAG_ SOURCE signal; that is, the event flag bit is latched on the rising edge of the EVENT_FLAG_SOURCE signal. This signal also asserts the external IRQ pins. 5. 6. Read the status of the event flag bits that are being monitored. Set the interrupt enable bit low so that the unlatched EVENT_FLAG_SOURCE signal can be monitored directly. Perform any actions that may be required to clear the EVENT_FLAG_SOURCE signal. In many cases, no specific actions may be required. Read the event flag to verify that the actions taken have cleared the EVENT_FLAG_SOURCE signal. Clear the interrupt by writing 1 to the event flag bit. Set the interrupt enable bits of the events to be monitored. Note that some EVENT_FLAG_SOURCE signals are latched signals. These signals are cleared by writing to the corresponding event flag bit. For more information about each of the event flags, see the Device Configuration Register Map section. When an interrupt enable bit is set low, the event flag bit reflects the present status of the EVENT_FLAG_SOURCE signal, and the event flag has no effect on the external IRQ pins. Clear the latched version of an event flag (the INTERRUPT_ SOURCE signal) in one of two ways. The recommended 0 1 EVENT_FLAG IRQ INTERRUPT_ENABLE EVENT_FLAG_SOURCE INTERRUPT_ SOURCE OTHER INTERRUPT SOURCES 11901-054 WRITE_1_TO_EVENT_FLAG DEVICE_RESET Figure 51. Simplified Schematic of IRQ Circuitry Rev. A | Page 40 of 72 Data Sheet AD9142A TEMPERATURE SENSOR The AD9142A has a diode-based temperature sensor for measuring the temperature of the die. The temperature reading is accessed using Register 0x1D and Register 0x1E. The temperature of the die can be calculated as T DIE = TA = TDIE – PD × θJA = 50 – 0.8 × 20.7 = 33.4°C ( DieTemp [ 15 : 0 ] − 41, 237 ) 106 where TDIE is the die temperature in degrees Celsius. The temperature accuracy is ±7°C typical over the +85°C to −40°C range with one point temperature calibration against a known temperature. A typical plot of the die temperature code readback vs. die temperature is shown in Figure 52. 51000 49000 where: TA is the ambient temperature in degrees Celsius. TDIE is the die temperature in degrees Celsius. PD is power consumption of the device. θJA is the thermal resistance from junction to ambient of the AD9142A as shown in Table 8. To use the temperature sensor, it must be enabled by setting Register 0x1C[0] to 1. In addition, to obtain accurate readings, set the die temperature control register (Register 0x1C) to 0x03. 47000 45000 43000 41000 39000 37000 35000 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 11901-201 DIE CODE READBACK Estimates of the ambient temperature can be made if the power dissipation of the device is known. For example, if the device power dissipation is 800 mW and the measured die temperature is 50°C, then the ambient temperature can be calculated as Figure 52. Die Temperature Code Readback vs. Die Temperature Rev. A | Page 41 of 72 AD9142A Data Sheet DAC INPUT CLOCK CONFIGURATIONS The AD9142A DAC sample clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying employs the on-chip PLL that accepts a reference clock operating at a submultiple of the desired DACCLK rate. The PLL then multiplies the reference clock up to the desired DACCLK frequency, which can then be used to generate all of the internal clocks required by the DAC. The clock multiplier provides a high quality clock that meets the performance requirements of most applications. Using the on-chip clock multiplier removes the burden of generating and distributing the high speed DACCLK. The second mode bypasses the clock multiplier circuitry and lets DACCLK be sourced directly to the DAC core. This mode lets the user source a very high quality clock directly to the DAC core. DRIVING THE DACCLK AND REFCLK INPUTS The DACCLKx and REFx/SYNCx differential inputs share similar clock receiver input circuitry. Figure 53 shows a simplified circuit diagram of the input. The on-chip clock receiver has a differential input impedance of about 10 kΩ. It is self biased to a common-mode voltage of about 1.25 V. The inputs can be driven by differential PECL or LVDS drivers with ac coupling between the clock source and the receiver. 1~100nF AD9142A DACCLKP/ REFP/SYNCP Direct clocking with a low noise clock produces the lowest noise spectral density at the DAC outputs. To select the differential CLK inputs as the source for the DAC sampling clock, set the PLL enable bit (Register 0x12[7]) to 0. This powers down the internal PLL clock multiplier and selects the input from the DACCLKP and DACCLKN pins as the source for the internal DAC sampling clock. The REFCLKx input can remain floating. The device also has clock duty cycle correction circuitry and differential input level correction circuitry. Enabling these circuits can provide improved performance in some cases. The control bits for these functions are in Register 0x10 and Register 0x11. CLOCK MULTIPLICATION The on-chip PLL clock multiplier circuit generates the DAC sample rate clock from a lower frequency reference clock. When the PLL enable bit (Register 0x12[7]) is set to 1, the clock multiplication circuit generates the DAC sampling clock from the lower rate REFx/SYNCx input and the DACCLKx input is left floating. The functional diagram of the clock multiplier is shown in Figure 54. The clock multiplier circuit operates such that the VCO outputs a frequency, fVCO, equal to the REFx/SYNCx input signal frequency multiplied by N1 × N0. N1 is the divide ratio of the loop divider; N0 is the divide ratio of the VCO divider. fVCO = fREFCLK × (N1 × N0) 5kΩ 1~100nF 5kΩ DACCLKN/ REFN/SYNCN The DAC sample clock frequency, fDACCLK, is equal to 1.25V fDACCLK = fREFCLK × N1 11901-055 100Ω Figure 53. Clock Receiver Input Simplified Equivalent Circuit The minimum input drive level to the differential clock input is 100 mV p-p differential. The optimal performance is achieved when the clock input signal is between 800 mV p-p differential and 1.6 V p-p differential. Whether using the on-chip clock multiplier or sourcing the DACCLK directly, the input clock signal to the device must have low jitter and fast edge rates to optimize the DAC noise performance. REFP/SYNCP (PIN 2) REFN/SYNCN (PIN 3) PHASE FREQUENCY DETECTION The output frequency of the VCO must be chosen to keep fVCO in the optimal operating range of 1.03 GHz to 2.07 GHz. It is important to select a frequency of the reference clock and values of N1 and N0 so that the desired DACCLK frequency can be synthesized and the VCO output frequency is in the correct range. ADC PLL CHARGE PUMP CURRENT REG 0x14[4:0] PLL LOOP BW REG 0x14[7:5] CHARGE PUMP ON-CHIP LOOP FILTER VCO (1GHz~2.1GHz) LOOP DIVIDER REG 0x15[1:0] VCO DIVIDER REG 0x15[3:2] DIVIDE BY 2, 4, 8, OR 16 DIVIDE BY 1, 2, OR 4 DACCLKN (PIN 62) VCO CONTROL VOLTAGE REG 0x16[3:0] DACCLK DACCLKP (PIN 61) PLL ENABLE REG 0x12[7] Figure 54. PLL Clock Multiplication Circuit Rev. A | Page 42 of 72 11901-056 RECOMMENDED EXTERNAL CIRCUITRY DIRECT CLOCKING Data Sheet AD9142A PLL SETTINGS 61 57 The PLL circuitry requires three settings to be programmed to their nominal values. The PLL values shown in Table 24 are the recommended settings for these parameters. 53 49 45 PLL BAND 41 Table 24. PLL Settings Register Address 0x14[7:5] 0x14[4:0] 0x15[4] Optimal Setting (Binary) 111 00111 0 33 29 25 21 17 13 9 5 1 950 CONFIGURING THE VCO TUNING BAND 1150 1350 1550 1750 1950 VCO FREQUENCY (MHz) 2150 11901-057 PLL SPI Control Register PLL Loop Bandwidth PLL Charge Pump Current PLL Cross Point Control Enable 37 The PLL VCO has a valid operating range from approximately 1.03 GHz to 2.07 GHz covered in 64 overlapping frequency bands. For any desired VCO output frequency, there may be several valid PLL band select values. The frequency bands of a typical device are shown in Figure 55. Device-to-device variations and operating temperature affect the actual band frequency range. Therefore, it is required that the optimal PLL band select value be determined for each individual device. The device includes a manual band select mode (PLL auto manual enable, Register 0x12[6] = 1) that lets the user select the VCO tuning band. In manual mode, the VCO band is set directly with the value written to the manual VCO band bits (Register 0x12[5:0]). AUTOMATIC VCO BAND SELECT PLL ENABLE SEQUENCE The device has an automatic VCO band select feature on chip. Using the automatic VCO band select feature is a simple and reliable method of configuring the VCO frequency band. This feature is enabled by starting the PLL in manual mode, and then placing the PLL in autoband select mode by setting Register 0x12 to a value of 0xC0 and then to a value of 0x80. When these values are written, the device executes an automated routine that determines the optimal VCO band setting for the device. To enable the PLL in automatic or manual mode properly, the following sequence must be followed: The setting selected by the device ensures that the PLL remains locked over the full −40°C to +85°C operating temperature range of the device without further adjustment. The PLL remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes. 6. 7. 8. Figure 55. PLL Lock Range for a Typical Device MANUAL VCO BAND SELECT Automatic Mode Sequence 4. 5. Configure the loop divider and the VCO divider registers for the desired divide ratios. Set 00111b to PLL charge pump current and 111b to PLL loop bandwidth for the best performance. Register 0x14 = 0xE7 (default). Set the PLL mode to manual using Register 0x12[6] = 1. Enable the PLL using Register 0x12[7] = 1. Set the PLL mode to automatic using Register 0x12[6] = 0. Manual Mode 1. 2. 3. 4. 5. Rev. A | Page 43 of 72 Configure the loop divider and the VCO divider registers for the desired divide ratios. Set 00111b to PLL charge pump current and 111 to PLL loop bandwidth for the best performance. Register 0x14 = 0xE7 (default). Select the desired band using Register 0x12[5:0]. Set the PLL mode to manual using Register 0x12[6] = 1. Enable the PLL using Register 0x12[7] = 1. AD9142A Data Sheet ANALOG OUTPUTS Figure 56 shows a simplified block diagram of the transmit path DACs. The DAC core consists of a current source array, a switch core, digital control logic, and full-scale output current control. The DAC full-scale output current (IOUTFS) is nominally 20 mA. The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the DAC. The digital input code to the DAC determines the effective differential current delivered to the load. 1.2V I DAC FS ADJUST REG 0x18, REG 0x19 For nominal values of VREF (1.2 V), RSET (10 kΩ), and DAC gain (512), the full-scale current of the DAC is typically 20 mA. The DAC full-scale current can be adjusted from 8.64 mA to 31.68 mA by setting the DAC gain parameter, as shown in Figure 57. 35 30 25 IFS (mA) TRANSMIT DAC OPERATION 20 15 IOUT1P I DAC FSADJ CURRENT SCALING 10kΩ RSET 5 IOUT2N Q DAC IOUT2P Q DAC FS ADJUST REG 0x1A, REG 0x1B 0 11901-058 0.1µF 10 IOUT1N Figure 56. Simplified Block Diagram of DAC Core The DAC has a 1.2 V band gap reference with an output impedance of 5 kΩ. The reference output voltage appears on the VREF pin. When using the internal reference, decouple the VREF pin to AVSS with a 0.1 μF capacitor. Use the internal reference only for external circuits that draw dc currents of 2 μA or less. For dynamic loads or static loads greater than 2 μA, buffer the VREF pin. If desired, the internal reference can be overdriven by applying an external reference (from 1.10 V to 1.30 V) to the VREF pin. A 10 kΩ external resistor, RSET, must be connected from the FSADJ pin to AVSS. This resistor, together with the reference control amplifier, sets up the correct internal bias currents for the DAC. Because the full-scale current is inversely proportional to this resistor, the tolerance of RSET is reflected in the full-scale output amplitude. The full-scale current equation, where the DAC gain is individually set for the Q and I DACs in Register 0x40 and Register 0x44, respectively, is as follows: I FS VREF 3 72 DAC gain RSET 16 0 200 400 600 800 DAC GAIN CODE 1000 11901-059 5kΩ VREF Figure 57. DAC Full-Scale Current vs. DAC Gain Code Transmit DAC Transfer Function The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the DAC. The digital input code to the DAC determines the effective differential current delivered to the load. IOUT1P/IOUT2P provide maximum output current when all bits are high. The output currents vs. DACCODE for the DAC outputs is expressed as DACCODE I OUTP I OUTFS 2N IOUTN = IOUTFS – IOUTP (1) (2) where DACCODE = 0 to 2N − 1. Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9142A is realized when it is configured for differential operation. The common-mode rejection of a transformer or differential amplifier significantly reduces the common-mode error sources of the DAC outputs. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the firstorder cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Rev. A | Page 44 of 72 Data Sheet AD9142A VIP IOUT1P AD9142A IOUT1P ADL537x 67 IOUT1N + IOUT2N 66 RLI 100Ω RBIN 50Ω IBBN 59 QBBN RBQN 50Ω RO VOUTI RO IBBP RBIP 50Ω VIN – IOUT2P RLQ 100Ω RBQP 50Ω 58 QBBP IOUT1N 11901-062 Figure 58 shows the most basic DAC output circuitry. A pair of resistors, RO, converts each of the complementary output currents to a differential voltage output, VOUT. Because the current outputs of the DAC are high impedance, the differential driving point impedance of the DAC outputs, ROUT, is equal to 2 × RO. See Figure 59 for the output voltage waveforms. Figure 60. Typical Interface Circuitry Between the AD9142A and the ADL537x Family of Modulators VQP + IOUT2P The baseband inputs of the ADL537x family require a dc bias of 500 mV. The nominal midscale output current on each output of the DAC is 10 mA (one-half the full-scale current). Therefore, a single 50 Ω resistor to ground from each of the DAC outputs results in the desired 500 mV dc common-mode bias for the inputs to the ADL537x. The addition of the load resistor in parallel with the modulator inputs reduces the signal level. The peak-to-peak voltage swing of the transmitted signal is RO VQN – IOUT2N 11901-060 VOUTQ RO Figure 58. Basic Transmit DAC Output Circuit +VPEAK V SIGNAL I FS VCM VN VP (2 R B R L ) (2 R B R L ) Baseband Filter Implementation 0 Most applications require a baseband anti-imaging filter between the DAC and the modulator to filter out Nyquist images and broadband DAC noise. The filter can be inserted between the I-V resistors at the DAC output and the signal level setting resistor across the modulator input. This configuration establishes the input and output impedances for the filter. 11901-061 VOUT Figure 61 shows a fifth-order, low-pass filter. A common-mode choke is placed between the I-V resistors and the remainder of the filter to remove the common-mode signal produced by the DAC and to prevent the common-mode signal from being converted to a differential signal, which can appear as unwanted spurious signals in the output spectrum. Splitting the first filter capacitor into two and grounding the center point creates a common-mode low-pass filter, which provides additional common-mode rejection of high frequency signals. A purely differential filter can pass common-mode signals. Figure 59. Output Voltage Waveforms The common-mode signal voltage, VCM, is calculated as VCM I FS RO 2 The peak output voltage, VPEAK, is calculated as VPEAK = IFS × RO In this circuit configuration, the single-ended peak voltage is the same as the peak differential output voltage. INTERFACING TO MODULATORS For more details about interfacing the AD9142A DAC to an IQ modulator, refer to the Circuits from the Lab™ Circuit Note CN-0205, Interfacing the ADL5375 I/Q Modulator to the AD9122 Dual Channel, 1.2 GSPS High Speed DAC on the Analog Devices website. The AD9142A interfaces to the ADL537x family of modulators with a minimal number of components. An example of the recommended interface circuitry is shown in Figure 60. 22pF 50Ω AD9142A 33nH 33nH 33nH 33nH 3.6pF 50Ω 3pF 6pF 22pF 140Ω ADL537x 3pF Figure 61. DAC Modulator Interface with Fifth-Order, Low-Pass Filter Rev. A | Page 45 of 72 11901-063 –VPEAK AD9142A Data Sheet REDUCING LO LEAKAGE AND UNWANTED SIDEBANDS Analog quadrature modulators can introduce unwanted signals at the local oscillator (LO) frequency due to dc offset voltages in the I and Q baseband inputs, as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output using the digital dc offset adjustments (Register 0x3B through Register 0x3E). Effective sideband suppression requires both gain and phase matching of the I and Q signals. The I/Q phase adjust registers (Register 0x37 and Register 0x38) and the DAC FS adjust registers (Register 0x18 through Register 0x1B) can be used to calibrate the I and Q transmit paths to optimize sideband suppression. For more information about suppressing LO leakage and sideband image, refer to the AN-1039 Application Note, Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity and the AN-1100 Application Note, Wireless Transmitter IQ Balance and Sideband Suppression from the Analog Devices website. Rev. A | Page 46 of 72 Data Sheet AD9142A EXAMPLE START-UP ROUTINE To ensure reliable startup of the AD9142A, certain sequences must be followed. 0x33 → 0xAA DEVICE CONFIGURATION AND START-UP SEQUENCE 1 0x30 → 0x01 1. 2. 3. 4. Set fDCI = 375 MHz, fOUT = 250 MHz, and interpolation to 4×. Disable the PLL. Enable fine NCO and the inverse sinc filter. Use the DLL-based interface mode with DLL phase offset = 0. Derived NCO Settings 2. 3. 4. 5. /* Enable inverse sinc filter */ 0x27 → 0xC0 0x01 → 0x00 DEVICE CONFIGURATION AND START-UP SEQUENCE 2 fDAC = 375 × 4 = 1500 MHz. fCARRIER = fOUT = 250 MHz. FTW = fCARRIER/fDAC × 232 = 0x2AAAAAAA. Start-Up Sequence 1 1. Read 0x30[1] /* Expect 1b if the NCO update is complete */ /* Power up DAC outputs */ The following NCO settings can be derived from the device configuration: • • • 0x34 → 0x2A Power up the device (no specific power supply sequence is required). Apply stable DAC clock. Apply stable DCI clock. Feed stable input data. Issue hardware reset (optional). /* Device configuration register write sequence */ 0x00 → 0x20 /* Issue software reset */ 0x20 → 0x01 /* Device startup configuration */ 1. 2. 3. 4. Derived PLL Settings The following PLL settings can be derived from the device configuration: • • • • 1. 2. 3. 4. 5. 0x0A → 0xC0 /* Enable the DLL and duty cycle correction. Set DLL phase offset to 0 */ Read 0x0E[7:4] /* Expect 1000b if the DLL is locked */ fDAC = 200 × 8 = 1600 MHz. fVCO= fDAC = 1600 MHz (1.03 GHz < fVCO < 2.07 GHz). VCO divider = fVCO/fDAC = 1. Loop divider = fDAC/fREF = 8. Start-Up Sequence 2 /* Configure data interface */ 0x5E → 0xFE /* Turn off LSB delay cell */ Set fDCI = 200 MHz and interpolation to 8×. Enable the PLL, and set fREF = 200 MHz. Enable the inverse sinc filter. Use the delay line-based interface mode with a delay setting of 0. Power up the device (no specific power supply sequence is required). Apply stable DAC clock. Apply stable DCI clock. Feed stable input data. Issue hardware reset (optional). /* Configure interpolation filter */ /* Device configuration register write sequence */ 0x28 → 0x02 /* 4× interpolation */ 0x00 → 0x20 /* Issue software reset */ 0x20 → 0x01 /* Device startup configuration */ /* Reset FIFO */ 0x25 → 0x01 /* Configure PLL */ Read 0x25[1] /* Expect 1b if the FIFO reset is complete */ 0x14 → 0xE7 /* Configure PLL loop BW and charge pump current */ Read 0x24 /* The readback should be one of the three values: 0x33, 0x40, or 0x41 */ 0x15 → 0xC2 /* Configure VCO divider and loop divider */ 0x12 → 0xC0 /*Enable the PLL */ /* Configure NCO */ 0x27→ 0x40 /* Enable NCO */ 0x31 → 0xAA 0x32 → 0xAA 0x12 → 0x80 Wait 10ms for autoband selection to finish Read 0x16[7] /* Expect 1b if the PLL is locked */ Rev. A | Page 47 of 72 AD9142A Data Sheet /* Configure data interface */ /* Reset FIFO */ 0x5E → 0x00 /* Configure the delay setting */ 0x25 → 0x01 0x5F → 0x60 0x0D → 0x16 /* DC couple DCI */ 0x0A → 0x00 /* Turn off DLL and duty cycle correction */ Read 0x25[1] /* Expect 1b if the FIFO reset is complete */ Read 0x24 /* The readback should be one of the three values: 0x37, 0x40, or 0x41 */ /* Enable inverse sinc filter */ 0x27 → 0x80 /* Configure interpolation filter */ 0x28 → 0x03 /* 8× interpolation */ /* Power up DAC outputs */ 0x01 → 0x00 Rev. A | Page 48 of 72 Data Sheet AD9142A DEVICE CONFIGURATION REGISTER MAP Table 25. Device Configuration Register Map Reg 0x00 Name Common Bits Bit 7 [7:0] Reserved 0x01 0x03 PD_CONTROL INTERRUPT_ ENABLE0 [7:0] PD_IDAC [7:0] Reserved 0x04 INTERRUPT_ ENABLE1 [7:0] ENABLE_ ENABLE_ PARITY_FAIL SED_FAIL 0x05 [7:0] Reserved 0x07 INTERRUPT_ FLAG0 INTERRUPT_ FLAG1 IRQ_SEL0 0x08 IRQ_SEL1 0x09 [7:0] SEL_PARITY_ SEL_SED_ FAIL FAIL [7:0] Reserved 0x0A FRAME_ MODE DATA_CNTR_0 [7:0] DLL_ENABLE 0x0B 0x0C 0x0D DATA_CNTR_1 [7:0] CLEAR_WARN DATA_CNTR_2 [7:0] DATA_CNTR_3 [7:0] LOW_DCI_EN 0x0E DATA_STAT_0 [7:0] DLL_LOCK 0x10 [7:0] DACCLK_ Reserved DUTYCYCLE_ CORRECTION [7:0] DUTYCYCLE_ Reserved CORRECTION 0x12 DACCLK_ RECEIVER_ CTRL REFCLK_ RECEIVER_ CTRL PLL_CTRL0 0x14 0x15 PLL_CTRL2 PLL_CTRL3 [7:0] [7:0] 0x16 0x17 0x18 PLL_STATUS0 PLL_STATUS1 IDAC_FS_ ADJ0 IDAC_FS_ ADJ1 QDAC_FS_ADJ0 QDAC_FS_ADJ1 [7:0] PLL_LOCK [7:0] Reserved [7:0] DIE_TEMP_ SENSOR_CTRL DIE_TEMP_ LSB DIE_TEMP_ MSB CHIP_ID INTERRUPT_ CONFIG SYNC_CTRL [7:0] Reserved FRAME_RST_ CTRL [7:0] 0x06 0x11 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 Bit 6 SPI_LSB_ FIRST PD_QDAC ENABLE_ SYNC_LOST SYNC_LOST [7:0] PARITY_FAIL SED_FAIL [7:0] Reserved SEL_SYNC_ LOST Bit 5 DEVICE_ RESET PD_DATARCV ENABLE_ SYNC_ LOCKED ENABLE_DLL_ WARNING Bit 4 ENABLE_ DLL_LOCKED Reserved ENABLE_FIFO_ UNDERFLOW SYNC_ LOCKED DLL_ WARNING SEL_SYNC_ LOCKED SYNC_DONE PLL_LOST PLL_LOCKED DLL_LOCKED Reserved SEL_DLL_ WARNING PARUSAGE SEL_DLL_ LOCKED FRMUSAGE Bit 2 Reserved Reserved PD_DEVICE ENABLE_ ENABLE_PLL_ ENABLE_PLL_ SYNC_DONE LOST LOCKED SEL_SYNC_ DONE FIFO_ UNDERFLOW SEL_PLL_LOST SEL_PLL_ LOCKED Reserved SEL_FIFO_ UNDERFLOW Reserved Reserved DUTY_ CORRECTION_ ENABLE Reserved DLL_WARN Bit 3 DLL_START_ WARNING DACCLK_ CROSSPOINT_ CTRL_ENABLE REFCLK_ CROSSPOINT_ CTRL_ENABLE PD_DACCLK ENABLE_ OVER_ THRESHOLD ENABLE_ FIFO_ OVERFLOW OVER_ THRESHOLD FIFO_ OVERFLOW SEL_OVER_ THRESHOLD PD_FRAME ENABLE_ DACOUT_ MUTED ENABLE_ FIFO_ WARNING DACOUT_ MUTED FIFO_ WARNING SEL_ DACOUT_ MUTED SEL_FIFO_ SEL_FIFO_ OVERFLOW WARNING FRAME_PIN_USAGE Reserved Reserved Reserved DC_COUPLE_ LOW_EN Reserved DCI_ON Reserved DLL_END_ WARNING DACCLK_CROSSPOINT_LEVEL PLL_CP_CURRENT VCO_DIVIDER Reserved DLL_ RUNNING Reserved [7:0] [7:0] QDAC_FULLSCALE_ADJUST_LSB Reserved LOOP_DIVIDER IDAC_FULLSCALE_ADJUST_ MSB FS_CURRENT REF_CURRENT [7:0] DIE_TEMP_LSB [7:0] DIE_TEMP_MSB [7:0] [7:0] CHIP_ID INTERRUPT_CONFIGURATION Rev. A | Page 49 of 72 0x00 R 0x00 R 0x00 RW 0x00 RW 0x00 RW 0x00 R 0xFF RW 0x5F RW 0xE7 RW 0xC9 RW 0x00 R 0x00 R 0xF9 RW 0xE1 RW 0xF9 RW QDAC_FULLSCALE_ADJUST_ 0x01 RW MSB DIE_TEMP_ 0x02 RW SENSOR_EN 0x00 R 0x00 R 0x0A R 0x00 RW Reserved ARM_FRAME 0x00 RW 0x00 RW VCO_CTRL_VOLTAGE_READBACK PLL_BAND_READBACK IDAC_FULLSCALE_ADJUST_LSB [7:0] 0xC0 RW 0x00 RW 0x39 RW 0x64 RW 0x06 RW REFCLK_CROSSPOINT_LEVEL CROSSPOINT_ CTRL_EN Reset RW 0x00 RW 0x40 RW PLL_MANUAL_BAND AUTO_ MANUAL_ SEL PLL_LOOP_BW DIGLOGIC_DIVIDER Reserved Reserved Bit 0 DLL_PHASE_OFFSET [7:0] PLL_ENABLE [7:0] Bit 1 EN_CON_ FRAME_RESET SYNC_CLK_ SYNC_ EDGE_SEL ENABLE FRAME_RESET_MODE 0x00 RW 0x12 RW AD9142A Data Sheet Reg 0x23 Name FIFO_LEVEL_ CONFIG Bits Bit 7 [7:0] Reserved 0x24 FIFO_LEVEL_ READBACK [7:0] Reserved 0x25 FIFO_CTRL [7:0] 0x26 DATA_ FORMAT DATAPATH_ CTRL [7:0] DATA_ FORMAT [7:0] INVSINC_ ENABLE INTERPOLATION _CTRL OVER_ THRESHOLD_ CTRL0 OVER_ THRESHOLD_ CTRL1 OVER_ THRESHOLD_ CTRL2 INPUT_ POWER_ READBACK_LSB INPUT_POWER_ READBACK_ MSB NCO_CTRL [7:0] NCO_FREQ_ TUNING_ WORD0 NCO_FREQ_ TUNING_ WORD1 NCO_FREQ_ TUNING_ WORD2 NCO_FREQ_ TUNING_ WORD3 NCO_PHASE_ OFFSET0 NCO_PHASE_ OFFSET1 IQ_PHASE_ ADJ0 IQ_PHASE_ ADJ1 LVDS_IN_ PWR_DOWN_0 IDAC_DC_ OFFSET0 IDAC_DC_ OFFSET1 QDAC_DC_ OFFSET0 QDAC_DC_ OFFSET1 IDAC_GAIN_ ADJ QDAC_GAIN_ ADJ GAIN_STEP_ CTRL0 [7:0] NCO_FTW0 0x00 RW [7:0] NCO_FTW1 0x00 RW [7:0] NCO_FTW2 0x00 RW [7:0] NCO_FTW3 0x10 RW [7:0] NCO_PHASE_OFFSET_LSB 0x00 RW [7:0] NCO_PHASE_OFFSET_MSB 0x00 RW [7:0] IQ_PHASE_ADJ_LSB 0x00 RW 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 Bit 6 Bit 5 Bit 4 INTEGER_FIFO_LEVEL_REQUEST Bit 3 Reserved INTEGER_FIFO_LEVEL_READBACK Reserved [7:0] FIFO_SPI_ RESET_ACK Reserved SAMPLE_WINDOW_LENGTH INPUT_POWER_READBACK_LSB Reserved NCO_FRAME_ SPI_NCO_ UPDATE_ACK PHASE_RST_ ACK Reserved Reserved 0x00 RW IQ_PHASE_ADJ_MSB 0x00 RW 0x00 RW 0x00 R INPUT_POWER_READBACK_MSB SPI_NCO_ PHASE_ RST_REQ 0x00 R 0x00 RW THRESHOLD_LEVEL_REQUEST_MSB Reserved Reset RW 0x40 RW 0x00 RW FIFO_SPI_ RESET_ REQUEST DATA_BUS_ 0x00 RW WIDTH SEND_IDATA 0x00 RW _TO_QDAC NCO_ SIDEBAND_ SEL INTERPOLATION_MODE THRESHOLD_LEVEL_REQUEST_LSB [7:0] [7:0] Reserved FRACTIONAL_FIFO_LEVEL_READBACK Reserved DATA_ DATA_BUS_ PAIRING INVERT NCO_ENABLE IQ_GAIN_ADJ_ IQ_PHASE_ADJ_ Reserved FS4_ DCOFFSET_ ENABLE MODULATION_ ENABLE ENABLE Reserved [7:0] ENABLE_ IQ_DATA_ PROTECTION SWAP [7:0] Bit 1 Bit 0 FRACTIONAL_FIFO_LEVEL_REQUEST Reserved [7:0] [7:0] Bit 2 NCO_SPI_ UPDATE_ACK 0x00 R 0x00 RW NCO_SPI_ UPDATE_REQ 0x00 RW [7:0] PWR_DOWN_DATA_INPUT_BITS 0x00 RW [7:0] IDAC_DC_OFFSET_LSB 0x00 RW [7:0] IDAC_DC_OFFSET_MSB 0x00 RW [7:0] QDAC_DC_OFFSET_LSB 0x00 RW [7:0] QDAC_DC_OFFSET_MSB 0x00 RW [7:0] Reserved IDAC_GAIN_ADJ 0x20 RW [7:0] Reserved QDAC_GAIN_ADJ 0x20 RW Reserved RAMP_UP_STEP 0x01 RW Rev. A | Page 50 of 72 Data Sheet AD9142A Reg 0x42 Name GAIN_STEP_ CTRL1 0x43 TX_ENABLE_ CTRL 0x44 DAC_ OUTPUT_CTRL [7:0] DAC_ OUTPUT_ CTRL_EN 0x5E ENABLE_DLL_ DELAY_CELL0 ENABLE_DLL_ DELAY_CELL1 SED_CTRL [7:0] 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x6A 0x6B 0x6C 0x7F SED_PATT_ L_I0 SED_PATT_ H_I0 SED_PATT_ L_Q0 SED_PATT_ H_Q0 SED_PATT_ L_I1 SED_PATT_ H_I1 SED_PATT_ L_Q1 SED_PATT_ H_Q1 PARITY_CTRL PARITY_ERR_ RISING PARITY_ERR_ FALLING Version Bits Bit 7 Bit 6 DAC_ DAC_ OUTPUT_OFF OUTPUT_ STATUS [7:0] Bit 5 Bit 4 Bit 2 RAMP_DOWN_STEP Reserved Reserved [7:0] Bit 3 TXENABLE_ GAINSTEP_EN AED_ENABLE Bit 0 TXENABLE_ SLEEP_EN TXENABLE_ 0x07 RW POWER_ DOWN_EN FIFO_ERROR_ 0x8D RW SHUTDOWN_ EN FIFO_ OVERTHRESHOLD Reserved WARNING_ _SHUTDOWN_EN SHUTDOWN_ EN DELAY_CELL_ENABLE [7:0] Reserved [7:0] SED_ENABLE SED_ERR_ CLEAR [7:0] Bit 1 0xFF DELAY_CELL_ENABLE [10:8] SED_DEPTH Reserved AED_PASS AED_FAIL Reset RW 0x41 RW SED_FAIL 0x67 RW 0x00 RW SED_PATTERN_RISE_I0[7:0] 0x00 RW [7:0] SED_PATTERN_RISE_I0[15:8] 0x00 RW [7:0] SED_PATTERN_FALL_Q0[7:0] 0x00 RW [7:0] SED_PATTERN_FALL_Q0[15:8] 0x00 RW [7:0] SED_PATTERN_RISE_I1[7:0] 0x00 RW [7:0] SED_PATTERN_RISE_I1[15:8] 0x00 RW [7:0] SED_PATTERN_FALL_Q1[7:0] 0x00 RW [7:0] SED_PATTERN_FALL_Q1[15:8] 0x00 RW [7:0] PARITY_ ENABLE [7:0] PARITY_EVEN PARITY_ERR CLEAR Reserved PARERRFAL PARERRIS 0x00 RW Parity Rising Edge Error Count 0x00 R [7:0] Parity Falling Edge Error Count 0x00 R [7:0] Version 0x0B R Rev. A | Page 51 of 72 AD9142A Data Sheet REGISTER DESCRIPTIONS Defined reserved bits are those whose reset values are not 0x00. Access indicates the read and/or write nature of the register. SPI CONFIGURE REGISTER Address: 0x00, Reset: 0x00, Name: Common Table 26. Bit Descriptions for Common Bits 6 Bit Name SPI_LSB_FIRST Settings 0 1 5 DEVICE_RESET Description Serial port communication, MSB-first or LSB-first selection. MSB first. LSB first. The device resets when 1 is written to this bit. DEVICE_RESET is a self clear bit. After the reset, the bit returns to 0 automatically. The readback is always 0. Reset 0 Access RW 0 RW Reset 1 Access RW 1 RW 0 RW 0 RW 0 RW 0 RW Reset 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW POWER-DOWN CONTROL REGISTER Address: 0x01, Reset: 0xC0, Name: PD_CONTROL Table 27. Bit Descriptions for PD_CONTROL Bits 7 Bit Name PD_IDAC 6 PD_QDAC 5 PD_DATARCV 2 PD_DEVICE 1 PD_DACCLK 0 PD_FRAME Settings Description The IDAC is powered down when PD_IDAC is set to 1. This bit powers down only the analog portion of the IDAC. The IDAC digital data path is not affected. The QDAC is powered down when PD_QDAC is set to 1. This bit powers down only the analog portion of the QDAC. The QDAC digital datapath is not affected. The data interface circuitry is powered down when PD_DATARCV is set to 1. This bit powers down the data interface and the write side of the FIFO. The band gap circuitry is powered down when set to 1. This bit powers down the entire chip. The DAC clock powers down when PD_DEVICE is set to 1. This bit powers down the DAC clocking path and, thus, the majority of the digital functions. The frame receiver powers down when PD_FRAME is set to 1. The frame signal is internally pulled low. Set to 1 when the frame is not used. INTERRUPT ENABLE0 REGISTER Address: 0x03, Reset: 0x00, Name: INTERRUPT_ENABLE0 Table 28. Bit Descriptions for INTERRUPT_ENABLE0 Bits 6 5 4 3 2 1 0 Bit Name ENABLE_SYNC_LOST ENABLE_SYNC_LOCKED ENABLE_SYNC_DONE ENABLE_PLL_LOST ENABLE_PLL_LOCKED ENABLE_OVER_THRESHOLD ENABLE_DACOUT_MUTED Settings Description Enable interrupt for sync lost. Enable interrupt for sync lock. Enable interrupt for sync done. Enable interrupt for PLL lost. Enable interrupt for PLL locked. Enable interrupt for overthreshold. Enable interrupt for DACOUT muted. Rev. A | Page 52 of 72 Data Sheet AD9142A INTERRUPT ENABLE1 REGISTER Address: 0x04, Reset: 0x00, Name: INTERRUPT_ENABLE1 Table 29. Bit Descriptions for INTERRUPT_ENABLE1 Bits 7 6 5 4 2 1 0 Bit Name ENABLE_PARITY_FAIL ENABLE_SED_FAIL ENABLE_DLL_WARNING ENABLE_DLL_LOCKED ENABLE_FIFO_UNDERFLOW ENABLE_FIFO_OVERFLOW ENABLE_FIFO_WARNING Settings Description Enable interrupt for parity failure. Enable interrupt for SED failure. Enable interrupt for DLL warning. Enable interrupt for DLL locked. Enable interrupt for FIFO underflow. Enable interrupt for FIFO overflow. Enable interrupt for FIFO warning. Reset 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW INTERRUPT FLAG0 REGISTER Address: 0x05, Reset: 0x00, Name: INTERRUPT_FLAG0 Table 30. Bit Descriptions for INTERRUPT_FLAG0 Bits 6 5 4 3 2 1 0 Bit Name SYNC_LOST SYNC_LOCKED SYNC_DONE PLL_LOST PLL_LOCKED OVER_THRESHOLD DACOUT_MUTED Settings Description SYNC_LOST is set to 1 when sync is lost. SYNC_LOCKED is set to 1 when sync is locked. SYNC_DONE is set to 1 when sync is done. PLL_LOST is set to 1 when PLL loses lock. PLL_LOCKED is set to 1 when PLL is locked. OVER_THRESHOLD is set to 1 when input power is overthreshold. DACOUT_MUTED is set to 1 when the DAC output is muted (midscale dc). Reset 0 0 0 0 0 0 0 Access R R R R R R R Reset 0 0 0 0 0 Access R R R R R 0 R 0 R INTERRUPT FLAG1 REGISTER Address: 0x06, Reset: 0x00, Name: INTERRUPT_FLAG1 Table 31. Bit Descriptions for INTERRUPT_FLAG1 Bits 7 6 5 4 2 Bit Name PARITY_FAIL SED_FAIL DLL_WARNING DLL_LOCKED FIFO_UNDERFLOW 1 FIFO_OVERFLOW 0 FIFO_WARNING Settings Description PARITY_FAIL is set to 1 when the parity check fails. SED_FAIL is set to 1 when the SED comparison fails. DLL_WARNING is set to 1 when the DLL raises a warning. DLL_LOCKED is set to 1 when the DLL is locked. FIFO_UNDERFLOW is set to 1 when the FIFO read pointer catches the FIFO write pointer. FIFO_OVERFLOW is set to 1 when the when the FIFO read pointer catches the FIFO read pointer. FIFO_WARNING is set to 1 when the FIFO is one slot from empty (≤1) or full (≥6). Rev. A | Page 53 of 72 AD9142A Data Sheet INTERRUPT SELECT0 REGISTER Address: 0x07, Reset: 0x00, Name: IRQ_SEL0 Table 32. Bit Descriptions for IRQ_SEL0 Bits 6 Bit Name SEL_SYNC_LOST 5 Settings 0 1 Description Selects the IRQ1 pin. Selects the IRQ2 pin. Reset 0 Access RW SEL_SYNC_LOCKED 0 1 Selects the IRQ1 pin. Selects the IRQ2 pin. 0 RW 4 SEL_SYNC_DONE 0 1 Selects the IRQ1 pin. Selects the IRQ2 pin. 0 RW 3 SEL_PLL_LOST 0 1 Selects the IRQ1 pin. Selects the IRQ2 pin. 0 RW 2 SEL_PLL_LOCKED 0 1 Selects the IRQ1 pin. Selects the IRQ2 pin. 0 RW 1 SEL_OVER_THRESHOLD 0 1 Selects the IRQ1 pin. Selects the IRQ2 pin. 0 RW 0 SEL_DACOUT_MUTED 0 Selects the IRQ1 pin. 0 RW INTERRUPT SELECT1 REGISTER Address: 0x08, Reset: 0x00, Name: IRQ_SEL1 Table 33. Bit Descriptions for IRQ_SEL1 Bits 7 Bit Name SEL_PARITY_FAIL 6 Settings 1 0 Description Selects the IRQ2 pin. Selects the IRQ1 pin. Reset 0 Access RW SEL_SED_FAIL 1 0 Selects the IRQ2 pin. Selects the IRQ1 pin. 0 RW 5 SEL_DLL_WARNING 0 Selects the IRQ1 pin. 0 RW 4 SEL_DLL_LOCKED 1 0 Selects the IRQ2 pin. Selects the IRQ1 pin. 0 RW 2 SEL_FIFO_UNDERFLOW 1 0 Selects the IRQ2 pin. Selects the IRQ1 pin. 0 RW 1 SEL_FIFO_OVERFLOW 1 0 Selects the IRQ2 pin. Selects the IRQ1 pin. 0 RW 0 SEL_FIFO_WARNING 1 0 Selects the IRQ2 pin. Selects the IRQ1 pin. 0 RW FRAME MODE REGISTER Address: 0x09, Reset: 0x00, Name: FRAME_MODE Table 34. Bit Descriptions for FRAME_MODE Bits 5 4 [1:0] Bit Name PARUSAGE FRMUSAGE FRAME_PIN_USAGE Description Must set to 1 when parity is used Must set to 1 when frame is used. 0 = no effect. 1 = parity. 2 = frame. 3 = reserved. Rev. A | Page 54 of 72 Reset 0 0 0x0 Access RW RW RW Data Sheet AD9142A DATA CONTROL 0 REGISTER Address: 0x0A, Reset: 0x40, Name: DATA_CNTR_0 Table 35. Bit Descriptions for DATA_CNTR_0 Bits 7 Bit Name DLL_ENABLE 6 DUTY_CORRECTION_ENABLE [3:0] DLL_PHASE_OFFSET Description 1 = enable DLL. 0 = disable DLL. 1 = enable duty cycle correction. 0 = disable duty cycle correction. Locked phase = 90° + n ×11.25°, where n is the 4 bit signed magnitude number. Valid phase setting ranges from −6 to +6, 13 phases in total. Reset 0 Access RW 1 RW 0x0 RW DATA CONTROL 1 REGISTER Address: 0x0B, Reset: 0x39, Name: DATA_CNTR_1 Table 36. Bit Descriptions for DATA_CNTR_1 Bits 7 [6:0] Bit Name CLEAR_WARN Reserved Description 1= clears data receiver warning bits (Register 0x0E[6:4]). Must write the default value for optimal performance. Reset 0 0x39 Access RW RW Reset 0x64 Access RW Reset 0 Access RW 0 RW 0x6 RW Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R DATA CONTROL 2 REGISTER Address: 0x0C, Reset: 0x64, Name: DATA_CNTR_2 Table 37. Bit Descriptions for DATA_CNTR_2 Bits [7:0] Bit Name Reserved Description Must write the default value for optimal performance. DATA CONTROL 3 REGISTER Address: 0x0D, Reset: 0x06, Name: DATA_CNTR_3 Table 38. Bit Descriptions for DATA_CNTR_3 Bits 7 Bit Name LOW_DCI_EN 4 DC_COUPLE_LOW_EN [3:0] Reserved Description Set to 0 when DLL is enabled and DCI rate is ≥350 MHz. Set to 1 when DLL is enabled and DCI rate is <350 MHz. Set to 0 when DLL is enabled and delay line is disabled. Set to 1 when DLL is disabled and delay line is enabled. It is recommended that DLL mode be used for a DCI rate faster than 250 MHz and the delay line mode be used for DCI rate slower than 250 MHz. Must write the default value for optimal performance. DATA STATUS 0 REGISTER Address: 0x0E, Reset: 0x00, Name: DATA_STAT_0 Table 39. Bit Descriptions for DATA_STAT_0 Bits 7 6 5 4 3 2 1 0 Bit Name DLL_LOCK DLL_WARN DLL_START_WARNING DLL_END_WARNING Reserved DCI_ON Reserved DLL_RUNNING Description 1 = DLL lock. 1 = DLL near beginning/end of delay line. 1 = DLL at beginning of delay line. 1 = DLL at end of delay line. Reserved. 1 = user has provided a clock >100 MHz. Reserved. 1 = closed loop DLL attempting to lock. 0 = delay fixed at middle of delay line. Rev. A | Page 55 of 72 AD9142A Data Sheet DAC CLOCK RECEIVER CONTROL REGISTER Address: 0x10, Reset: 0xFF, Name: DACCLK_RECEIVER_CTRL Table 40. Bit Descriptions for DACCLK_RECEIVER_CTRL Bits 7 Bit Name DACCLK_DUTYCYCLE_CORRECTION 6 5 Reserved DACCLK_CROSSPOINT_CTRL_ENABLE [4:0] DACCLK_CROSSPOINT_LEVEL Settings Description Enables duty cycle correction at the DACCLK input. For best performance, the default and recommended status is turned on. Must write the default value for optimal performance Enables crosspoint control at the DACCLK input. For best performance, the default and recommended status is turned on. A twos complement value. For best performance, it is recommended to set DACCLK_CROSSPOINT_LEVEL to the default value. Highest crosspoint. Lowest crosspoint. 01111 11111 Reset 1 Access RW 1 1 RW RW 0x1F RW Reset 0 Access RW 1 0 RW RW 0x1F RW Reset 0 0 Access RW RW 0x00 RW REF CLOCK RECEIVER CONTROL REGISTER Address: 0x11, Reset: 0x5F, Name: REFCLK_RECEIVER_CTRL Table 41. Bit Descriptions for REFCLK_RECEIVER_CTRL Bits 7 Bit Name DUTYCYCLE_CORRECTION Settings 6 5 Reserved REFCLK_CROSSPOINT_CTRL_ENABLE [4:0] REFCLK_CROSSPOINT_LEVEL 01111 11111 Description Enables duty cycle correction at the REFx/SYNCx input. For best performance, the default and recommended status is turned off. Must write the default value for optimal performance Enables crosspoint control at the REFx/SYNCx input. For best performance, the default and recommended status is turned off. A twos complement value. For best performance, it is recommended to set REFCLK_CROSSPOINT_LEVEL to the default value. Highest crosspoint. Lowest crosspoint. PLL CONTROL 0 REGISTER Address: 0x12, Reset: 0x00, Name: PLL_CTRL0 Table 42. Bit Descriptions for PLL_CTRL0 Bits 7 6 Bit Name PLL_ENABLE AUTO_MANUAL_SEL Settings 0 1 [5:0] PLL_MANUAL_BAND 000000 111111 Description Enables PLL clock multiplier. PLL band selection mode. Automatic mode. Manual mode. PLL band setting in manual mode. 64 bands in total, covering a 1 GHz to 2.1 GHz VCO range. Lowest band (1 GHz). Highest band (2.1 GHz). Rev. A | Page 56 of 72 Data Sheet AD9142A PLL CONTROL 2 REGISTER Address: 0x14, Reset: 0xE7, Name: PLL_CTRL2 Table 43. Bit Descriptions for PLL_CTRL2 Bits [7:5] Bit Name PLL_LOOP_BW Settings 0x00 0x1F [4:0] PLL_CP_CURRENT 0x00 0x1F Description Selects the PLL filter bandwidth. The default and recommended setting is 111 for optimal PLL performance. Lowest setting. Highest setting. Sets nominal PLL charge pump current. The default and recommended setting is 00111 for optimal PLL performance. Lowest setting. Highest setting. Reset 0x7 Access RW 0x07 RW Reset 0x3 Access RW 0 RW 0x2 RW 0x1 RW Reset 0 0x0 Access R R PLL CONTROL 3 REGISTER Address: 0x15, Reset: 0xC9, Name: PLL_CTRL3 Table 44. Bit Descriptions for PLL_CTRL3 Bits [7:6] Bit Name DIGLOGIC_DIVIDER Settings 00 01 10 11 4 CROSSPOINT_CTRL_EN [3:2] VCO_DIVIDER 00 01 10 11 [1:0] LOOP_DIVIDER 00 01 10 11 Description REFCLK to PLL digital clock divide ratio. The PLL digital clock drives the internal PLL logics. The divide ratio must be set to ensure that the PLL digital clock is less than 75 MHz. fREFCLK/fDIG = 2. fREFCLK/fDIG = 4. fREFCLK/fDIG = 8. fREFCLK/fDIG = 16. Enable loop divider crosspoint control. The default and recommended setting is set to 0 for optimal PLL performance. PLL VCO divider. This divider determines the ratio of the VCO frequency to the DACCLK frequency. fVCO/fDACCLK = 1. fVCO/fDACCLK = 2. fVCO/fDACCLK = 4. fVCO/fDACCLK = 4. PLL divider. This divider determines the ratio of the DACCLK frequency to the REFCLK frequency. fDACCLK/fREFCLK = 2. fDACCLK/fREFCLK = 4. fDACCLK/fREFCLK = 8. fDACCLK/fREFCLK = 16. PLL STATUS 0 REGISTER Address: 0x16, Reset: 0x00, Name: PLL_STATUS0 Table 45. Bit Descriptions for PLL_STATUS0 Bits 7 [3:0] Bit Name PLL_LOCK VCO_CTRL_VOLTAGE_READBACK Settings 1111 0111 0000 Description PLL clock multiplier output is stable. VCO control voltage readback. A binary value. The highest VCO control voltage. The midvalue when a proper VCO band is selected. When the PLL is locked, selecting a higher VCO band decreases this value and selecting a lower VCO band increases this value. The lowest VCO control voltage. Rev. A | Page 57 of 72 AD9142A Data Sheet PLL STATUS 1 REGISTER Address: 0x17, Reset: 0x00, Name: PLL_STATUS1 Table 46. Bit Descriptions for PLL_STATUS1 Bits [5:0] Bit Name PLL_BAND_READBACK Settings Description Indicates the VCO band currently selected. Reset 0x00 Access R Description IDAC full-scale adjust, these bits, along with Bits[1:0] in Register 0x19, set the full-scale current of the IDAC. The fullscale current can be adjusted from 8.64 mA to 31.68 mA. The default value (0x1F9) sets the full-scale current to 20 mA. Reset 0xF9 Access RW Description Set to default value for optimal performance. IDAC full-scale adjust, these bits, along with Bits[7:0] in Register 0x18,the full-scale current of the IDAC. The full-scale current can be adjusted from 8.64 mA to 31.68 mA. The default value (0x1F9) sets the full-scale current to 20 mA. Reset 0x7 0x1 Access RW RW Description QDAC Full-Scale Adjust, these bits, along with Bits[1:0] in Register 0x1B, set the full-scale current of the QDAC. The full-scale current can be adjusted from 8.64 mA to 31.68 mA. The default value (0x1F9) sets the full-scale current to 20 mA. Reset 0xF9 Access RW Description QDAC Full-Scale Adjust, these bits, along with Bits[7:0] in Register 0x1A, set the full-scale current of the QDAC. The full-scale current can be adjusted from 8.64 mA to 31.68 mA. The default value (0x1F9) sets the full-scale current to 20 mA. Reset 0x1 Access RW IDAC FS ADJUST LSB REGISTER Address: 0x18, Reset: 0xF9, Name: IDAC_FS_ADJ0 Table 47. Bit Descriptions for IDAC_FS_ADJ0 Bits [7:0] Bit Name IDAC_FULLSCALE_ADJUST_LSB Settings IDAC FS ADJUST MSB REGISTER Address: 0x19, Reset: 0xE1, Name: IDAC_FS_ADJ1 Table 48. Bit Descriptions for IDAC_FS_ADJ1 Bits [7:5] [1:0] Bit Name Reserved IDAC_FULLSCALE_ADJUST_MSB Settings QDAC FS ADJUST LSB REGISTER Address: 0x1A, Reset: 0xF9, Name: QDAC_FS_ADJ0 Table 49. Bit Descriptions for QDAC_FS_ADJ0 Bits [7:0] Bit Name QDAC_FULLSCALE_ADJUST_LSB Settings QDAC FS ADJUST MSB REGISTER Address: 0x1B, Reset: 0x01, Name: QDAC_FS_ADJ1 Table 50. Bit Descriptions for QDAC_FS_ADJ1 Bits [1:0] Bit Name QDAC_FULLSCALE_ADJUST_MSB Settings Rev. A | Page 58 of 72 Data Sheet AD9142A DIE TEMPERATURE SENSOR CONTROL REGISTER Address: 0x1C, Reset: 0x02, Name: DIE_TEMP_SENSOR_CTRL Table 51. Bit Descriptions for DIE_TEMP_SENSOR_CTRL Bits [6:4] Bit Name FS_CURRENT Settings 000 001 … 110 111 [3:1] REF_CURRENT 000 001 … 110 111 0 DIE_TEMP_SENSOR_EN Description Temperature sensor ADC full-scale current. Using the default setting is recommended. 50 μA. 62.5 μA. 125 μA. 137.5 μA. Temperature sensor ADC reference current. Using the default setting is recommended. 12.5 μA. 19 μA. 50 μA. 56.5 μA. Enable the on-chip temperature sensor. Reset 0x0 Access RW 0x1 RW 0x0 RW Reset 0x00 Access R DIE TEMPERATURE LSB REGISTER Address: 0x1D, Reset: 0x00, Name: DIE_TEMP_LSB Table 52. Bit Descriptions for DIE_TEMP_LSB Bits [7:0] Bit Name DIE_TEMP_LSB Settings Description Die temperature, these bits, along with Bits[7:0] in Register 0x1E, indicate the approximate die temperature. For more information, see the Temperature Sensor section. DIE TEMPERATURE MSB REGISTER Address: 0x1E, Reset: 0x00, Name: DIE_TEMP_MSB Table 53. Bit Descriptions for DIE_TEMP_MSB Bits [7:0] Bit Name DIE_TEMP_MSB Settings Description Die temperature, these bits, along with Bits[7:0] in Register 0x1D, indicate the approximate die temperature. For more information, see the Temperature Sensor section. Reset 0x00 Access R CHIP ID REGISTER Address: 0x1F, Reset: 0x0A, Name: CHIP_ID Table 54. Bit Descriptions for CHIP_ID Bits [7:0] Bit Name CHIP_ID Settings Description The AD9142A chip ID is 0x0A. Reset 0x0A Access R Reset 0x00 Access RW INTERRUPT CONFIGUATION REGISTER Address: 0x20, Reset: 0x00, Name: INTERRUPT_CONFIG Table 55. Bit Descriptions for INTERRUPT_CONFIG Bits [7:0] Bit Name INTERRUPT_CONFIGURATION Settings 0x00 0x01 Description Test mode. Recommended mode (described in the Interrupt Request Operation section). Rev. A | Page 59 of 72 AD9142A Data Sheet SYNC CONTROL REGISTER Address: 0x21, Reset: 0x00, Name: SYNC_CTRL Table 56. Bit Descriptions for SYNC_CTRL Bits 1 Bit Name SYNC_CLK_EDGE_SEL Settings 0 1 0 SYNC_ENABLE Description Selects the sampling edge of the DACCLK on the sync clock. SYNC CLK is sampled by the falling edges of DACCLK. SYNC CLK is sampled by the rising edges of DACCLK. Enables multichip synchronization. Reset 0 Access RW 0 RW Reset 0 Access RW 0 RW 0x2 RW Reset 0x4 Access RW 0x0 RW FRAME RESET CONTROL REGISTER Address: 0x22, Reset: 0x12, Name: FRAME_RST_CTRL Table 57. Bit Descriptions for FRAME_RST_CTRL Bits 3 Bit Name ARM_FRAME 2 EN_CON_FRAME_RESET Settings 0 1 [1:0] FRAME_RESET_MODE 00 01 10 11 Description This bit is used to retrigger a frame reset in one shot mode (when Bit 2 is set to 0). Setting this bit to 1 requests the device to respond to the next valid frame pulse. Frame reset mode selection. Responds to the first valid frame pulse and resets the FIFO one time only. This is the default and recommended mode. Responds to every valid frame pulse and resets the FIFO continuously. These bits determine what is to be reset when the device receives a valid frame signal. FIFO only. NCO only. FIFO and NCO. None. FIFO LEVEL CONFIGURATION REGISTER Address: 0x23, Reset: 0x40, Name: FIFO_LEVEL_CONFIG Table 58. Bit Descriptions for FIFO_LEVEL_CONFIG Bits [6:4] Bit Name INTEGER_FIFO_LEVEL_REQUEST Settings 000 001 … 111 [2:0] FRACTIONAL_FIFO_LEVEL_REQUEST 000 001 Description These bits set the integer FIFO level. This is the difference between the read pointer and the write pointer values in the unit of input data rate (fDATA). The default and recommended FIFO level is integer level = 4 and fractional level = 0. See the FIFO Operation section for details. 0. 1. 7. Set the fractional FIFO level. This is the difference between the read pointer and the write pointer values in the unit of DACCLK rate (fDAC). The maximum allowed setting value = interpolation rate − 1. See the FIFO Operation section for details. 0. 1. Rev. A | Page 60 of 72 Data Sheet AD9142A FIFO LEVEL READBACK REGISTER Address: 0x24, Reset: 0x00, Name: FIFO_LEVEL_READBACK Table 59. Bit Descriptions for FIFO_LEVEL_READBACK Bits [6:4] Bit Name INTEGER_FIFO_LEVEL_READBACK Settings [2:0] FRACTIONAL_FIFO_LEVEL_READBACK Description The integer FIFO level read back. The difference between the overall FIFO level request and readback should be within two DACCLK cycles. See the FIFO Operation section for details. The fractional FIFO level read back. This value should be used in combination with the readback in Bits[6:4]. Reset 0x0 Access R 0x0 R Reset 0x0 0x0 Access R RW FIFO CONTROL REGISTER Address: 0x25, Reset: 0x00, Name: FIFO_CTRL Table 60. Bit Descriptions for FIFO_CTRL Bits 1 0 Bit Name FIFO_SPI_RESET_ACK FIFO_SPI_RESET_REQUEST Settings Description Acknowledge a serial port initialized FIFO reset. Initialize a FIFO reset via the serial port. DATA FORMAT SELECT REGISTER Address: 0x26, Reset: 0x00, Name: DATA_FORMAT_SEL Table 61. Bit Descriptions for DATA_FORMAT_SEL Bits 7 Bit Name DATA_FORMAT Settings 0 1 6 DATA_PAIRING 0 1 5 DATA_BUS_INVERT 0 1 0 DATA_BUS_WIDTH 0 1 Description Select binary or twos complement data format. Input data in twos complement format. Input data in binary format. Indicate I/Q data pairing on data input. I samples are paired with the next Q samples. I samples are paired with the prior Q samples. Swap the bit order of the data input port. MSBs become the LSBs: D[15:0] changes to D[0:15]. The order of the data bits corresponds to the pin descriptions in Table 9. The order of the data bits is inverted. Data interface mode. See the LVDS Input Data Ports section for information about the operation of the different interface modes. Word interface mode; 16-bit interface bus width. Byte interface mode; 8-bit interface bus width. Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW 0x0 RW DATAPATH CONTROL REGISTER Address: 0x27, Reset: 0x00, Name: DATAPATH_CTRL Table 62. Bit Descriptions for DATAPATH_CTRL Bits 7 6 5 4 2 1 Bit Name INVSINC_ENABLE NCO_ENABLE IQ_GAIN_ADJ_DCOFFSET_ENABLE IQ_PHASE_ADJ_ENABLE FS4_MODULATION_ENABLE NCO_SIDEBAND_SEL Settings 0 1 0 SEND_IDATA_TO_QDAC Description Enable the inverse sinc filter. Enable the NCO. Enable digital IQ gain adjustment and dc offset. Enable digital IQ phase adjustment. Enable fS/4 modulation function. Selects the single-side NCO modulation image. The NCO outputs the high-side image. The NCO outputs the low-side image. Send the IDATA to the QDAC. When enabled, I data is sent to both the IDAC and the QDAC. The Q data path still runs, and the Q data is ignored. Rev. A | Page 61 of 72 AD9142A Data Sheet INTERPOLATION CONTROL REGISTER Address: 0x28, Reset: 0x00, Name: INTERPOLATION_CTRL Table 63. Bit Descriptions for INTERPOLATION_CTRL Bits [1:0] Bit Name INTERPOLATION_MODE Settings 00 10 11 Description Interpolation rate and mode selection. 2× Mode; use HB1 filter. 4× mode; use HB1 and HB2 filters. 8× mode; use all three filters (HB1, HB2, and HB3). Reset 0x0 Access RW Reset 0x0 Access RW Reset 0x00 Access RW Reset 0x0 0x0 0x0 Access RW RW RW Reset 0x0 Access R OVER THRESHOLD CONTROL 0 REGISTER Address: 0x29, Reset: 0x00, Name: OVER_THRESHOLD_CTRL0 Table 64. Bit Descriptions for OVER_THRESHOLD_CTRL0 Bits [7:0] Bit Name THRESHOLD_LEVEL_REQUEST_LSB Settings Description These bits, along with Bits[4:0] in Register 0x2A, set the minimum average input power (I2 + Q2) to trigger the input power protection function. OVER THRESHOLD CONTROL 1 REGISTER Address: 0x2A, Reset: 0x00, Name: OVER_THRESHOLD_CTRL1 Table 65. Bit Descriptions for OVER_THRESHOLD_CTRL1 Bits [4:0] Bit Name THRESHOLD_LEVEL_REQUEST_MSB Settings Description These bits, along with Bits[7:0] in Register 0x29, set the minimum average input power (I2 + Q2) to trigger the input power protection function. OVER THRESHOLD CONTROL 2 REGISTER Address: 0x2B, Reset: 0x00, Name: OVER_THRESHOLD_CTRL2 Table 66. Bit Descriptions for OVER_THRESHOLD_CTRL2 Bits 7 6 [3:0] Bit Name ENABLE_PROTECTION IQ_DATA_SWAP SAMPLE_WINDOW_LENGTH Settings 0000 0001 … 1010 1011 to 1111 Description Enable input power protection. Swap I and Q data in average power calculation. Number of data input samples for power averaging. 512 IQ data sample pairs. 1024 IQ data sample pairs. 219 IQ data sample pairs. invalid. INPUT POWER READBACK LSB REGISTER Address: 0x2C, Reset: 0x00, Name: INPUT_POWER_READBACK_LSB Table 67. Bit Descriptions for INPUT_POWER_READBACK_LSB Bits [7:0] Bit Name INPUT_POWER_READBACK_LSB Settings Description These bits, along with Bits[4:0] in Register 0x2D, set the input signal average power readback. Rev. A | Page 62 of 72 Data Sheet AD9142A INPUT POWER READBACK MSB REGISTER Address: 0x2D, Reset: 0x00, Name: INPUT_POWER_READBACK_MSB Table 68. Bit Descriptions for INPUT_POWER_READBACK_MSB Bits [4:0] Bit Name INPUT_POWER_READBACK_MSB Settings Description These bits, along with Bits[7:0] in Register 0x2C, set the input signal average power readback. Reset 0x00 Access R NCO CONTROL REGISTER Address: 0x30, Reset: 0x00, Name: NCO_CTRL Table 69. Bit Descriptions for NCO_CTRL Bits 6 5 4 1 0 Bit Name NCO_FRAME_UPDATE_ACK SPI_NCO_PHASE_RST_ACK SPI_NCO_PHASE_RST_REQ NCO_SPI_UPDATE_ACK NCO_SPI_UPDATE_REQ Settings Description Frequency tuning word update request from frame. NCO phase SPI reset acknowledge. NCO phase SPI reset request. Frequency tuning word update acknowledge. Frequency tuning word update request from SPI. Reset 0x0 0x0 0x0 0x0 0x0 Access R R RW R RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW NCO FREQUENCY TUNING WORD 0 REGISTER Address: 0x31, Reset: 0x00, Name: NCO_FREQ_TUNING_WORD0 Table 70. Bit Descriptions for NCO_FREQ_TUNING_WORD0 Bits [7:0] Bit Name NCO_FTW0 Settings Description Bits[7:0] together with the bits in Register 0x32, Register 0x33, and Register 0x34 form the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when a serial port update or frame update is initialized in Register 0x30. It is in twos complement format. NCO FREQUENCY TUNING WORD 1 REGISTER Address: 0x32, Reset: 0x00, Name: NCO_FREQ_TUNING_WORD1 Table 71. Bit Descriptions for NCO_FREQ_TUNING_WORD1 Bits [7:0] Bit Name NCO_FTW1 Settings Description Bits[7:0] together with the bits in Register 0x31, Register 0x33, and Register 0x34 form the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when a serial port update or frame update is initialized in Register 0x30. It is in twos complement format. NCO FREQUENCY TUNING WORD 2 REGISTER Address: 0x33, Reset: 0x00, Name: NCO_FREQ_TUNING_WORD2 Table 72. Bit Descriptions for NCO_FREQ_TUNING_WORD2 Bits [7:0] Bit Name NCO_FTW2 Settings Description Bits[7:0] together with the bits in Register 0x31, Register 0x32, and Register 0x34 form the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when a serial port update or frame update is initialized in Register 0x30. It is in twos complement format. Rev. A | Page 63 of 72 AD9142A Data Sheet NCO FREQUENCY TUNING WORD 3 REGISTER Address: 0x34, Reset: 0x10, Name: NCO_FREQ_TUNING_WORD3 Table 73. Bit Descriptions for NCO_FREQ_TUNING_WORD3 Bits [7:0] Bit Name NCO_FTW3 Settings Description Bits[7:0] together with the bits in Register 0x31 through Register 0x33 form the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when a serial port update or frame update is initialized in Register 0x30. It is in twos complement format. Reset 0x10 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x0 Access RW NCO PHASE OFFSET 0 REGISTER Address: 0x35, Reset: 0x00, Name: NCO_PHASE_OFFSET0 Table 74. Bit Descriptions for NCO_PHASE_OFFSET0 Bits [7:0] Bit Name NCO_PHASE_OFFSET_LSB Settings Description This register, together with Register 0x36, sets the initial phase of the complex carrier signal upon reset. The phase offset spans from 0° to 360°. Each bit represents an offset of 0.0055°. This value is in twos complement format. NCO PHASE OFFSET 1 REGISTER Address: 0x36, Reset: 0x00, Name: NCO_PHASE_OFFSET1 Table 75. Bit Descriptions for NCO_PHASE_OFFSET1 Bits [7:0] Bit Name NCO_PHASE_OFFSET_MSB Settings Description This register, together with Register 0x35, sets the initial phase of the complex carrier signal upon reset. The phase offset spans from 0° to 360°. Each bit represents an offset of 0.0055°. This value is in twos complement format. IQ PHASE ADJUST 0 REGISTER Address: 0x37, Reset: 0x00, Name: IQ_PHASE_ADJ0 Table 76. Bit Descriptions for IQ_PHASE_ADJ0 Bits [7:0] Bit Name IQ_PHASE_ADJ_LSB Settings Description Q phase adjust, Bits[7:0] along with Bits[4:0] in Register 0x38, is used to insert a phase offset between the I and Q datapaths. It provides an adjustment range of ±14° with a step of 0.0035°. This value is in twos complement. See the Quadrature Phase Adjustment section for more information. IQ PHASE ADJUST 1 REGISTER Address: 0x38, Reset: 0x00, Name: IQ_PHASE_ADJ1 Table 77. Bit Descriptions for IQ_PHASE_ADJ1 Bits [4:0] Bit Name IQ_PHASE_ADJ_MSB Settings Description IQ phase adjust, Bits[4:0] along with Bits[7:0] in Register 0x37, is used to insert a phase offset between the I and Q datapaths. It provides an adjustment range of ±14° with a step of 0.0035°. This value is in twos complement. See the Quadrature Phase Adjustment section for more information. Rev. A | Page 64 of 72 Data Sheet AD9142A POWER DOWN DATA INPUT 0 REGISTER Address: 0x39, Reset: 0x00, Name: LVDS_IN_PWR_DOWN_0 Table 78. Bit Descriptions for LVDS_IN_PWR_DOWN_0 Bits [3:0] Bit Name PWR_DOWN_DATA_INPUT_BITS Settings Description Powers down data input D[3:0]. Each bit controls one data input bit. These bits can be powered down individually. Reset 0x0 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x20 Access RW IDAC DC OFFSET 0 REGISTER Address: 0x3B, Reset: 0x00, Name: IDAC_DC_OFFSET0 Table 79. Bit Descriptions for IDAC_DC_OFFSET0 Bits [7:0] Bit Name IDAC_DC_OFFSET_LSB Settings Description DAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3C, is a dc value that is added directly to the sample values written to the DAC. IDAC DC OFFSET 1 REGISTER Address: 0x3C, Reset: 0x00, Name: IDAC_DC_OFFSET1 Table 80. Bit Descriptions for IDAC_DC_OFFSET1 Bits [7:0] Bit Name IDAC_DC_OFFSET_MSB Settings Description DAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3B, is a dc value that is added directly to the sample values written to the DAC. QDAC DC OFFSET 0 REGISTER Address: 0x3D, Reset: 0x00, Name: QDAC_DC_OFFSET0 Table 81. Bit Descriptions for QDAC_DC_OFFSET0 Bits [7:0] Bit Name QDAC_DC_OFFSET_LSB Settings Description QDAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3E, is a dc value that is added directly to the sample values written to the QDAC. QDAC DC OFFSET 1 REGISTER Address: 0x3E, Reset: 0x00, Name: QDAC_DC_OFFSET1 Table 82. Bit Descriptions for QDAC_DC_OFFSET1 Bits [7:0] Bit Name QDAC_DC_OFFSET_MSB Settings Description QDAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3D, is a dc value that is added directly to the sample values written to the QDAC. IDAC GAIN ADJUST REGISTER Address: 0x3F, Reset: 0x20, Name: IDAC_GAIN_ADJ Table 83. Bit Descriptions for IDAC_GAIN_ADJ Bits [5:0] Bit Name IDAC_GAIN_ADJ Settings Description This register is the 6-bit digital gain adjust on the I channel. The bit weighting is MSB = 20, LSB = 2−5, which yields a multiplier range of 0 to 2 or −∞ to 6 dB. The default gain setting is 0x20, which maps to unity gain (0 dB). Rev. A | Page 65 of 72 AD9142A Data Sheet QDAC GAIN ADJUST REGISTER Address: 0x40, Reset: 0x20, Name: QDAC_GAIN_ADJ Table 84. Bit Descriptions for QDAC_GAIN_ADJ Bits [5:0] Bit Name QDAC_GAIN_ADJ Settings Description This register is the 6-bit digital gain adjust on the Q channel. The bit weighting is MSB = 20, LSB = 2−5, which yields a multiplier range of 0 to 2 or −∞ to 6 dB. The default gain setting is 0x20, which maps to unity gain (0 dB). Reset 0x20 Access RW Reset 0x01 Access RW Reset 0x0 Access RW 0x1 R 0x01 RW Reset 1 Access RW 1 RW 1 RW GAIN STEP CONTROL 0 REGISTER Address: 0x41, Reset: 0x01, Name: GAIN_STEP_CTRL0 Table 85. Bit Descriptions for GAIN_STEP_CTRL0 Bits [5:0] Bit Name RAMP_UP_STEP Settings Description This register sets the step size of the increasing gain. The digital gain increases by the configured amount in every four DAC cycles until the gain reaches the setting in IDAC_GAIN_ADJ (Register 0x3F). The bit weighting is MSB = 21, LSB = 2−4. Note that the value in this register must not be greater than the values in the IDAC_GAIN_ADJ. GAIN STEP CONTROL 1 REGISTER Address: 0x42, Reset: 0x41, Name: GAIN_STEP_CTRL1 Table 86. Bit Descriptions for GAIN_STEP_CTRL1 Bits 7 Bit Name DAC_OUTPUT_OFF 6 DAC_OUTPUT_STATUS [5:0] RAMP_DOWN_STEP Settings Description This bit allows for turning the DAC output on and off manually. The digital IQ gain function (Register 0x27, Bit 5) must be turned on for this bit to function. This bit indicates the DAC output on/off status. When the DAC output is turned off, this bit is 1. Upon power-up, this bit is 1. The digital IQ gain function (Register 0x27, Bit 5) must be turned on for this bit to track the on/off status This register sets the step size of the decreasing gain. The digital gain decreases by the configured amount in every four DAC cycles until the gain reaches zero. The bit weighting is MSB = 21, LSB = 2−4. Note that the value in this register must not be greater than the values in the IDAC_GAIN_ADJ (Register 0x3F). TX ENABLE CONTROL REGISTER Address: 0x43, Reset: 0x07, Name: TX_ENABLE_CTRL Table 87. Bit Descriptions for TX_ENABLE_CTRL Bits 2 Bit Name TXENABLE_GAINSTEP_EN 1 TXENABLE_SLEEP_EN 0 TXENABLE_POWER_DOWN_EN Settings Description DAC output gradually turns on/off under the control of the TXENABLE signal from the TXEN pin according to the settings in Register 0x41 and Register 0x42. When set to 1, the device is put in sleep mode when the TXENABLE signal from the TXEN pin is low. When set to 1, the device is put in power down mode when the TXENABLE signal from the TXEN pin is low. Rev. A | Page 66 of 72 Data Sheet AD9142A DAC OUTPUT CONTROL REGISTER Address: 0x44, Reset: 0x8D, Name: DAC_OUTPUT_CTRL Table 88. Bit Descriptions for DAC_OUTPUT_CTRL Bits 7 Bit Name DAC_OUTPUT_CTRL_EN 3 FIFO_WARNING_SHUTDOWN_EN 2 OVERTHRESHOLD_SHUTDOWN_EN 0 FIFO_ERROR_SHUTDOWN_EN Settings Description Enables the DAC output control. This bit needs to be set to 1 to enable the remaining bits in this register. When this bit and Bit 7 are both high, if a FIFO warning occurs, the DAC output shuts down automatically. By default, this function is on. The DAC output is turned off when the input average power is greater than the predefined threshold. The DAC output is turned off when the FIFO reports warnings. Reset 0x1 Access RW 0x1 RW 0x1 RW 0x1 RW DLL CELL ENABLE 0 REGISTER Address: 0x5E, Reset: 0xFF, Name: ENABLE_DLL_DELAY_CELL0 Table 89. Bit Descriptions for ENABLE_DLL_DELAY_CELL0 Bits [7:0] Bit Name DELAY_CELL_ENABLE [7:0] Description Set each bit to enable or disable the delay cell. Delay cell number corresponds to bit number. 1 = enable delay cell (default). 0 = disable delay cell. Different recommended values should be used in DLL mode and delay line mode. See the Data Interface section. Reset 0xFF Access RW Description Must write the default value for optimal performance. Set each bit to enable or disable the delay cell. Delay cell numbers are 10, 9, 8 corresponding to bits Bit, Bit 2, and Bit 0, respectively. 1 = enable delay cell (default). 0 = disable delay cell. Reset 0x0C 0x7 Access RW RW Description Set to 1 to Enable the SED compare logic. When set to 1, clears all SED reported error bits, Bit 2, Bit 1, and Bit 0. When set to 1, enables the AED function (SED with auto clear after eight passing sets). 0 = SED depth of two words, 1 = SED depth of four words. Reserved. When AED = 1, it signals eight true compare cycles. When AED = 1, it signals a mismatch in comparison. Signals that an SED mismatch in comparison occurred (with SED or AED enabled). Reset 0 0 Access RW RW 0 RW 0 0 0 0 0 RW R RW R R DLL CELL ENABLE 1 REGISTER Address: 0x5F, Reset: 0x67, Name: ENABLE_DLL_DELAY_CELL1 Table 90. Bit Descriptions for ENABLE_DLL_DELAY_CELL1 Bits [7:3] [2:0] Bit Name Reserved DELAY_CELL_ENABLE [10:8] SED CONTROL REGISTER Address: 0x60, Reset: 0x00, Name: SED_CTRL Table 91. Bit Descriptions for SED_CTRL Bits 7 6 Bit Name SED_ENABLE SED_ERR_CLEAR 5 AED_ENABLE 4 3 2 1 0 SED_DEPTH Reserved AED_PASS AED_FAIL SED_FAIL Rev. A | Page 67 of 72 AD9142A Data Sheet SED PATTERN I0 LOW BITS REGISTER Address: 0x61, Reset: 0x00, Name: SED_PATT_L_I0 Table 92. Bit Descriptions for SED_PATT_L_I0 Bits [7:0] Bit Name SED_PATTERN_RISE_I0[7:0] Description SED I0 rising edge low bits. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW SED PATTERN I0 HIGH BITS REGISTER Address: 0x62, Reset: 0x00, Name: SED_PATT_H_I0 Table 93. Bit Descriptions for SED_PATT_H_I0 Bits [7:0] Bit Name SED_PATTERN_RISE_I0[15:8] Description SED I0 rising edge high bits. SED PATTERN Q0 LOW BITS REGISTER Address: 0x63, Reset: 0x00, Name: SED_PATT_L_Q0 Table 94. Bit Descriptions for SED_PATT_L_Q0 Bits [7:0] Bit Name SED_PATTERN_FALL_Q0[7:0] Description SED Q0 falling edge low bits. SED PATTERN Q0 HIGH BITS REGISTER Address: 0x64, Reset: 0x00, Name: SED_PATT_H_Q0 Table 95. Bit Descriptions for SED_PATT_H_Q0 Bits [7:0] Bit Name SED_PATTERN_FALL_Q0[15:8] Description SED Q0 falling edge high bits. SED PATTERN I1 LOW BITS REGISTER Address: 0x65, Reset: 0x00, Name: SED_PATT_L_I1 Table 96. Bit Descriptions for SED_PATT_L_I1 Bits [7:0] Bit Name SED_PATTERN_RISE_I1[7:0] Description SED I1 rising edge low bits. SED PATTERN I1 HIGH BITS REGISTER Address: 0x66, Reset: 0x00, Name: SED_PATT_H_I1 Table 97. Bit Descriptions for SED_PATT_H_I1 Bits [2:0] Bit Name SED_PATTERN_RISE_I1[15:8] Description SED I1 rising edge high bits. SED PATTERN Q1 LOW BITS REGISTER Address: 0x67, Reset: 0x00, Name: SED_PATT_L_Q1 Table 98. Bit Descriptions for SED_PATT_L_Q1 Bits [7:0] Bit Name SED_PATTERN_FALL_Q1[7:0] Description SED Q1 falling edge low bits. Rev. A | Page 68 of 72 Data Sheet AD9142A SED PATTERN Q1 HIGH BITS REGISTER Address: 0x68, Reset: 0x00, Name: SED_PATT_H_Q1 Table 99. Bit Descriptions for SED_PATT_H_Q1 Bits [2:0] Bit Name SED_PATTERN_FALL_Q1[15:8] Description SED Q1 falling edge high bits. Reset 0x00 Access RW PARITY CONTROL REGISTER Address: 0x6A, Reset: 0x00, Name: PARITY_CTRL Table 100. Bit Descriptions for PARITY_CTRL Bits 7 6 Bit Name PARITY_ENABLE PARITY_EVEN 5 [4:2] 1 0 PARITY_ERR_CLEAR Reserved PARERRFAL PARERRRISE Settings 1 0 1 Description Enable parity. Odd parity. Even parity. Set to 1 to clear parity error counters. Reserved. When 1, signals a falling edge parity error was detected. When 1, signals a rising edge parity error was detected. Reset 0 0 Access RW RW 0 0x0 0 0 RW R R R PARITY ERROR RISING EDGE REGISTER Address: 0x6B, Reset: 0x00, Name: PARITY_ERR_RISING Table 101. Bit Descriptions for PARITY_ERR_RISING Bits [7:0] Bit Name Parity Rising Edge Error Count Description Number of rising edge-based errors detected (S0 and S2). Clipped to 256. Reset 0x00 Access R Reset 0x00 Access R PARITY ERROR FALLING EDGE REGISTER Address: 0x6C, Reset: 0x00, Name: PARITY_ERR_FALLING Table 102. Bit Descriptions for PARITY_ERR_FALLING Bits [7:0] Bit Name Parity Falling Edge Error Count Description Number of falling edge-based errors detected (S1 and S3). Clipped to 256. VERSION REGISTER Address: 0x7F, Reset: 0x0B, Name: Version Table 103. Bit Descriptions for Version Bits [7:0] Bit Name Version Settings Description Chip version. Reset 0x0B Rev. A | Page 69 of 72 Access R AD9142A Data Sheet DAC LATENCY AND SYSTEM SKEWS DACCLK/8 DIV 2 DIV 2 DACCLK/4 DACCLK DIV 2 DACCLK/2 FIFO RdPtr DATA INTERFACE FIFO HB1 HB2 OTHER DIGITAL FUNCTIONALITIES HB3 I AND Q DAC FIFO WrPtr DCI VARYING LATENCY VARYING LATENCY FIXED LATENCY 11901-064 FIXED LATENCY Figure 62. Breakdown of Pipeline Latencies Figure 63 is an example of FIFO latency variation. The latency in Case 2 is two data cycles longer than that in Case 1. If other latencies are the same, the skew between the DAC outputs in these two cases is, likewise, two data cycles. Therefore, to keep a constant FIFO latency, the FIFO depth needs to be reset to a predefined value. Theoretically, any value other than 0 is valid but typically it is set to 4 to maximize the capacity of absorbing the rate fluctuation between the read and write sides. FIFO WrPtr DATA 1 FIFO WrPtr DATA 1 FIFO RdPtr DATA 2 FIFO LATENCY VARIATION There are eight data slots in the FIFO. The FIFO read and write pointers circulate the FIFO from Slot 0 to Slot 7 and back to Slot 0. The FIFO depth is defined as the number of FIFO slots that are required for the read pointer to catch the write pointer. It is also the time a particular piece of data stays in the FIFO from the point that it is written into the FIFO to the point where it is read out from the FIFO. Therefore, the latency of the FIFO is equivalent to its depth. FIFO DATA 0 DATA 2 DATA 3 DATA 3 DATA 4 DATA 4 DATA 5 DATA 5 DATA 6 DATA 6 DATA 7 DATA 7 CASE 1: LATENCY = 4 DCI CYCLES CASE 2: LATENCY = 6 DCI CYCLES FIFO RdPtr Figure 63. Example of FIFO Latency Difference Figure 64 shows two equivalent cases of FIFO latency of four data cycles. Although neither the read nor the write pointer match each other in these two cases, the FIFO depth is the same in both cases. Also, note that the beginning slots of the data stream in the two cases are not the same, but the read and write pointers point to the same piece of data in both cases. This does not affect the alignment accuracy of the DAC outputs as long as the data and the DCIs are well aligned at multiple devices. FIFO FIFO DATA 0 DATA 5 FIFO WrPtr DATA 1 DATA 2 FIFO RdPtr DATA 3 DATA 4 FIFO WrPtr DATA 6 DATA 7 DATA 0 LATENCY = 4 DCI CYCLES DATA 1 DATA 5 DATA 2 DATA 6 DATA 3 DATA 7 DATA 4 Figure 64. Example of Equal FIFO Latencies Rev. A | Page 70 of 72 FIFO RdPtr 11901-066 DACs, like any other devices with internal multiphase clocks, have an inherent pipeline latency variation. Figure 62 shows the delineation of pipeline latencies in the AD9142A. The highlighted section, including the FIFO and the clock generation circuitry, is where the pipeline latencies vary. Upon each poweron, the status of both the FIFO and the clock generation state machine is arbitrary. This leads to varying latency in these two blocks. FIFO DATA 0 11901-065 DAC LATENCY VARIATIONS Data Sheet AD9142A CLOCK GENERATION LATENCY VARIATION CORRECTING SYSTEM SKEWS The state machine of the clock generation circuitry is another source of latency variations; this type of latency variation results from inherent phase uncertainty of the static frequency dividers. The divided down clock can be high or low at the rising edge of the input clock, unless specifically forced to a known state. This means that whenever there is interpolation (when slower clocks must be internally generated by dividing down the DACCLK), there is an inherent latency variation in the DAC. Figure 65 is an example of this latency variation in 2× interpolation. Generally, it is assumed that the input data and the DCI among multiple devices are well aligned to each other. Depending on the system design, the data and DCI being input into each DAC can originate from various FPGAs or ASICs. Without synchronizing the data sources, the output of one data source can be skewed from that of another. The alignment between multiple data sources can also drift over temperature. There are two phase possibilities in the DACCLK/2 clock. The DACCLK/2 clock is used to read data from the FIFO and to drive the interpolation filter. Regardless of which clock edge is used to drive the digital circuit, there is a latency of one DAC clock cycle between Case 1 and Case 2 (see Figure 65). Because the poweron state arbitrarily falls in one of the two cases, the phase uncertainty of the divider appears as a varying skew between two DAC outputs. HB1 HB2 Figure 66 shows an example of a 2-channel transmitter with two data sources and two dual DACs. A constant but unknown phase offset appears between the outputs of the DAC devices, even if the DAC does not introduce any latency variations. The multidevice synchronization in the AD9142A can be used to compensate the skew due to misalignment of the data sources by resetting the two sides of the FIFO independently through two external reference clocks: the frame and the sync clock. The offset between the two data sources is then absorbed by the FIFO and clock generation block in the DAC. For more information about using the multidevice synchronization function, refer to the Synchronization Implementation section. DCI HB3 FRAME DAC 16-BIT DATA MATCH SYNC LINE FOR ALL DATA GEN DATA GEN DACCLK DACCLK/2 (CASE 1) 11901-067 DACCLK/2 (CASE 2) LATENCY VARIATION = 1 DACCLK CYCLE Figure 65. Latency Variation in 2× Interpolation from Clock Generation DCI FRAME DAC 16-BIT DATA DCI FRAME DAC 16-BIT DATA DATA GEN DCI FRAME DAC 16-BIT DATA 2 SYNC CLOCK DATA SKEW Figure 66. DAC Output Skew from Skewed Input Data and DCI Rev. A | Page 71 of 72 11901-068 4 MASTER REF CLOCK AD9142A Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 55 54 72 1 PIN 1 INDICATOR PIN 1 INDICATOR 9.85 9.75 SQ 9.65 0.50 BSC 0.50 0.40 0.30 18 37 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN 8.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 06-25-2012-A 1.00 0.85 0.80 19 36 TOP VIEW 12° MAX 6.15 6.00 SQ 5.85 EXPOSED PAD Figure 67. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-7) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9142ABCPZ AD9142ABCPZRL AD9142A-M5372-EBZ AD9142A-M5375-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ Evaluation Board Connected to ADL5372 Modulator Evaluation Board Connected to ADL5375 Modulator Z = RoHS Compliant Part. ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11901-0-5/14(A) Rev. A | Page 72 of 72 Package Option CP-72-7 CP-72-7