DI2CS I2C Bus Interface - Slave ver 3.02 OVERVIEW I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CS core provides an interface between a microprocessor /microcontroller and an I2C bus. It can works as a slave transmitter or slave receiver depending on working mode determined by a master device. The DI2CS core incorporates all features required by the latest I2C specification including clock synchronization, arbitration and High-speed transmission mode. The DI2CS supports all the transmission speed modes. KEY FEATURES ● Conforms to v.2.1 of the I2C specification ● Slave operation Fully synthesizable ● Static synchronous design with positive edge clocking and synchronous reset ● No internal tri-states ● Scan test ready APPLICATIONS ● Embedded microprocessor boards ● Consumer and professional audio/video ● Home and automotive radio ● Low-power applications ● Communication systems ● Cost-effective reliable automotive systems DELIVERABLES ○ Slave transmitter ○ Slave receiver ● ● Supports 3 transmission speed modes ○ Standard (up to 100 kb/s) ○ Fast (up to 400 kb/s) ○ High Speed (up to 3,4 Mb/s) ● Allows operation from a wide range of input clock frequencies ● Simple interface allows easy connection to microprocessor/microcontroller devices ● Interrupt generation ● User-defined data setup time All trademarks mentioned in this document are trademarks of their respective owners. ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet Synthesis scripts Example application Technical support ◊ ◊ ◊ ♦ ♦ ♦ ♦ ♦ http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. ◊ ◊ IP Core implementation support 3 months maintenance ● ● ● SYMBOL Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support datai(7:0) datao(7:0) address(1:0) cs rd we irq LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. scli sdai Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. rst clk Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. ● Single Design license for ○ VHDL, Verilog source code called HDL Source ○ Encrypted, or plain text EDIF called Netlist ● One Year license for ○ ● Encrypted Netlist only Unlimited Designs license for ○ HDL Source ○ Netlist ● sclo sdao PINS DESCRIPTION PIN TYPE DESCRIPTION clk input Global clock rst input Global reset address(1:0) input Processor address lines cs input Chip select we input Processor write strobe rd input Processor read strobe scli input I2C bus clock line (input) sdai input I2C bus data line (input) datai(7:0) input Processor data bus (input) datao(7:0) output Processor data bus (output) sclo output I2C bus clock line (output) sdao output I2C bus data line (output) irq output Processor interrupt line Upgrade from ○ HDL Source to Netlist ○ Single Design to Unlimited Designs All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. BLOCK DIAGRAM IMPLEMENTATION Figure below shows the DI2CS IP Core block diagram. Figure below show the typical DI2CS implementations in system with Standard/Fast and High-speed devices. Receive Data datai(7:0) datao(7:0) address(1:0) cs we rd Shift Register CPU Interface Send Data Input Filter sdai Output Register sdao VDD RP RP SDA Own address detection irq Control Register Status Register SCL Control Logic RS RS RS RS sdai rst clk Synchronization Logic Input Filter scli Clock Stretching Output Register sclo CPU Interface – Performs the interface functions between DI2CS internal blocks and microprocessor. Allows easy connection of the core to a microprocessor/microcontroller system. Control Logic – Manages execution of all commands sent via interface. Synchronizes internal data flow. Shift Register – Controls SDA line, performs data and address shifts during the data transmission and reception. Control Register – Contains five control bits used for performing all types of I2C Bus transmissions. Status Register – Contains seven status bits that indicates state of the I2C Bus and the DI2CS core. Input Filter – Performs spike filtering. Synchronization Logic – Performs DI2CS core synchronization. Clock Stretching – Performs I2C SCL clock stretching when DI2CS core is not ready for next transmission. All trademarks mentioned in this document are trademarks of their respective owners. sda sdao open drain DI2CS scli Master device scl sclo open drain PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route (all key features have been included): Speed Logic Cells Fmax grade MERCURY -5 170 250 MHz STRATIX -5 170 260 MHz CYCLONE -6 170 220 MHz APEX II -7 170 270 MHz APEX20KC -7 170 150 MHz APEX20KE -1 170 120 MHz APEX20K -1 170 90 MHz ACEX1K -1 170 107 MHz FLEX10KE -1 170 107 MHz MAX 7000AE -5 83 96 MHz MAX 3000A -5 83 104 MHz Core performance in ALTERA® devices Device http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. - - - I2C cores summary table CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND [email protected] e-mail: [email protected] tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: ttp://www.dcd.pl/apartn.php Please check hhttp://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. Spike filtering User defined timing High-speed mode Fast mode - Standard mode - 10-bit addressing Arbitration - - 7-bit addressing Clock synchronization - Passive device interface CPU interface - Slave operation 3.0 2.1 2.1 Interrupt generation DI2CM DI2CS DI2CSB Master operation Design I2C specification version The main features of each Digital Core Design I2C compliant cores have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application.